Gate driving unit, gate driving circuit, gate driving method and display device

Abstract

A gate drive unit, a gate drive circuit, a gate drive method and a display device. The gate drive unit comprises a first output circuit (11) and a second output circuit; the second output circuit comprises a first output subcircuit (121); the first output circuit (11) is electrically connected to a first node (N1), a second node (N2) and a first gate drive signal output terminal (OUT_P) respectively, and is used to control the first gate drive signal output terminal (OUT_P) to output a first gate drive signal under the control of the potential of the first node (N1) and the potential of the second node (N2); the first output subcircuit (121) is electrically connected to the first node (N1), the second gate drive signal output terminal (OUT_N) and a first clock signal terminal respectively, and is used to control the second gate drive signal output terminal (OUT_N) to be connected to the first clock signal terminal under the control of the potential of the first node (N1).

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a gate driving unit, a gate driving circuit, a gate driving method and a display device. Background Art

[0002] As people's demand for display continues to increase, high and low frequency display has become a hot topic of research. Oxide TFT (thin film transistor) has low leakage, can achieve low frequency, and is compatible with LTPS (low temperature polycrystalline silicon) process, so it is used in OLED (organic light emitting diode) pixel circuits. Because oxide TFT is an n-type transistor, the gate drive circuit that provides control signals for it has become one of the key technologies of LTPO (Low Temperature Polycrystalline Oxide) technology. Summary of the invention

[0003] The main purpose of the present invention is to provide a gate driving unit, a gate driving circuit, a gate driving method and a display device to solve the problem that the existing gate driving unit suitable for LTPO (Low Temperature Polycrystalline Oxide) pixel circuit cannot achieve a step-free drop in the output gate driving signal.

[0004] In one aspect, an embodiment of the present invention provides a gate driving unit, comprising a first output circuit and a second output circuit; the second output circuit comprises a first output sub-circuit;

[0005] The first output circuit is electrically connected to the first node, the second node and the first gate drive signal output terminal respectively, and is used to control the first gate drive signal output terminal to output the first gate drive signal under the control of the potential of the first node and the potential of the second node;

[0006] The first output subcircuit is electrically connected to the first node, the second gate drive signal output terminal and the first clock signal terminal respectively, and is used to control the connection between the second gate drive signal output terminal and the first clock signal terminal under the control of the potential of the first node.

[0007] Optionally, the first output subcircuit includes a first output transistor;

[0008] The control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the first clock signal terminal, and the second electrode of the first output transistor is electrically connected to the second gate drive signal output terminal.

[0009] Optionally, the second output circuit further includes a second output subcircuit and a third node control subcircuit;

[0010] The second output subcircuit is electrically connected to the third node, the second gate drive signal output terminal and the first voltage terminal respectively, and is used to control the first voltage signal provided by the first voltage terminal to be written into the second gate drive signal output terminal under the control of the potential of the third node;

[0011] The third node control subcircuit is electrically connected to the first gate drive signal output terminal, the second clock signal terminal, the third clock signal terminal, the first voltage terminal and the second voltage terminal, respectively, and is used to control the potential of the third node under the control of the first gate drive signal output from the first gate drive signal output terminal, the second clock signal provided by the second clock signal terminal and the third clock signal provided by the third clock signal terminal.

[0012] Optionally, the second output subcircuit includes a second output transistor;

[0013] The control electrode of the second output transistor is electrically connected to the third node, the first electrode of the second output transistor is electrically connected to the second gate drive signal output terminal, and the second electrode of the second output transistor is electrically connected to the first voltage terminal.

[0014] Optionally, the third node control subcircuit is specifically used to control the writing of the second voltage signal provided by the second voltage terminal into the third node under the control of the first gate drive signal, and to control the writing of the first voltage signal into the third node under the control of the second clock signal, and to control the potential of the third node according to the third clock signal.

[0015] Optionally, the third node control subcircuit includes a first control transistor, a second control transistor and a first control capacitor,

[0016] The control electrode of the first control transistor is electrically connected to the first gate drive signal output terminal, the first electrode of the first control transistor is electrically connected to the second voltage terminal, and the second electrode of the first control transistor is electrically connected to the third node;

[0017] The control electrode of the second control transistor is electrically connected to the second clock signal terminal, the first electrode of the second control transistor is electrically connected to the third node, and the second electrode of the second control transistor is electrically connected to the first voltage terminal;

[0018] A first end of the first control capacitor is electrically connected to the third node, and a second end of the first control capacitor is electrically connected to the third clock signal end.

[0019] Optionally, the third node control subcircuit includes a third isolation node control unit circuit and a third node control unit circuit, wherein:

[0020] The third isolation node control unit circuit is electrically connected to the first gate drive signal output terminal, the second voltage terminal, the third isolation node, the second clock signal terminal, the third clock signal terminal and the first voltage terminal, respectively, and is used to control the second voltage signal to be written into the third isolation node under the control of the first gate drive signal, control the first voltage signal to be written into the third isolation node under the control of the second clock signal, and control the potential of the third isolation node according to the third clock signal;

[0021] The third node control unit circuit is electrically connected to the first gate drive signal output terminal, the third isolation node, the second voltage terminal and the third node, respectively, and is used to write the second voltage signal to the third node under the control of the first gate drive signal, and to control the connection between the third node and the third isolation node under the control of the potential of the third isolation node, and to maintain the potential of the third node.

[0022] Optionally, the third isolation node control unit circuit includes a first control transistor, a second control transistor and a first control capacitor, wherein:

[0023] The control electrode of the first control transistor is electrically connected to the first gate drive signal output terminal, the first electrode of the first control transistor is electrically connected to the second voltage terminal, and the second electrode of the first control transistor is electrically connected to the third isolation node;

[0024] The control electrode of the second control transistor is electrically connected to the second clock signal terminal, the first electrode of the second control transistor is electrically connected to the third isolation node, and the second electrode of the second control transistor is electrically connected to the first voltage terminal;

[0025] A first end of the first control capacitor is electrically connected to the third isolation node, and a second end of the first control capacitor is electrically connected to the third clock signal end.

[0026] Optionally, the third node control unit circuit includes a third control transistor, a fourth control transistor and a first storage capacitor, wherein:

[0027] The control electrode of the third control transistor is electrically connected to the first gate drive signal terminal, the first electrode of the third control transistor is electrically connected to the second voltage terminal, and the second electrode of the third control transistor is electrically connected to the third node;

[0028] The control electrode of the fourth control transistor and the first electrode of the fourth control transistor are both electrically connected to the third isolation node, and the second electrode of the fourth control transistor is electrically connected to the third node;

[0029] A first terminal of the first storage capacitor is electrically connected to the third node, and a second terminal of the first storage capacitor is electrically connected to the first voltage terminal.

[0030] Optionally, the first output circuit includes a first node control subcircuit and an energy storage subcircuit;

[0031] The first node control subcircuit is electrically connected to the third clock signal terminal, the input terminal, the second voltage terminal, the second node and the first node respectively, and is used to write the input signal provided by the input terminal into the first node under the control of the third clock signal provided by the third clock signal terminal, and is used to write the second voltage signal provided by the second voltage terminal into the first node under the control of the potential of the second node;

[0032] The first end of the energy storage subcircuit is electrically connected to the first node, the second end of the energy storage subcircuit is electrically connected to the first gate drive signal output end, and the energy storage subcircuit is used to store electrical energy.

[0033] Optionally, the first node control subcircuit includes a fifth control transistor and a sixth control transistor, wherein:

[0034] The control electrode of the fifth control transistor is electrically connected to the third clock signal terminal, the first electrode of the fifth control transistor is electrically connected to the input terminal, and the second electrode of the fifth control transistor is electrically connected to the first node;

[0035] The control electrode of the sixth control transistor is electrically connected to the second node, the first electrode of the sixth control transistor is electrically connected to the second voltage terminal, and the second electrode of the sixth control transistor is electrically connected to the first node;

[0036] The energy storage subcircuit includes a second storage capacitor;

[0037] A first end of the second storage capacitor is electrically connected to the first node, and a second end of the second storage capacitor is electrically connected to the first gate driving signal output end.

[0038] Optionally, the first node control subcircuit includes a first control unit circuit, a second control unit circuit, a third control unit circuit, a fourth control unit circuit, a fifth control unit circuit and a sixth control unit circuit, wherein:

[0039] The first control unit circuit is electrically connected to the third clock signal terminal, the input terminal and the fourth node respectively, and is used to write the input signal into the fourth node under the control of the third clock signal;

[0040] The second control unit circuit is electrically connected to the third clock signal terminal, the fourth node and the first node respectively, and is used to control the fourth node to be connected to the first node under the control of the third clock signal;

[0041] The third control unit circuit is electrically connected to the first gate drive signal output terminal, the fourth clock signal terminal and the fourth node respectively, and is used to write the fourth clock signal provided by the fourth clock signal terminal into the fourth node under the control of the first gate drive signal provided by the first gate drive signal output terminal;

[0042] The fourth control unit circuit is electrically connected to the second node, the second voltage terminal and the fifth node respectively, and is used to write the second voltage signal provided by the second voltage terminal into the fifth node under the control of the potential of the second node;

[0043] The fifth control unit circuit is electrically connected to the second node, the fifth node and the first node respectively, and is used to control the connection between the fifth node and the first node under the control of the potential of the second node;

[0044] The sixth control unit circuit is electrically connected to the first node, the fifth node and the first voltage terminal respectively, and is used to write the first voltage signal provided by the first voltage terminal into the fifth node under the control of the potential of the first node.

[0045] Optionally, the first control unit circuit includes a fifth control transistor, the second control unit circuit includes a seventh control transistor, the third control unit circuit includes an eighth control transistor, the fourth control unit circuit includes a sixth control transistor, the fifth control unit circuit includes a ninth control transistor, and the sixth control unit circuit includes a tenth control transistor, wherein:

[0046] The control electrode of the fifth control transistor is electrically connected to the third clock signal terminal, the first electrode of the fifth control transistor is electrically connected to the input terminal, and the second electrode of the fifth control transistor is electrically connected to the fourth node;

[0047] The control electrode of the seventh control transistor is electrically connected to the third clock signal terminal, the first electrode of the seventh control transistor is electrically connected to the fourth node, and the second electrode of the seventh control transistor is electrically connected to the first node;

[0048] The control electrode of the eighth control transistor is electrically connected to the first gate drive signal output terminal, the first electrode of the eighth control transistor is electrically connected to the fourth clock signal terminal, and the second electrode of the eighth control transistor is electrically connected to the fourth node;

[0049] The control electrode of the sixth control transistor is electrically connected to the second node, the first electrode of the sixth control transistor is electrically connected to the second voltage terminal, and the second electrode of the sixth control transistor is electrically connected to the fifth node;

[0050] The control electrode of the ninth control transistor is electrically connected to the second node, the first electrode of the ninth control transistor is electrically connected to the fifth node, and the second electrode of the ninth control transistor is electrically connected to the first node;

[0051] A control electrode of the tenth control transistor is electrically connected to the first node, a first electrode of the tenth control transistor is electrically connected to the fifth node, and a second electrode of the tenth control transistor is electrically connected to the first voltage terminal.

[0052] Optionally, the first output circuit further includes a second node control subcircuit and a third output subcircuit;

[0053] The second node control subcircuit is electrically connected to the second node, the input terminal, the second clock signal terminal, the first voltage terminal and the second voltage terminal respectively, and is used to write the second voltage signal provided by the second voltage terminal into the second node under the control of the input signal, write the first voltage signal provided by the first voltage terminal into the second node under the control of the second clock signal provided by the second clock signal terminal, and maintain the potential of the second node;

[0054] The third output sub-circuit is electrically connected to the second node, the second voltage terminal, the first gate drive signal output terminal, the first node and the fourth clock signal terminal, respectively, and is used to write the fourth clock signal provided by the fourth clock signal terminal into the first gate drive signal output terminal under the control of the potential of the first node, and to write the second voltage signal into the first gate drive signal output terminal under the control of the potential of the second node.

[0055] Optionally, the second node control subcircuit includes a seventh control transistor, an eighth control transistor and a second control capacitor;

[0056] The control electrode of the seventh control transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh control transistor is electrically connected to the second node, and the second electrode of the seventh control transistor is electrically connected to the first voltage terminal;

[0057] The control electrode of the eighth control transistor is electrically connected to the input terminal, the first electrode of the eighth control transistor is electrically connected to the second voltage terminal, and the second electrode of the eighth control transistor is electrically connected to the second node;

[0058] A first end of the second control capacitor is electrically connected to the second node, and a second end of the second control capacitor is electrically connected to the second voltage end.

[0059] Optionally, the third output subcircuit includes a third output transistor and a fourth output transistor, wherein:

[0060] The control electrode of the third output transistor is electrically connected to the second node, the first electrode of the third output transistor is electrically connected to the second voltage terminal, and the second electrode of the third output transistor is electrically connected to the first gate drive signal output terminal;

[0061] The control electrode of the fourth output transistor is electrically connected to the first node, the first electrode of the fourth output transistor is electrically connected to the first gate drive signal output terminal, and the second electrode of the fourth output transistor is electrically connected to the fourth clock signal terminal.

[0062] In a second aspect, an embodiment of the present invention further provides a gate driving circuit, comprising the above-mentioned gate driving unit.

[0063] Optionally, the gate driving circuit described in at least one embodiment of the present invention further includes a first clock signal input terminal, a second clock signal input terminal, a third clock signal input terminal, a first first clock signal terminal, a second first clock signal terminal and a third first clock signal terminal;

[0064] The input end of the gate driving unit is electrically connected to the first gate driving signal output end of the adjacent previous gate driving unit;

[0065] The third clock signal terminal of the 3n-2nd gate driving unit is electrically connected to the first clock signal input terminal, the fourth clock signal terminal of the 3n-2nd gate driving unit is electrically connected to the second clock signal input terminal, the second clock signal terminal of the 3n-2nd gate driving unit is electrically connected to the third clock signal input terminal; the first clock signal terminal of the 3n-2nd gate driving unit is electrically connected to the second first clock signal terminal;

[0066] The third clock signal terminal of the 3n-1th gate driving unit is electrically connected to the second clock signal input terminal, the fourth clock signal terminal of the 3n-1th gate driving unit is electrically connected to the third clock signal input terminal, the second clock signal terminal of the 3n-1th gate driving unit is electrically connected to the first clock signal input terminal; the first clock signal terminal of the 3n-1th gate driving unit is electrically connected to the third first clock signal terminal;

[0067] The third clock signal terminal of the 3n-stage gate driving unit is electrically connected to the third clock signal input terminal, the fourth clock signal terminal of the 3n-stage gate driving unit is electrically connected to the first clock signal input terminal, the second clock signal terminal of the 3n-stage gate driving unit is electrically connected to the second clock signal input terminal; the first clock signal terminal of the 3n-stage gate driving unit is electrically connected to the first first clock signal terminal;

[0068] n is a positive integer.

[0069] In a third aspect, an embodiment of the present invention further provides a gate driving method, which is applied to the above-mentioned gate driving circuit, and the gate driving method includes:

[0070] The first output circuit controls the first gate drive signal output terminal to output the first gate drive signal under the control of the potential of the first node and the potential of the second node;

[0071] The first output subcircuit controls the connection between the second gate drive signal output terminal and the first clock signal terminal under the control of the potential of the first node.

[0072] In a fourth aspect, an embodiment of the present invention further provides a display device, comprising the above-mentioned gate driving circuit.

[0073] Compared with the prior art, the gate driving unit, gate driving circuit, gate driving method and display device described in the present invention can provide a first gate driving signal and a second gate driving signal, the first gate driving signal is used to control a p-type transistor, and the second gate driving signal is used to control an n-type transistor, so that the gate driving unit described in the embodiment of the present invention can be applicable to an LTPO pixel circuit; and in the gate driving unit described in the embodiment of the present invention, the first output sub-circuit controls the connection between the second gate driving signal output terminal and the first clock signal terminal at the potential of the first node. Since the potential of the first node is bootstrapped and pulled down during the output time period, the transistor included in the first output sub-circuit can be fully turned on without any threshold voltage loss, so that the second gate driving signal drops without steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] Figure 1 is a structural diagram of a gate driving unit according to at least one embodiment of the present invention;

[0075] Figure 2 is a structural diagram of a gate driving unit according to at least one embodiment of the present invention;

[0076] Figure 3A is a structural diagram of a gate driving unit according to at least one embodiment of the present invention;

[0077] Figure 3B is a structural diagram of a gate driving unit according to at least one embodiment of the present invention;

[0078] Figure 4 is a structural diagram of a gate driving unit according to at least one embodiment of the present invention;

[0079] Figure 5 is a structural diagram of at least one embodiment of a first output circuit in a gate driving unit according to the present invention;

[0080] Figure 6 is a structural diagram of at least one embodiment of a first output circuit in a gate driving unit according to the present invention;

[0081] Figure 7 is a structural diagram of at least one embodiment of a first output circuit in a gate driving unit according to the present invention;

[0082] Figure 8 is a circuit diagram of a gate driving unit according to at least one embodiment of the present invention;

[0083] Fig. 9 The present invention Figure 8 A working timing diagram of at least one embodiment of the gate driving unit shown;

[0084] Fig.10 is a structural diagram of a gate driving circuit according to at least one embodiment of the present invention;

[0085] Fig.11 This is a working timing diagram of the gate driving circuit according to at least one embodiment of the present invention. DETAILED DESCRIPTION

[0086] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0087] The transistors used in all embodiments of the present invention may be triodes, thin film transistors, field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, in order to distinguish the two electrodes of the transistor except the control electrode, one of the electrodes is called the first electrode and the other is called the second electrode.

[0088] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0089] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.

[0090] like Figure 1 As shown, the gate driving unit according to at least one embodiment of the present invention includes a first output circuit 11 and a second output circuit; the second output circuit includes a first output sub-circuit 121;

[0091] The first output circuit 11 is electrically connected to the first node N1, the second node N2 and the first gate drive signal output terminal OUT_P respectively, and is used to control the first gate drive signal output terminal OUT_P to output the first gate drive signal under the control of the potential of the first node N1 and the potential of the second node N2;

[0092] The first output sub-circuit 121 is electrically connected to the first node N1, the second gate drive signal output terminal OUT_N and the first clock signal terminal respectively, and is used to control the second gate drive signal output terminal OUT_N to be connected to the first clock signal terminal under the control of the potential of the first node N1;

[0093] The first clock signal terminal is used to provide a first clock signal GCKO.

[0094] The gate driving unit described in at least one embodiment of the present invention can provide a first gate driving signal and a second gate driving signal, the first gate driving signal is used to control a p-type transistor, and the second gate driving signal is used to control an n-type transistor. The gate driving unit described in at least one embodiment of the present invention can be applicable to an LTPO (Low Temperature Polycrystalline Oxide) pixel circuit.

[0095] In the gate driving unit described in at least one embodiment of the present invention, the first output sub-circuit 121 controls the connection between the second gate driving signal output terminal OUT_N and the first clock signal terminal under the potential of the first node N1. Since the potential of the first node N1 is bootstrapped and pulled down during the output time period, the transistor included in the first output sub-circuit 121 can be fully turned on without any threshold voltage loss, so that the second gate driving signal output by OUT_N drops without steps, and the first output sub-circuit 121 is electrically connected to the first clock signal terminal, and the waveform of the first clock signal GCKO in the output stage is the same as the waveform of the gate driving signal output by OUT_N.

[0096] In the related art, in the related art, LTPO pixels integrate LTPS (low temperature polycrystalline silicon) TFT (thin film transistor) devices and oxide (oxide) TFT devices, wherein the LTPS TFT device is a p-type transistor and the oxide TFT device is an n-type transistor.

[0097] Optionally, the first output subcircuit may include a first output transistor;

[0098] The control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the first clock signal terminal, and the second electrode of the first output transistor is electrically connected to the second gate drive signal output terminal.

[0099] In at least one embodiment of the present invention, the first output transistor may be a p-type transistor, but is not limited thereto.

[0100] like Figure 2 As shown, in Figure 1 Based on at least one embodiment of the gate driving unit shown, the second output circuit further includes a second output sub-circuit 122 and a third node control sub-circuit 123;

[0101] The second output sub-circuit 122 is electrically connected to the third node N3, the second gate drive signal output terminal OUT_N and the first voltage terminal V1 respectively, and is used to control the first voltage signal provided by the first voltage terminal V1 to be written into the second gate drive signal output terminal OUT_N under the control of the potential of the third node N3;

[0102] The third node control subcircuit 123 is electrically connected to the first gate drive signal output terminal OUT_P, the second clock signal terminal, the third clock signal terminal, the first voltage terminal V1 and the second voltage terminal V2, respectively, and is used to control the potential of the third node N3 under the control of the first gate drive signal output terminal OUT_P, the second clock signal GCK3 provided by the second clock signal terminal and the third clock signal GCK1 provided by the third clock signal terminal.

[0103] In at least one embodiment of the present invention, the first voltage terminal V1 may be a low voltage terminal, and the second voltage terminal V2 may be a high voltage terminal, but the present invention is not limited thereto.

[0104] The present invention Figure 2When at least one embodiment of the gate driving unit shown is in operation, the second output sub-circuit 122 controls OUT_N to output a first voltage signal under the control of the potential of the third node N3; the third node control sub-circuit 123 controls the potential of N3 under the control of the first gate driving signal, the second clock signal GCK3 and the third clock signal GCK1.

[0105] Optionally, the second output subcircuit includes a second output transistor;

[0106] The control electrode of the second output transistor is electrically connected to the third node, the first electrode of the second output transistor is electrically connected to the second gate drive signal output terminal, and the second electrode of the second output transistor is electrically connected to the first voltage terminal.

[0107] In at least one embodiment of the present invention, the third node control subcircuit 123 is specifically used to control the writing of the second voltage signal into the third node N3 under the control of the first gate drive signal, and to control the writing of the first voltage signal into the third node N3 under the control of the second clock signal GCK3, and to control the potential of the third node N3 according to the third clock signal GCK1.

[0108] Optionally, the third node control subcircuit includes a first control transistor, a second control transistor and a first control capacitor, wherein:

[0109] The control electrode of the first control transistor is electrically connected to the first gate drive signal output terminal, the first electrode of the first control transistor is electrically connected to the second voltage terminal, and the second electrode of the first control transistor is electrically connected to the third node;

[0110] The control electrode of the second control transistor is electrically connected to the second clock signal terminal, the first electrode of the second control transistor is electrically connected to the third node, and the second electrode of the second control transistor is electrically connected to the first voltage terminal;

[0111] A first end of the first control capacitor is electrically connected to the third node, and a second end of the first control capacitor is electrically connected to the third clock signal end.

[0112] like Figure 3A As shown, in Figure 2 Based on at least one embodiment of the gate driving unit shown in FIG. 1 , the third node control subcircuit 123 may include a first control transistor M11, a second control transistor M12 and a first control capacitor C3, wherein:

[0113] The gate of the first control transistor M11 is electrically connected to the first gate drive signal output terminal OUT_P, the source of the first control transistor M11 is electrically connected to the high voltage terminal, and the drain of the first control transistor M11 is electrically connected to the third node N3;

[0114] The gate of the second control transistor M12 is electrically connected to the second clock signal terminal, the source of the second control transistor M12 is electrically connected to the third node N3, and the drain of the second control transistor M12 is electrically connected to the low voltage terminal; the second clock signal terminal is used to provide a second clock signal GCK3;

[0115] A first end of the first control capacitor C3 is electrically connected to the third node N3, and a second end of the first control capacitor C3 is electrically connected to the third clock signal end; the third clock signal end is used to provide a third clock signal GCK1.

[0116] exist Figure 3A In at least one embodiment shown, M11 and M12 are p-type thin film transistors, but the present invention is not limited thereto.

[0117] The present invention Figure 3A When at least one embodiment of the gate driving unit shown is in operation, when OUT_P outputs a low voltage signal, M11 is turned on, and when OUT_P outputs a high voltage signal, M11 is turned off; when GCK3 is a low voltage, M12 is turned on, and when GCK3 is a high voltage, M12 is turned off; C3 is used to control the potential of N3 according to the potential of GCK1.

[0118] The present invention Figure 3A At least one embodiment of the gate driving unit shown in the figure is in operation.

[0119] When GCK3 is at a low voltage, M12 is turned on and VGL is written to N3. At this time, GCK1 is at a high voltage, and C3 stores a negative voltage.

[0120] When GCK1 decreases from a high voltage to a low voltage, the potential of N3 further decreases, so that the second output transistor included in the second output sub-circuit can be fully turned on.

[0121] like Figure 3B As shown, in Figure 2 Based on at least one embodiment of the gate driving unit shown in FIG. 1 , the third node control subcircuit may include a third isolation node control unit circuit 31 and a third node control unit circuit 32, wherein:

[0122] The third isolation node control unit circuit 31 is electrically connected to the first gate drive signal output terminal OUT_P, the second voltage terminal V2, the third isolation node N03, the second clock signal terminal, the third clock signal terminal and the first voltage terminal V1, respectively, and is used to control the second voltage signal to be written into the third isolation node N03 under the control of the first gate drive signal provided by OUT_P, and to control the first voltage signal to be written into the third isolation node N03 under the control of the second clock signal GCK3, and to control the potential of the third isolation node N03 according to the third clock signal GCK1;

[0123] The third node control unit circuit 32 is electrically connected to the first gate drive signal output terminal OUT_P, the third isolation node N03, the second voltage terminal V2 and the third node N3, respectively, and is used to write the second voltage signal to the third node N3 under the control of the first gate drive signal, and to control the connection between the third node N3 and the third isolation node N03 under the control of the potential of the third isolation node N03, and to maintain the potential of the third node N3.

[0124] Optionally, the third isolation node control unit circuit includes a first control transistor, a second control transistor and a first control capacitor, wherein:

[0125] The control electrode of the first control transistor is electrically connected to the first gate drive signal output terminal, the first electrode of the first control transistor is electrically connected to the second voltage terminal, and the second electrode of the first control transistor is electrically connected to the third isolation node;

[0126] The control electrode of the second control transistor is electrically connected to the second clock signal terminal, the first electrode of the second control transistor is electrically connected to the third isolation node, and the second electrode of the second control transistor is electrically connected to the first voltage terminal;

[0127] A first end of the first control capacitor is electrically connected to the third isolation node, and a second end of the first control capacitor is electrically connected to the third clock signal end.

[0128] In at least one embodiment of the present invention, the third node control unit circuit may include a third control transistor, a fourth control transistor and a first storage capacitor, wherein:

[0129] The control electrode of the third control transistor is electrically connected to the first gate drive signal terminal, the first electrode of the third control transistor is electrically connected to the second voltage terminal, and the second electrode of the third control transistor is electrically connected to the third node;

[0130] The control electrode of the fourth control transistor and the first electrode of the fourth control transistor are both electrically connected to the third isolation node, and the second electrode of the fourth control transistor is electrically connected to the third node;

[0131] A first terminal of the first storage capacitor is electrically connected to the third node, and a second terminal of the first storage capacitor is electrically connected to the first voltage terminal.

[0132] like Figure 4 As shown, in Figure 3B Based on at least one embodiment of the gate driving unit shown,

[0133] The third isolation node control unit circuit 31 includes a first control transistor M11, a second control transistor M12 and a first control capacitor C3, wherein:

[0134] The gate of the first control transistor M11 is electrically connected to the first gate drive signal output terminal OUT_P, the source of the first control transistor M11 is electrically connected to the high voltage terminal, and the drain of the first control transistor M11 is electrically connected to the third isolation node N03; the high voltage terminal is used to provide a high voltage VGH;

[0135] The gate of the second control transistor M12 is electrically connected to the second clock signal terminal, the source of the second control transistor M12 is electrically connected to the third isolation node N03, and the drain of the second control transistor M12 is electrically connected to the low voltage terminal; the low voltage terminal is used to provide a low voltage VGL; the second clock signal terminal is used to provide a second clock signal GCK3;

[0136] The first end of the first control capacitor C3 is electrically connected to the third isolation node N03, and the second end of the first control capacitor C3 is electrically connected to the third clock signal end; the third clock signal end is used to provide a third clock signal GCK1;

[0137] The third node control unit circuit 32 includes a third control transistor M14, a fourth control transistor M13 and a first storage capacitor C4, wherein:

[0138] The gate of the third control transistor M14 is electrically connected to the first gate drive signal terminal OUT_P, the source of the third control transistor M14 is electrically connected to the high voltage terminal, and the drain of the third control transistor M14 is electrically connected to the third node N3;

[0139] The gate of the fourth control transistor M13 and the source of the fourth control transistor M13 are both electrically connected to the third isolation node N03, and the drain of the fourth control transistor M13 is electrically connected to the third node N3;

[0140] A first end of the first storage capacitor C4 is electrically connected to the third node N3, and a second end of the first storage capacitor C3 is electrically connected to the low voltage end;

[0141] The high voltage terminal is used to provide a high voltage VGH, and the low voltage terminal is used to provide a low voltage VGL.

[0142] exist Figure 4 In at least one embodiment shown, all transistors are p-type thin film transistors, but the present invention is not limited thereto.

[0143] The present invention Figure 4 At least one embodiment of the gate driving unit shown in the figure is in operation.

[0144] When GCK3 is at a low voltage, M12 is turned on and VGL is written to N03. At this time, GCK1 is at a high voltage, and C3 stores a negative voltage.

[0145] When GCK1 decreases from a high voltage to a low voltage, the potential of N3 further decreases, M13 is turned on, and the potential of N3 is pulled down to a sufficiently low level so that the second output transistor included in the second output sub-circuit can be fully turned on.

[0146] In the present invention, Figure 4 In at least one embodiment of the gate driving unit shown, if M13 is not used, since the potential of GCK1 is constantly switched between high voltage and low voltage, the potential of N3 cannot always maintain a sufficiently low potential, and the second output transistor included in the second output subcircuit cannot be fully turned on, resulting in poor low voltage output effect;

[0147] The present invention Figure 4 At least one embodiment of the gate driving unit shown uses M13. When GCK1 increases the potential of N03, M13 is turned off, so that the potential of N3 can be maintained at a sufficiently low level, thereby ensuring the effect of low voltage output.

[0148] like Figure 5 As shown, the first output circuit may include a first node control subcircuit 51 and an energy storage subcircuit 52;

[0149] The first node control subcircuit 51 is electrically connected to the third clock signal terminal, the input terminal GSTV, the second voltage terminal V2, the second node N2 and the first node N1 respectively, and is used to write the input signal provided by the input terminal GSTV into the first node N1 under the control of the third clock signal GCK1 provided by the third clock signal terminal, and is used to write the second voltage signal provided by the second voltage terminal V2 into the first node N1 under the control of the potential of the second node N2;

[0150] A first end of the energy storage sub-circuit 52 is electrically connected to the first node N1 , and a second end of the energy storage sub-circuit 52 is electrically connected to the first gate drive signal output terminal OUT_P. The energy storage sub-circuit 52 is used to store electrical energy.

[0151] Optionally, the first node control subcircuit includes a fifth control transistor and a sixth control transistor, wherein:

[0152] The control electrode of the fifth control transistor is electrically connected to the third clock signal terminal, the first electrode of the fifth control transistor is electrically connected to the input terminal, and the second electrode of the fifth control transistor is electrically connected to the first node;

[0153] The control electrode of the sixth control transistor is electrically connected to the second node, the first electrode of the sixth control transistor is electrically connected to the second voltage terminal, and the second electrode of the sixth control transistor is electrically connected to the first node;

[0154] The energy storage subcircuit includes a second storage capacitor;

[0155] A first end of the second storage capacitor is electrically connected to the first node, and a second end of the second storage capacitor is electrically connected to the first gate driving signal output end.

[0156] In at least one embodiment of the present invention, the first node control subcircuit may include a first control unit circuit, a second control unit circuit, a third control unit circuit, a fourth control unit circuit, a fifth control unit circuit and a sixth control unit circuit, wherein:

[0157] The first control unit circuit is electrically connected to the third clock signal terminal, the input terminal and the fourth node respectively, and is used to write the input signal into the fourth node under the control of the third clock signal;

[0158] The second control unit circuit is electrically connected to the third clock signal terminal, the fourth node and the first node respectively, and is used to control the fourth node to be connected to the first node under the control of the third clock signal;

[0159] The third control unit circuit is electrically connected to the first gate drive signal output terminal, the fourth clock signal terminal and the fourth node respectively, and is used to write the fourth clock signal provided by the fourth clock signal terminal into the fourth node under the control of the first gate drive signal provided by the first gate drive signal output terminal;

[0160] The fourth control unit circuit is electrically connected to the second node, the second voltage terminal and the fifth node respectively, and is used to write the second voltage signal provided by the second voltage terminal into the fifth node under the control of the potential of the second node;

[0161] The fifth control unit circuit is electrically connected to the second node, the fifth node and the first node respectively, and is used to control the connection between the fifth node and the first node under the control of the potential of the second node;

[0162] The sixth control unit circuit is electrically connected to the first node, the fifth node and the first voltage terminal respectively, and is used to write the first voltage signal provided by the first voltage terminal into the fifth node under the control of the potential of the first node.

[0163] In a specific implementation, the first node control subcircuit may include a first control unit circuit, a second control unit circuit, a third control unit circuit, a fourth control unit circuit, a fifth control unit circuit and a sixth control unit circuit. The first control unit circuit is used to write the input signal to the fourth node under the control of the third clock signal. The fourth control unit circuit is used to write the second voltage signal to the fifth node under the control of the potential of the second node. The second control unit circuit, the third control unit circuit, the fifth control unit circuit and the sixth control unit circuit are used to prevent leakage current.

[0164] like Figure 6 As shown, in Figure 5 Based on at least one embodiment of the gate driving unit shown in FIG. 1 , the first node control subcircuit 51 includes a first control unit circuit, a second control unit circuit, a third control unit circuit, a fourth control unit circuit, a fifth control unit circuit and a sixth control unit circuit, wherein:

[0165] The first control unit circuit includes a fifth control transistor M1, the second control unit circuit includes a seventh control transistor M2, the third control unit circuit includes an eighth control transistor M10, the fourth control unit circuit includes a sixth control transistor M6, the fifth control unit circuit includes a ninth control transistor M7, and the sixth control unit circuit includes a tenth control transistor M8, wherein:

[0166] The gate of M1 is electrically connected to the third clock signal terminal, the source of M1 is electrically connected to the input terminal GSTV, and the drain of M1 is electrically connected to the fourth node N4; the third clock signal terminal provides a third clock signal GCK1;

[0167] The gate of M2 is electrically connected to the third clock signal terminal, the source of M2 is electrically connected to the fourth node N4, and the drain of M2 is electrically connected to the first node N1;

[0168] The gate of M10 is electrically connected to the first gate drive signal output terminal OUT_P, the source of M10 is electrically connected to the fourth clock signal terminal, and the drain of M10 is electrically connected to the fourth node N4; the fourth clock signal terminal is used to provide a fourth clock signal GCK2;

[0169] The gate of M6 is electrically connected to the second node N2, the source of M6 is electrically connected to the high voltage terminal, and the drain of M6 is electrically connected to the fifth node N5; the high voltage terminal is used to provide a high voltage VGH;

[0170] The gate of M7 is electrically connected to the second node N2, the source of M7 is electrically connected to the fifth node N5, and the drain of M7 is electrically connected to the first node N1;

[0171] The gate of M8 is electrically connected to the first node N1 , the source of M8 is electrically connected to the fifth node N5 , and the drain of M8 is electrically connected to a low voltage terminal; the low voltage terminal is used to provide a low voltage VGL.

[0172] exist Figure 6 In at least one embodiment shown, all transistors are p-type thin film transistors, but the present invention is not limited thereto.

[0173] exist Figure 6 In at least one embodiment shown, M1 and M2 constitute a dual-gate transistor, M6 and M7 constitute a dual-gate transistor, the dual-gate transistor has a small leakage current, and M10 is used to control the potential of N4 to reduce the drain-source voltage of M1 and the drain-source voltage of M2 in a predetermined time period to reduce the leakage current of M1 and the leakage current of M2; and M8 is used to control the potential of N5 to reduce the drain-source voltage of M6 and the drain-source voltage of M7 in a predetermined time period to reduce the leakage current of M6 and the leakage current of M7.

[0174] In at least one embodiment of the present invention, the first output circuit further includes a second node control subcircuit and a third output subcircuit;

[0175] The second node control subcircuit is electrically connected to the second node, the input terminal, the second clock signal terminal, the first voltage terminal and the second voltage terminal respectively, and is used to write the second voltage signal provided by the second voltage terminal into the second node under the control of the input signal, write the first voltage signal provided by the first voltage terminal into the second node under the control of the second clock signal provided by the second clock signal terminal, and maintain the potential of the second node;

[0176] The third output sub-circuit is electrically connected to the second node, the second voltage terminal, the first gate drive signal output terminal, the first node and the fourth clock signal terminal, respectively, and is used to write the fourth clock signal provided by the fourth clock signal terminal into the first gate drive signal output terminal under the control of the potential of the first node, and to write the second voltage signal into the first gate drive signal output terminal under the control of the potential of the second node.

[0177] like Figure 7 As shown, in Figure 5 Based on at least one embodiment of the gate driving unit shown, the first output circuit further includes a second node control subcircuit 53 and a third output subcircuit 54;

[0178] The second node control subcircuit 53 is electrically connected to the second node N2, the input terminal GSTV, the second clock signal terminal, the first voltage terminal V1 and the second voltage terminal V2 respectively, and is used to write the second voltage signal provided by the second voltage terminal V2 into the second node N2 under the control of the input signal provided by GSTV, write the first voltage signal provided by the first voltage terminal V1 into the second node N2 under the control of the second clock signal GCK3 provided by the second clock signal terminal, and maintain the potential of the second node N2;

[0179] The third output sub-circuit 54 is electrically connected to the second node N2, the second voltage terminal V2, the first gate drive signal output terminal OUT_P, the first node N1 and the fourth clock signal terminal, respectively, and is used to write the fourth clock signal GCK2 provided by the fourth clock signal terminal into the first gate drive signal output terminal OUT_P under the control of the potential of the first node N1, and to write the second voltage signal into the first gate drive signal output terminal OUT_P under the control of the potential of the second node N2.

[0180] like Figure 7 When at least one embodiment of the gate driving unit shown is in operation, the second node control subcircuit 53 writes the second voltage signal into N2 under the control of the input signal, writes the first voltage signal into N2 under the control of the second clock signal GCK3, and maintains the potential of N2; the third output subcircuit controls OUT_P to output GCK2 under the control of the potential of N1, and controls OUT_P to output the second voltage signal under the control of the potential of N2.

[0181] Optionally, the second node control subcircuit includes a seventh control transistor, an eighth control transistor and a second control capacitor;

[0182] The control electrode of the seventh control transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh control transistor is electrically connected to the second node, and the second electrode of the seventh control transistor is electrically connected to the first voltage terminal;

[0183] The control electrode of the eighth control transistor is electrically connected to the input terminal, the first electrode of the eighth control transistor is electrically connected to the second voltage terminal, and the second electrode of the eighth control transistor is electrically connected to the second node;

[0184] A first end of the second control capacitor is electrically connected to the second node, and a second end of the second control capacitor is electrically connected to the second voltage end.

[0185] Optionally, the third output subcircuit includes a third output transistor and a fourth output transistor, wherein:

[0186] The control electrode of the third output transistor is electrically connected to the second node, the first electrode of the third output transistor is electrically connected to the second voltage terminal, and the second electrode of the third output transistor is electrically connected to the first gate drive signal output terminal;

[0187] The control electrode of the fourth output transistor is electrically connected to the first node, the first electrode of the fourth output transistor is electrically connected to the first gate drive signal output terminal, and the second electrode of the fourth output transistor is electrically connected to the fourth clock signal terminal.

[0188] like Figure 8 As shown, in Figure 4 Based on at least one embodiment of the gate driving unit shown, the first output sub-circuit 121 includes a first output transistor M16; the second output sub-circuit includes a second output transistor M15; the first output circuit includes a first node control sub-circuit 51, an energy storage sub-circuit 52, a second node control sub-circuit 53 and a third output sub-circuit 54;

[0189] The gate of M16 is electrically connected to the first node N1, the source of M16 is electrically connected to the first clock signal terminal, and the drain of M16 is electrically connected to the second gate drive signal output terminal OUT_N; the first clock signal terminal is used to provide a first clock signal GCKO;

[0190] The gate of M15 is electrically connected to the third node N3, the source of M15 is electrically connected to the second gate drive signal output terminal OUT_N, and the drain of M15 is electrically connected to a low voltage terminal; the low voltage terminal is used to provide a low voltage VGL;

[0191] The first node control subcircuit 51 includes a first control unit circuit, a second control unit circuit, a third control unit circuit, a fourth control unit circuit, a fifth control unit circuit and a sixth control unit circuit, wherein:

[0192] The first control unit circuit includes a fifth control transistor M1, the second control unit circuit includes a seventh control transistor M2, the third control unit circuit includes an eighth control transistor M10, the fourth control unit circuit includes a sixth control transistor M6, the fifth control unit circuit includes a ninth control transistor M7, and the sixth control unit circuit includes a tenth control transistor M8, wherein:

[0193] The gate of M1 is electrically connected to the third clock signal terminal, the source of M1 is electrically connected to the input terminal GSTV, and the drain of M1 is electrically connected to the fourth node N4; the third clock signal terminal provides a third clock signal GCK1;

[0194] The gate of M2 is electrically connected to the third clock signal terminal, the source of M2 is electrically connected to the fourth node N4, and the drain of M2 is electrically connected to the first node N1;

[0195] The gate of M10 is electrically connected to the first gate drive signal output terminal OUT_P, the source of M10 is electrically connected to the fourth clock signal terminal, and the drain of M10 is electrically connected to the fourth node N4; the fourth clock signal terminal is used to provide a fourth clock signal terminal GCK2;

[0196] The gate of M6 is electrically connected to the second node N2, the source of M6 is electrically connected to the high voltage terminal, and the drain of M6 is electrically connected to the fifth node N5; the high voltage terminal is used to provide a high voltage VGH;

[0197] The gate of M7 is electrically connected to the second node N2, the source of M7 is electrically connected to the fifth node N5, and the drain of M7 is electrically connected to the first node N1;

[0198] The gate of M8 is electrically connected to the first node N1, the source of M8 is electrically connected to the fifth node N5, and the drain of M8 is electrically connected to a low voltage terminal; the low voltage terminal is used to provide a low voltage VGL;

[0199] The energy storage subcircuit 52 includes a second storage capacitor C1;

[0200] A first end of C1 is electrically connected to the first node N1, and a second end of C1 is electrically connected to OUT_P;

[0201] The second node control subcircuit 53 includes a seventh control transistor M5, an eighth control transistor M9 and a second control capacitor C2;

[0202] The gate of M5 is electrically connected to the second clock signal terminal, the source of M5 is electrically connected to the second node N2, and the drain of M5 is electrically connected to the low voltage terminal; the low voltage terminal is used to provide a low voltage VGL;

[0203] The gate of M9 is electrically connected to the input terminal GSTV, the source of M9 is electrically connected to the high voltage terminal, and the drain of M9 is electrically connected to the second node N2; the high voltage terminal is used to provide a high voltage VGH;

[0204] A first end of the second control capacitor C2 is electrically connected to the second node N2, and a second end of the second control capacitor C2 is electrically connected to the high voltage end;

[0205] The third output sub-circuit 54 includes a third output transistor M4 and a fourth output transistor M3, wherein:

[0206] The gate of the third output transistor M4 is electrically connected to the second node N2, the source of the third output transistor M4 is electrically connected to the high voltage terminal, and the drain of the third output transistor M4 is electrically connected to the first gate drive signal output terminal OUT_P;

[0207] The gate of the fourth output transistor M3 is electrically connected to the first node N1, the source of the fourth output transistor M3 is electrically connected to the first gate drive signal output terminal OUT_P, and the drain of the fourth output transistor M3 is electrically connected to the fourth clock signal terminal; the fourth clock signal terminal is used to provide a fourth clock signal GCK2.

[0208] exist Figure 8 In at least one embodiment of the gate driving unit shown, all transistors are p-type thin film transistors, but the present invention is not limited thereto.

[0209] exist Figure 8 In at least one embodiment of the gate driving unit shown, the size of M1 is the same as the size of M2, and M1 and M2 are adjacent on the layout, so the threshold voltage of M1 and the threshold voltage of M2 can be the same, but not limited thereto.

[0210] like Fig. 9 As shown, the present invention is Figure 8 At least one embodiment of the gate driving unit shown in the figure is in operation.

[0211] In the pre-charge stage S1, GSTV provides a low voltage, GCK1 is a low voltage, GCK2 is a high voltage, M1 and M2 are turned on, the potential of N1 is pulled to a low potential VGL+Vth, M3 is turned on, OUT_P outputs a high voltage, and the voltage stored at both ends of C1 is VGL+Vth-VGH; at the same time, M9 is turned on, the potential of N2 is a high potential, and M4 is turned off; where Vth is the threshold voltage of M1;

[0212] In the bootstrap output stage S2, GSTV provides a high voltage, GCK1 is a high voltage, and GCK2 is a low voltage. Since M3 has been turned on in the previous stage, the low voltage of GCK2 is transmitted to OUT_P through M3. At the same time, since the voltage across C1 cannot change suddenly, the potential of N1 is raised to a lower potential, and the potential of N1 is 2VGL+Vth-2VGH, so that M3 can be turned on better.

[0213] In the second half of the bootstrap output stage S2, GCK2 jumps from a low voltage to a high voltage, because the potential of N1 is still lower than the potential of GCK2, so M3 is turned on, OUTP outputs GCK2, and a low pulse output of OUT_P is achieved;

[0214] In the bootstrap output stage S2, the low potential of N1 turns on M16, and OUT_N outputs GCKO. Since the high pulse width of GCKO is smaller than the low pulse width of GCK2, the pulse of GCKO can be fully transmitted to OUT_N, including the rising and falling parts; the low potential of OUT_P turns on M11 and M14, stabilizes the potential of N3 and the potential of N03 at a high potential, and turns off M15, avoiding the conflict in the output logic of OUT_N;

[0215] In the node pull-up stage S3, GCK3 is at a low voltage, M5 is turned on, the potential of N2 is pulled down to a low potential, M4 is turned on, and OUT_P outputs VGH; at the same time, the low potential of N2 turns on M6 and M7, the potential of N1 is pulled up to a high potential, M3 is turned off, M12 is turned on, and the potential of N03 is at a low potential. Since GCK1 is at a high voltage, the potential stored in C3 is VGL+Vth12-VGH at this time; wherein Vth12 is the threshold voltage of M12;

[0216] In the holding phase S4, GCK3 periodically pulls the potential of N2 to VGL to ensure that M4 is turned on, so that OUT_P stably outputs VGH. GCK3 periodically pulls down the potential of N03 and N3, and stores VGL+Vth12-VGH in C3. At the same time, GCK1 periodically jumps to a low voltage, and pulls the potential of N03 and N3 to a lower potential through C3 to ensure that M15 is fully turned on and outputs VGL to OUT_N.

[0217] like Fig. 9 As shown, the duty cycles of GCK1, GCK2 and GCK3 can be the same; GCK2 is delayed by a predetermined time than GCK1, and GCK3 is delayed by a predetermined time than GCK2, so that GCK1, GCK2 and GCK3 are not in low voltage at the same time, but not limited to this.

[0218] In at least one embodiment of the present invention, the duty cycle of GCK1, the duty cycle of GCK2 and the duty cycle of GCK3 may be slightly less than 1 / 3, or the duty cycle of GCK1, the duty cycle of GCK2 and the duty cycle of GCK3 may also be equal to 1 / 3; but the present invention is not limited thereto.

[0219] A gate driving circuit according to at least one embodiment of the present invention includes the above-mentioned gate driving unit.

[0220] The gate driving circuit described in at least one embodiment of the present invention further includes a first clock signal input terminal, a second clock signal input terminal, a third clock signal input terminal, a first first clock signal terminal, a second first clock signal terminal and a third first clock signal terminal;

[0221] The input end of the gate driving unit is electrically connected to the first gate driving signal output end of the adjacent previous gate driving unit;

[0222] The third clock signal terminal of the 3n-2nd gate driving unit is electrically connected to the first clock signal input terminal, the fourth clock signal terminal of the 3n-2nd gate driving unit is electrically connected to the second clock signal input terminal, the second clock signal terminal of the 3n-2nd gate driving unit is electrically connected to the third clock signal input terminal; the first clock signal terminal of the 3n-2nd gate driving unit is electrically connected to the second first clock signal terminal;

[0223] The third clock signal terminal of the 3n-1th gate driving unit is electrically connected to the second clock signal input terminal, the fourth clock signal terminal of the 3n-1th gate driving unit is electrically connected to the third clock signal input terminal, the second clock signal terminal of the 3n-1th gate driving unit is electrically connected to the first clock signal input terminal; the first clock signal terminal of the 3n-1th gate driving unit is electrically connected to the third first clock signal terminal;

[0224] The third clock signal terminal of the 3n-stage gate driving unit is electrically connected to the third clock signal input terminal, the fourth clock signal terminal of the 3n-stage gate driving unit is electrically connected to the first clock signal input terminal, the second clock signal terminal of the 3n-stage gate driving unit is electrically connected to the second clock signal input terminal; the first clock signal terminal of the 3n-stage gate driving unit is electrically connected to the first first clock signal terminal;

[0225] n is a positive integer.

[0226] like Fig.10As shown, X1 is a first-stage gate driving unit included in the gate driving circuit according to at least one embodiment of the present invention, X2 is a second-stage gate driving unit included in the gate driving circuit, X3 is a third-stage gate driving unit included in the gate driving circuit according to at least one embodiment of the present invention, X4 is a fourth-stage gate driving unit included in the gate driving circuit, X5 is a fifth-stage gate driving unit included in the gate driving circuit according to at least one embodiment of the present invention, and X6 is a sixth-stage gate driving unit included in the gate driving circuit;

[0227] The terminal labeled STV is the starting terminal; the terminal labeled OUT_P(1) is the first gate drive signal output terminal of X1, and the terminal labeled OUT_N(1) is the second gate drive signal output terminal of X1; the terminal labeled OUT_P(2) is the first gate drive signal output terminal of X2, and the terminal labeled OUT_N(2) is the second gate drive signal output terminal of X2; the terminal labeled OUT_P(3) is the first gate drive signal output terminal of X3, and the terminal labeled OUT_N(3) is the second gate drive signal output terminal of X3. signal output terminal; OUT_P(4) is a first gate drive signal output terminal of X4, OUT_N(4) is a second gate drive signal output terminal of X4; OUT_P(5) is a first gate drive signal output terminal of X5, OUT_N(5) is a second gate drive signal output terminal of X5; OUT_P(6) is a first gate drive signal output terminal of X6, OUT_N(6) is a second gate drive signal output terminal of X6;

[0228] The terminal labeled CK1 is a first clock signal input terminal, the terminal labeled CK2 is a second clock signal input terminal, and the terminal labeled CK3 is a third clock signal input terminal;

[0229] The terminal labeled CKO1 is the first first clock signal terminal, the terminal labeled CKO2 is the second first clock signal terminal, and the terminal labeled CKO3 is the third first clock signal terminal;

[0230] The third clock signal terminal of X1 is electrically connected to CK1, the fourth clock signal terminal of X1 is electrically connected to CK2, the second clock signal terminal of X1 is electrically connected to CK3, and the first clock signal terminal of X1 is electrically connected to CKO2;

[0231] The third clock signal terminal of X2 is electrically connected to CK2, the fourth clock signal terminal of X2 is electrically connected to CK3, the second clock signal terminal of X2 is electrically connected to CK1, and the first clock signal terminal of X1 is electrically connected to CKO3;

[0232] The third clock signal terminal of X3 is electrically connected to CK3, the fourth clock signal terminal of X3 is electrically connected to CK1, the second clock signal terminal of X1 is electrically connected to CK2, and the first clock signal terminal of X1 is electrically connected to CKO1;

[0233] The third clock signal terminal of X4 is electrically connected to CK1, the fourth clock signal terminal of X4 is electrically connected to CK2, the second clock signal terminal of X4 is electrically connected to CK3, and the first clock signal terminal of X4 is electrically connected to CKO2;

[0234] The third clock signal terminal of X5 is electrically connected to CK2, the fourth clock signal terminal of X5 is electrically connected to CK3, the second clock signal terminal of X5 is electrically connected to CK1, and the first clock signal terminal of X5 is electrically connected to CKO3;

[0235] The third clock signal terminal of X6 is electrically connected to CK3, the fourth clock signal terminal of X6 is electrically connected to CK1, the second clock signal terminal of X6 is electrically connected to CK2, and the first clock signal terminal of X6 is electrically connected to CKO1.

[0236] Fig.11 yes Fig.10 An operating timing diagram of at least one embodiment of the gate drive circuit in FIG.

[0237] like Fig.11 As shown, the duty cycle of the clock signal provided by CK1, the duty cycle of the clock signal provided by CK2, and the duty cycle of the clock signal provided by CK3 can be the same; the clock signal provided by CK2 is delayed by a predetermined time than the clock signal provided by CK1, and the clock signal provided by CK3 is delayed by a predetermined time than the clock signal provided by CK2, so that the clock signal provided by CK1, the clock signal provided by CK2, and the clock signal provided by CK3 are not low voltages at the same time, but not limited to this.

[0238] In at least one embodiment of the present invention, the duty cycle of the clock signal provided by CK1, the duty cycle of the clock signal provided by CK2, and the duty cycle of the clock signal provided by CK3 may be slightly less than 1 / 3, or the duty cycle of the clock signal provided by CK1, the duty cycle of the clock signal provided by CK2, and the duty cycle of the clock signal provided by CK3 may also be equal to 1 / 3; but not limited to this.

[0239] like Fig.11 As shown, the duty cycle of the first first clock signal provided by CKO1, the duty cycle of the second first clock signal provided by CKO2, and the duty cycle of the third first clock signal provided by CKO3 are all smaller than the duty cycle of the clock signal provided by CK1; and the first first clock signal, the second first clock signal and the third first clock signal are not high voltages at the same time.

[0240] A gate driving method according to at least one embodiment of the present invention is applied to the above-mentioned gate driving circuit, and the gate driving method includes:

[0241] The first output circuit controls the first gate drive signal output terminal to output the first gate drive signal under the control of the potential of the first node and the potential of the second node;

[0242] The first output subcircuit controls the connection between the second gate drive signal output terminal and the first clock signal terminal under the control of the potential of the first node.

[0243] A display device according to at least one embodiment of the present invention includes the above-mentioned gate driving circuit.

[0244] The display device provided in at least one embodiment of the present invention may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or the like.

[0245] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A gate driving unit, characterized in that: It includes a first output circuit and a second output circuit; the second output circuit includes a first output sub-circuit; The first output circuit is electrically connected to the first node, the second node and the first gate drive signal output terminal respectively, and is used to control the first gate drive signal output terminal to output the first gate drive signal under the control of the potential of the first node and the potential of the second node; The first output subcircuit is electrically connected to the first node, the second gate drive signal output terminal and the first clock signal terminal respectively, and is used to control the second gate drive signal output terminal to be connected to the first clock signal terminal under the control of the potential of the first node; The second output circuit further includes a second output subcircuit and a third node control subcircuit; The second output subcircuit is electrically connected to the third node, the second gate drive signal output terminal and the first voltage terminal respectively, and is used to control the first voltage signal provided by the first voltage terminal to be written into the second gate drive signal output terminal under the control of the potential of the third node; The third node control subcircuit is electrically connected to the first gate drive signal output terminal, the second clock signal terminal, the third clock signal terminal, the first voltage terminal and the second voltage terminal, respectively, and is used to control the potential of the third node under the control of the first gate drive signal output from the first gate drive signal output terminal, the second clock signal provided by the second clock signal terminal and the third clock signal provided by the third clock signal terminal.

2. The gate driving unit according to claim 1, characterized in that: The first output subcircuit includes a first output transistor; The control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the first clock signal terminal, and the second electrode of the first output transistor is electrically connected to the second gate drive signal output terminal.

3. The gate driving unit according to claim 1, wherein: The second output subcircuit includes a second output transistor; The control electrode of the second output transistor is electrically connected to the third node, the first electrode of the second output transistor is electrically connected to the second gate drive signal output terminal, and the second electrode of the second output transistor is electrically connected to the first voltage terminal.

4. The gate driving unit according to claim 1, characterized in that: The third node control subcircuit is specifically used to control the writing of the second voltage signal provided by the second voltage terminal into the third node under the control of the first gate drive signal, and to control the writing of the first voltage signal into the third node under the control of the second clock signal, and to control the potential of the third node according to the third clock signal.

5. The gate driving unit according to claim 4, characterized in that: The third node control subcircuit includes a first control transistor, a second control transistor and a first control capacitor, wherein: The control electrode of the first control transistor is electrically connected to the first gate drive signal output terminal, the first electrode of the first control transistor is electrically connected to the second voltage terminal, and the second electrode of the first control transistor is electrically connected to the third node; The control electrode of the second control transistor is electrically connected to the second clock signal terminal, the first electrode of the second control transistor is electrically connected to the third node, and the second electrode of the second control transistor is electrically connected to the first voltage terminal; A first end of the first control capacitor is electrically connected to the third node, and a second end of the first control capacitor is electrically connected to the third clock signal end.

6. The gate driving unit according to claim 1, wherein: The third node control subcircuit includes a third isolation node control unit circuit and a third node control unit circuit, wherein: The third isolation node control unit circuit is electrically connected to the first gate drive signal output terminal, the second voltage terminal, the third isolation node, the second clock signal terminal, the third clock signal terminal and the first voltage terminal, respectively, and is used to control the second voltage signal provided by the second voltage terminal to be written into the third isolation node under the control of the first gate drive signal, control the first voltage signal to be written into the third isolation node under the control of the second clock signal, and control the potential of the third isolation node according to the third clock signal; The third node control unit circuit is electrically connected to the first gate drive signal output terminal, the third isolation node, the second voltage terminal and the third node, respectively, and is used to write the second voltage signal to the third node under the control of the first gate drive signal, and to control the connection between the third node and the third isolation node under the control of the potential of the third isolation node, and to maintain the potential of the third node.

7. The gate driving unit according to claim 6, characterized in that: The third isolation node control unit circuit includes a first control transistor, a second control transistor and a first control capacitor, wherein: The control electrode of the first control transistor is electrically connected to the first gate drive signal output terminal, the first electrode of the first control transistor is electrically connected to the second voltage terminal, and the second electrode of the first control transistor is electrically connected to the third isolation node; The control electrode of the second control transistor is electrically connected to the second clock signal terminal, the first electrode of the second control transistor is electrically connected to the third isolation node, and the second electrode of the second control transistor is electrically connected to the first voltage terminal; A first end of the first control capacitor is electrically connected to the third isolation node, and a second end of the first control capacitor is electrically connected to the third clock signal end.

8. The gate driving unit according to claim 6, characterized in that: The third node control unit circuit includes a third control transistor, a fourth control transistor and a first storage capacitor, wherein: The control electrode of the third control transistor is electrically connected to the first gate drive signal output terminal, the first electrode of the third control transistor is electrically connected to the second voltage terminal, and the second electrode of the third control transistor is electrically connected to the third node; The control electrode of the fourth control transistor and the first electrode of the fourth control transistor are both electrically connected to the third isolation node, and the second electrode of the fourth control transistor is electrically connected to the third node; A first terminal of the first storage capacitor is electrically connected to the third node, and a second terminal of the first storage capacitor is electrically connected to the first voltage terminal.

9. The gate driving unit according to any one of claims 1 to 8, characterized in that: The first output circuit includes a first node control subcircuit and an energy storage subcircuit; The first node control subcircuit is electrically connected to the third clock signal terminal, the input terminal, the second voltage terminal, the second node and the first node respectively, and is used to write the input signal provided by the input terminal into the first node under the control of the third clock signal provided by the third clock signal terminal, and is used to write the second voltage signal provided by the second voltage terminal into the first node under the control of the potential of the second node; The first end of the energy storage subcircuit is electrically connected to the first node, the second end of the energy storage subcircuit is electrically connected to the first gate drive signal output end, and the energy storage subcircuit is used to store electrical energy.

10. The gate driving unit according to claim 9, characterized in that: The first node control subcircuit includes a fifth control transistor and a sixth control transistor, wherein: The control electrode of the fifth control transistor is electrically connected to the third clock signal terminal, the first electrode of the fifth control transistor is electrically connected to the input terminal, and the second electrode of the fifth control transistor is electrically connected to the first node; The control electrode of the sixth control transistor is electrically connected to the second node, the first electrode of the sixth control transistor is electrically connected to the second voltage terminal, and the second electrode of the sixth control transistor is electrically connected to the first node; The energy storage subcircuit includes a second storage capacitor; A first end of the second storage capacitor is electrically connected to the first node, and a second end of the second storage capacitor is electrically connected to the first gate driving signal output end.

11. The gate driving unit according to claim 9, characterized in that: The first node control subcircuit includes a first control unit circuit, a second control unit circuit, a third control unit circuit, a fourth control unit circuit, a fifth control unit circuit and a sixth control unit circuit, wherein: The first control unit circuit is electrically connected to the third clock signal terminal, the input terminal and the fourth node respectively, and is used to write the input signal into the fourth node under the control of the third clock signal; The second control unit circuit is electrically connected to the third clock signal terminal, the fourth node and the first node respectively, and is used to control the fourth node to be connected to the first node under the control of the third clock signal; The third control unit circuit is electrically connected to the first gate drive signal output terminal, the fourth clock signal terminal and the fourth node respectively, and is used to write the fourth clock signal provided by the fourth clock signal terminal into the fourth node under the control of the first gate drive signal provided by the first gate drive signal output terminal; The fourth control unit circuit is electrically connected to the second node, the second voltage terminal and the fifth node respectively, and is used to write the second voltage signal provided by the second voltage terminal into the fifth node under the control of the potential of the second node; The fifth control unit circuit is electrically connected to the second node, the fifth node and the first node respectively, and is used to control the connection between the fifth node and the first node under the control of the potential of the second node; The sixth control unit circuit is electrically connected to the first node, the fifth node and the first voltage terminal respectively, and is used to write the first voltage signal provided by the first voltage terminal into the fifth node under the control of the potential of the first node.

12. The gate driving unit according to claim 11, characterized in that: The first control unit circuit includes a fifth control transistor, the second control unit circuit includes a seventh control transistor, the third control unit circuit includes an eighth control transistor, the fourth control unit circuit includes a sixth control transistor, the fifth control unit circuit includes a ninth control transistor, and the sixth control unit circuit includes a tenth control transistor, wherein: The control electrode of the fifth control transistor is electrically connected to the third clock signal terminal, the first electrode of the fifth control transistor is electrically connected to the input terminal, and the second electrode of the fifth control transistor is electrically connected to the fourth node; The control electrode of the seventh control transistor is electrically connected to the third clock signal terminal, the first electrode of the seventh control transistor is electrically connected to the fourth node, and the second electrode of the seventh control transistor is electrically connected to the first node; The control electrode of the eighth control transistor is electrically connected to the first gate drive signal output terminal, the first electrode of the eighth control transistor is electrically connected to the fourth clock signal terminal, and the second electrode of the eighth control transistor is electrically connected to the fourth node; The control electrode of the sixth control transistor is electrically connected to the second node, the first electrode of the sixth control transistor is electrically connected to the second voltage terminal, and the second electrode of the sixth control transistor is electrically connected to the fifth node; The control electrode of the ninth control transistor is electrically connected to the second node, the first electrode of the ninth control transistor is electrically connected to the fifth node, and the second electrode of the ninth control transistor is electrically connected to the first node; A control electrode of the tenth control transistor is electrically connected to the first node, a first electrode of the tenth control transistor is electrically connected to the fifth node, and a second electrode of the tenth control transistor is electrically connected to the first voltage terminal.

13. The gate driving unit according to claim 9, characterized in that: The first output circuit further includes a second node control subcircuit and a third output subcircuit; The second node control subcircuit is electrically connected to the second node, the input terminal, the second clock signal terminal, the first voltage terminal and the second voltage terminal respectively, and is used to write the second voltage signal provided by the second voltage terminal into the second node under the control of the input signal, write the first voltage signal provided by the first voltage terminal into the second node under the control of the second clock signal provided by the second clock signal terminal, and maintain the potential of the second node; The third output sub-circuit is electrically connected to the second node, the second voltage terminal, the first gate drive signal output terminal, the first node and the fourth clock signal terminal, respectively, and is used to write the fourth clock signal provided by the fourth clock signal terminal into the first gate drive signal output terminal under the control of the potential of the first node, and to write the second voltage signal into the first gate drive signal output terminal under the control of the potential of the second node.

14. The gate driving unit according to claim 13, characterized in that: The second node control subcircuit includes a seventh control transistor, an eighth control transistor and a second control capacitor; The control electrode of the seventh control transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh control transistor is electrically connected to the second node, and the second electrode of the seventh control transistor is electrically connected to the first voltage terminal; The control electrode of the eighth control transistor is electrically connected to the input terminal, the first electrode of the eighth control transistor is electrically connected to the second voltage terminal, and the second electrode of the eighth control transistor is electrically connected to the second node; A first end of the second control capacitor is electrically connected to the second node, and a second end of the second control capacitor is electrically connected to the second voltage end.

15. The gate driving unit according to claim 13, characterized in that: The third output subcircuit includes a third output transistor and a fourth output transistor, wherein: The control electrode of the third output transistor is electrically connected to the second node, the first electrode of the third output transistor is electrically connected to the second voltage terminal, and the second electrode of the third output transistor is electrically connected to the first gate drive signal output terminal; The control electrode of the fourth output transistor is electrically connected to the first node, the first electrode of the fourth output transistor is electrically connected to the first gate drive signal output terminal, and the second electrode of the fourth output transistor is electrically connected to the fourth clock signal terminal.

16. A gate drive circuit, characterized in that: The method comprises a gate driving unit as claimed in any one of claims 1 to 15.

17. The gate driving circuit according to claim 16, wherein: Also includes a first clock signal input terminal, a second clock signal input terminal, a third clock signal input terminal, a first first clock signal terminal, a second first clock signal terminal and a third first clock signal terminal; The input end of the gate driving unit is electrically connected to the first gate driving signal output end of the adjacent previous gate driving unit; The third clock signal terminal of the 3n-2nd gate driving unit is electrically connected to the first clock signal input terminal, the fourth clock signal terminal of the 3n-2nd gate driving unit is electrically connected to the second clock signal input terminal, the second clock signal terminal of the 3n-2nd gate driving unit is electrically connected to the third clock signal input terminal; the first clock signal terminal of the 3n-2nd gate driving unit is electrically connected to the second first clock signal terminal; The third clock signal terminal of the 3n-1th gate driving unit is electrically connected to the second clock signal input terminal, the fourth clock signal terminal of the 3n-1th gate driving unit is electrically connected to the third clock signal input terminal, the second clock signal terminal of the 3n-1th gate driving unit is electrically connected to the first clock signal input terminal; the first clock signal terminal of the 3n-1th gate driving unit is electrically connected to the third first clock signal terminal; The third clock signal terminal of the 3n-stage gate driving unit is electrically connected to the third clock signal input terminal, the fourth clock signal terminal of the 3n-stage gate driving unit is electrically connected to the first clock signal input terminal, the second clock signal terminal of the 3n-stage gate driving unit is electrically connected to the second clock signal input terminal; the first clock signal terminal of the 3n-stage gate driving unit is electrically connected to the first first clock signal terminal; n is a positive integer.

18. A gate driving method, applied to the gate driving unit according to any one of claims 1 to 15, characterized in that: The gate driving method comprises: The first output circuit controls the first gate drive signal output terminal to output the first gate drive signal under the control of the potential of the first node and the potential of the second node; The first output subcircuit controls the connection between the second gate drive signal output terminal and the first clock signal terminal under the control of the potential of the first node.

19. A display device, characterized in that: Comprising the gate drive circuit as claimed in claim 16 or 17.

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