Discharge current mitigation in memory arrays

Abstract

This application relates to mitigation of discharge current in memory arrays. Access lines of the memory array can be divided into discrete segments, each segment being coupled to a driver for the access line via one or more vias corresponding to the segment. For example, a first segment of the access line may be coupled to a first group of memory cells, a second segment of the access line may be coupled to a second group of memory cells, and a driver may be coupled to the first segment via a first via and to the second segment via a second via. To access memory cells in the first or second group, the first segment and the second segment of the access line may be activated together by a common driver.

Description

[0001] Cross-referencing

[0002] This patent application is a national phase application of Wang’s National Patent Application No. PCT / US2020 / 063100, filed December 3, 2020, entitled “Discharge Current Mitigation in a Memory Array,” which claims priority to Wang’s U.S. Patent Application No. 17 / 085,154, filed October 30, 2020, entitled “Discharge Current Mitigation in a Memory Array,” and U.S. Provisional Patent Application No. 16 / 717,944, filed December 17, 2019, entitled “Discharge Current Mitigation in a Memory Array,” each of which is assigned to the assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to mitigation of discharge current in memory arrays. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, often represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states and can store any of them. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write states into the memory device or program states.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, and chalcogenide memory technology. Memory cells can be volatile or non-volatile. For example, non-volatile FeRAM can maintain its stored logic state for a long time, even without external power. Volatile DRAM devices, on the other hand, may lose their stored state when disconnected from external power. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include: a first segment of an access line coupled to a first group of memory cells; a second segment of the access line separate from the first segment and coupled to a second group of memory cells; and a driver coupled to the first segment and the second segment.

[0007] Describe a method. The method may include: receiving a command to perform an access operation on a memory cell; activating a first segment of an access line and a second segment of the access line in response to the command, the second segment being discontinuous with the first segment, wherein the first segment is coupled to a first group of memory cells including the memory cell, and wherein the second segment is coupled to a second group of memory cells not including the memory cell; and performing the access operation at least in part based on the activation in response to the command.

[0008] Describe an apparatus. The apparatus may include: a plurality of memory cells arranged in rows and columns; a plurality of word lines, each coupled to a corresponding row of the memory cells; and a plurality of bit lines, each coupled to a corresponding column of the memory cells, wherein: each word line includes a plurality of discontinuous word line segments, each word line segment being coupled to a corresponding subset of the corresponding row of the memory cells; and each bit line includes a plurality of discontinuous bit line segments, each bit line segment being coupled to a corresponding subset of the corresponding column of the memory cells. Attached Figure Description

[0009] Figure 1 This describes an example of a memory die that supports discharge current mitigation in a memory array, based on examples disclosed herein.

[0010] Figure 2 This describes an example of a memory array that supports discharge current mitigation in a memory array, based on examples disclosed herein.

[0011] Figures 3 to 5 This document describes an example of a memory architecture that supports discharge current mitigation in a memory array, based on examples disclosed herein.

[0012] Figure 6 A block diagram illustrating a memory array that supports discharge current mitigation in a memory array according to aspects of this disclosure.

[0013] Figure 7 The flowchart illustrates one or more methods for mitigating discharge current in a memory array, based on examples disclosed herein. Detailed Implementation

[0014] In some memory arrays, current discharge through memory cells can cause current “spiking” (e.g., a relatively high current discharge through a memory cell over a relatively short period of time), which can damage the memory cell. Some of these spikes may be caused by external discharges, which can refer to discharges from parasitic capacitances or other sources outside the memory array (e.g., peripheral circuitry). Alternatively, such spikes may be caused by internal discharges, which can refer to discharges from parasitic capacitances or other sources within the memory array. Current spikes caused by internal discharges can be particularly problematic because mitigation circuitry or other techniques can be more easily applied to mitigate the effects of external discharges.

[0015] For example, various voltages of a memory array can be varied to perform access operations. These voltage changes can cause charge to accumulate in the memory array, for example, in parasitic capacitances associated with the array (e.g., the parasitic capacitances of the access lines of the memory array). In some cases, the accumulated charge can be discharged through selected memory cells. For example, a memory cell can become conductive based on its selection (e.g., when access is performed, such as when the voltage across the memory cell exceeds a threshold voltage of the memory cell), which allows charge to accumulate on the access lines coupled to the memory cell to discharge through current spikes. Memory cells can degrade or wear down proportionally to the number and magnitude of current spikes experienced by the memory cell over time.

[0016] In some cases, current spikes may be higher for memory cells located close to or near the access line driver contacts (e.g., near electrical distance (ED)) compared to memory cells located far from the access line driver contacts (e.g., far ED). For example, discharge through memory cells with near ED may be more severe due to the relatively low resistance path between the memory cell and the charge that accumulates in parasitic capacitance along the entire length of the access line. This can result in a higher current flow through the memory cell when it becomes conductive (e.g., a relatively high magnitude current spike) compared to memory cells with far ED, which may be more separated from the charge that accumulates further along the access line (e.g., the charge that accumulates further along the access line on the other side of the contacts).

[0017] This document describes techniques for mitigating discharge current in memory arrays. Access lines of a memory array can be cut (slit, segmented, divided) into segments. In some cases, the overall tile size or other dimensions associated with the memory array may not be changed. Each access line can be driven by a corresponding access line driver. For segmented access lines, each segment of the access line can be coupled to the same access line driver corresponding to the access line, but to a via corresponding to the segment. In other words, the access line driver can be coupled to multiple vias, each of which corresponds to a specific segment of the access line corresponding to the driver. Such segmented access lines can reduce current discharge through the memory cells of the access lines. For example, when accessing a memory cell (e.g., via access line selection), the signal path from one segment of the access line to another segment of the access line can pass through multiple vias connecting different segments to bit line drivers, which may introduce additional length and resistance into the signal path. Therefore, the length of the signal path, the resistance of the signal path, or both can be extended, which can reduce the magnitude of current spikes through the accessed memory cell.

[0018] Originally in reference Figure 1 and 2 Features of this disclosure are described in the context of the memory dies and arrays described herein. (See references...) Figures 3 to 5 The features of this disclosure are described in the context of the memory architecture described herein. (See references...) Figure 6 and 7 The device diagrams and flowcharts related to the discharge current mitigation in the described memory array further illustrate and describe these and other features of this disclosure, and are described with reference to the device diagrams and flowcharts.

[0019] Figure 1 The example memory device 100 is described below, as shown in the examples disclosed herein. The memory device 100 may also be referred to as an electronic memory device. Figure 1This is an illustrative representation of the various components and features of the memory device 100. Therefore, it should be understood that the components and features of the memory device 100 are shown to illustrate functional interrelationships and are not necessarily their actual physical locations within the memory device 100. Figure 1 In an illustrative example, memory device 100 includes a three-dimensional (3D) memory array 102. The 3D memory array 102 includes memory cells 105 that can be programmed to store different states. In some instances, each memory cell 105 can be programmed to store one of two states represented as logic 0 and logic 1. In some instances, memory cells 105 can be configured to store one of more than two logic states. Although Figure 1 Some of the components are labeled with numerical indicators, while other corresponding components are not labeled, but they are the same or will be understood to be similar, in order to increase the visibility and clarity of the depicted features.

[0020] 3D memory array 102 may comprise two or more two-dimensional (2D) memory arrays formed on top of each other. Compared to 2D arrays, this increases the number of memory cells that can be placed or created on a single die or substrate, which in turn can reduce manufacturing costs or increase the performance of the memory device, or both. Memory array 102 may comprise two levels of memory cells 105 and can therefore be considered a 3D memory array; however, the number of levels is not limited to two, and in some cases may be one or more. Each level may be aligned or positioned such that memory cells 105 can be aligned (fully, overlapping, or substantially) with each other across each level, thereby forming a memory cell stack 145. In some cases, the memory cell stack 145 may comprise multiple memory cells 105 stacked on top of each other and sharing access lines simultaneously. In some cases, memory cells 105 may be configured to each store one data bit.

[0021] In some instances, memory cell 105 may be a self-select memory cell, a phase-change memory (PCM) cell, and / or another type of resistance- or threshold-based memory cell. Self-select memory cell 105 may contain one or more components of a certain material (e.g., a chalcogenide material), each acting as both a storage element and a cell selector (selection) element, thereby eliminating the need for a separate cell selector circuitry (which does not contribute to storage). Such components may be referred to as storage and selector components (or elements), or self-select memory components (or elements). In contrast, other types of memory cells, such as random access memory (RAM) (e.g., dynamic RAM (DRAM)) or PCM cells, may each contain a separate (dedicated) cell selector element, such as a three-terminal selector element (e.g., a transistor), to facilitate the selection or non-selection of the memory cell without contributing to the storage of any logical state.

[0022] Memory array 102 may include multiple word lines 110 (e.g., row lines) for each level (e.g., a first set of word lines at a first level labeled WLa_l to WLa_M, and a second set of word lines at a second level labeled WLb_l to WLb_M), and multiple bit lines 115 (e.g., column lines) labeled BL_1 to BL_N, where M and N depend on the array size. In some instances, each row of memory cells 105 is connected to a word line 110 and each column of memory cells 105 is connected to a bit line 115. In some cases, word lines 110 and bit lines 115 may be generally referred to as access lines because they allow access to memory cells 105. In some instances, bit lines 115 may also be referred to as digital lines 115. References to access lines, word lines, and bit lines, or the like, are interchangeable without affecting understanding or operation. Activating or selecting a word line 110 or bit line 115 may involve applying a voltage to the corresponding line. Word lines 110 and bit lines 115 may be made of conductive materials such as metals (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), metal alloys, carbon, conductive doped semiconductors or other conductive materials, alloys, compounds, etc.

[0023] Word lines 110 and bit lines 115 may be substantially perpendicular (i.e., orthogonal) to each other or otherwise intersect each other to form a memory cell array. For example... Figure 1 As shown, two memory cells 105 in the memory cell stack 145 may share a common conductive line, such as bit line 115. That is, bit line 115 may be electronically communicated with the bottom electrode of the upper memory cell 105 and the top electrode of the lower memory cell 105. Other configurations are possible, such as a third layer sharing access line 110 with the lower layer. Generally, a memory cell 105 may be located at the intersection of two conductive lines, such as word line 110 and bit line 115. This intersection may be referred to as the address of memory cell 105. A target memory cell 105 may be a memory cell 105 located at the intersection of energized word line 110 and bit line 115; that is, word line 110 and bit line 115 may be energized to read or write memory cell 105 at their intersection. Other memory cells 105 that are electronically communicated (e.g., connected) with the same word line 110 or bit line 115 may be referred to as non-target memory cells 105.

[0024] Electrodes may be coupled to memory cell 105 and word line 110 or bit line 115. The term electrode may refer to an electrical conductor and, in some cases, may serve as an electrical contact to memory cell 105. Electrodes may comprise traces, wires, conductive lines, conductive layers, etc., which provide conductive paths between elements or components of memory device 100. In some instances, memory cell 105 may include a plurality of selectable or other memory components (e.g., selectable components and storage components) connected to each other via electrodes and separated from access lines 110, 115. As described above, for selectable memory cell 105, a single component (e.g., a segment or layer of chalcogenide material within memory cell 105) may serve as a storage element (e.g., for storing or facilitating the storage of the state of memory cell 105) and as a selector element (e.g., for selecting or facilitating the selection of memory cell 105).

[0025] The electrodes within the memory cell stack 145 may each have the same material (e.g., carbon) or may have various (different) materials. In some cases, the electrodes may be made of a material different from that of the access lines. In some instances, the electrodes may shield the word line 110, the bit line 115, or another memory component with a material contained in the select or other memory components (e.g., a chalcogenide material) to prevent chemical interactions between the material and the word line 110, the bit line 115, or another memory component.

[0026] Operations such as reading and writing can be performed on memory cell 105 by activating or selecting the corresponding word line 110 and bit line 115. Access to memory cell 105 can be controlled by row decoder 120 and column decoder 130. For example, row decoder 120 may receive a row address from memory controller 140 and activate the appropriate word line 110 based on the received row address. This process may be referred to as decoding a row or word line address. Similarly, column decoder 130 may receive a column address from memory controller 140 and activate the appropriate bit line 115. This process may be referred to as decoding a column or bit line address. For example, row decoder 120 and / or column decoder 130 may be instances of decoders implemented using decoder circuitry. In some cases, row decoder 120 and / or column decoder 130 may include charge pump circuitry configured to increase the voltage applied to word line 110 or bit line 115 (respectively).

[0027] When accessing memory cell 105 (e.g., in cooperation with memory controller 140, row decoder 120, and / or column decoder 130) to determine the logical state stored in memory cell 105, memory cell 105 may be read (e.g., sensed) by sensing component 125. Sensing component 125 may provide an output signal indicating (e.g., at least in part based on) the logical state stored in memory cell 105 to one or more components (e.g., column decoder 130, input / output component 135, memory controller 140). In some instances, the detected logical state may be provided to a host device (e.g., a device using memory device 100 for data storage, a processor coupled to memory device 100 in an embedded application), wherein this signaling may be provided directly from input / output component 135 or via memory controller 140.

[0028] In some instances, memory controller 140 may control access to memory cell 105 via various components (e.g., row decoder 120, column decoder 130, sensing component 125). In some instances, one or more of row decoder 120, column decoder 130, and sensing component 125 may be located in the same location as memory controller 140. Memory controller 140 may be used to receive one or more commands or data from one or more different memory controllers (e.g., an external memory controller associated with a host device, another controller associated with memory device 100), transform the commands or data (or both) into information usable by memory device 100, perform one or more operations on memory device 100, and transfer data from memory device 100 to a host device (not shown) based on the performance of one or more operations. Memory controller 140 may generate row signals and column address signals to activate target word line 110 and target digital line 115. Memory controller 140 may also generate and control various voltages or currents used during operation of memory device 100. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may vary and may differ for the various operations discussed when operating the memory device 100.

[0029] In some instances, a host device (not shown) may communicate with memory controller 140. For example, memory controller 140 may receive commands from the host device and may perform one or more operations on memory device 100. Such operations may include performing access operations based on received commands. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. Memory controller 140 may be used to perform other access operations not listed herein or other operations related to the operation of memory device 100 that are not directly related to accessing memory cell 105.

[0030] Sensing component 125 may include various transistors or amplifiers for detecting and amplifying signal differences (also known as latching). The detected logic state of the output memory unit 105 may then be output as output 135 via column decoder 130. In some cases, sensing component 125 may be part of column decoder 130 or row decoder 120. Alternatively, sensing component 125 may be connected to or in electronic communication with column decoder 130 or row decoder 120. Those skilled in the art will appreciate that sensing components can be associated with column decoders or row decoders without losing their functional purpose.

[0031] In some memory architectures, accessing memory cell 105 can degrade or destroy the logic state stored in one or more memory cells 105, and a rewrite or refresh operation can be performed to transfer the original logic state back to memory cell 105. In architectures that include a material portion for logic storage, for example, a sensing operation can change the atomic configuration or distribution of memory cell 105, thus altering the resistance or threshold characteristics of memory cell 105. Therefore, in some instances, the logic state stored in memory cell 105 can be rewritten after an access operation.

[0032] In some instances, reading memory cell 105 may be non-destructive. That is, after reading memory cell 105, it may not be necessary to rewrite the logic state of memory cell 105. For example, in an architecture that includes a material portion for logic storage, sensing memory cell 105 may not destroy the logic state, and therefore, memory cell 105 may not need to be rewritten after an access. However, in some instances, refreshing the logic state of memory cell 105 may or may not be necessary in the absence of or presence of other access operations. For example, the logic state stored in memory cell 105 can be refreshed periodically by applying appropriate write or refresh pulses or bias voltages to maintain the stored logic state. Refreshing memory cell 105 can reduce or eliminate read interference errors or logic state corruption.

[0033] Although the sides of memory array 102 are shown for clarity, row decoder 120 and column decoder 130 may, in some cases, be located below memory array 102. Each decoder 120, 130 may include or be coupled to one or more drivers configured to drive access lines 110, 115 to a desired voltage (e.g., to access one or more associated memory cells 105). As an example, each of word lines WLa_l to WLa_M may be coupled to a corresponding driver from a first set of drivers associated with row decoder 120, and each of word lines WLb_l to WLb_M may be coupled to a corresponding driver from a second set of drivers associated with row decoder 120, but other configurations are possible. In some cases, drivers may be distributed across the entire area under memory array 102. Vias may extend through one or more layers or levels of memory device 100 to couple drivers to their corresponding access lines 110, 115. For example, if access lines 110 and 115 are considered to extend in a horizontal direction (e.g., the x or y direction), vias may extend in a vertical (z) direction. In some cases, one or more layers between the driver and the access lines may contain metallic wiring, which may be referred to as interconnect layers or collectively as interconnect layers, wherein the driver may be coupled to the corresponding line in the interconnect layer and vias may extend between the interconnect layer and the layer containing access lines 110 and 115.

[0034] In some instances, the voltage within memory device 100 may be altered as part of one or more memory operations (e.g., access operations). For example, components of memory device 100 (e.g., memory controller 140, row decoder 120, and column decoder 130, or associated drivers) may increase or decrease the voltage of word lines 110 and digital lines 115 relative to each other to access (e.g., read or write) memory cells 105. As the voltage within memory device 100 changes, charge may accumulate within the memory array (e.g., charge may be stored in the parasitic capacitances of word lines 110 and digital lines 115). When memory cell 105 becomes conductive (e.g., because the voltage across memory cell 105 exceeds a threshold voltage of the memory cell, such as during an access operation of memory cell 105), the charge stored in the parasitic capacitances of word lines 110 or digital lines 115 coupled to memory cell 105 may discharge through memory cell 105, thereby generating a current spike through memory cell 105. The memory cell 105 may deteriorate or wear out in proportion to the number and magnitude of the current spikes experienced by the memory cell.

[0035] According to some examples described herein, access lines of a memory array can be segmented. For example, word line 110 and / or digital line 115 may each comprise two or more segments. Each segment of the access line may be coupled to an access line driver using at least one corresponding via; for example, a first segment may be coupled to a driver via a first via, and a second segment may be coupled to a driver via a second via, etc. Such segmentation can mitigate current discharge through memory cells 105 of the access lines. For example, when accessing memory cell 105 (e.g., during write operations, read operations, refresh operations, etc.), the signal path (i.e., discharge path) from one segment of the access line to another segment of the access line may be routed through vias that connect each segment to an interconnect layer (e.g., conductive lines or other structures associated with the array). This configuration can create a resistive ballast, which may mitigate current spikes (e.g., increase the amount of time current is dissipated from the parasitic capacitance of the access line), partly due to the relatively long length and relatively high resistance of the discharge path through memory cell 105. For example, when accessing a memory cell associated with a segment of an access line, the charge accumulated along different segments of the access line may have to traverse a longer and more resistive signal path, which may reduce its contribution to the current spikes passing through the accessed memory cell.

[0036] Figure 2 This describes an example of a memory array 200 as disclosed herein. The memory array 200 may be used as a reference. Figure 1 An example of a portion of the described memory die. Memory array 200 may include a first layer 205 of memory cells positioned above a substrate and a second layer 210 of memory cells on top of the first array or layer 205. While an example of memory array 200 may include two layers 205, 210, memory array 200 may include any number of layers (e.g., one or more than two).

[0037] The memory array 200 may also include row lines 110-a, 110-b, 110-c, 110-d, column lines 115-a and 115-b, which may be as shown in the reference. Figure 1 Examples of the described word line 110 and digital line 115. One or more memory cells of the first layer 205 and the second layer 210 may be contained in one or more chalcogenide materials in the struts between the access lines. For example, a single stack between the access lines may contain one or more of a first electrode, a first chalcogenide material (e.g., a selector assembly), a second electrode, a second chalcogenide material (e.g., a memory element), or a third electrode. In some cases, the chalcogenide material may be configured to provide both select and storage functionality, and the component containing this chalcogenide material may be referred to as selector. Although Figure 2Some of the components are labeled with numerical indicators, while other corresponding components are not labeled, but they are the same or will be understood to be similar, in order to increase the visibility and clarity of the depicted features.

[0038] The memory cells of the first layer 205 may each include one or more of electrode 225-a, memory element 220-a, or electrode 225-b. The memory cells of the second layer 210 may each include one or more of electrode 225-c, memory element 220-b, and electrode 225-d. The memory element 220 may each be an example of an element containing a chalcogenide material, such as a phase-change memory element or a self-selecting memory element. In some embodiments, the memory cells of the first layer 205 and the second layer 210 may have a common conductive line, such that corresponding memory cells of one or more layers 205 and one or more layers 210 may share column line 115 or row line 110. For example, the first electrode 225-c of the second layer 210 and the second electrode 225-b of the first layer 205 may be coupled to column line 115-a, such that column line 115-a may be shared by vertically adjacent memory cells.

[0039] In some instances, the material of the memory element 220 may comprise a chalcogenide material or other alloy, such as a material comprising selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In), gallium (Ga), palladium (Pd), sulfur (S), or various combinations thereof. In some instances, the material of the memory element 220 may be a chalcogenide glass and may contain additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular form. It should be understood that these are merely examples and the claims are not limited thereto.

[0040] In some instances, storage element 220 may be an example of a phase-change memory element. In such instances, the material used in storage element 220 may be based on an alloy (such as those listed above) and operable to undergo a phase transition or change of physical state during normal operation of the memory cell. For example, a phase-change memory cell may switch between an amorphous state and a crystalline state (or between one or more relatively amorphous states and one or more relatively crystalline states).

[0041] Phase change memory cells can exhibit observable differences in resistance or threshold voltage between crystalline and amorphous states in phase change materials (which can be chalcogenide materials). Crystalline materials can have atoms arranged in a periodic structure, which can produce relatively low resistance or threshold voltage. In contrast, amorphous materials, which have little or no periodic atomic structure, can have relatively high resistance or threshold voltage.

[0042] The difference in resistance or threshold voltage between the amorphous and crystalline states of a material can be significant. For example, a material in its amorphous state may have a resistance one or more orders of magnitude greater than that of a material in its crystalline state. In some instances, the material may be partially amorphous and partially crystalline, and the resistance or threshold voltage may be somewhere between the resistance or threshold voltage of a material in its fully crystalline or fully amorphous state. In such instances, the material can be used to store more than two logic states (e.g., three or more logic states).

[0043] During programming (writing) operations of a phase-change memory cell (e.g., electrode 225-a, memory element 220-a, electrode 225-b), various parameters of the programming pulse can influence (e.g., determine, set, program) specific behavior or properties of the material of memory element 220, such as the threshold voltage or resistance of the material. To program a low-resistance or low-threshold-voltage state (e.g., a relatively crystalline state) in the phase-change memory cell, a programming pulse can be applied to heat or melt the material of memory element 220, which may be associated with at least temporarily forming a relatively disordered (e.g., amorphous) atomic arrangement. The amplitude of the programming pulse can decrease over a period of time (e.g., relatively slowly) to allow the material to form a crystalline structure as it cools, thereby forming a stable crystalline material state. To program a high-resistance or high-threshold-voltage state (e.g., a relatively amorphous state) in the phase-change memory cell, a programming pulse can be applied to heat and / or melt the material of memory element 220. For low-resistance or low-threshold-voltage states, the amplitude of the programming pulse can decrease more rapidly than the programming pulse. In such cases, the material may cool along with the atoms in a more disordered atomic arrangement because the atoms cannot form a crystalline structure before the material reaches a stable state, thus forming a stable amorphous material state. The difference in threshold voltage or resistance of the material of storage element 220 depends on the logic state stored in the material of storage element 220, and this difference may correspond to the read window of storage element 220. In some cases, portions of the storage element may undergo material changes associated with the logic state.

[0044] In some instances, such as for a self-selecting memory cell, some or all of the set of logic states supported by the memory cell may be associated with an amorphous state of a chalcogenide material (e.g., the material can be used to store different logic states without changing the phase). For example, both logic state '0' and logic state '1' may be associated with an amorphous state of a chalcogenide material. In some instances, memory element 220 may be an example of a self-selecting memory cell. In such instances, the material used in memory element 220 may be an alloy (e.g., alloys listed above) and operable so as not to undergo a phase transition during normal operation of the memory cell (e.g., not to undergo a change between a relatively crystalline state and a relatively amorphous state). For example, the material of memory element 220 may contain a chemical element such as arsenic, which prevents the chalcogenide material from changing states and thus can be maintained in a single state (e.g., an amorphous state or a crystalline state).

[0045] During a programming (writing) operation of a self-selected memory cell (e.g., including electrode 225-a, memory element 220-a, and electrode 225-b), the polarity of the write operation can affect (determine, set, program) the specific behavior or characteristics of the material of memory element 220, such as the threshold voltage of the material when reading with a given polarity (e.g., when reading with the same polarity as the write voltage versus when reading with a different polarity). The observed difference in threshold voltages of the material of memory element 220 depends on the logic state stored by the material of memory element 220 (e.g., the difference between the threshold voltages when the material is storing logic state '0' versus logic state '1'), which may correspond to the read window of memory element 220.

[0046] In some instances, the architecture of memory array 200 may be referred to as a crosspoint architecture, wherein memory cells are formed at topological intersections between row lines 110 and column lines 115. For example, in addition to other instances of memory types in which a crosspoint architecture can be used, the architecture of memory array 200 may be referred to as or an example of an aspect of a resistive RAM (RRAM) crosspoint memory array or a ferroelectric RAM (FeRAM) crosspoint memory array. This crosspoint architecture can provide relatively high-density data storage with lower manufacturing costs compared to at least some other memory architectures. For example, a crosspoint architecture may have memory cells with a reduced area and thus increased memory cell density compared to other architectures. For example, the architecture may have a 4F2 memory cell area compared to other architectures with a 6F2 memory cell area (e.g., those with three-terminal selector elements), where F is the minimum feature size. For example, DRAM may use transistors, which are three-terminal devices, as selector elements for each memory cell and may have a larger memory cell area compared to a crosspoint architecture. Alternatively, DRAM memory cells may include cell selector elements below the memory cell.

[0047] Although Figure 2 The examples illustrate two memory layers, but other configurations are possible. In some instances, a single memory layer of memory cells can be constructed above the substrate, which may be referred to as a two-dimensional memory. In some instances, two or more layers of memory cells can be configured in a similar manner in a three-dimensional intersection architecture. Furthermore, in some cases, Figure 2 As shown or referenced Figure 2 The described elements may be electrically coupled to each other as shown or described, but physically rearranged (e.g., storage element 220 and possibly selection element or electrode 225 may be electrically connected in series between row line 110 and column line 115, but do not need to be in a strut or stack configuration).

[0048] In some instances, the voltages of different components within memory array 200 may be altered as part of one or more memory operations (e.g., access operations). In such instances, charge may accumulate within memory array 200 (e.g., parasitic capacitances on word line 110 and digital line 115 may accumulate charge). This charge may generate current spikes through one or more memory cells (e.g., contained within memory layer 210 and / or memory layer 205), which can cause damage to the memory cells. For example, a memory cell may be selectively made conductive, allowing any accumulated charge on the access line to discharge through the memory cell in the current spike. Current spikes can lead to degradation or wear of the memory cells.

[0049] Based on some examples described herein, a memory array may contain access lines, each divided into discrete segments. For example, word line 110 and / or digital line 115 may each contain two or more segments. Each segment of an access line may be coupled to the same access line driver (the driver for the access line) but through different vias. Thus, all segments of the access line can be driven together (simultaneously) but through different interconnects with a common driver (e.g., to increase or decrease their voltage).

[0050] Such segmented access lines can mitigate current discharge through memory cells. For example, when accessing a memory cell coupled to one segment of the access line (e.g., memory element 220 becomes conductive based on selecting the memory cell using word line 110 and digital line 115), current discharge from parasitic capacitances associated with any other segment of the access line can follow an improved signal path before discharging through the accessed memory cell. The improved signal path may include a path from another segment of the access line through at least one via or conductive line (e.g., conductive line in an interconnect layer) to the segment coupled to the accessed cell. This configuration can create a resistive ballast, which mitigates current spikes, partly due to the relatively long length and relatively high resistance of the signal path to the memory cell.

[0051] Figure 3 This describes an example of a memory architecture 300 that supports discharge current mitigation in a memory array, as disclosed herein. In some cases, memory architecture 300 may be implemented as described in the references. Figure 1 The described memory device 100 and / or as referenced Figure 2 One or more features of the described memory array 200. Memory architecture 300 may show a cross-sectional schematic of a portion of the memory array supporting discharge current mitigation as described herein.

[0052] The memory architecture 300 can contain any number of memory cells 305 (although for clarity, in...) Figure 3 Only one is shown in the text, which can be as shown in the reference. Figure 1 and 2 An example of the described memory cell 105. Memory cell 305-a may be referred to as a target memory cell (e.g., when memory cell 305-a is selected as part of an access operation). Target memory cell 305-a and any number of other memory cells 305 may be coupled to access lines 307. For example, access lines 307 may be word lines or bit lines as described herein. Target memory cell 305-a may also be coupled to at least one other access line (not shown), but for clarity... Figure 3 Only one access line 307 is shown in the image.

[0053] As described herein, memory architecture 300 can be configured to mitigate current spikes that may degrade or damage memory cell 305. For example, internal charge may accumulate on access lines coupled to target memory cell 305-a (e.g., parasitic capacitance of access line 307 may accumulate stored charge). In some instances, the accumulated charge may discharge through memory cell 305-a (e.g., when memory cell 305-a is selected and becomes conductive as part of an access operation), which can generate relatively high current spikes that may damage memory cell 305-a.

[0054] Therefore, the memory architecture 300 can be configured to mitigate current spikes through memory cells 305. For example, access lines 307 can be segmented into one or more segments 310 (e.g., segments 310-a and 310-b, or any number of segments 310). For example, during the formation of the memory array, processing steps (e.g., chopping masks) can be used to generate interrupts in access lines 307 (e.g., to cut out one or more gaps 335 and form segments 310). Each segment 310 can be associated with (e.g., coupled to) one or more memory cells 305. In some instances, access lines 307 can be associated with physical addresses within the memory array, such as row or column addresses, and segments 310 may not be individually addressed, but alternatively, each can be accessed based on the address of access line 307, such that an access operation to any memory cell 305 on the access line will address all segments 310 of the access line.

[0055] Segment 310 may each be coupled to one or more corresponding vias 315. For example, segment 310-a may be coupled to via 315-a and segment 310-b may be coupled to via 315-b. In some instances, vias 315 may extend in a direction different from the access lines. For example, vias 315 may extend through a layer or plane of the memory device, which for clarity may be referred to as the vertical direction (or z-direction), and access lines (e.g., word lines 110 and digital lines 115) may extend horizontally (e.g., in the x or y direction) within the respective layers or planes of the memory device. Vias 315 may be used to carry signals (e.g., signals from driver 330) through and through the access lines. Although Figure 3 The example illustrates each segment 310 as coupled to a corresponding via 315, but other configurations are possible (e.g., multiple vias 315 coupled to each segment 310, among other examples). Furthermore, the position of the vias 315 can be changed. For example, although... Figure 3The via 315-a contacts segment 310-a near the right end of segment 310-a and the via 315-b contacts segment 310-b near the left end of segment 310-b. Thus, each via 315 contacts access line 307 relatively near the midpoint of access line 307, but the via 315 can be coupled to segment 310 at any position along segment 310.

[0056] In some cases, one or more layers between access line 307 and the driver 330 for access line 307 may contain conductive (e.g., metallic) wiring, which may be referred to as interconnect layers or collectively as interconnect layers 320. Interconnect layers can be used to route signals from components below the memory array to components within the memory array, such that the driver 330 is not necessarily located directly below access line 307. In some cases, the wiring within interconnect layer 320 may extend in a direction parallel to access line 307 (e.g., in a horizontal direction). In some cases, via 315 may couple segment 310 to one or more wirings within interconnect layer 320, and the output of the driver 330 for access line may also be coupled to one or more wirings within interconnect layer 320 (that is, via 315 may couple to the output of driver 330 through one or more wirings within interconnect layer 320).

[0057] Although described as a single transistor for clarity, driver 330 can be any circuit system configured to drive a line to a desired voltage and can contain any number of transistors or other circuit system components. In some cases, driver 330 may be coupled to or included in a corresponding decoder (e.g., row decoder 120 or column decoder 130). Driver 330 can drive access line segment 310 to a desired voltage using layer 320 and corresponding via 315 (e.g., via 315-a can electrically connect voltage or current from driver 330 to access line segment 310-a). Driver 330 can be configured to apply current and / or voltage to the access lines of memory cells as part of an access operation (e.g., a memory device of memory controller 140 can operate driver 330 to select word line 110 or digital line 115 by applying current and voltage). In some instances, driver 330 may be an example of a word line driver or a bit line driver. Furthermore, although described as being below layer 320 (e.g., below the layer), in some cases, the driver 330 may be located within or around the elements of the memory architecture 300 in various other physical configurations.

[0058] The memory architecture 300 may include a gap 335 between segments 310-a and 310-b. The gap 335 may be filled with a material such as a non-conductive material (e.g., a dielectric material) or another suitable material (e.g., an electrically insulating material) to at least partially prevent current discharge from flowing directly from segment 310-b to segment 310-a. Alternatively, the gap 335 may be an unfilled space between segments 310-a and 310-b. As discussed herein, any number of masking or etching processes may be used, such as using a chopper mask to form the gap 335 during the formation of the memory array. In some instances, the gap may not be located in the middle of the illustrated access lines 307 (e.g., such that segments 310-a and 310-b are of equal length), and may instead be placed elsewhere in the memory architecture 300 (e.g., such that segments 310-a and 310-b are of different lengths).

[0059] In the example schematic illustrated by memory architecture 300, charge associated with a current spike through target memory cell 305-a (e.g., due to threshold processing of target memory cell 305-a) can flow through discharge path 325, which can mitigate (e.g., reduce) the magnitude of the current spike through memory cell 305-a. For example, internal charge that can accumulate on access line 307 can follow discharge path 325 to discharge through target memory cell 305-a to another access line coupled to target memory cell 305-a. If access line 307 is a word line, the other access line (not shown) can be, for example, a bit line, or if access line 307 is a bit line, the other access line can be a word line.

[0060] Discharge path 325-a illustrates the path taken by the charge distributed on segment 310-a of the access line before passing through memory cell 305-a. Discharge path 325-b illustrates the path taken by the charge distributed on segment 310-b (i.e., the segment not directly coupled to memory cell 305-a) before passing through memory cell 305-a. Before current discharges through memory cell 305-a, discharge path 325-b can be routed through via 315-b, layer 320, via 315-a, and then through segment 310-a. The additional electrical discharge (ED) and resistance introduced by via 315-b, interconnect layer 320, and via 315-b can mitigate (reduce) the contribution of the charge associated with segment 310-b to the discharge current through memory cell 305-a.

[0061] In some instances, the resistivity of via 315 may be different from (e.g., higher than) the resistivity of the access lines (e.g., the resistivity of segments 310-a and 310-b). For example, via 315 may be made of one or more materials different from the access lines, and via 315 may have different physical properties (e.g., physical dimensions, such as cross-sectional area), or both.

[0062] Discharge path 325-b may incorporate a resistive ballast including via 315 and layer 320. That is, due to the relatively long length of discharge path 325-b and its corresponding resistance (e.g., rather than charge flowing directly from segment 310-b to segment 310-a), current spikes through memory cell 305-a are reduced because some charge dissipates and / or discharges more slowly through memory cell 305-a (e.g., resulting in a reduced current discharge amplitude). By reducing the amplitude of the current discharged through memory cell 305-a when accessing memory cell 305-a (e.g., peak amplitude, average amplitude), in addition to other benefits available to those skilled in the art, the lifespan of memory cell 305-a is extended and the likelihood of damage to memory cell 305-a is reduced.

[0063] Figure 4 This describes an example of a memory architecture 400 that supports discharge current mitigation in a memory array, as disclosed herein. In some cases, memory architecture 400 may be implemented as described in the references. Figure 1 The described memory device 100, as referenced Figure 2 The described memory array 200 or as referenced Figure 3 One or more features of the described memory architecture 300. Memory architecture 400 may show an example of a cross-sectional schematic diagram of a portion of a memory array that supports discharge current mitigation as described herein.

[0064] The memory architecture 400 may contain any number of memory cells 405 (although for clarity, in...) Figure 4 Only one is shown in the text, which can be as shown in the reference. Figure 1 An example of the described memory cell 105. Memory cell 405-a may be referred to as a target memory cell (e.g., when memory cell 405-a is selected as part of an access operation). Target memory cell 405-a and any number of other memory cells 405 may be coupled to access lines 407. For example, access lines 407 may be word lines or bit lines as described herein. Target memory cell 405-a may also be coupled to at least one other access line (not shown), but for clarity... Figure 4 Only one access line, 407, is shown in the image.

[0065] As described herein, memory architecture 400 can be configured to mitigate current spikes that may degrade or damage memory cell 405. For example, internal charge may accumulate on access lines coupled to target memory cell 405-a (e.g., parasitic capacitance of access line 407 may accumulate stored charge). In some instances, the accumulated charge may discharge through memory cell 405-a (e.g., when memory cell 405-a is selected and becomes conductive as part of an access operation), which can generate relatively high current spikes that may damage memory cell 405-a.

[0066] Therefore, the memory architecture 400 can be configured to mitigate current spikes through memory cells 405. For example, access lines 407 can be segmented into one or more segments 410 (e.g., segments 410-a and 410-b, or any number of segments 410). For example, during the formation of the memory array, processing steps (e.g., chopping masks) can be used to generate interrupts in access lines 407 (e.g., to cut out one or more gaps 435 and form segments 410). Each segment 410 can be associated with (e.g., coupled to) one or more memory cells 405. In some instances, access lines 407 can be associated with physical addresses within the memory array, such as row or column addresses, and segments 410 may not be individually addressed, but alternatively, each can be accessed based on the address of access line 407, such that an access operation to any memory cell 405 on the access line will address all segments 410 of the access line.

[0067] Segment 410 may each be coupled to one or more corresponding vias 415. For example, segment 410-a may be coupled to via 415-a and segment 410-b may be coupled to via 415-b. In some instances, vias 415 may extend in a direction different from that of the access lines. For example, via 415 may extend through a layer or plane of the memory device, which for clarity may be referred to as the vertical direction (or z-direction), and access lines (e.g., word lines 110 and digital lines 115) may extend horizontally (e.g., in the x or y direction) within the respective layer or plane of the memory device. Vias 415 may be used to carry signals (e.g., signals from a driver) through the access lines. Although Figure 4 The example illustrates each segment 410 as coupled to a corresponding via 415, but other configurations are possible (e.g., multiple vias 415 coupled to each segment 410, among other instances). Furthermore, the position of the via 415 can be changed. For example, although... Figure 4The via 415-a contacts segment 410-a near the right end of segment 410-a and the via 415-b contacts segment 410-b near the left end of segment 410-b. Thus, each via 415 contacts access line 407 relatively near the midpoint of access line 407, but the via 415 can be coupled to segment 410 at any position along segment 410.

[0068] Memory architecture 400 may include a gap 435 between segments 410-a and 410-b. Gap 435 may be filled with a material such as a non-conductive material (e.g., a dielectric material) or another suitable material (e.g., an electrically insulating material) to at least partially prevent current discharge from flowing directly from segment 410-b to segment 410-a. Alternatively, gap 435 may be an unfilled space between segments 410-a and 410-b. As discussed herein, any number of masking or etching processes may be used, such as using a chopper mask during the formation of the memory array, to form gap 435. In some instances, the gap may not be located in the middle of the illustrated access lines 407 (e.g., such that segments 410-a and 410-b are of equal length), and may instead be placed elsewhere in memory architecture 400 (e.g., such that segments 410-a and 410-b are of different lengths).

[0069] In some cases, one or more layers between access line 407 and the driver for access line 407 may contain one or more conductive (e.g., metallic) wirings, which may be referred to as interconnect layers or conductive layers. In memory architecture 400, an interconnect layer may contain interconnect layer segments 420, which may be instances of conductive lines (e.g., interconnect layer segment 420-a may be an instance of a first conductive line and interconnect layer segment 420-b may be an instance of a second conductive line). Interconnect layer segments 420 may be contained within interconnect layers 320 as described elsewhere herein. For example, interconnect layer 320 may contain a set of corresponding interconnect layer segments 420 for each access line 407. For example, for access line 407, the set of corresponding interconnect layer segments 420 may contain a corresponding interconnect layer segment 420 for each segment 410 of access line 407, wherein each segment 410 is coupled to the corresponding interconnect layer segment 420 for the segment via one or more vias 415.

[0070] In some cases, the interconnect layer segments 420 of the corresponding set of interconnect layer segments 420 for access line 407 may each be collinear. In some instances, interconnect layer segments 420 may be lower than segment 410 (e.g., interconnect layer segments 420 may be between the substrate and segment 410, wherein, among other instances, interconnect layer segments 420 may be relatively closer to the substrate than segment 410). The interconnect layer segments 420 for access line 407 may or may not be directly below segment 410 of the access line (e.g., via 415 may include or be coupled to one or more structures extending in the horizontal direction, such that the interconnect layer segment 420 coupled to segment 410 is not necessarily directly below segment 410).

[0071] In some instances, the memory device may comprise different layers containing metal or other conductive lines, and metal lines having the same or different layers may extend in different directions. Interconnections between structures at one level of the device (e.g., the level containing transistor 430) and structures at another level of the device (e.g., access line 407) may be coupled to each other via interconnects extending in different directions. Thus, one or more interconnect layer segments 420 may extend in a direction parallel to access line 407 (e.g., in a horizontal direction), and additionally or alternatively, one or more interconnect layer segments 420 may extend in a direction orthogonal to access line 407 (e.g., in different horizontal directions).

[0072] As described in this article, refer to Figure 3 For example, the driver for access line 407 can be any circuit system configured to drive the line to a desired voltage and can include any number of transistors 430 or other circuit system components. In some cases, the driver may be coupled to or included in a corresponding decoder (e.g., row decoder 120 or column decoder 130). The driver can drive access line segment 410 to a desired voltage using interconnect layer segment 420 and corresponding via 415 (e.g., via 415-a and interconnect layer segment 420-a can electrically connect voltage or current from the driver to access line segment 410-a). The driver can be configured to apply current and / or voltage to the access lines of memory cells as part of an access operation (e.g., a memory device of memory controller 140 can operate the driver to select word line 110 or digital line 115 by applying current and voltage). In some instances, the driver may be an example of a word line driver or a bit line driver. Furthermore, although discussed herein as being below interconnect layer segment 420, in some cases the driver may be located within or around the elements of memory architecture 400 in various other physical configurations.

[0073] In some cases, the driver may include at least one transistor 430 for each access line segment 410 of access line 407 (e.g., coupled thereto). Alternatively, the driver may include at least one transistor 430 for each interconnect layer segment 420 (e.g., coupled thereto). For example, such as... Figure 4 As shown, the driver may include a first transistor 430-a coupled to first interconnect layer segments 420-a and 410-a, and a second transistor 430-b coupled to second interconnect layer segments 420-b and 410-b. Each transistor 430 of the driver for access line 407 may include a corresponding gate coupled to a common select signal 440 (e.g., an LSEL signal may be coupled to the gates of both transistors 430-a and 430-b). The common select signal 440 may be used to simultaneously activate or deactivate transistors 430 to drive segment 410 of access line 407 to a common voltage. Although in some cases transistors 430 may be part of the driver for access line 407, transistors 430 may alternatively be coupled to a separate driver circuit, and transistors may be used to selectively couple and decouple interconnect layer segments 420 (and therefore segment 410) from the driver. When an address corresponding to access line 407 is associated with an access operation (e.g., for memory cell 405-a), transistor 430 coupled to the access line may be activated simultaneously (e.g., based on common select signal 440). For example, as described elsewhere herein, segment 410 of the access line may not be addressed separately, but may instead be activated or deactivated simultaneously based on a command or operation addressing access line 407.

[0074] In the example schematic illustrated by memory architecture 400, charge associated with a current spike through target memory cell 405-a (e.g., due to threshold processing of target memory cell 405-a) can flow through discharge path 425, which can mitigate (e.g., reduce) the magnitude of the current spike through memory cell 405-a. For example, internal charge that can accumulate on access line 407 can follow discharge path 425 to discharge through target memory cell 405-a to another access line coupled to target memory cell 405-a. If access line 407 is a word line, then the other access line (not shown) can be, for example, a bit line, or if access line 407 is a bit line, then the other access line can be a word line.

[0075] Discharge path 425-a illustrates the path taken by the charge distributed on segment 410-a of the access line before passing through memory cell 405-a. Discharge path 425-b illustrates the path taken by the charge distributed on segment 410-b (i.e., the segment not directly coupled to memory cell 405-a) before passing through memory cell 405-a.

[0076] As illustrated in memory architecture 400, before current discharges through memory cell 405-a, discharge path 425-b can be routed from segment 410-b through via 415-b, interconnect layer segment 420-b, transistor 430-b, transistor 430-a, interconnect layer segment 420-a, via 415-a, and then through segment 410-a. The additional ED and resistance introduced by via 415, interconnect layer segment 420, and transistor 430 can mitigate (e.g., reduce) the effect of charge associated with segment 410-b on the discharge current through memory cell 405-a. In some cases, the resistance of transistor 430 can be configured by common selection signal 440 (e.g., transistor 430 can be activated to a greater or lesser extent, and thus exhibit higher or lower resistance based on whether the voltage of common selection signal 440 is higher or lower).

[0077] In some instances, the resistivity of via 415 may be different from (e.g., higher than) the resistivity of access line 407 (e.g., the resistivity of segments 410-a and 410-b). For example, via 415 may be made of one or more materials different from the access line, and via 415 may have different physical properties (e.g., physical dimensions, such as cross-sectional area), or both.

[0078] The discharge path 425-b may incorporate a resistive ballast comprising vias 415 and interconnect segments 420. For example, two vias 415, two interconnect segments 420, two transistors 430, or any combination thereof, may act as a relatively robust resistive ballast to reduce current spikes across memory cell 405-a. That is, due to the relatively long length of the discharge path 425-b and the corresponding resistance (e.g., rather than charge flowing directly from segment 410-b to segment 410-a), current spikes through memory cell 405-a are reduced because some charge dissipates and / or discharges more slowly through memory cell 405-a (e.g., resulting in a reduced current discharge amplitude). By reducing the amplitude (e.g., peak amplitude, average amplitude) of the current discharging through memory cell 405-a when memory cell 405-a is accessed, in addition to other benefits available to those skilled in the art, the lifetime of memory cell 405-a is extended and the likelihood of damage to memory cell 405-a is reduced.

[0079] Figure 5 This describes an example of a memory architecture 500 that supports discharge current mitigation in a memory array, as disclosed herein. In some cases, memory architecture 500 may be implemented as described in the references. Figure 1 The described memory device 100, as referenced Figure 2The memory array 200 described, as referenced Figure 3 The memory architecture 300 described, or as referenced Figure 4 The memory architecture 400 described includes one or more features. The memory architecture 500 can be illustrated as a top-down schematic of a memory array supporting discharge current mitigation as described herein.

[0080] The memory architecture 500 may include access lines such as word lines and bit lines, which may be as described in reference to [references to other architectures]. Figure 1 and 2 Examples of word line 110 and digital line 115 are described. Memory architecture 500 may include any number of access lines. As described herein, access lines can be segmented (e.g., using, as referenced). Figure 3 (The described chopper mask). For example, word line segments 505-a and 505-b can illustrate two segments of the same word line that have been cut (e.g., indicated by alignment (e.g., collinear, coaxial) of word line segments 505-a and 505-b). Word line segments 505-a and 505-b can be separated by gap 520-a. Similarly, bit line segments 510-a and 510-b can illustrate a bit line that has been cut into segments, wherein the segments are separated by gap 520-b. In some instances, each word line or bit line can be cut into any number of segments, and the segments of the same access line can be of equal or unequal length.

[0081] For reference Figure 3 and Figure 4 As discussed, at least one corresponding via can couple each access line segment to a driver structure for the associated access line, wherein the driver structure is common to all segments of the access line (e.g., via 315 can couple each access line segment 310 to layer 320, which in turn can couple the segments to, as referenced). Figure 3 The described driver 330; or at least one corresponding via 415, at least one corresponding layer segment 420, or both, can couple each access line segment 410 to a component contained in, as referenced Figure 4 At least one corresponding transistor 430 in or coupled to the described driver.

[0082] For example, each access line can be cut into segments (e.g., two segments) and each segment can have a driver contact 515. The driver contact 515 can indicate the location where the through-hole contacts the access line segment (e.g., near the end of the segment and therefore near the midpoint of the access line, but other locations are also possible, such as near the midpoint of the segment).

[0083] The memory architecture 500 can be configured to mitigate current discharge (e.g., current spikes) of memory cells coupled during access lines. For example, the memory device can receive commands (e.g., from a host device) to respond to current discharges coupled to memory cells during access lines. Figure 5 At least one memory cell, one of the word lines and one of the bit lines described, performs an access operation. The memory controller of the memory device can receive commands and use a driver structure to apply or adjust the voltage of the access line corresponding to the memory cell. This voltage adjustment can be part of an access operation, such as reading or writing to a selected memory cell. When adjusting the voltage of the access line coupled to the selected memory cell, the corresponding voltage of each segment of the access line can increase or decrease simultaneously because each segment is coupled to the same driver (the driver for the access line).

[0084] A driver structure can apply voltage or current to activate access lines coupled to a target memory cell (e.g., activate multiple segments of the access line). In some cases, the memory controller can select the access line to be activated based on the address of the access line indicated by a command (e.g., the physical address of the access line containing the segment of the access line). Thus, the memory controller can select (i.e., access) a memory cell where some or all of the charge accompanying the parasitic capacitance associated with the access line can pass through the memory cell (e.g., via a reference). Figure 3 The discharge path 325 described herein discharges, for example, by attributing the memory cell to becoming conductive based on the applied voltage or current from the driver structure. As described herein, this is achieved through a relatively long discharge path with high resistance (e.g., reference...). Figure 3 and 4 The described discharge path discharges any accumulated charge on the access line, resulting in reduced current spikes across memory cells (e.g., due to charge dissipation and slower discharge across memory cells). Additionally, this configuration can have a relatively small impact on signal transmission (e.g., the quality of signals used in access operations and the timing of access operations can be relatively unaffected by the segmented access line structure, while reducing the amplitude of potential current spikes).

[0085] Figure 6 A block diagram 600 illustrates a memory array 605 supporting discharge current mitigation in a memory array, according to an example disclosed herein. The memory array 605 may be as described in the references... Figures 1 to 5 Examples of aspects of the described memory array. Memory array 605 may include command component 610, activation component 615, address component 620, and access component 625. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0086] Command component 610 may receive commands to perform access operations on memory cells. In some instances, command component 610 may receive a second command to perform a second access operation on a second memory cell contained in a second set of memory cells.

[0087] Activation component 615 can activate a first segment and a second segment of the access line in response to a command, wherein the second segment is discontinuous with the first segment, the first segment is coupled to a first group of memory cells containing memory cells, and the second segment is coupled to a second group of memory cells not containing memory cells. In some instances, activation component 615 can activate the second segment and the first segment of the access line in response to a second command. In some cases, the first segment is coupled to a driver via a first via. In some cases, the second segment is coupled to a driver via a second via. In some cases, activation in response to a command includes simultaneously adjusting the voltage of the first segment and the voltage of the second segment using the driver. In some cases, activation in response to a second command includes simultaneously adjusting the voltage of the second segment and the voltage of the first segment.

[0088] In some instances, a first segment is coupled to a driver via a first via and a conductive line, the first segment being parallel to the conductive line; a second segment is coupled to a driver via a second via and a conductive line, the second segment being parallel to the conductive line; and activation of a command includes simultaneously adjusting the voltage of the first segment and the voltage of the second segment using the driver.

[0089] In some instances, the driver includes a first transistor and a second transistor, a first segment coupled to the first transistor via a first via and a first conductive line, the first segment being parallel to the first conductive line, a second segment coupled to the second transistor via a second via and a second conductive line, the second segment being parallel to the second conductive line, and activation in response to a command includes simultaneously activating the first transistor and the second transistor.

[0090] Access component 625 can perform an access operation based on activation in response to a command. In some instances, access component 625 can perform a second access operation based on activation in response to a second command.

[0091] Address component 620 can identify the address of an access line based on an access command, wherein activation in response to a command is based on the address of the access line.

[0092] Figure 7 The flowchart illustrates one or more methods 700 for mitigating discharge current in a memory array according to aspects of this disclosure. Operation of method 700 can be implemented by a memory array or its components as described herein. For example, operation of method 700 can be achieved by referring to... Figure 6The described memory array performs the functions described. In some instances, the memory array may execute a set of instructions to control the functional elements of the memory array to perform the described functions. Alternatively, the memory array may use dedicated hardware to perform aspects of the described functions.

[0093] At 705, the memory array can receive commands to perform access operations on memory cells. The operation at 705 can be performed according to the methods described herein. In some instances, aspects of the operation at 705 may be as described in the references... Figure 6 The described command component is executed.

[0094] At 710, the memory array can activate a first segment and a second segment of the access line in response to a command. In some instances, the second segment is discontinuous with the first segment, the first segment is coupled to a first group of memory cells containing memory cells, and the second segment is coupled to a second group of memory cells not containing memory cells. Operation of 710 can be performed according to the method described herein. In some instances, aspects of the operation of 710 can be as described in reference... Figure 6 The described activation component is executed.

[0095] At 715, the memory array can perform access operations based on activation in response to a command. Operations at 715 can be performed according to the methods described herein. In some instances, aspects of the operation at 715 can be as described in the references... Figure 6 The described access component is executed.

[0096] In some instances, the device described herein may perform one or more methods, such as method 700. The device may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a command to perform an access operation on a memory cell; activating a first segment and a second segment of an access line in response to the command; and performing the access operation based on the activation in response to the command. In some instances, the second segment is discontinuous with the first segment, the first segment is coupled to a first set of memory cells containing memory cells, and the second segment is coupled to a second set of memory cells not containing memory cells.

[0097] Some examples of the method 700 and apparatus described herein may further include operations, features, means or instructions for identifying the address of an access line based on an access command, wherein activation in response to the command may be based on the address of the access line.

[0098] In some instances of the method 700 and apparatus described herein, a first segment may be coupled to a driver via a first via, a second segment may be coupled to a driver via a second via, and activation of a command includes simultaneously adjusting the voltage of the first segment and the voltage of the second segment using the driver.

[0099] Some examples of the method 700 and apparatus described herein may further include operations, features, means, or instructions for: receiving a second command to perform a second access operation on a second memory cell included in a second set of memory cells; activating a second segment of an access line and a first segment of an access line in response to the second command; and performing the second access operation based on the activation in response to the second command.

[0100] In some instances of the method 700 and device described herein, activation in response to the second command includes simultaneously adjusting the voltage of the second segment and the voltage of the first segment.

[0101] In some instances of the method 700 and apparatus described herein, a first segment is coupled to a driver via a first via and a conductive line, the first segment being parallel to the conductive line; a second segment is coupled to a driver via a second via and a conductive line, the second segment being parallel to the conductive line; and activation of a command includes simultaneously adjusting the voltage of the first segment and the voltage of the second segment using the driver.

[0102] In some instances of the method 700 and apparatus described herein, the driver includes a first transistor and a second transistor, a first segment coupled to the first transistor via a first via and a first conductive line, the first segment being parallel to the first conductive line, a second segment coupled to the second transistor via a second via and a second conductive line, the second segment being parallel to the second conductive line, and activation in response to a command includes simultaneously activating the first transistor and the second transistor.

[0103] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods can be combined.

[0104] Describe an apparatus. The apparatus may include: a first segment of an access line coupled to a first group of memory cells; a second segment of the access line separate from the first segment and coupled to a second group of memory cells; and a driver coupled to the first segment and the second segment.

[0105] Some instances of the device may include a first via coupled to a first segment, through which a driver can be coupled to the first segment; and a second via coupled to a second segment, through which a driver can be coupled to the second segment.

[0106] Some instances of the device may include conductive lines beneath the first segment and the second segment, wherein the first via, the second via, and the driver may each be coupled to the conductive lines.

[0107] Some examples of the device may include a first conductive line below a first segment and a second conductive line below a second segment, wherein a first via is coupled to the first conductive line and a second via is coupled to the second conductive line.

[0108] In some instances, the driver includes a first transistor coupled to a first conductive line and a second transistor coupled to a second conductive line.

[0109] In some instances, the gate of the first transistor is coupled to the gate of the second transistor.

[0110] In some instances, both the first segment and the second segment may have a first resistivity, and both the first via and the second via may have a second resistivity, which may be greater than the first resistivity.

[0111] In some instances, the first via may couple to the first segment at a first location closer to the end of the first segment than the midpoint of the first segment, and the second via may couple to the second segment at a second location closer to the end of the second segment than the midpoint of the second segment.

[0112] In some instances, the first segment and the second segment may be on the same layer (e.g., level) of the device, and the first segment and the second segment may be separated by a gap on the same layer (e.g., level).

[0113] Some instances of the device may include a dielectric material comprising a first layer (e.g., a hierarchy) between the first segment and the second segment, wherein the first segment may be coupled to the second segment at a second layer (e.g., a hierarchy) that may be located below the first layer (e.g., a hierarchy).

[0114] In some instances, the second segment may be collinear with the first segment. In some instances, the first and second segments may have the same length. In some instances, the first and second segments may have different lengths.

[0115] Some instances of the device may include one or more additional segments of the access line, each additional segment of the access line being collinear with the first segment and the second segment, and each additional segment of the access line being coupled to a driver and a corresponding set of additional memory cells.

[0116] In some instances, the driver can be used to simultaneously activate the first segment and the second segment to access memory cells in either the first group of memory cells or the second group of memory cells.

[0117] In some instances, access lines may have addresses, memory cells in the first group and memory cells in the second group may be accessed based on addresses, and drivers may be used to adjust the voltage of the first segment and the voltage of the second segment based on access commands associated with the addresses.

[0118] In some instances, the memory cells in the first and second groups each contain chalcogenide materials.

[0119] Describe an apparatus. The apparatus may include a set of memory cells arranged in rows and columns, a set of word lines each coupled to a corresponding row of the memory cells, and a set of bit lines each coupled to a corresponding column of the memory cells, wherein each word line comprises a set of discontinuous word line segments, each word line segment coupled to a corresponding subset of a corresponding row of the memory cells, and each bit line comprises a set of discontinuous bit line segments, each bit line segment coupled to a corresponding subset of a corresponding column of the memory cells.

[0120] Some instances of the device may include a set of drivers, each driver being coupled to a corresponding word line or corresponding bit line through a set of corresponding vias.

[0121] In some instances, each of the corresponding vias in the set may be coupled to a corresponding word line segment of the same word line or a corresponding bit line segment of the same bit line.

[0122] In some instances, each of the multiple drivers includes a corresponding plurality of transistors, each of the corresponding plurality of transistors is coupled to a corresponding via in a corresponding plurality of vias, and each of the corresponding plurality of transistors is configured to be activated or deactivated simultaneously.

[0123] In some instances, the set of word line segments contained in word lines may be collinear, and the set of bit line segments contained in bit lines may be collinear.

[0124] In some instances, the set of word line segments contained in a word line may be separated by a first gap at the same layer (e.g., level) as the word line, and the set of bit line segments contained in a bit line may be separated by a second gap at the same layer (e.g., level) as the bit line.

[0125] In some instances, the set of word line segments contained in a word line each corresponds to the same word line address, and the set of bit line segments contained in a bit line each corresponds to the same bit line address.

[0126] Some instances of the device may include: a set of word line drivers, each word line driver coupled to a corresponding word line; a set of bit line drivers, each bit line driver coupled to a corresponding bit line; and a controller coupled to the set of word line drivers and the set of bit line drivers, wherein the controller can be configured to enable the device to recognize an access operation to a memory cell coupled to a word line segment contained in a word line and a bit line segment contained in a bit line; activate each of a plurality of word line segments contained in a word line using the same word line driver, at least in part based on the recognition of the access operation; and activate each of a plurality of bit line segments contained in a bit line using the same bit line driver, at least in part based on the recognition of the access operation.

[0127] The information and signals described herein can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that a signal can represent a bus of signals, where the bus can have various bit widths.

[0128] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to a relationship between components that enables the flow of signals between them. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled) if any conductive path exists between them that enables the flow of signals between them at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path between connected components that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0129] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via conductive paths, while in a closed-circuit relationship, signals can travel between components via conductive paths. When a component, such as a controller, couples other components together, the component initially allows signals to flow between the other components via conductive paths that were previously not permitted.

[0130] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0131] As used herein, the term "layer" or "level" refers to a layer or sheet of geometry (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure in which two dimensions are greater than the third, such as a thin film. A layer or level may contain different elements, components, and / or materials. In some instances, a layer or level may consist of two or more sublayers or sublevels.

[0132] As used in this article, the term “generally” means that the modified feature (e.g., a verb or adjective modified by the term “generally”) does not have to be absolute but must be close enough to obtain the advantage of the feature.

[0133] As used herein, the term "electrode" can refer to an electrical conductor and, in some instances, can be used as an electrical contact to a memory cell or other component of a memory array. An electrode may comprise traces, wires, conductive lines, conductive layers, etc., that provide a conductive path between elements or components of the memory array.

[0134] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0135] The switching components or transistors discussed herein may represent field-effect transistors (FETs), and include three-terminal devices comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped semiconductor regions, such as degenerate semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or a channel. If the channel is n-type (e.g., most carriers are signals), the FET may be called an n-type FET. If the channel is p-type (i.e., most carriers are holes), the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0136] This document describes example configurations in conjunction with the accompanying drawings, and does not represent all implementable or claim-scoped instances. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "advantageous" over other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and apparatus are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0137] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0138] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0139] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0140] The functionality described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functionality described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality may also be physically located in various locations, including distributed so that portions of the functionality are implemented in different physical locations. And, as used herein, the word “or” used in the list of items included in the claims (e.g., a list of items beginning with phrases such as “at least one of” or “one or more of”) indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase “based on” should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same way as the phrase "at least partially based on".

[0141] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compressed optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0142] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device comprising: The first segment of the access line, the first segment being coupled to the first group of memory cells; The second segment of the access line is separate from the first segment and coupled to the second group of memory cells; A driver that is coupled to the first segment and the second segment; A first via is coupled to the first segment, wherein the driver is coupled to the first segment through the first via; and A second via is coupled to the second segment, wherein the driver is coupled to the first segment and the second segment through the first via, the second via, and at least one conductive line, and wherein each of the at least one conductive line is directly coupled to the driver.

2. The memory device of claim 1, wherein the at least one conductive line comprises: A conductive line below the first segment and the second segment, wherein the first via and the second via are coupled to the conductive line, and wherein the driver includes a transistor below the conductive line and coupled to the conductive line.

3. The memory device of claim 1, wherein the at least one conductive line comprises: A first conductive line below the first segment and a second conductive line below the second segment, wherein the first via is coupled to the first conductive line and the second via is coupled to the second conductive line.

4. The memory device of claim 3, wherein the driver includes a first transistor coupled to the first conductive line and a second transistor coupled to the second conductive line.

5. The memory device of claim 4, wherein the gate of the first transistor is coupled to the gate of the second transistor.

6. The memory device according to claim 1, wherein: Both the first segment and the second segment have a first resistivity; and Both the first through hole and the second through hole have a second resistivity greater than the first resistivity.

7. The memory device according to claim 1, wherein: The first through-hole is coupled to the first segment at a first position closer to the end of the first segment than the midpoint of the first segment; and The second through hole is coupled to the second segment at a second position, closer to the end of the second segment than the midpoint of the second segment.

8. The memory device according to claim 1, wherein: The first segment and the second segment are at the same level in the memory device; and The first segment and the second segment are separated by a gap at the same level.

9. The memory device of claim 1, further comprising: A dielectric material between the first segment and the second segment at a first level comprising the first segment and the second segment, wherein the first segment is coupled to the second segment at a second level below the first level.

10. The memory device of claim 1, wherein the second segment is collinear with the first segment.

11. The memory device of claim 1, wherein the first segment and the second segment are of equal length.

12. The memory device of claim 1, wherein the first segment and the second segment have unequal lengths.

13. The memory device of claim 1, further comprising: One or more additional segments of the access line, each additional segment of the access line being collinear with the first segment and the second segment, and each additional segment of the access line being coupled to the driver and a corresponding set of additional memory cells.

14. The memory device of claim 1, wherein the driver is configured to simultaneously activate the first segment and the second segment to access memory cells in the first group of memory cells or the second group of memory cells.

15. The memory device according to claim 1, wherein: The access line has an address; At least in part based on the address, the memory cells in the first group and the memory cells in the second group are accessible; and The driver can be used to adjust the voltage of the first segment and the voltage of the second segment, at least in part, based on access commands associated with the address.

16. The memory device of claim 1, wherein each of the memory cells in the first group and the second group comprises a chalcogenide material.

17. A method at a memory device, comprising: Receive commands to perform access operations on memory cells; In response to the command, a first segment of the access line and a second segment of the access line are activated, the second segment being discontinuous with the first segment, wherein: The first segment is coupled to a first group of memory cells containing the memory cells, and the second segment is coupled to a second group of memory cells not containing the memory cells. The first segment is coupled to the driver through a first via, and the second segment is coupled to the driver through a second via. The driver is coupled to the first segment and the second segment through the first through-hole, the second through-hole, and at least one conductive line, and Each of the at least one conductive line is directly coupled to the driver; and The access operation is performed at least in part based on the activation in response to the command.

18. The method of claim 17, further comprising: The address of the access line is identified at least in part based on the command, wherein the activation in response to the command is at least in part based on the address of the access line.

19. The method of claim 17, wherein: The first segment is coupled to the driver via a conductive line, and the first segment is parallel to the conductive line; The second segment is coupled to the driver via the conductive line, and the second segment is parallel to the conductive line; and The activation in response to the command includes simultaneously adjusting the voltage of the first segment and the voltage of the second segment using the driver.

20. The method of claim 19, wherein: The driver includes a first transistor and a second transistor; The first segment is coupled to the first transistor through the first through-hole and the first conductive line, and the first segment is parallel to the first conductive line; The second segment is coupled to the second transistor through the second via and the second conductive line, and the second segment is parallel to the second conductive line; and The activation in response to the command includes activating both the first transistor and the second transistor simultaneously.

21. The method of claim 17, further comprising: Receive a second command to perform a second access operation on a second memory cell contained in the second group of memory cells; In response to the second command, the second segment of the access line and the first segment of the access line are activated; and The second access operation is performed at least in part based on the activation in response to the second command.

22. A memory device comprising: Multiple memory cells arranged in rows and columns; Multiple word lines, each coupled to the corresponding row of a memory cell; and Multiple bit lines, each coupled to a corresponding column of a memory cell, wherein: Each word line comprises multiple discontinuous word line segments, each word line segment being coupled to a corresponding subset of the corresponding row of the memory cell; Each bit line comprises multiple discontinuous bit line segments, each bit line segment being coupled to a corresponding subset of the corresponding column of the memory cell; Each of one or more drivers is coupled to a corresponding word line or corresponding bit line through corresponding vias and at least one conductive line, and Each of the at least one conductive line is directly coupled to one or more of the drivers.

23. The memory device of claim 22, wherein each of the respective plurality of vias is coupled to a corresponding word line segment of the same word line or a corresponding bit line segment of the same bit line.

24. The memory device of claim 22, wherein: Each of the plurality of drivers includes a corresponding plurality of transistors; Each of the respective plurality of transistors is coupled to a corresponding via of the respective plurality of vias; and Each of the respective plurality of transistors is configured to be activated or deactivated simultaneously.

25. The memory device according to claim 22, wherein: The plurality of word line segments contained in the word line are collinear; and The plurality of bit line segments contained in the bit line are collinear.

26. The memory device of claim 25, wherein: The plurality of word line segments contained in the word line are separated by a first gap at the same layer as the word line; and The plurality of bit line segments contained in the bit line are separated by a second gap at the same layer as the bit line.

27. The memory device of claim 22, wherein: The plurality of word line segments contained in the word line each correspond to the same word line address; and The plurality of bit line segments contained in the bit line each correspond to the same bit line address.

28. The memory device of claim 22, further comprising: Multiple word line drivers, each coupled to its corresponding word line; Multiple bit line drivers, each coupled to a corresponding bit line; and A controller, coupled to the plurality of word line drivers and the plurality of bit line drivers, wherein the controller is configured to enable the device to: Identify access operations of memory cells, which are coupled to a word line segment contained in a word line and a bit line segment contained in a bit line; Each of the plurality of word line segments contained in the word line is activated using the same word line driver, at least in part based on identifying the access operation; and Each of the plurality of bit line segments contained in the bit line is activated using the same bit line driver, at least in part based on identifying the access operation.

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