3D integrated circuit package encapsulating copper pillars and double-sided redistribution layers

Abstract

A semiconductor package. In some embodiments, the package has a top surface and a bottom surface, and includes: a semiconductor die having a front surface, a rear surface, and a plurality of edges; a molding compound located on the rear surface of the die and the edges of the die; a plurality of first conductive elements extending through the molding compound on the rear surface of the die to the top surface of the package; and a plurality of second conductive elements located on the bottom surface of the package.

Description

Technical Field

[0001] One or more aspects of embodiments of this disclosure relate to packaging, and more specifically to an integrated circuit package comprising copper pillars and an epoxy molding compound. Background Technology

[0002] Semiconductor dies through which vias extend (such as silicon dies with silicon through-holes) can be very thin due to the process of forming the vias. In some embodiments, the die is about 200 micrometers thick, and therefore it may be relatively brittle, for example, prone to cracking or fracturing.

[0003] Therefore, packaging is needed to protect the thin semiconductor die while allowing electrical connections to be formed to one or both surfaces of the die. Summary of the Invention

[0004] According to an embodiment of the present invention, a package is provided having a top surface and a bottom surface, and comprising: a semiconductor die having a front surface, a rear surface and a plurality of edges; a molding compound located on the rear surface of the die; a plurality of first conductive elements extending through the molding compound on the rear surface of the die to the top surface of the package; and a plurality of second conductive elements located on the bottom surface of the package.

[0005] In some embodiments, the molding compound is also located on the edge of the core.

[0006] In some embodiments, the semiconductor die is a silicon die, and the molding compound is an epoxy molding compound.

[0007] In some embodiments, the semiconductor die includes a plurality of vias extending from the front surface of the die to the rear surface of the die.

[0008] In some embodiments, the semiconductor die includes a plurality of transistors located on the front surface of the die.

[0009] In some embodiments, the package further includes a first redistribution layer located on the front surface of the die.

[0010] In some implementations, the first redistribution layer does not extend through the first edge of the plurality of edges of the die.

[0011] In some embodiments, the package further includes a second redistribution layer located on the rear surface of the die.

[0012] In some embodiments: each of the first conductive elements is a copper pillar with a diameter of at least 100 micrometers and a height of at least 50 micrometers, and the distance between adjacent first conductive elements is at least 300 micrometers; each of the second conductive elements is a copper rod bump with a diameter of at most 50 micrometers and a height of at most 50 micrometers, and the distance between adjacent second conductive elements is at most 120 micrometers.

[0013] In some embodiments, the package further includes: a first redistribution layer located on the front surface of the die; and a second redistribution layer located on the rear surface of the die, wherein each of the second conductive elements is connected to the front surface of the die through the first redistribution layer and through the via.

[0014] In some embodiments: the semiconductor die includes a transimpedance amplifier located on the front surface of the semiconductor die; and the transimpedance amplifier has: an input terminal connected to one of the plurality of second conductive elements through a first redistribution layer; and an output terminal connected to one of the plurality of first conductive elements through the first redistribution layer, through one of the plurality of vias, and through a second redistribution layer.

[0015] In some embodiments: the semiconductor die includes a modulator driver located on the front surface of the semiconductor die, the modulator driver having: an input terminal connected to a conductive element of a plurality of first conductive elements through a first redistribution layer, through one of the plurality of vias, and through a second redistribution layer; and an input terminal connected to a conductive element of a plurality of second conductive elements through the first redistribution layer.

[0016] In some embodiments, the method further includes: forming a plurality of conductive pillars on the surface of a semiconductor wafer having a front surface and a rear surface, the conductive pillars being formed on the rear surface of the semiconductor wafer; dicing the semiconductor wafer to form a plurality of semiconductor dies, each of the semiconductor dies having a front surface corresponding to the front surface of the semiconductor wafer, a rear surface corresponding to the rear surface of the semiconductor wafer, and a plurality of edges; applying a molding compound to the semiconductor die, the application including using the molding compound to cover the rear surface of each of the semiconductor dies; grinding the molding compound to expose the conductive pillars; and forming a plurality of conductive rod bumps on the front surface of each of the semiconductor dies.

[0017] In some embodiments, the application of the molding compound further includes using the molding compound to cover the edges of each of the semiconductor dies.

[0018] In some embodiments, the conductive pillar is a copper pillar, and the conductive rod bump is a copper rod bump.

[0019] In some embodiments, each of the semiconductor dies is a silicon die having a plurality of through-silicon vias, each of the plurality of through-silicon vias extending from the front surface of the semiconductor die to the rear surface of the semiconductor die.

[0020] In some embodiments, the method further includes forming a first redistribution layer on the front surface of the semiconductor wafer prior to the formation of the plurality of conductive rod bumps, wherein the formation of the plurality of conductive rod bumps includes forming the plurality of conductive rod bumps directly on the first redistribution layer.

[0021] In some embodiments, the method further includes forming a second redistribution layer on the back surface of the semiconductor wafer prior to the formation of the conductive pillar, wherein the formation of the conductive pillar includes forming the conductive pillar directly on the second redistribution layer. Attached Figure Description

[0022] These and other features and advantages of this disclosure will be understood and appreciated by referring to the specification, claims, and drawings, in which:

[0023] Figure 1A This is a cross-sectional view of an integrated circuit package according to an embodiment of this disclosure;

[0024] Figure 1B yes Figure 1A A magnified view of a portion;

[0025] Figure 2A This is a cross-sectional view of an intermediate product in a process for manufacturing an integrated circuit package according to an embodiment of this disclosure;

[0026] Figure 2B yes Figure 2A A magnified view of a portion;

[0027] Figure 3A This is a cross-sectional view of an intermediate product in a process for manufacturing an integrated circuit package according to an embodiment of this disclosure;

[0028] Figure 3B yes Figure 3A A magnified view of a portion;

[0029] Figure 4AThis is a cross-sectional view of an intermediate product in a process for manufacturing an integrated circuit package according to an embodiment of this disclosure;

[0030] Figure 4B yes Figure 4A A magnified view of a portion;

[0031] Figure 5A This is a cross-sectional view of an integrated circuit package according to an embodiment of this disclosure;

[0032] Figure 5B yes Figure 5A A magnified view of a portion;

[0033] Figure 6A This is a cross-sectional view of an intermediate product located on a carrier in a process for manufacturing an integrated circuit package according to an embodiment of the present disclosure;

[0034] Figure 6B This is a cross-sectional view of an intermediate product located on a carrier in a process for manufacturing an integrated circuit package according to an embodiment of the present disclosure;

[0035] Figure 6C This is a cross-sectional view of an integrated circuit package according to an embodiment of the present disclosure; and

[0036] Figure 7 The adoption of the implementation scheme of this disclosure Figure 1A and Figure 1B A three-dimensional view of an integrated circuit packaging system. Detailed Implementation

[0037] The detailed description below, taken in conjunction with the accompanying drawings, is intended as a description of exemplary embodiments of integrated circuit packages provided according to this disclosure and is not intended to represent the only form in which this disclosure may be constructed or utilized. The description is used to illustrate the features of this disclosure in conjunction with the illustrated embodiments. However, it should be understood that the same or equivalent functions and structures may be implemented by different embodiments that are also intended to be encompassed within the scope of this disclosure. As described elsewhere herein, similar element designations are intended to indicate similar elements or features.

[0038] refer to Figure 1A and Figure 1B ( Figure 1B yes Figure 1A (A partially enlarged view), in some embodiments, the integrated circuit package includes a silicon die 105 encapsulated on several sides by a molding compound (e.g., epoxy molding compound (EMC)) 110. Figure 1A and Figure 1BIn this orientation, the front surface of the silicon die 105 (on which active components (e.g., transistors) can be fabricated in a foundry) is the bottom surface of the silicon die 105, and the top surface is the rear surface. A first redistribution layer 115 (or "front-side RDL") is attached to the front surface of the silicon die 105, and a second redistribution layer 120 (or "rear-side RDL") is attached to the rear surface of the silicon die 105.

[0039] Multiple first conductive elements (e.g., copper pillars 125) form external connections to the second redistribution layer 120 through an epoxy molding compound 110 layer located on the rear surface of the silicon die 105. The copper pillars may be positioned with a center-to-center distance of at least 300 micrometers (e.g., they may be positioned on a grid with a spacing of at least 300 micrometers), and each copper pillar may have a diameter of about 200 micrometers (e.g., a diameter between 100 and 1000 micrometers) and a height of at least 50 micrometers (e.g., a height of about 100 micrometers). A passivation layer (e.g., a polyimide passivation layer) may be present on the second redistribution layer 120; a via (e.g., a via with a diameter of 10 micrometers) through the passivation layer may be used to form connections between the second redistribution layer 120 and the copper pillars 125. Multiple second conductive elements (e.g., copper bar bumps 130) form external connections to the first redistribution layer 115. The copper rod bumps may be positioned with a center-to-center distance of 120 micrometers or less (e.g., they may be positioned on a grid with a spacing of up to 120 micrometers), and each copper rod bump may have a diameter of up to 50 micrometers and a height of up to 50 micrometers. The silicon die 105 may include a plurality of through-silicon vias (TSVs) 135, which form a conductive path between (i) the front surface of the silicon die 105 and the first redistribution layer 115 and (ii) the rear surface of the silicon die 105 and the second redistribution layer 120.

[0040] In some embodiments, no external connections are formed on the outer periphery of the silicon die 105, and each edge of each of the first redistribution layer 115 and the second redistribution layer 120 may be flush with the corresponding edge of the silicon die 105 (e.g., Figure 1B As shown in the diagram, the silicon die 105 may extend slightly beyond the edge of one or both of the first redistribution layer 115 and the second redistribution layer 120, or one or the other or both of the first redistribution layer 115 and the second redistribution layer 120 may extend slightly (e.g., less than 500 micrometers or less than 100 micrometers) beyond the edge of the silicon die 105.

[0041] Third redistribution layer ( Figure 1A and Figure 1B(Not shown) can be formed on the top surface of the integrated circuit package, i.e., on the epoxy molding compound 110 layer located on the rear surface of the silicon die 105. Surface finish 140 can be formed on the third redistribution layer (if present) and on the outer ends of the copper pillars 125 (i.e., on...). Figure 1A and Figure 1B In the orientation, it is formed on the upper end). This surface finish can be, for example, (i) nickel / gold, (ii) electroless nickel immersion gold (ENIG), or (iii) electroless nickel, electroless palladium and immersion gold (ENEPIG). The surface finish can provide conductive pads suitable for use as overlapping grid arrays, for example to achieve connections to another integrated circuit (discussed in more detail below).

[0042] The presence of (i) an epoxy molding compound 110 layer on the rear surface of silicon die 105 and (ii) copper pillars 125 reduces the risk that connections to the rear surface of silicon die 105 will damage silicon die 105. For example, in some embodiments, another integrated circuit (e.g., a CMOS packet switching ASIC) may have a conductor array (e.g., an overlap grid array) on its lower surface, said other integrated circuit being mounted on the top surface of the integrated circuit package during operation, and may, for example, use components including compressible conductive elements 145 (…). Figure 1A For illustrative purposes, one of the arrays of sockets is shown to establish multiple electrical connections between the conductor array of the CMOS packet switching ASIC and the copper pillars 125 of the integrated circuit package. Compared to the area that the compressive force (and any shear force) applied to the silicon die 105 by each of the compressible conductive elements 145 would distribute in the absence of (i) the epoxy molding compound 110 layer on the rear surface of the silicon die 105 and (ii) the copper pillars 125, the forces in the presence of (i) the epoxy molding compound 110 layer on the rear surface of the silicon die 105 and (ii) the copper pillars 125 can be distributed over a larger area of ​​the silicon die 105.

[0043] In addition to covering the back surface of the silicon die 105, the epoxy molding compound 110 may also cover the edges (i.e., side surfaces) of the silicon die 105. The epoxy molding compound 110 present on the edges of the silicon die 105 protects the silicon die 105 from breakage. In some embodiments, the epoxy molding compound 110 layer on each edge is between 50 micrometers and 100 micrometers thick.

[0044] Figure 2A and Figure 2B ( Figure 2B yes Figure 2A (A magnified view of a portion) shows what can be made for use in manufacturing Figure 1A and Figure 1B An intermediate product that is part of the integrated circuit packaging process. Figure 2A and Figure 2BThe intermediate product can be manufactured by first fabricating a primary silicon die in a foundry. The primary silicon die can be fabricated from a silicon wafer and may include structures (e.g., transistors) on its front surface and vias (e.g., blind vias for forming silicon through-holes) extending from the front surface into the wafer to a depth (e.g., about 200 micrometers). A first redistribution layer 115 can be formed on the front side of the wafer. The wafer can be bonded to a first carrier, and the back side of the wafer can be ground to expose the ends of the silicon through-holes, such that after the back side of the wafer is ground, the silicon through-holes 135 extend through the wafer. A second redistribution layer 120 can then be formed on the back side of the wafer. In some embodiments, the silicon through-holes are formed after thinning the wafer by grinding.

[0045] Figure 3A and Figure 3B ( Figure 3B yes Figure 3A (A magnified view of a portion) shows that it can be obtained from Figure 2A and Figure 2B Intermediate products formed from intermediate products. Copper pillars 125 may be formed on the back side of the wafer (e.g., on the second redistribution layer 120) (e.g., by plating), and the wafer may be peeled off from the first carrier. At this point in the process, if the remaining manufacturing steps are to be performed in another factory, the wafer may be in a form suitable for packaging and shipping to that other factory.

[0046] Figure 4A and Figure 4B ( Figure 4B yes Figure 4A (A magnified view of a portion) shows that it can be obtained from Figure 3A and Figure 3B The intermediate product is formed from the intermediate product. The wafer can be diced and the resulting die can be repositioned onto the second carrier, and overmolded using epoxy molding compound 110. Next, the rear side of the overmolded intermediate product can be ground to expose (i.e., expose) the end of the copper pillar 125, and if the third redistribution layer is part of the integrated circuit package, a third redistribution layer (not shown) can be formed on the top surface of the epoxy molding compound 110 layer located on the rear surface of the silicon die 105. Then, a surface finish 140 can be formed on the third redistribution layer (if present) and on the outer end of the copper pillar 125. Figure 4A and Figure 4B The view is drawn to show only one wrapper, but in conjunction with... Figure 4A and Figure 4B At the corresponding manufacturing step, multiple cores can be joined together using epoxy molding compound 110.

[0047] Figure 5A and Figure 5B ( Figure 5B yes Figure 5A(A magnified view of a portion) shows that it can be obtained from Figure 4A and Figure 4B Intermediate products are used to form integrated circuit packages. This allows for... Figure 4A and Figure 4B The intermediate product is peeled off from the second carrier, and the back side of the intermediate product can be bonded to the third carrier. An additional (e.g., fourth) redistribution layer can be formed on the front side of the silicon die at this step (or if the first redistribution layer 115 was not formed in a previous fabrication step), and copper rod bumps 130 can be formed on the front redistribution layer (e.g., on the first redistribution layer 115 or on the fourth redistribution layer if both the first and fourth redistribution layers are present). The copper rod bumps 130 can be formed, for example, in two or three steps, including: a step of depositing copper (e.g., plating); an optional step of depositing nickel on the copper; and a step of depositing a tin-silver alloy on (i) nickel (if present) or (ii) copper if nickel is absent. The intermediate product can then be peeled off from the third carrier, cut (e.g., split at the strips of epoxy molding compound 110 located between adjacent dies), packaged, and shipped.

[0048] Figure 6A Shown on the second carrier 610 Figure 4A and Figure 4B intermediate products, Figure 6B This intermediate product is shown after being peeled from the second carrier 610 and bonded to the third carrier 620, and Figure 6C The final product is shown in some implementation schemes. For ease of illustration, Figure 6A and Figure 6B Only two dies encapsulated in epoxy molding compound 110 are shown; however, in some embodiments, a larger number of dies are present in this intermediate product.

[0049] Figure 7A system employing an integrated circuit package 705 is illustrated in some embodiments. The integrated circuit package 705 is mounted on a photonic integrated circuit (PIC) 710, which in turn is mounted on an optical engine carrier 715. The upper surface of each of the copper pillars 125 forms a conductive surface 720 of an overlapping grid array (e.g., formed by surface finish 140) to form contact with one or more other components (e.g., a CMOS packet switching ASIC (not shown), as discussed above). The PIC 710 may include a V-groove and a mode converter for aligning an optical fiber 725 to the PIC 710 and for performing mode conversion between the optical intrinsic mode of the optical fiber and the intrinsic mode of the optical waveguide (e.g., a 3-micron ribbed waveguide or strip waveguide). The PIC may also include optoelectronic devices (such as photodetectors) and an optical modulator for converting optical signals (e.g., amplitude-modulated light) into electrical signals (and vice versa), the optical modulator being connected to the optical waveguide. The electrical terminals of the optoelectronic device can be connected to the copper bumps 130 of the integrated circuit package 705 via conductive traces on the PIC. The structure on the front surface of the silicon die 105 of each integrated circuit package 705 may include transistor circuitry, such as interface circuitry (e.g., circuitry for amplifying signals from a photodetector, such as a transimpedance amplifier, and a modulator driver for driving a modulator) that interfaces the optoelectronic device to, for example, a CMOS packet switching ASIC. In this embodiment, the optoelectronic device can be connected to the interface circuitry via the copper bumps 130 and through a first redistribution layer 115, and the interface circuitry can be connected to the CMOS packet switching ASIC via the first redistribution layer 115, through a through-silicon via 135, through a second redistribution layer 120, and through copper pillars 125.

[0050] As used herein, a “copper pillar” is a pillar containing at least 50% copper by weight. As used herein, a “copper rod bump” is a rod bump containing at least 50% copper by weight. As used herein, the word “or” is inclusive, such that, for example, “A or B” means (i) A, (ii) B, and (iii) either A or B.

[0051] It will be understood that when a component or layer is referred to as "located on another component or layer," "formed on another component or layer," "connected to another component or layer," "coupled to another component or layer," or "adjacent to another component or layer," the component or layer may be directly located on another component or layer, directly formed on another component or layer, directly connected to another component or layer, directly coupled to another component or layer, or immediately adjacent to another component or layer, or one or more intermediate components or layers may exist. In contrast, when a component or layer is referred to as "located directly on another component or layer," "formed directly on another component or layer," "directly connected to another component or layer," "directly coupled to another component or layer," or "immediately adjacent to another component or layer," then there is no intermediate component or layer.

[0052] Any numerical range cited herein is intended to include all subranges containing the same numerical precision. For example, the range “1.0 to 10.0” or “between 1.0 and 10.0” is intended to include all subranges between (and including) the cited minimum value of 1.0 and the cited maximum value of 10.0, i.e., a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit cited herein is intended to include all lower numerical limits contained within the maximum numerical limit, and any minimum numerical limit cited herein is intended to include all higher numerical limits contained within the minimum numerical limit.

[0053] Although exemplary embodiments of integrated circuit packaging have been specifically described and illustrated herein, those skilled in the art will appreciate numerous modifications and variations. Therefore, it should be understood that integrated circuit packaging constructions based on the principles of this disclosure may be embodied in forms other than those specifically described herein. This invention is also defined by the following claims and their equivalents.

Claims

1. A system comprising: Photonic integrated circuits; as well as A package directly mounted on the photonic integrated circuit and having a top surface and a bottom surface, wherein the package comprises: A semiconductor die having a front surface, a rear surface and a plurality of edges, the die including a plurality of through holes extending from the front surface of the die to the rear surface of the die; A molding compound, the molding compound being located on the rear surface of the die; A plurality of first conductive elements extend through the molding compound on the rear surface of the die to the top surface of the package; A plurality of second conductive elements are located on the bottom surface of the package; A first redistribution layer directly located on the front surface of the die, wherein the first redistribution layer does not extend through the plurality of edges of the die, and wherein the plurality of second conductive elements are directly located on the first redistribution layer and connected to the front surface of the die through the first redistribution layer and through the vias; and A second redistribution layer is located directly on the rear surface of the die, wherein the second redistribution layer does not extend through the plurality of edges of the die, and wherein the plurality of first conductive elements are located directly on the second redistribution layer. The molding compound is also located directly on the plurality of edges of the core.

2. The system of claim 1, wherein the semiconductor die is a silicon die and the molding compound is an epoxy molding compound.

3. The system of claim 1 or claim 2, wherein the semiconductor die includes a plurality of transistors located on the front surface of the die.

4. The system as claimed in claim 1 or claim 2, wherein: Each of the first conductive elements is a copper pillar with a diameter of at least 100 micrometers and a height of at least 50 micrometers. The distance between adjacent first conductive elements is at least 300 micrometers. Each of the second conductive elements is a copper rod bump with a diameter of up to 50 micrometers and a height of up to 50 micrometers, and The distance between adjacent second conductive elements is a maximum of 120 micrometers.

5. The system as claimed in claim 1, wherein: The semiconductor die includes a transimpedance amplifier located on the front surface of the semiconductor die; and The transimpedance amplifier has: The input terminal is connected to one of the plurality of second conductive elements through the first redistribution layer; as well as The output terminal is connected to one of the plurality of first conductive elements through the first redistribution layer, through one of the plurality of through holes, and through the second redistribution layer.

6. The system as claimed in claim 1 or claim 5, wherein: The semiconductor die includes a modulator driver located on the front surface of the semiconductor die. The modulator driver has: The input terminal is connected to one of the plurality of first conductive elements through the first redistribution layer, through one of the plurality of through holes, and through the second redistribution layer; as well as The output terminal is connected to one of the plurality of second conductive elements through the first redistribution layer.

7. A method for fabricating a package, the method comprising: A plurality of conductive pillars are formed on the surface of a semiconductor wafer, the semiconductor wafer having a front surface and a rear surface, the conductive pillars being formed on the rear surface of the semiconductor wafer; The semiconductor wafer is diced to form a plurality of semiconductor dies, each of the semiconductor dies having a front surface corresponding to the front surface of the semiconductor wafer, a rear surface corresponding to the rear surface of the semiconductor wafer, and a plurality of edges; Applying a molding compound to the semiconductor die, the application including using the molding compound to cover the back surface of each of the semiconductor dies; Grind the molding compound to expose the conductive pillars; A plurality of conductive rod bumps are formed on the front surface of each of the semiconductor dies; A first redistribution layer is formed directly on the front surface of the semiconductor wafer prior to the formation of the plurality of conductive rod bumps, wherein the formation of the plurality of conductive rod bumps includes forming the plurality of conductive rod bumps directly on the first redistribution layer; and A second redistribution layer is formed on the back surface of the semiconductor wafer prior to the formation of the conductive pillars, wherein the formation of the conductive pillars includes forming the conductive pillars directly on the second redistribution layer. Each of the semiconductor dies is a silicon die having a plurality of through-silicon vias, each of the plurality of through-silicon vias extending from the front surface of the semiconductor die to the rear surface of the semiconductor die, and The application of the molding compound further includes using the molding compound to apply it directly to the plurality of edges of each of the semiconductor dies. The first redistribution layer and the second redistribution layer do not extend through the plurality of edges of the die.

8. The method of claim 7, wherein the conductive post is a copper post and the conductive rod bump is a copper rod bump.

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