Multiplexing different signals on a single pin of a memory device

Abstract

This application is directed to multiplexing distinct signals on a single pin of a memory device. Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques for multiplexing data using a modulation scheme having at least three levels are described herein. The modulated data can be transmitted to multiple memory dies on a shared bus. Each of the dies can include the same or different types of memory cells, and in some examples, the multi-level signaling scheme can be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal can be configured to represent multiple data bits.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application. The parent application is a Chinese invention patent application entitled “Multiplexing Different Signals on a Single Pin of a Memory Device,” filed on September 26, 2018, with application number 201811124389.5. Technical Field

[0003] The technical field relates to multiplexing distinct signals on a single pin of a memory device. Background Art

[0004] The following generally relates to the use of signaling in memory devices. Memory devices are widely used to store information related to various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of memory cells.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory devices such as FeRAM can maintain their stored logic state for a long period of time, even without an external power source. Volatile memory devices (e.g., DRAM) can lose their stored state over time unless periodically refreshed by an external power source. FeRAM can use a device architecture similar to volatile memory, but can have non-volatile properties due to the use of ferroelectric capacitors as storage devices.

[0006] Generally speaking, improving memory devices may include increasing memory cell density, increasing read / write speeds, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. Summary of the Invention

[0007] An apparatus is described. In some examples, the apparatus may include: a multiplexer coupled to a bus, the multiplexer configured to multiplex first data and second data in a signal modulated using a first modulation scheme having at least three levels; a first memory die coupled to the bus, the first memory die configured to use at least the first data of the signal; a second memory die coupled to the bus, the second memory die configured to use at least the second data of the signal; and a memory controller coupled to the bus, the memory controller configured to transmit the first data and the second data in the signal to the first memory die and the second memory die over the bus.

[0008] A method is described. In some examples, the method may include: identifying first data and second data; multiplexing the first data and the second data in a signal modulated using a first modulation scheme having at least three levels based at least in part on identifying the first data and the second data; and transmitting the signal in the signal to a first memory die coupled to a bus and a second memory die coupled to the bus.

[0009] An apparatus is described. In some examples, the apparatus may include: a first memory die coupled to a bus; a second memory die coupled to the bus; and a memory controller coupled to the bus. In some examples, the memory controller is operable to: identify first data and second data, wherein at least one of the first data or the second data comprises control data; multiplex the first data and the second data in a signal modulated using a first modulation scheme having at least three levels; and transmit the signal to the first memory die and the second memory die.

[0010] An apparatus is described. In some examples, the apparatus may include: a first memory die coupled to a bus; a second memory die coupled to the bus; a third memory die coupled to the bus; and a memory controller coupled to the bus. In some examples, the memory controller is operable to: identify first data, second data, and third data; multiplex the first data, the second data, and the third data in a signal modulated using a first modulation scheme having at least five levels; and transmit the signal to the first memory die, the second memory die, and the third memory die.

[0011] An apparatus is described. In some examples, the apparatus may include: a first memory die coupled to a bus; a second memory die coupled to the bus; means for identifying first data and second data, wherein at least one of the first data or the second data comprises control data; means for multiplexing the first data and the second data in a signal modulated using a first modulation scheme having at least three levels; and means for transmitting a signal to the first memory die and the second memory die.

[0012] An apparatus is described. In some examples, the apparatus may include: a first memory die coupled to a bus; a second memory die coupled to the bus; a third memory die coupled to the bus; means for identifying first data, second data, and third data; means for multiplexing the first data, second data, and third data in a signal modulated using a first modulation scheme having at least five levels; and means for transmitting a signal to the first memory die, the second memory die, and the third memory die. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 An example of a memory device supporting multiplexing of distinct signals on a single pin according to an example of the present invention is described.

[0014] Figure 2 An example of a circuit supporting multiplexing of different signals on a single pin according to an example of the present invention is described.

[0015] Figure 3 An example of a circuit supporting multiplexing of different signals on a single pin according to an example of the present invention is described.

[0016] Figure 4 An example of a diagram illustrating support for multiplexing distinct signals on a single pin according to an example of the present invention.

[0017] Figure 5 An example of a diagram illustrating support for multiplexing distinct signals on a single pin according to an example of the present invention.

[0018] Figure 6 An example of a memory device supporting multiplexing of distinct signals on a single pin according to an example of the present invention is described.

[0019] Figure 7 An example of a memory device supporting multiplexing of distinct signals on a single pin according to an example of the present invention is described.

[0020] Figure 8 An example of a process flow diagram is illustrated that supports multiplexing distinct signals on a single pin according to an example of the present invention.

[0021] Figure 9 An example of a circuit supporting multiplexing of different signals on a single pin according to an example of the present invention is described.

[0022] Figure 10 An example of a circuit supporting multiplexing of different signals on a single pin according to an example of the present invention is described.

[0023] Figure 11 An example of a circuit supporting multiplexing of different signals on a single pin according to an example of the present invention is described.

[0024] Figure 12 An example of a circuit supporting multiplexing of different signals on a single pin according to an example of the present invention is described.

[0025] Figure 13 An example of a circuit supporting multiplexing of different signals on a single pin according to an example of the present invention is described.

[0026] Figure 14 An example of a circuit supporting multiplexing of different signals on a single pin according to an example of the present invention is described.

[0027] Figure 15 An example of a diagram illustrating waveforms that support multiplexing of distinct signals on a single pin according to an example of the present invention.

[0028] Figure 16 An example of a diagram illustrating waveforms that support multiplexing of distinct signals on a single pin according to an example of the present invention.

[0029] Figure 17 An example of a diagram illustrating waveforms that support multiplexing of distinct signals on a single pin according to an example of the present invention.

[0030] Figure 18 An example of a process flow diagram is illustrated that supports multiplexing distinct signals on a single pin according to an example of the present invention.

[0031] Figure 19 An example of a process flow diagram is illustrated that supports multiplexing distinct signals on a single pin according to an example of the present invention.

[0032] Figure 20 An example of a memory device supporting multiplexing of distinct signals on a single pin according to an example of the present invention is described.

[0033] Figure 21 An example of a process flow diagram is illustrated that supports multiplexing distinct signals on a single pin according to an example of the present invention.

[0034] Figure 22An example of a process flow diagram is illustrated that supports multiplexing distinct signals on a single pin according to an example of the present invention.

[0035] Figure 23 An example block diagram illustrating a device that supports multiplexing distinct signals on a single pin according to an example of the present invention.

[0036] Figure 24 An example block diagram illustrating a device that supports multiplexing distinct signals on a single pin according to an example of the present invention.

[0037] Figure 25 An example flow chart illustrating a method of supporting multiplexing of distinct signals on a single pin according to an example of the present invention.

[0038] Figure 26 An example flow chart illustrating a method of supporting multiplexing of distinct signals on a single pin according to an example of the present invention. DETAILED DESCRIPTION

[0039] Some memory devices may transmit data across several channels in the memory device using a signal modulated using a first modulation scheme having multiple levels (e.g., at least three levels). This signaling may be configured to increase the data transfer rate without increasing the frequency of data transfers and / or the transmit power of the transferred data. An example of this signaling scheme may be pulse amplitude modulation (PAM), in which a unique symbol of the signal may be configured to represent multiple data bits.

[0040] In this signaling scheme, different symbols can represent different data, different types of data, or both. For example, control data, storage data, metadata, or a combination thereof can be transmitted in a single signal containing multiple symbols. As a result, the read and write speeds of the memory array can be improved.

[0041] In some examples, multiplexing first data and second data into a signal modulated using a modulation scheme having at least three levels can result in improved read and write speeds for a memory array. To multiplex the signal, the first data and second data, which can represent one or more types of data, can be multiplexed into a single signal. This signal can be transmitted to a first memory die and a second memory die coupled to a bus. The signal can be transmitted to the memory die, for example, in response to a read command or a write command (e.g., based on one or more requests). This transmission (e.g., transmitting a single signal) can result in improved read and write speeds for the memory die, as well as improved performance and operational reliability.

[0042] The features of the present disclosure introduced above are further described below in the context of an exemplary memory device and various other components. Specific examples are described for a memory device that supports multi-symbol signaling. These and other features of the present disclosure are further illustrated by and described with reference to apparatus diagrams, system diagrams, and flow diagrams related to multi-symbol signaling.

[0043] Figure 1 An example system 100 according to various embodiments of the present invention is described. System 100 may also be referred to as an electronic memory device. System 100 may be configured to multiplex first and second data into a signal modulated using a modulation scheme having at least three levels. System 100 may include multiple memory dies 105 and a memory controller 110. Memory dies 105 may be coupled to memory controller 110 using one or more internal signal paths 115. Each internal signal path 115 may be configured to transmit internal signals representing data (e.g., binary symbol signals, multi-symbol signals) between memory controller 110 and one or more of memory dies 105. In some examples, internal signal paths 115 may be used to send and receive internal signals between various components within a semiconductor package.

[0044] In some cases, system 100 includes a computing device 120, such as a processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU)), or a system-on-chip (SoC). System 100, including computing device 120, can be a subsystem of a larger system (e.g., a laptop, a server, a personal computing device, a smartphone, a personal computer). In either case, computing device 120 can exchange information with memory controller 110 using signals transmitted via first signal path 125.

[0045] The memory die 105 may include a plurality of memory cells (eg Figure 2 As shown and referenced in Figure 2 1 , the plurality of memory cells may be programmable to store different logical states. For example, each memory cell may be programmable to store one or more logical states (e.g., logic '0', logic '1', logic '00', logic '01', logic '10', logic '11'). The memory cells of the memory die 105 may store data using any number of memory technologies, including DRAM, FeRAM, PCM, 3DXP memory, NAND memory, NOR memory, or a combination thereof. In some cases, the first memory die 105 of the system 100 may use a first memory technology (e.g., NAND flash memory), and the second memory die 105 of the system 100 may use a second memory technology (e.g., FeRAM) that is different from the first memory technology.

[0046] In some cases, memory die 105 may be an example of a two-dimensional (2D) array of memory cells. Or, memory die 105 may be an example of a three-dimensional (3D) array, in which multiple 2D arrays of multiple memory cells are formed on top of each other. Compared to a 2D array, this configuration can increase the number of memory cells that can be formed on a single die or substrate. In turn, this can reduce production costs, or improve the performance of the memory array, or both. Each level of array can be positioned so that the memory cells on each level can be roughly aligned with each other, thereby forming a stack of memory cells. In some cases, memory die 105 can be stacked directly on each other. In other cases, one or more of memory die 105 can be positioned away from the stack of memory die (e.g., in different memory stacks).

[0047] The memory die 105 may include one or more vias 130 (e.g., through-silicon vias (TSVs)). In some cases, one or more vias 130 may be part of the internal signal path 115 and perform a similar function. For example, when the memory dies 105 are stacked on top of each other, the vias 130 may be used to communicate between the memory dies 105. Some vias 130 may be used to facilitate communication between the memory controller 110 and at least some of the memory dies 105. In some cases, a single via 130 may be coupled to multiple memory dies 105. In some cases, each memory die 105 may include a via 130.

[0048] Memory controller 110 can control the operation (e.g., reading, writing, rewriting, refreshing, emptying) of memory cells in memory die 105 through one or more various components (e.g., row decoders, column decoders, sensing components). In some cases, the row decoder, column decoder, or sensing components, or some combination, can be co-located with memory controller 110. Memory controller 110 can generate row and column address signals to activate the desired word lines and digit lines. In other examples, memory controller 110 can control various voltages or currents, or both, used during operation of system 100. For example, memory controller 110 can apply a discharge voltage to a word line or digit line after accessing one or more memory cells. In general, the amplitude, shape, or duration of the applied voltage or current discussed herein can be adjusted or varied and can be different for the various operations discussed with respect to operating system 100. Furthermore, one, multiple, or all memory cells within memory die 105 can be accessed in parallel. For example, multiple memory cells or all memory cells of memory die 105 may be accessed simultaneously during a reset operation, in which multiple memory cells or all memory cells may be set to a single logic state (eg, logic '0').

[0049] In some cases, memory controller 110 may be integrated as part of computing device 120. For example, a processor of computing device 120 may execute one or more processes, operations, or programs configured to control various aspects of system 100 or initiate various operations or actions. In some cases, memory controller 110 may be integrated as part of a buffer in a stack of memory dies 105. For example, memory controller 110 may be an example of a semiconductor die that may execute one or more processes, operations, or programs configured to control various aspects of system 100 or initiate various operations or actions.

[0050] The memory controller 110 may include a multi-symbol signal component 135 configured to transmit a multi-symbol signal (i.e., a signal modulated using an M-ary modulation scheme, where M is greater than or equal to 3) within the system 100 (e.g., an internal signal transmitted across the internal signal path 115) and / or to transmit a multi-symbol signal with other components (e.g., an external signal transmitted across the first signal path 125). In some examples, the multi-symbol signal component 135 may modulate the first data and the second data using a modulation scheme having at least three levels. The memory controller 110 may be coupled to a single bus, for example, and may transmit the first data and the second data to one or more memory dies 105. For example, the memory controller 110 may transmit the modulated signal to each of the memory dies 105 via the bus.

[0051] In some cases, the memory controller 110 can be configured to transmit binary symbol signals and multi-symbol signals in parallel. Features and functionality associated with transmitting multi-symbol signals and binary symbol signals can be implemented in devices and contexts other than memory storage devices. For example, features of the functionality described herein can be implemented in a personal computing device, a laptop computer, a server, a portable communication device, or a combination thereof.

[0052] Figure 2 An example of a circuit 200 is shown according to various examples of the present disclosure. The circuit 200 may illustrate an example of a memory cell 205, which may be part of one or more memory dies 105. The circuit 200 may include the memory cell 205 coupled to a digit line 210 and a voltage source 215.

[0053] Memory cell 205 may implement any type of memory technology (e.g., DRAM, FeRAM, PCM, NAND, NOR). Thus, some aspects of circuit 200 may be based on the memory technology implemented by memory cell 205. For example, if memory cell 205 is an FeRAM memory cell, voltage source 215 may be an example of a plate or a plate line coupled to a plate driver. If memory cell 205 is a DRAM memory cell, voltage source 215 may be an example of ground or a virtual ground. One of ordinary skill will understand and appreciate the differences in memory cell 205 between different memory technologies.

[0054] Memory cell 205 may include capacitor 220 and selection element 225. In some cases, capacitor 220 may be or include a resistor-type device, as in the case of a PCM memory cell. Memory cell 205 may store a charge representing a programmable state in capacitor 220; for example, a charged and uncharged capacitor may represent two logic states, respectively. DRAM memory cells may include capacitors with a dielectric material as the insulating material. For example, the dielectric material may have linear or parasitic polarization characteristics, and ferroelectric memory cells may include capacitors with a ferroelectric material as the insulating material. In examples where the storage medium includes FeRAM, different charges in the ferroelectric capacitor may represent different logic states.

[0055] The memory cells 205 of the memory die 105 can be accessed (e.g., during a read operation, a write operation, or other operation) using various combinations of word lines 230, digit lines 210, plate lines, or a combination thereof in certain types of memory technologies. In some cases, some memory cells 205 may share access lines (e.g., digit lines, word lines, plate lines) with other memory cells. For example, digit lines 210 may be shared by memory cells 205 in the same column, and word lines 230 may be shared by memory cells in the same row. In some cases, plate lines may be shared by memory cells in the same segment, block, or one or more decks. As described above, various states can be stored by charging and discharging capacitors 220 of the memory cells 205.

[0056] The stored state of capacitor 220 of memory cell 205 can be read or sensed by operating various components. Capacitor 220 can be in electronic communication with digit line 210. When select component 225 is disabled, capacitor 220 can be separated from digit line 210, and when select component 225 is enabled, capacitor 220 can be coupled to digit line 210 (e.g., via word line 230). In some examples, enabling select component 225 can be referred to as selecting memory cell 205. In some cases, select component 225 can be a transistor, and its operation can be controlled by applying a voltage to the transistor gate, where the voltage magnitude is greater than a threshold magnitude of the transistor. Word line 230 can enable select component 225 based on instructions received from memory controller 110. For example, memory controller 110 can control the bias of word line 230 to selectively enable / disable select component 225, thereby connecting capacitor 220 of memory cell 205 to digit line 210.

[0057] In some examples, the change in voltage of digit line 210 depends on the intrinsic capacitance of the digit line. That is, when charge flows through digit line 210, a finite amount of charge can be stored in digit line 210, and the resulting voltage depends on the intrinsic capacitance. The intrinsic capacitance can depend on the physical characteristics of the digit line, including its size. Digit line 210 can connect multiple memory cells in memory die 105, and therefore digit line 210 can have a length that produces a non-negligible capacitance (e.g., on the order of a few picofarads (pF)). The resulting voltage of digit line 210 can then be compared to a reference voltage by sensing component 240 to determine the logic state stored in the memory cell. Other sensing methods can be used. Sensing component 240 can be coupled to digit line 210.

[0058] Sensing component 240 may include various transistors or amplifiers for detecting and amplifying signal differences, which may be referred to as latching. Sensing component 240 may include a sense amplifier that receives and compares the voltage of digital line 210 with the voltage of reference line 245, which may be a reference voltage. The sense amplifier output may be driven to a higher (e.g., positive) or lower (e.g., negative or ground) supply voltage based on the comparison result. For example, if the voltage of the digital line is higher than the reference line, the sense amplifier output may be driven to the positive supply voltage.

[0059] In some cases, the sense amplifier may drive the digit line to a supply voltage. Sense component 240 may then latch the output of the sense amplifier and / or the voltage of digit line 210, which may be used to determine the state stored in the memory cell (e.g., a logic '1'). Alternatively, for example, if the voltage of digit line 210 is lower than reference line 245, the sense amplifier output may be driven to a negative or ground voltage. Sense component 240 may similarly latch the sense amplifier output to determine the state stored in memory cell 205 (e.g., a logic '0'). The latched logic state of memory cell 205 may then be output to memory controller 110, for example, using one or more internal signal paths 115 or vias 130.

[0060] To write to a memory cell, a voltage may be applied to capacitor 220 of memory cell 205. Various methods may be used to write to memory cell 205. In one example, select component 225 may be activated via word line 230 to electrically connect capacitor 220 to digit line 210. The voltage may be applied to capacitor 220 by controlling the voltage of a first cell plate (e.g., via voltage source 215) and the voltage of a second cell plate (e.g., via digit line 210). To write a logic '0', the cell plate may be high (e.g., the voltage level may be increased to a voltage above a predetermined voltage that is a "high" voltage). That is, a positive voltage may be applied to the plate line, and the cell bottom may be low (e.g., a virtual ground or applying a negative voltage to the digit line). The reverse process may be performed to write a logic '1', where the cell plate is low and the cell bottom is high.

[0061] As reference Figure 1 As discussed, a memory controller (e.g., memory controller 110) can transmit a modulated signal to each of the memory dies (e.g., memory die 105) via a bus. In some examples, the modulated signal can be transmitted to the memory dies in response to first and / or second data requests corresponding to a first memory die and a second memory die, respectively. Each of the first and / or second data requests can, in some examples, relate to a read command or a write command. Thus, in response to the first and / or second data requests, the memory controller can transmit a modulated signal to one or more (or each) memory die associated with the read or write command.

[0062] Figure 3An example of a circuit 300 according to various examples of the present disclosure is shown. The circuit 300 may include one or more internal signal paths 315-a to 315-N that couple at least one memory die 305 with a memory controller 310. The internal signal paths 315 may be configured to transmit a multi-symbol signal 320 or a binary symbol signal 325, or both. In some cases, a first internal signal path 315-a may be dedicated to transmitting a first signal type (e.g., a multi-symbol signal 320). In some cases, a second internal signal path 315-b may be dedicated to transmitting a different second signal type (e.g., a binary symbol signal 325). In some cases, the internal signal path 315 may include one or more through-vias or TSVs, or may pass through one or more through-vias or TSVs. The memory die 305 may be a reference Figure 1 1. The memory controller 310 may be a reference to an example of a memory die 105. Figure 1 The example of memory controller 110 described in FIG. 3 is a signal path 315 that may be referenced by Figure 1 An example of signal path 115 is depicted.

[0063] The memory device may use multi-symbol signaling to increase the amount of information transmitted using a given bandwidth of a frequency resource (e.g., an internal signal may be an example of a multi-symbol signal). In some cases, the memory controller 310 may be configured to select the type of modulation scheme applied to the signal (e.g., binary symbols or multi-symbols) based on one or more parameters. Such parameters may include power consumption parameters of the memory device, performance requirements of an application implemented using the memory device, other parameters, or a combination thereof.

[0064] In binary symbol signal 325, the modulation scheme includes two symbols (e.g., two voltage levels) that represent up to two logic states (e.g., logic state '0' or logic state '1'). In multi-symbol signal 320, the modulation scheme may include a larger repertoire of symbols that can represent three or more logic states. For example, if multi-symbol signal 320 is modulated using a modulation scheme that includes four unique symbols, then multi-symbol signal 320 can be used to represent up to four logic states: '00', '01', '10', and '11'. Thus, multiple bits of data can be contained within a single symbol, thereby increasing the amount of data that can be transmitted using a given bandwidth.

[0065] The multi-symbol signal 320 may be any signal modulated using a modulation scheme that includes three or more unique symbols representing data (e.g., two or more bits of data). An M-ary signal is modulated using a modulation scheme, where M represents the number of unique symbols (e.g., level), or other conditions or combinations of conditions that may be present in the modulation scheme. The multi-symbol signal 320 may be an example of any M-ary modulation scheme, where M is greater than or equal to 3. In some cases, the multi-symbol signal 320 or the multi-symbol modulation scheme may be referred to as a non-binary signal or a non-binary modulation scheme. Examples of multi-symbol (or M-ary) modulation schemes associated with multi-symbol signals may include, but are not limited to, pulse amplitude modulation (PAM) schemes, quadrature amplitude modulation (QAM) schemes, quadrature phase shift keying (QPSK) schemes, and the like.

[0066] The binary symbol signal 325 may be any signal modulated using a modulation scheme that includes two unique symbols representing one bit of data. The binary symbol signal 325 may be an example of an M-ary modulation scheme, where M is equal to 2. Examples of binary symbol modulation schemes associated with binary symbol signals include, but are not limited to, non-return-to-zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, PAM2, and the like.

[0067] In some cases, the modulation scheme of various signals may be an amplitude modulation scheme that encodes information in terms of the amplitude (or level) of the signal (e.g., voltage amplitude or current amplitude), such as PAM4 and / or NRZ. The symbols of the modulation scheme may be referred to as levels, amplitudes, or signal strengths. For example, the first level of a signal may represent '00', the second level may represent '01', the third level may represent '10', and the fourth level may represent '11'. In some cases, a single symbol of the amplitude modulation scheme may be a constant level applied during a single symbol duration or two or more levels applied during a single symbol duration. The functionality of the features described herein may be applied with other types of modulation schemes, such as phase modulation schemes, phase shift keying modulation schemes, frequency shift keying modulation schemes, amplitude shift keying modulation schemes, on-off keying (OOK) modulation schemes, orthogonal frequency division multiplexing (OFDM) modulation schemes, spread spectrum modulation schemes, time-based modulation schemes, or a combination thereof. Thus, the sign or level of the modulation scheme may be related to signal parameters other than amplitude (eg, phase, time, frequency).

[0068] In some instances, some multi-symbol signaling schemes include symbols separated by smaller voltage differences (or other variable signal parameter measurements) than symbols in binary symbol signaling schemes. In some instances, the smaller voltage spacing can make the multi-symbol signal 320 more susceptible to errors caused by noise and other factors. However, the voltage spacing of the symbols in the multi-symbol signal 320 can be amplified by increasing the peak-to-peak transmit power of the transmitted signal. In some cases, however, such an increase in peak-to-peak transmit power may be impossible or may be difficult due to a fixed power supply voltage, fixed signal power requirements, or other factors. Therefore, in order to implement multi-level signaling, the transmitter may utilize more power and / or the receiver may be susceptible to an increased error rate when compared to the binary symbol signal 325. Despite this smaller voltage difference and related aspects, multi-level signaling facilitates different and advantageous implementations. For example, given a limited amount of communication resources, multi-level signaling transmits more information than a binary level signal. In some instances, as shown in reference Figure 1 As described, a memory controller (e.g., memory controller 110) can transmit a modulated signal to multiple memory dies (e.g., memory die 105) via a bus. Because the signal can include first and second data modulated using a modulation scheme having at least three levels, information associated with the first and second data can be transmitted to the first and second memory dies using a single signal. For example, the first and second data can be modulated in a signal having at least three levels. This signal can be transmitted to the first and second memory dies, for example, via a bus. Due to the modulation scheme, information related to the first data can be transmitted to the first memory die, and information related to the second data can be transmitted to the second memory die via a single signal. This can result in improved read and write times, reduced power consumption, improved memory device reliability, or a combination thereof.

[0069] Utilizing multi-symbol signaling among stacked memory dies within a semiconductor package can improve the performance of system 100. Multi-symbol signaling within the semiconductor package can reduce the number of internal interconnects (e.g., TSVs). Reducing the number of internal interconnects (e.g., TSVs) can reduce the memory die area, thereby reducing manufacturing costs. Furthermore, reducing the number of internal interconnects (e.g., TSVs) can reduce various parasitic components (e.g., resistance, capacitance) associated with the internal interconnects, thereby alleviating various issues associated with degradation of multi-symbol signals when transmitted through the internal interconnects.

[0070] In some cases, features and functionality associated with transmitting multi-symbol signal 320 and binary symbol signal 325 may be implemented in devices and contexts other than memory storage devices. For example, features of the functionality described herein may be implemented in a personal computing device, a laptop computer, a server, a portable communication device, or a combination thereof.

[0071] Figures 4 to 6 A memory device configured to transmit data using a binary symbol signal, a multi-symbol signal, or a combination thereof is shown. The memory device may include a computing device electrically coupled to a semiconductor package, the semiconductor package including several semiconductor dies stacked on each other. The computing device may exchange information with a host via a first signal path using a binary symbol signal, the binary symbol signal being encoded with a modulation scheme including two symbols (e.g., two voltage levels) representing one bit of data. The computing device may generate a multi-symbol signal encoded with a modulation scheme including three or more symbols representing more than one bit of data based on receiving the binary symbol signal. The computing device may transmit the multi-symbol signal to other semiconductor dies inside the semiconductor package via a set of internal signal paths (e.g., TSVs). Reference Figures 4 to 6 The features and / or functions described may be comparable to those described in Figures 1 to 3 and Figures 7 to 22 Combinations of features and / or functionality of other aspects of the described memory devices.

[0072] Figure 4 An exemplary diagram 401 of a memory system interface and associated exemplary circuitry according to various examples of the present disclosure is shown, along with a voltage driver 402 and a current driver 403. A memory controller 405 may receive a first signal 410 from a computing device 120-a and process information contained in the first signal 410 to generate a second signal 415. The memory controller 405 may be a reference Figure 1 In some examples, the first signal 410 can be a binary symbol signal configured with two levels. In some examples, the first signal 410 can be encoded using a modulation scheme that includes two unique symbols representing one bit of data.

[0073] In some examples, the second signal 415 can be a multi-symbol signal using a modulation scheme that includes three or more unique symbols representing more than one bit of data. In some examples, the first signal 410 can be encoded using an NRZ modulation scheme, and the second signal 415 can be encoded using a PAM scheme. An example of the second signal 415 encoded using a PAM scheme can be a reference signal. Figure 3 The described configuration is for PAM4 signaling with four signal levels.

[0074] In some examples, the memory controller 405 may be located within a semiconductor package 480, which may be electrically coupled to a computing device 120-a located outside the semiconductor package 480. The computing device 120-a may be a system-on-chip (SoC) or a processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU)). The semiconductor package 480 may include other semiconductor dies (which may also be referred to as semiconductor chips, not shown) electrically coupled to the memory controller 405, such as memory chips employing DRAM, NAND, FeRAM, or 3DXP technology. In some examples, the second signal 415 may be used to send and receive encoded information within the semiconductor package 480 among various components therein.

[0075] The memory controller 405 may include a voltage driver 402 configured to generate a second signal 415 based on receiving a first signal 410. The voltage driver 402 may be a reference Figure 1 1. The first signal 410 may include a portion of the multi-symbol signal component 135 described above. The first signal 410 may include a first signal 410-a corresponding to a first bit (e.g., a least significant bit (LSB)) of the signal 410. In some examples, the first signal 410-a may be connected to an input of a 1X complementary metal oxide semiconductor (CMOS) branch 420. In addition, the first signal 410 may include a first signal 410-b corresponding to a second bit (e.g., a most significant bit (MSB)) of the first signal 410.

[0076] In some examples, first signal 410-b may be connected to the input of 2X CMOS branch 430. 1X CMOS branch 420 may be connected to 1X voltage node 421, while 2X CMOS branch 430 may be connected to 2X voltage node 431. The description 1X or 2X in voltage driver 402 may indicate the voltage value of the operating voltage supplied to the CMOS branch. For example, 2X CMOS branch 430 may be connected to 2X voltage node 431, which has a voltage (e.g., 1.6V) that is approximately twice the voltage (e.g., 0.8V) of 1X voltage node 421. The output nodes of 1X CMOS branch 420 and 2X CMOS branch 430 may be connected to generate second signal 415-a. Voltage driver 402 may generate second signal 415-a associated with four voltage levels, which may be determined by four different combinations of first signal 410-a and first signal 410-b, e.g., 00, 01, 10, or 11.

[0077] The memory controller 405 may include a current driver 403 configured to generate a second signal 415 based on receiving the first signal 410. The current driver 403 may be a reference Figure 11 . The first signal 410 may include a first signal 410-c corresponding to a first bit (e.g., a least significant bit (LSB)) of the signal 410. In some examples, the first signal 410-c may be connected to a gate of a 1X n-type MOS (NMOS) device 440. In addition, the first signal 410 may include a first signal 410-d corresponding to a second bit (e.g., a most significant bit (MSB)) of the first signal 410. In some examples, the first signal 410-d may be connected to a gate of a 2X NMOS device 450.

[0078] The description 1X or 2X in current driver 403 may indicate a current value that the NMOS device can conduct. For example, 2X NMOS device 450 can conduct approximately twice the current (e.g., 500 μA) that 1X NMOS device 440 can conduct (e.g., 250 microamperes (μA)). The drain nodes of 1X NMOS device 440 and 2X NMOS device 450 are connected to generate a second signal 415-b in the form of a current flowing through a resistive load 460. Resistive load 460 may represent the equivalent resistance of the circuit connected to the drain nodes of 1X NMOS device 440 and 2X NMOS device 450. Current driver 403 may generate second signal 415-b associated with four current levels, which may be determined by four different combinations of first signal 410-c and first signal 410-d, for example, 00, 01, 10, or 11.

[0079] The specific configurations depicted in the voltage driver 402 and the current driver 403, e.g., the LSB signal 410-a connected to the 1X CMOS branch 420 and the MSB signal 410-b connected to the 2X CMOS branch 430 in the voltage driver 402, or the LSB signal 410-c connected to the 1X NMOS device 440 and the MSB signal 410-b connected to the 2X NMOS device 450 in the current driver 403, may represent possible examples to illustrate the functionality of the memory controller 405, which may be configured to generate the second signal 415 including four signal levels (e.g., voltage amplitudes or current amplitudes).

[0080] Other circuit configurations are possible to generate a second signal 415 comprising four signal levels based on receiving a first signal 410 comprising two signal levels. For example, in some instances, NMOS transistors 440 or 450 may be replaced by p-type MOS (PMOS) transistors. Furthermore, different circuits may be used to generate a second signal 415 comprising at least three or more different signal levels, such that the second signal 415 encodes more than one bit of data. Furthermore, voltage driver 402 and current driver 403 may include other circuit components (e.g., each CMOS branch 420 or 430 may include a resistor network or other circuit element (not shown)) to generate a robust second signal 415, thereby mitigating various issues (e.g., jitter, distortion, width reduction, and opening of the second signal 415).

[0081] The second signal 415 can be modulated using a modulation scheme including at least three levels to encode more than one bit of information. The second signal 415 can be used to send and receive encoded information among various components within the semiconductor package 480, which can include semiconductor dies or chips (e.g., memory chips using DRAM, NAND, FeRAM, or 3DXP memory technology, or a combination of such memory chips). Because the second signal 415 represents more than one bit of information, the number of interconnects (e.g., through-silicon vias (TSVs)) between two semiconductor dies within the semiconductor package 480 can be reduced.

[0082] In some examples, the second signal 415 can be modulated so that a single level of the second signal 415 represents two bits of information (e.g., 00, 01, 10, or 11), and the number of TSVs carrying the second signal 415 can be reduced to half the number of TSVs carrying the second signal representing one bit of information (e.g., 0 or 1). By reducing the number of TSVs, the die area occupied by the TSVs can also be reduced. In addition, various circuits associated with the TSVs (e.g., receivers, drivers) can be removed.

[0083] For example, a semiconductor package including several memory chips connected by internal interconnects (e.g., TSVs) may be configured to have one external pin connected to a first number of interconnects (e.g., eleven TSVs). The metal routing between the external pin and the first number of interconnects may become a significant source of parasitic components (e.g., resistance and capacitance). The second signal 415 representing two bits of information may reduce the number of interconnects (e.g., from eleven TSVs to six TSVs), and the accompanying reduction in parasitic components may improve the performance of a memory system including the semiconductor package.

[0084] Figure 5An exemplary diagram 501 and a serial-to-parallel converter 502 are shown illustrating a memory system interface and associated exemplary circuitry according to various examples of the present disclosure. The memory controller 505 may be a reference Figure 4 The first signal 510 and the second signal 515 may be reference signals. Figure 4 4 and 5. Serializer / deserializer 520 may receive first signal 510 from computing device 120-b and generate deserialized signal 525. In some cases, serializer / deserializer 520 may be referred to as a SerDes functional block. Memory controller 505 may receive deserialized signal 525 to generate second signal 515. In some examples, memory controller 505 may include serializer / deserializer 520.

[0085] The serializer / serializer 520 may include a serializer 502 to generate a deserialized signal 525 based on receiving a first signal 510. The serializer 502 may include comparators 530-a and 530-b and a multiplexer 540. The serializer 502 may operate with a two-phase clock system, wherein a first clock signal 545-a may be associated with the first comparator 530-a, and a second clock signal 545-b may be associated with the second comparator 530-b. In some examples, each comparator 530-a and 530-b may be supplied with the first signal 510-a and a Vref signal 550. The Vref signal 550 may provide a reference voltage for the comparators 530-a and 530-b to generate an output by comparing the Vref signal 550 with the first signal 510-a.

[0086] In some examples, comparator 530-a may be configured to capture information contained in even-numbered bits of first signal 510-a at rising edges of first clock signal 545-a. Furthermore, comparator 530-b may be configured to capture information contained in odd-numbered bits of first signal 510-a at rising edges of second clock signal 545-b. Multiplexer 540 may then compare the output signals of comparators 530-a and 530-b to generate deserialized signal 525-a.

[0087] The specific configuration depicted in deserializer 502, for example, using a two-phase clock system to deserialize odd and even bits, may represent an example for illustrating the functionality of serializer / serializer 520. Other configurations of the circuitry are possible to generate deserialized signal 525 with a 2:1 deserialization factor. For example, a single-phase clock system may be used to capture odd bits on the rising edge of a single clock signal, while even bits may be captured on the falling edge of the single clock signal. Furthermore, different circuits may be used to generate deserialized signal 525 with a serialization factor other than 2:1 (e.g., 4:1 or 8:1).

[0088] Figure 6 An exemplary diagram 601 of a memory system according to various examples of the present disclosure is shown. Diagram 601 shows a memory controller 605 located within a semiconductor package 680. The memory controller 605 may be a reference Figure 4 and 5 The semiconductor package 680 may be an example of a memory controller 405 or 505 as described herein. Figure 4 and 5 Examples of semiconductor packages 480 or 580 are described. In some cases, the memory controller 605 may also include reference Figure 5 Serializer / deserializer 520 is depicted. Memory controller 605 may receive a first signal 610 from computing device 120-c.

[0089] In some cases, computing device 120 may be referred to as a host device. The first signal 610 may be a reference Figure 4 and 5 4 or 510. In some cases, the first signal 610 may be a binary signal comprising two signal levels. In some cases, the first signal 610 may be encoded using a modulation scheme comprising two unique symbols representing one bit of data. The memory controller 605 may generate the second signal 620 based on information from the first signal 610 of the computing device 120-c. The second signal 620 may be a reference signal. Figure 4 and 5 4 or 515. In some cases, the second signal 620 can be encoded using a PAM scheme. In some cases, the second signal 620 can be a PAM4 signal configured with four signal levels.

[0090] In some cases, semiconductor package 680 may include one or more memory dies 625 (which may also be referred to as chips, semiconductor chips, and / or semiconductor dies) positioned above memory controller 605. Memory die 625 may be referenced to Figure 1105. The memory dies 625, 626 may be implemented in different memory technologies, such as DRAM, NAND, FeRAM, 3DXP, or a combination thereof. In some cases, the different dies may be implemented in a different memory technology than the other dies in the memory stack. In some examples, the semiconductor package 680 may include a first number of memory dies 625 (e.g., eight memory dies).

[0091] Memory die 625 may be electrically coupled to memory controller 605 and stacked directly on top of each other. In some cases, memory die 625 may include a memory die having its own package that is distinct from semiconductor package 680. In some cases, memory die 625 may include one or more dies having a set of TSVs 621 to relay second signal 620. In other words, memory die 625 may relay second signal 620 through a set of TSVs 621. In some examples, the topmost memory die in memory die 625 (e.g., memory die 625-n) may not have TSVs if it does not need to relay second signal 620 further (absent repeater 607 and second set of memory dies 626). In some examples, each memory die in memory die 625 may include a receiver (not shown) configured to receive and decode second signal 620.

[0092] When the memory controller 605 transmits the second signal 620 through the set of TSVs 621, the memory controller 605 may send a chip enable (CE) signal to the memory die 625. The CE signal indicates the target memory die (e.g., 625-a, or any of the memory dies 625 depicted in diagram 601) among the memory dies 625 that receives the second signal 620. In some examples, the memory controller 605 may send the CE signal directly to the target memory die. When the target memory die (e.g., memory die 625-a) receives the CE signal, the target memory die (e.g., memory die 625-a) may enable its receiver to receive the second signal 620 and decode the information contained therein.

[0093] Other memory dies (e.g., memory dies 625 other than 625-a) may not activate their receivers to avoid the power consumption associated with activating their receivers. In some examples, the CE signal may be encoded, for example, using a PAM scheme. In these cases, one or more of the memory dies 625 may include another receiver configured to decode the CE signal to determine whether they are intended to receive the second signal 620. After determining that it is intended to receive the second signal 620, the target memory die (e.g., memory die 625-a) may activate its receiver configured to receive the second signal 620 and decode the information contained therein.

[0094] Diagram 601 further illustrates a repeater 607 and a second set of memory dies 626 in the same location within semiconductor package 680. Repeater 607 and the second set of memory dies 626 may be positioned above the first set of memory dies 625. The second set of memory dies 626 (e.g., memory dies 626-a through 626-m) may be one or more memory chips or dies employing the same or different memory technologies, such as DRAM, NAND, FeRAM, 3DXP, or a combination thereof. In some cases, memory dies 626 may include one or more dies having a set of TSVs 622 to relay multi-level signals including second signal 620. In some examples, the topmost memory die (e.g., memory die 626-m) may not include TSVs if it does not need to relay signals further. In some examples, each memory die in memory dies 626 may include a receiver (not shown) configured to receive and decode the signal.

[0095] Repeater 607 can alleviate issues associated with the vertical distance traveled by second signal 620. In some cases, such issues may be referred to as Z-height limitation issues. Z-height limitation issues may occur when a first number of memory dies 625 (e.g., eight memory dies) form a vertical distance that may be long enough to cause degradation of second signal 620 received at the next memory die (e.g., memory die 626-a in the absence of repeater 607). Consequently, failures may occur when decoding second signal 620 due to degradation of second signal 620 (e.g., at memory die 626-a in the absence of repeater 607). In some instances, after traveling the vertical distance associated with first number of memory dies 625, the extended rise and fall times, combined with jitter, distortion, and reduced amplitude, may contribute to degradation of second signal 620.

[0096] Repeater 607 can be electrically coupled to a first number of memory dies 625 via a first set of TSVs 621 and to a second number of memory dies 626 via a second set of TSVs 622. Repeater 607 can be configured to receive a second signal 620 via the first set of TSVs 621 and retransmit the second signal 620 to a second number of memory dies 626 positioned above the first number of memory dies 625 via the second set of TSVs 622. Repeater 607 can be referred to as a redriver based on its signal retransmission function. In some examples, the first number of memory dies 625 can be referred to as a first tier, and the second number of memory dies 626 can be referred to as a second tier.

[0097] As described above, in some examples, the first number of memory dies 625 may include a first set of TSVs 621 through which the second signal 620 may be relayed. Furthermore, in some examples, the second number of memory dies 626 may include a second set of TSVs 622 through which the second signal 620 may be relayed. The memory controller 605 may be referred to as a primary master, configured to communicate with the repeater 607 when the memory controller 605 sends the second signal 620 to the second number of memory dies 626. In some examples, a set of through-TSVs (not shown) may be used to directly couple the memory controller 605 and the repeater 607. The through-TSVs may be configured with different structural features (e.g., smaller in three dimensions and fewer in number) than the first set of TSVs 621 or the second set of TSVs 622 because the signal properties between the repeater 607 and the memory controller 605 are relatively simpler without the various circuits associated with the first or second set of TSVs.

[0098] The memory controller 605 may be restricted from accessing the memory dies 625 in the first tier when sending the second signal 620 to the second number of memory dies 626 in the second tier. This restriction arises from the fact that the first set of TSVs 621 associated with the first number of memory dies 625 can be used to relay the second signal 620 to the second number of memory dies 626 in conjunction with the repeater 607 that receives and retransmits the second signal 620. In other words, accessing the first number of memory dies 625 in the first tier and accessing the second number of memory dies 626 in the second tier can be performed in a time-division manner.

[0099] In some examples, during a first time duration, the memory controller 605 can access a first number of memory dies 625 in the first tier while a second number of memory dies 626 in the second tier are isolated. During a second time duration following the first time duration, the memory controller 605 (e.g., a primary master) in cooperation with the repeater 607 (e.g., a redriver) can access the second number of memory dies 626 in the second tier through the first set of TSVs 621 and the second set of TSVs 622 while the first number of memory dies 625 in the first tier are isolated.

[0100] Diagram 601 further illustrates a third set of TSVs 623 in the same location within semiconductor package 680. The third set of TSVs 623 may be electrically coupled to memory controller 605 and repeater 607. Figure 6 6. A single representation of the third set of TSVs 623 is shown in FIG. 5 in an effort to increase visibility and clarity of the depicted features. Additional configurations are contemplated. The third set of TSVs 623 can alleviate issues associated with the time-division approach to accessing the first number of memory dies 625 in the first tier and the second number of memory dies 626 in the second tier. The memory controller 605 can generate a signal 620-a to be sent through the third set of TSVs 623. Signal 620-a can be considered a modified instance of the second signal 620 due to its nature of bypassing the first number of memory dies 625.

[0101] For example, signal 620-a may be identical to second signal 620, except that signal 620-a may be less susceptible to degradation associated with second signal 620 passing through first number of memory dies 625. Third set of TSVs 623 may be configured with structural features (e.g., similar three-dimensional dimensions and number) of first set of TSVs 621 or second set of TSVs 622. Memory controller 605 may be configured to communicate with repeater 607 when memory controller 605 transmits signal 620-a to second number of memory dies 626 through third set of TSVs 623. Repeater 607 may also be configured to receive signal 620-a through third set of TSVs 623 and retransmit signal 620-a to second number of memory dies 626 through second set of TSVs 622.

[0102] In some examples, the addition of the third set of TSVs 623 can enable the memory controller 605 to access the first number of memory dies 625 and the second number of memory dies 626 simultaneously, or at least during partially overlapping periods. In other words, the memory controller 605 can operate independently of the second number of memory dies in the second tier while sending the second signal 620 to the first number of memory dies 625 in the first tier. At the same time, or at least during partially overlapping periods, the memory controller 605 (e.g., a primary master) in cooperation with the repeater 607 (e.g., a redriver) can access the second number of memory dies 626 in the second tier due to the presence of the third set of TSVs 623 that simultaneously relay the signal 620-a and the second signal 620. Thus, the configuration depicted in diagram 601 can support expansion of memory capacity in the first and second tiers to improve the performance of the memory system.

[0103] Figures 7 to 8 A memory device is shown configured to transmit one or more binary symbol signals and / or one or more multi-symbol signals using signal paths within the memory device that are dedicated to transmitting a specific type of signal (e.g., binary symbol signals or multi-symbol signals). The memory device can transmit data across a large number of channels within the memory device using binary or multi-level signaling, such as NRZ and PAM, respectively. Signals can be transmitted via different dedicated signal paths, which can improve read and write times, reduce power consumption, and / or increase the reliability of the memory device. Figures 7 to 8 The features and / or functions described may be comparable to those described in Figures 1 to 6 and Figures 9 to 22 Combinations of features and / or functionality of other aspects of the described memory devices.

[0104] Figure 7 An example memory device 700 is shown according to various examples of the present disclosure. The memory device 700 may be a memory device 700 as shown in FIG. Figure 1 1. An example of the described system 100. The memory device 700 can include a memory controller 705, a first memory die 710, a second memory die 715, and a host 740. In some examples, the memory controller 705 can include an encoder 745 and a path selection component 750. In other examples, the first memory die 710 can be coupled to the memory controller 705 via a first signal path 720 and a second signal path 725.

[0105] The second memory die 715 can be coupled to the memory controller 705 via a third signal path 730 and a fourth signal path 735. In some examples, the first signal path 720, the second signal path 725, the third signal path 730, and the fourth signal path 735 can be as described in reference to FIG. Figure 11. In other examples, the first memory die 710 and the second memory die 715 may be as described with reference to FIG. Figure 1 105. Additionally or alternatively, for example, the memory controller 705 may be a memory controller 705 as described with reference to FIG. Figure 1 In other examples, the host 740 may be a memory controller 110 as described in Figure 1 An example of computing device 120 is described.

[0106] The first memory die 710 may include one or more memory cells (not illustrated), which may be referred to as a plurality of memory cells of the first memory die 710. In some examples, the memory controller 705 may transmit one or more signals to the plurality of memory cells of the memory die 710 via a first signal path 720 and a second signal path 725. For example, the first signal path 720 may be coupled with the memory controller 705 and the first memory die 710 and may be configured to transmit a multi-level signal to the first memory die 710. Additionally or alternatively, for example, the second signal path 725 may be coupled with the memory controller 705 and the first memory die 710 and may be configured to transmit a binary symbol signal to the first memory die 710.

[0107] In other examples, each of the first signal path 720 and the second signal path 725 can be configured to transmit a multi-level signal or a binary symbol signal to the first memory die 710. In some examples, each of the signal paths can be configured to transmit a specific signal type. For example, the first signal path 720 and the second signal path 725 can be configured to transmit a binary symbol signal. In other examples, the third signal path 730 and the fourth signal path 735 can be configured to transmit a multi-level signal. In other examples, any of the first signal path 720, the second signal path 725, the third signal path 730, and the fourth signal path 735 can be configured to transmit a binary symbol signal or a multi-level signal.

[0108] Memory die 715 may include one or more memory cells (e.g., as described in reference Figure 2715 ), which can be referred to as a plurality of memory cells of the second memory die 715. In some examples, the memory controller 705 can transmit one or more signals to the plurality of memory cells of the memory die 710 via the third signal path 730 and the fourth signal path 735. For example, the third signal path 730 can be coupled with the memory controller 705 and the second memory die 715 and can be configured to transmit a multi-level signal to the second memory die 715. Additionally or alternatively, for example, the fourth signal path 735 can be coupled with the memory controller 705 and the second memory die 715 and can be configured to transmit a binary-signed signal to the second memory die 715. In other examples, each of the third signal path 730 and the fourth signal path 735 can be configured to transmit a multi-level signal or a binary-signed signal to the second memory die 710.

[0109] In some examples, the path selection component 750 can facilitate the selection of one or more paths. For example, the path selection component 750 can select the first signal path 720 to transmit a signal to the first memory die 710. In other examples, the path selection component 750 can select the third signal path 730 to transmit a signal to the second memory die 715. In either example, the path selection component 750 can select the one or more signal paths based on the signal type (e.g., a binary symbol signal), the type of data being transmitted (e.g., control data), or the availability of a channel for data transmission.

[0110] In an additional example, each of the first memory die 710 and the second memory die 715 can receive a multi-level or binary-signed signal in response to a CE signal (e.g., chip enable). For example, the memory controller 705 can transmit the CE signal to one of the first memory die 710 or the second memory die 715. Upon receiving the CE signal, one of the first memory die 710 or the second memory die 715 can instruct the memory controller 705 to transmit the multi-level or binary-signed signal.

[0111] In some examples, the memory device 700 may include a bus binary symbol signal configured to transmit a multi-level signal or a binary level signal along any one of the signal paths. When transmitting the multi-level signal or the binary symbol signal, the bus or memory controller 705 may transmit the signal based on the timing of the system clock. In some examples, the system clock may be associated with (e.g., integrated with) the memory controller 705. In other examples, the system clock may be external to the memory controller 705. For example, the memory controller 705 may transmit the multi-level signal, the binary level signal, or both during the rising edge of the system clock, the falling edge of the system clock, or both.

[0112] Specific data may be transmitted in each of the multilevel signal and the binary symbol signal. For example, the multilevel signal may include control data, while the binary level signal may include metadata. In other instances, the multilevel signal may include metadata, while the binary level signal may include control data. In other instances, the multilevel signal may include metadata or control data, while the binary symbol signal may include metadata or control data. In other instances, either the multilevel signal or the binary symbol signal may include storage data. The storage data may correspond to one or more memory cells of the first memory die 710 or the second memory die 715. In some instances, one or both of the metadata and control data may be transmitted to one or more memory devices or one or more stacks of a single memory device. In other instances, one or both of the metadata and control data may be redundantly stored in more than one memory device. For example, one or both of the metadata and control data may be stored in a NAND device as long-term backup data and may be transmitted simultaneously to both the NAND device and the DRAM device.

[0113] In either configuration, the multi-level signal and the binary symbol signal can be transmitted simultaneously by the memory controller 705. For example, at least a portion of the multi-level signal can be transmitted to the first memory die 710 while, at the same time, at least a portion of the binary symbol signal can be transmitted to the second memory die 715. The signals can be transmitted so that part or all of each signal is transmitted at the same time—for example, during the rising edge of the system clock of the memory controller 705.

[0114] Each of the multi-level and binary-level signals can be modulated using a modulation scheme. In some examples, the multi-level and binary-level signals can be modulated by encoder 745. For example, the multi-level signal can be modulated using a pulse amplitude modulation (PAM) modulation scheme, while the binary symbol signal can be modulated using a non-return-to-zero (NRZ) scheme. In a PAM modulation scheme, multi-level signaling can include PAM4 signaling, PAM8 signaling, and the like. In this modulation scheme, for example, data (e.g., control data or metadata) can be encoded in terms of the amplitude of the signal. The amplitude or a single symbol can represent one bit of data. In other examples, the amplitude or a single symbol can represent two or more bits of data.

[0115] For example, a signal can be demodulated by detecting the amplitude level of the signal during a given time period. In another example, a binary-level signal can be modulated using a two-level amplitude modulation scheme (e.g., an NRZ modulation scheme). In such an example, a logic "1" can be represented by a first voltage level (e.g., a positive voltage), and a logic "0" can be represented by a second voltage level (e.g., a negative voltage). In other examples, the two-level amplitude modulation scheme can include non-return-to-zero level (NRZ(L)), non-return-to-zero inversion (NRZ(I)), non-return-to-zero mark (NRZ(M)), non-return-to-zero space (NRZ(S)), or non-return-to-zero change (NRZ(C)) modulation schemes.

[0116] Figure 8 An example process flow diagram 800 is shown according to various examples of the present disclosure. The process flow diagram 800 may illustrate a process flow diagram of a process flow diagram of a process according to various examples of the present disclosure. Figure 7 One or more operations performed by the described memory device 700. Process flow diagram 800 may include operations performed by a memory controller 805, a memory die 810, and a memory die 815. In some examples, memory controller 805, memory die 810, and memory die 815 may be instances of memory controller 705, memory die 710, and memory die 715, respectively, as described with reference to FIG. Figure 1 In other examples, the memory die 810 and the memory die 815 can be referred to as a first memory die 810 and a second memory die 815, respectively.

[0117] At block 820, the memory controller 805 may identify first data to be transferred to the first memory die 810. For example, the first memory die 810 may include one or more memory cells, which may be referred to as a plurality of memory cells. In some examples, the first memory die 810 may include ferroelectric memory cells, dynamic random access memory cells, NAND memory cells, NOR memory cells, or a combination thereof. The first data may include, for example, metadata or control data, and may be transferred to the first memory die 810 by, for example, a memory cell. Figure 1 The host computing device 120 is provided to the memory controller 805.

[0118] In other examples, the stored data may be stored by referring to Figure 1 The host computing device 120 described above is provided to the memory controller 805. In some examples, the storage data may be associated with one or more memory cells of the first memory die 810 or the second memory die 815. After identifying the first data, the memory controller 805 may determine the modulation scheme of the data at block 825. As described above with reference to Figure 7As described, the first data may be modulated using a multi-symbol modulation scheme (eg, PAM) or a binary symbol modulation scheme (eg, NRZ), which may correspond to multi-level and binary symbol signals, respectively.

[0119] At block 830, the memory controller 805 may select a signal path for transmitting the first data. The signal path may be, for example, as described in reference Figure 7 One of the first signal path 720, the second signal path 725, the third signal path 730, or the fourth signal path 735 described. Figure 7 As described above, the signal path may be a conductor in a through-silicon via (TSV). Once the signal path is selected, the memory controller 805 may transmit the first signal modulated using the modulation scheme to the first memory die 810 using the predetermined signal path via transmit 235. In some cases, the memory controller 805 may select the signal path. The memory controller 805 may identify one or more capabilities (e.g., bandwidth) of the signal path or the availability of the signal path to transmit the signal.

[0120] For example, the memory controller 805 may identify the type of signal that can be transmitted using a signal path. If the signal path is configured to transmit the type of signal requested for transmission (e.g., the signal is a multi-symbol signal and the signal path is configured to transmit multi-symbol signals), the memory controller 805 may select the given signal path. In some cases, the availability of the signal path (e.g., bandwidth) may also be considered when selecting the signal path. In other examples, the signal path may be selected by the memory controller 805 based on the type of signal being transmitted (e.g., a binary symbol signal). When transmitting the first signal, the memory controller 805 may transmit the first signal based on the timing of a system clock. In some examples, the system clock may be associated with (e.g., integrated with) the memory controller 805. In other examples, the system clock may be external to the memory controller 805. For example, the memory controller 805 may transmit the first signal during a rising edge of the system clock, a falling edge of the system clock, or both.

[0121] For example, the memory controller 805 may identify control data to be transmitted to the first memory die 810. After identifying the control data, the memory controller 805 may select a PAM modulation scheme to encode the control data in a multi-symbol signal and may select the first signal path 720 (as shown in FIG. Figure 7) to transmit a multi-symbol signal encoded with control data. The selection of signal path 720 can be based at least in part on a determination of a PAM modulation scheme. In some examples, selecting a different signal path (e.g., third signal path 730) can be based at least in part on selecting a different modulation scheme (e.g., an NRZ modulation scheme). In either example, the memory controller 805 can use a first signal path (e.g., signal path 720) to transmit a first signal modulated using the PAM modulation scheme to the first memory die 810.

[0122] In another example, the memory controller 805 may identify second data at block 840. The second data may include, for example, metadata or control data and may be provided to the memory controller 805 by a host (not illustrated). In other examples, the second data may include stored data that may be associated with the first memory die 810 or the second memory die 815. In some examples, the second data may be of the same data type as the identified first data, while in other examples, the second data may be of a different data type (e.g., metadata) than the identified first data. After identifying the second data, the memory controller 805 may determine a modulation scheme for the data at block 845. As described above, the second data may be modulated using a multi-symbol modulation scheme (e.g., PAM4) or a binary symbol modulation scheme (e.g., NRZ modulation).

[0123] At block 850, the memory controller 805 may select a signal path for transmitting the second data. The signal path may be, for example, as described in reference Figure 7 The first signal path 720, the second signal path 725, the third signal path 730, or the fourth signal path 735 are described. As also described above, the signal path can be a conductive line in the TSV. In some examples, the type of the signal path can be the same as the type of the signal path used to transmit the first signal. In other examples, the type of the signal path can be different from the type of the signal path used to transmit the first signal.

[0124] Once the signal path is selected, at block 850, the memory controller 805 may transmit a second signal modulated using the modulation scheme to the first memory die 810 using the predetermined signal path. This may be performed by transmitting 855. When transmitting the second signal, the memory controller 805 may transmit the first signal based on the timing of the system clock. For example, the memory controller 805 may transmit the second signal during the rising edge of the system clock, the falling edge of the system clock, or both. In other examples, the memory controller 805 may transmit the first and second signals simultaneously. For example, at least a portion of the first signal may be transmitted to the first memory die 810 while at the same time, at least a portion of the second signal may be transmitted to the second memory die 815. The signals may be transmitted so that a portion or all of each signal is transmitted at the same time, for example, during the rising edge of the memory controller 805 system clock.

[0125] For example, the memory controller 805 may identify the second control data to be transmitted to the first memory die 810. After identifying the second control data, the memory controller 805 may determine the NRZ modulation scheme of the second control data and may select, for example, the second signal path 725 (as shown in FIG. Figure 7 ) to transmit control data. The selection of signal path 725 can be based at least in part on the determination of the NRZ modulation scheme. Thus, the memory controller 805 can use the second signal path (e.g., signal path 720) to transmit a second signal modulated using the NRZ modulation scheme to the first memory die 810.

[0126] In another example, the memory controller 805 can transmit a first signal to the second memory die 815 via transmission 860. For example, the second memory die 815 can include one or more memory cells, which can be referred to as a plurality of memory cells. In some examples, the plurality of memory cells of the second memory die 815 can include memory cells of a different type than the first memory die 810.

[0127] By way of example, the first data may include control data and may be modulated using a multi-symbol modulation scheme. The first data may be transmitted, for example, via a third signal path (e.g., as shown in FIG. Figure 7 730 as described above) to the second memory die 815. However, in other examples, the first data may include different types of data and / or be modulated using an NRZ modulation scheme. In either case, the modulation scheme may be based at least in part on the data type of the first data (e.g., control data). The first data may then be transmitted, for example, via different signal paths (e.g., as described above). Figure 7 8. The fourth signal path 735 described above is transmitted to the second memory die 815.

[0128] Additionally or alternatively, the memory controller 805 may transmit a second signal to the second memory die 815, for example, via transmission 865. By way of example above, the second data may include metadata and may be modulated using an NRZ modulation scheme. The second data may be transmitted, for example, via a fourth signal path (e.g., as described in reference to FIG. Figure 1 735) to the second memory die 815. However, in other examples, the second data may include different types of data and / or be modulated using a PAM modulation scheme. In either case, the modulation scheme may be based at least in part on the data type (e.g., control data) of the first data or the second data. The second data may then be transmitted, for example, via a different signal path (e.g., as described with reference to FIG. Figure 1 8. The third signal path 730 described above is transmitted to the second memory die 815.

[0129] Figures 9 to 13 A memory device configured to support both multi-symbol signaling and binary symbol signaling is shown, and the memory device can utilize various signaling modes to adjust data transfer rate or reduce output pin count (e.g., reduce the number of active output pins in the signaling scheme). In some cases, the memory device may include a memory array coupled to a buffer, wherein the buffer is coupled to a multiplexer, the multiplexer configured to output a group of bits, such as a bit pair, that includes more than one bit. Additionally, the multiplexer may be coupled to a driver, wherein the driver may be configured to generate a symbol representing the group of bits. The symbol may represent an integer number of bits (e.g., a PAM4 symbol representing two bits) or a non-integer number of bits (e.g., a PAM3 symbol representing more than one but less than two bits). The symbol representing the group of bits may be output on an output pin of the memory device. Reference Figures 9 to 13 The features and / or functions described may be comparable to those described in Figures 1 to 8 and Figures 14 to 22 Combinations of features and / or functionality of other aspects of the described memory devices.

[0130] Figure 9 An example circuit 900 is shown according to various examples of the present disclosure. Circuit 900 may include a memory array 905, an output circuit 935, and an output pin 925. Output circuit 935 may include a buffer 910, a multiplexer 915, and a driver 920.

[0131] The memory array 905 can store data and can include a plurality of memory cells that can be volatile memory cells, non-volatile memory cells, or a combination thereof. The memory array 905 can include one or more memory dies (e.g., Figure 1105). In some examples, the memory array 905 can be coupled to the output circuit 935 and can be directly or indirectly coupled to the buffer 910 within the output circuit 935. For example, the memory array 905 can be coupled to a data bus, to which the buffer 910 is also coupled. The data bus can be a serial or parallel data bus. Other components not shown in the circuit 900 can also be coupled to the data bus, such as one or more memory controllers, memory sensing components, row or column decoders, clock signals, or other output circuits.

[0132] The data stored in the memory array 905 can be sensed or read by one or more memory sensing components, and the buffer 910 can store bits reflecting the data stored in the memory array 905 for a certain length of time before supplying such bits to the multiplexer 915. The buffer 910 can include several logically or physically distinct portions—for example, one or more logically or physically distinct buffers can be included within the buffer 910. For example, the buffer 910 can include at least a first buffer and a second buffer. The buffers included in the buffer 910 can be examples of first-in-first-out (FIFO) buffers.

[0133] The buffer 910 can supply multiple bits simultaneously to the multiplexer 915, for example, via a parallel interface. For example, in some instances, the buffer 910 can supply eight bits simultaneously to the multiplexer 915. Additionally, the buffer 910 can intermittently supply bits to the multiplexer 915. For example, the buffer 910 can supply a group of bits to the multiplexer 915 and wait a number of clock cycles before supplying a subsequent group of bits to the multiplexer 915. The number of clock cycles between each group of bits can be based at least in part on the number of clock cycles required for the multiplexer 915 to process, or at least in part, process, the previous group of bits.

[0134] Multiplexer 915, which may also be referred to as a serializer in some cases, can receive multiple groups of bits from buffer 910, such as bits output simultaneously by buffer 910, and can output the received bits sequentially. Thus, multiplexer 915 can act as a parallel-to-serial converter—for example, multiplexer 915 can receive parallel bits from buffer 910 and output corresponding serial bits.

[0135] In some cases, multiplexer 915 may include several logically or physically distinct portions—for example, one or more logically or physically distinct multiplexers may be included within multiplexer 915. The portions of multiplexer 915 may be arranged in parallel with one another, in series with one another, or in some other cascaded fashion (e.g., as multiple stages of multiplexing). For example, as shown in circuit 900, multiplexer 915 may include a first multiplexer 915-a, a second multiplexer 915-b, and a third multiplexer 915-c. Multiplexer 915-a may be an example of a first multiplexer that may be configured to process bits output by a first buffer in buffer 910.

[0136] Multiplexer 915-b may be an example of a second multiplexer that may be configured to process bits output by a second buffer in buffer 910. In some examples, first multiplexer 915-a and second multiplexer 915-b may each serialize the same number of bits. For example, first multiplexer 915-a and second multiplexer 915-b may each be a four-to-one multiplexer (e.g., each receiving four bits through four parallel inputs and outputting those four bits serially through a single serial output), and thus collectively comprise an eight-to-two multiplexer. The third multiplexer 915-c may be a two-to-one multiplexer that serializes the respective outputs of the first multiplexer 915-a and the second multiplexer 915-b, so that the first multiplexer 915-a, the second multiplexer 915-b, and the third multiplexer 915-c collectively function as an eight-to-one multiplexer. For example, the multiplexer 915-c may receive one bit of information from the multiplexer 915-a and one bit of information from the multiplexer 915-b, respectively, through separate parallel inputs, and output those two bits in series through a single serial output. In some cases, the buffer 910 may supply bits to the multiplexer 915 and then wait a predetermined number of clock cycles before supplying additional bits to the multiplexer 915.

[0137] In some examples, the multiplexer 915 can be coupled to a driver 920. The driver 920 can also be coupled to an output pin 925. The driver 920 can be configured to receive bits from the multiplexer 915, generate a symbol representing each bit received from the multiplexer 915, and supply such symbols to the output pin 925. For example, the driver 920 can be a bi-level signal driver and can generate a symbol for each bit output by the multiplexer 915 and supply the symbol to the output pin 925. In some cases, the bi-level signal driver encodes data using a non-return-to-zero (NRZ) modulation scheme, a unipolar coded modulation scheme, a bipolar coded modulation scheme, a Manchester coded modulation scheme, a PAM2 modulation scheme, and the like.

[0138] In some cases, the memory array 905 may be coupled to multiple circuits 900. For example, the memory array 905 may be coupled to eight circuits 900, and those eight circuits 900 may be collectively configured to output eight bi-level signal symbols (collectively representing eight bits of information stored in the memory array 905) at each rising edge of the clock signal, each falling edge of the clock signal, or each rising and falling edge of the clock signal. These may be examples of a x8 (or byte mode) bi-level signaling mode of operation. As another example, the memory array 905 may be coupled to sixteen circuits 900, and those sixteen circuits 900 may be collectively configured to output sixteen bi-level signal symbols (collectively representing sixteen bits of information stored in the memory array 905) at each rising edge of the clock signal, each falling edge of the clock signal, or each rising and falling edge of the clock signal. These may be examples of a x16 bi-level signaling mode of operation. One of ordinary skill will appreciate that other numbers of circuits 900 may be utilized in a bi-level signaling mode of operation.

[0139] Figure 10 An example circuit 1000 is shown according to various examples of the present disclosure. The circuit 1000 may include a memory array 1005, an output circuit 1035, and an output pin 1025. The output circuit 1035 may include a buffer 1010, a multiplexer 1015, and a driver 1020.

[0140] Memory array 1005 can store data and can include a plurality of memory cells, which can be volatile memory cells, non-volatile memory cells, or a combination thereof. In some examples, memory array 1005 can be coupled to output circuitry 1035 and can be directly or indirectly coupled to buffer 1010 within output circuitry 1035. For example, memory array 1005 can be coupled to a data bus, to which buffer 1010 is also coupled. The data bus can be a serial or parallel data bus. Other components not shown in circuitry 1000 can also be coupled to the data bus, such as one or more memory controllers, memory sensing components, row or column decoders, clock signals, or other output circuitry.

[0141] Data stored in the memory array 1005 may be sensed or read by one or more memory sensing elements, and the buffer 1010 may store bits reflecting the data stored in the memory array 1005 for a certain length of time before supplying such bits to the multiplexer 1015. The buffer 1010 may include several logically or physically distinct portions—for example, one or more logically or physically distinct buffers may be included within the buffer 1010. For example, the buffer 1010 may include at least a first buffer 1010-a and a second buffer 1010-b.

[0142] Buffer 1010-a and buffer 1010-b may be examples of FIFO buffers. The first buffer 1010-a may process bits corresponding to data stored in a first portion of the memory array 1005, and the second buffer 1010-b may process bits corresponding to data stored in a second portion of the memory array 1005. In some cases, the first portion of the memory array 1005 may be closer to the buffer 1010 than the second portion of the memory array 1005. The buffer 1010 may simultaneously supply multiple bits to the multiplexer 1015, for example, via a parallel interface. In some cases, the first buffer 1010-a and the second buffer 1010-b may process bits corresponding to data stored in the same portion of the memory array 1005, including data stored in the same memory cell within the memory array 1005 (for example, the memory cell may be a memory cell that supports storage of non-binary symbols, such as a four-level NAND memory cell programmable to one of four logical states, and the first buffer 1010-a may process the first bit and the second buffer 1010-b may process the second bit, the first bit and the second bit collectively representing the data stored in the memory cell).

[0143] For example, in some instances, buffer 1010 may supply eight bits simultaneously to multiplexer 1015. Additionally, buffer 1010 may intermittently supply bits to multiplexer 1015. For example, buffer 1010 may supply a group of bits to multiplexer 1015 and wait a number of clock cycles before supplying a subsequent group of bits to multiplexer 1015. The number of clock cycles between groups of bits may be based at least in part on the number of clock cycles required for multiplexer 1015 to process, or at least in part, the previous group of bits.

[0144] Multiplexer 1015 can receive multiple groups of bits from buffer 1010, such as bits output simultaneously by buffer 1010, through a certain number of parallel inputs and can output the received bits through a different number of parallel outputs. In some cases, multiplexer 1015 can output bits through a fewer number of parallel outputs than the number of parallel inputs through which multiplexer 1015 receives bits from buffer 1010. For example, multiplexer 1015 can receive eight bits simultaneously from buffer 1010 and output those bits through two parallel outputs—e.g., as bit pairs. The bit pairs can represent data stored in memory array 1005. Thus, multiplexer 1015 can function as a partial parallel-to-serial converter or a partial serializer.

[0145] In some cases, the multiplexer 1015 may include several logically or physically distinct portions—for example, one or more logically or physically distinct multiplexers may be included within the multiplexer 1015. The portions of the multiplexer 1015 may be arranged in parallel with each other, in series with each other, or in some other cascaded fashion (e.g., as multiple stages of multiplexing). For example, as shown in the circuit 1000, the multiplexer 1015 may include a first multiplexer 1015-a and a second multiplexer 1015-b.

[0146] The first multiplexer 1015-a may be an example of a multiplexer that may be configured to process bits output by the first buffer 1010-a. The second multiplexer 1015-b may be an example of a multiplexer that may be configured to process bits output by the second buffer 1010-b. The first multiplexer 1015-a may output a first bit in a group of bits (e.g., a bit pair) to the driver 1020, and the second multiplexer 1015-b may output a second bit in the group of bits (e.g., a bit pair) to the driver 1020. The first multiplexer 1015-a may process the first bit in the bit pair output from the first buffer 1010-a, and the second multiplexer 1015-b may process the second bit in the bit pair output from the second buffer 1010-b.

[0147] In some examples, a first bit in a bit pair may represent data stored within a first portion of the memory array 1005. A second bit in the bit pair may represent data stored within a second portion of the memory array 1005, which is different from the first portion of the memory array 1005. In some cases, the first portion of the memory array 1005 may be closer to the buffer 1010 than the second portion of the memory array 1005. The buffer 1010 may simultaneously supply multiple bits to the multiplexer 1015, for example, via a parallel interface.

[0148] In some cases, the first bit in the bit pair and the second bit in the bit pair may represent data stored in the same portion of the memory array 1005, including data stored in the same memory cell within the memory array 1005 (for example, the memory cell may be a memory cell that supports storage of non-binary symbols, such as a four-level NAND memory cell programmable to one of four logic states, and the first buffer 1010-a may process the first bit and the second buffer 1010-b may process the second bit, the first bit and the second bit together representing the data stored in the memory cell).

[0149] In some examples, the first multiplexer 1015-a and the second multiplexer 1015-b can each be an example of a four-to-one multiplexer, and the first multiplexer 1015-a and the second multiplexer 1015-b can thus collectively comprise an eight-to-two multiplexer. A person of ordinary skill will appreciate that the multiplexer 1015 can be configured to output groups comprising more than two bits (e.g., via more than two parallel outputs).

[0150] In some examples, multiplexer 1015 can be coupled to driver 1020. Driver 1020 can also be coupled to output pin 1025. Driver 1020 can be configured to receive each group of bits (e.g., a bit pair) from multiplexer 1015, generate a symbol representing each group of bits received from multiplexer 1015, and supply such symbols to output pin 1025. For example, driver 1020 can receive one bit of a bit pair from multiplexer 1015-a and the other bit of a bit pair from multiplexer 1015-b, generate a symbol representing the bit pair, and supply the symbol representing the bit pair to output pin 1025.

[0151] In some cases, driver 1020 may be a pulse amplitude modulation (PAM) driver, and the symbols representing the bit pairs may be multi-symbol signals (e.g., PAM4 symbols). In other cases, driver 1020 may receive multiple groups of bits from multiplexer 1015 that include more than two bits (e.g., three bits, four bits, five bits, six bits, seven bits, eight bits), and driver 1020 may generate symbols that each represent more than two bits. For example, driver 1020 may receive multiple groups of three bits from multiplexer 1015 and generate multi-symbol signals (e.g., PAM8 symbols) that represent each bit group.

[0152] In some cases, the memory array 1005 can be coupled to multiple circuits 1000. For example, the memory array 1005 can be coupled to several circuits 1000 (in some cases, eight circuits), and these several circuits 1000 can be collectively configured to output a similar number of multi-symbol signal symbols at each rising edge of the clock signal, each falling edge of the clock signal, or each rising and falling edge of the clock signal. For example, each circuit 1000 can output a symbol of a multi-level modulation scheme, where the symbol represents two bits of data. If there are eight circuits 1000, then these eight symbols will collectively represent sixteen bits of data stored by the memory array 1005.

[0153] These may be examples of an x8 multi-symbol signal operating mode. As another example, the memory array 1005 may be coupled to sixteen circuits 1000, and those sixteen circuits may be collectively configured to output sixteen multi-symbol signal symbols (e.g., sixteen PAM4 symbols collectively representing 32 bits of information stored within the memory array 1005) at each rising edge of the clock signal, each falling edge of the clock signal, or each rising and falling edge of the clock signal. These may be examples of a x16 multi-symbol signal operating mode. One of ordinary skill will appreciate that other numbers of additional circuits 1000 may be utilized in the multi-symbol signal operating mode.

[0154] In some examples, circuit 1000 can operate at the same symbol rate (which may also be referred to as the baud rate) as circuit 900 while providing double the output data rate of circuit 900. In some examples, circuit 1000 can operate at half the symbol rate (which may also be referred to as the baud rate) of circuit 900 while providing the same output data rate per pin (which may also be referred to as the bandwidth per pin) as circuit 900. Thus, circuit 1000 can advantageously provide the same data rate per pin as circuit 900 while allowing the symbol rate to be reduced (e.g., while allowing the clock rate that may determine the symbol rate to be reduced), which can improve the reliability, robustness, or power consumption of circuit 1000 and a system or circuits coupled to the system.

[0155] In some examples, circuit 1000 can be obtained by disabling or bypassing third multiplexer 915-c of circuit 900. Driver 1020 includes both a multi-sign signal driver and a binary-sign signal driver and can be configured to generate a multi-sign signal symbol for each group of bits received from multiplexer 1015 and a binary-sign signal symbol for each bit received from multiplexer 1015.

[0156] Figure 11 An example circuit 1100 is shown according to various examples of the present disclosure. Circuit 1100 may include a memory array 1105, an output circuit 1135, and an output pin 1125. Output circuit 1135 may include a buffer 1110, a multiplexer 1115, and a driver 1120. Circuit 1100 may illustrate one or more aspects of circuit 900 or circuit 1000.

[0157] Memory array 1105 can store data and can include a plurality of memory cells, which can be volatile memory cells, non-volatile memory cells, or a combination thereof. In some examples, memory array 1105 can be coupled to output circuitry 1135 and can be directly or indirectly coupled to buffer 1110 within output circuitry 1135. For example, memory array 1105 can be coupled to a data bus, to which buffer 1110 is also coupled. The data bus can be a serial or parallel data bus. Other components not shown in circuitry 1100 can also be coupled to the data bus, such as one or more memory controllers, memory sensing components, row or column decoders, clock signals, or other output circuitry.

[0158] The data stored in the memory array 1105 may be sensed or read by one or more memory sensing components, and the buffer 1110 may store bits reflecting the data stored in the memory array 1105 for a certain length of time before supplying such bits to the multiplexer 1115. The buffer 1110 may include several logically or physically distinct portions—e.g., one or more logically or physically distinct buffers may be included within the buffer 1110.

[0159] For example, buffer 1110 may include at least a first buffer 1110-a and a second buffer 1110-b. Buffer 1110-a and buffer 1110-b may be examples of FIFO buffers. First buffer 1110-a may process bits corresponding to data stored in a first portion of memory array 1105, and second buffer 1110-b may process bits corresponding to data stored in a second portion of memory array 1105. In some cases, the first portion of memory array 1105 may be closer to buffer 1110 than the second portion of memory array 1105. In some cases, the first buffer 1110-a and the second buffer 1110-b may process bits corresponding to data stored in the same portion of the memory array 1105, including data stored in the same memory cell within the memory array 1105 (for example, the memory cell may be a memory cell that supports storage of non-binary symbols, such as a four-level NAND memory cell programmable to one of four logical states, and the first buffer 1110-a may process the first bit and the second buffer 1110-b may process the second bit, the first bit and the second bit collectively representing the data stored in the memory cell).

[0160] The buffer 1110 can supply multiple bits simultaneously to the multiplexer 1115, for example, via a parallel interface. Alternatively, the buffer 1110 can intermittently supply bits to the multiplexer 1115. For example, the buffer 1110 can supply a group of bits to the multiplexer 1115 and wait a number of clock cycles before supplying a subsequent group of bits to the multiplexer 1115. The number of clock cycles between groups of bits can be based at least in part on the number of clock cycles required for the multiplexer 1115 to process, or at least in part, process, the previous group of bits.

[0161] Multiplexer 1115 can receive multiple groups of bits from buffer 1110, such as bits output simultaneously by buffer 1110, through a certain number of parallel inputs and can output the received bits through a different number of parallel outputs. In some cases, multiplexer 1115 can output bits through a fewer number of parallel outputs than the number of parallel inputs through which multiplexer 1115 receives bits from buffer 1110. For example, multiplexer 1115 can receive sixteen bits simultaneously from buffer 1110 and output those bits through two parallel outputs—e.g., as bit pairs. The bit pairs can represent data stored in memory array 1105. Thus, multiplexer 1115 can function as part parallel-to-serial converter or part serializer.

[0162] In some cases, the multiplexer 1115 may include several logically or physically distinct sections—for example, one or more logically or physically distinct multiplexers may be included within the multiplexer 1115. The sections of the multiplexer 1115 may be arranged in parallel with each other, in series with each other, or in some other cascaded fashion (e.g., as multiple stages of multiplexing). For example, as shown in circuit 1100, the multiplexer 1115 may include a first multiplexer 1115-a, a second multiplexer 1115-b, a third multiplexer 1115-c, a fourth multiplexer 1115-d, a fifth multiplexer 1115-e, and a sixth multiplexer 1115-f.

[0163] Multiplexer 1115-a may be an example of a first multiplexer that may be configured to process bits output by a first buffer 1110-a in buffers 1110. Multiplexer 1115-b may be an example of a second multiplexer that may be configured to process additional bits output by the first buffer 1110-a in buffers 1110. In some examples, first multiplexer 1115-a and second multiplexer 1115-b may each serialize the same number of bits. For example, first multiplexer 1115-a and second multiplexer 1115-b may each be a four-to-one multiplexer (e.g., each may receive four bits through four parallel inputs and output those four bits in series through a single serial output), and thus collectively comprise an eight-to-two multiplexer. The third multiplexer 1115-c may be a two-to-one multiplexer, such that the first multiplexer 1115-a, the second multiplexer 1115-b, and the third multiplexer 1115-c collectively function as an eight-to-one multiplexer. For example, the third multiplexer 1115-c may receive one bit of information from the first multiplexer 1115-a and one bit of information from the second multiplexer 1115-b through separate parallel inputs, respectively, and output the two bits in series through a single serial output.

[0164] In some examples, multiplexer 1115 may additionally include a fourth multiplexer 1115-d, a fifth multiplexer 1115-e, and a sixth multiplexer 1115-f. Multiplexer 1115-d may be an example of a first multiplexer that may be configured to process bits output by second buffer 1110-b in buffer 1110. Multiplexer 1115-e may be an example of a second multiplexer that may be configured to process bits output by second buffer 1110-b in buffer 1110. In some examples, fourth multiplexer 1115-d and fifth multiplexer 1115-e may both serialize the same number of bits.

[0165] For example, the fourth multiplexer 1115-d and the fifth multiplexer 1115-e can each be a four-to-one multiplexer (e.g., each can receive four bits through four parallel inputs and can output those four bits in series through a single serial output), and thus collectively comprise an eight-to-two multiplexer. The sixth multiplexer 1115-f can be a two-to-one multiplexer, such that the fourth multiplexer 1115-d, the fifth multiplexer 1115-e, and the sixth multiplexer 1115-f collectively function as an eight-to-one multiplexer. For example, the sixth multiplexer 1115-f can receive one bit of information from the fourth multiplexer 1115-d and one bit of information from the fifth multiplexer 1115-e, respectively, through different parallel inputs, and output those two bits in series through a single serial output.

[0166] Thus, multiplexer 1115 can function as a sixteen-to-two multiplexer comprising two eight-to-one multiplexers arranged in parallel, with each eight-to-one multiplexer processing bits from a different portion of buffer 1110. One of ordinary skill in the art will appreciate that multiplexer 1115 can be configured to output groups comprising more than two bits (e.g., through more than two parallel outputs).

[0167] In some examples, the multiplexer 1115 can be coupled to a driver 1120. The driver 1120 can also be coupled to an output pin 1125. The driver 1120 can be configured to receive each group of bits, e.g., a bit pair, from the multiplexer 1115, generate a symbol representing each group of bits received from the multiplexer 1115, and supply such symbols to the output pin 1125. For example, the driver 1120 can receive one bit of the bit pair from the third multiplexer 1115-c and the other bit of the bit pair from the sixth multiplexer 1115-f, generate a symbol representing the bit pair, and supply the symbol representing the bit pair to the output pin 1125.

[0168] In some cases, driver 1120 may be a multi-symbol signal driver, and the symbols representing the bit pairs may be multi-symbol signal symbols. In other cases, driver 1120 may receive multiple groups of bits from multiplexer 1115 that include more than two bits, and driver 1120 may generate symbols that each represent more than two bits. For example, driver 1120 may receive multiple groups of three bits from multiplexer 1115 and generate multi-symbol signal symbols (e.g., PAM8 symbols) representing each bit group.

[0169] In some cases, the memory array 1105 can be coupled to multiple circuits 1100. For example, the memory array 1105 can be coupled to eight circuits 1100, and those eight circuits can be collectively configured to output eight multi-symbol signal symbols (e.g., eight PAM4 symbols collectively representing sixteen bits of information stored within the memory array 1105) at each rising edge of the clock signal, each falling edge of the clock signal, or each rising and falling edge of the clock signal. These can be additional examples of a x8 multi-symbol signal operating mode.

[0170] As another example, the memory array 1105 can be coupled to sixteen circuits 1100, and those sixteen circuits can be collectively configured to output sixteen multi-symbol signal symbols (e.g., sixteen PAM4 symbols collectively representing 32 bits of information stored within the memory array 1105) at each rising edge of the clock signal, each falling edge of the clock signal, or each rising and falling edge of the clock signal. These can be additional examples of a x16 multi-symbol signal operating mode. One of ordinary skill will appreciate that other numbers of additional circuits 1100 can be utilized in the multi-level signal operating mode.

[0171] In some examples, circuit 1100 can operate at the same symbol rate as circuit 900 while providing double the per-pin output data rate of circuit 900. Thus, circuit 1100 can advantageously achieve an increase in the per-pin data rate at which data stored in a memory array can be output without requiring an increase in the symbol rate (e.g., without requiring an increase in the clock rate that determines the symbol rate).

[0172] In some examples, circuit 900 can be derived from circuit 1100 by disabling or bypassing any eight-to-one multiplexers within multiplexer 1115 (e.g., disabling or bypassing first multiplexer 1115-a, second multiplexer 1115-b, and third multiplexer 1115-c, or fourth multiplexer 1115-d, fifth multiplexer 1115-e, and sixth multiplexer 1115-f). Driver 1120 includes both a multi-symbol signal driver and a binary symbol signal driver and can be configured to generate a multi-symbol signal symbol for each group of bits received from multiplexer 915 and a binary symbol signal symbol for each bit received from multiplexer 915.

[0173] In some instances, circuit 1000 can be obtained from circuit 1100 by disabling or bypassing any eight-to-one multiplexers within multiplexer 1115 (e.g., disabling or bypassing first multiplexer 1115-a, second multiplexer 1115-b, and third multiplexer 1115-c or fourth multiplexer 1115-d, fifth multiplexer 1115-e, and sixth multiplexer 1115-f) and disabling the remaining two-to-one multiplexers (e.g., disabling or bypassing third multiplexer 1115-c or sixth multiplexer 1115-f).

[0174] Figure 12 An example circuit 1200 according to various examples of the present disclosure is shown. The circuit 1200 may include a memory array 1205, an output circuit 1235, and an output pin 1225. The output circuit 1235 may include a buffer 1210, a multiplexer 1215, a first driver 1220-a, and a second driver 1220-b. The output circuit 1235 may be incorporated into a reference Figure 9 、 10 and 11 describe aspects of the output circuits 935, 1035, or 1135.

[0175] Memory array 1205 can store data and can include a plurality of memory cells, which can be volatile memory cells, non-volatile memory cells, or a combination thereof. In some examples, memory array 1205 can be coupled to output circuitry 1235 and can be directly or indirectly coupled to buffer 1210 within output circuitry 1235. For example, memory array 1205 can be coupled to a data bus, to which buffer 1210 is also coupled. The data bus can be a serial or parallel data bus. Other components not shown in circuitry 1200 can also be coupled to the data bus, such as one or more memory controllers, memory sensing components, row or column decoders, clock signals, or other output circuitry.

[0176] The data stored in the memory array 1205 can be sensed or read by one or more memory sensing components, and the buffer 1210 can store bits reflecting the data stored in the memory array 1205 for a certain length of time before supplying the bits to the multiplexer 1215. The buffer 1210 can incorporate a reference Figure 9 、 10 and 11 describe aspects of buffers 910, 1010, or 1110.

[0177] Multiplexer 1215 may be an example of a multiplexer that may be configured to process bits output by buffer 1210. In some cases, multiplexer 1215 may incorporate a reference Figure 9 、 101 and 11. The memory controller can configure multiplexer 1215 to output multiple groups of bits (e.g., bit pairs) or a single bit. In some cases, the bit pairs can represent data stored in memory array 1205. Multiplexer 1215 can be coupled to first driver 1220-a and second driver 1220-b. In some cases, second driver 1220-b can be parallel to first driver 1220-a. First driver 1220-a and second driver 1220-b can also be coupled to output pin 1225.

[0178] In some examples, the first driver 1220-a can be configured to receive bit pairs from the multiplexer 1215, generate symbols representing the bit pairs received from the multiplexer 1215, and supply such symbols to the output pin 1225. For example, the first driver 1220-a can be a multi-level signal driver and can generate multi-level signal symbols for each bit pair output by the multiplexer 1215 and supply those multi-level signal symbols to the output pin 1225.

[0179] In some cases, the second driver 1220-b can be configured to receive bits from the multiplexer 1215, generate a sign representing each bit received from the multiplexer 1215, and supply such a sign to the output pin 1225. For example, the second driver 1220-b can be a binary sign signal driver and can generate a binary sign signal symbol for each bit output by the multiplexer 1215 and supply those binary sign signal symbols to the output pin 1225.

[0180] In some cases, the memory array 1205 can be coupled to multiple circuits 1200, and the memory controller can configure one or more of the multiple circuits 1200 to implement a binary symbol signal or a multi-symbol signal (eg, PAM4) mode of operation.

[0181] Figure 13 1 shows an example circuit 1300 according to various examples of the present disclosure. The circuit 1300 may include a memory array 1305, a memory controller 1310, a data bus 1315, an output circuit 1335, and an output pin 1325. The memory array 1305 may be a memory controller 1310, a data bus 1315, an output circuit 1335, and an output pin 1325. Figures 9 to 12 Examples of memory arrays 905, 1005, 1105, and 1205 are described. Output pins 1325 may be as described in reference Figures 9 to 12 Examples of output pins 925, 1025, 1125, and 1225 are described. Output circuit 1335 may be as described in reference Figures 9 to 12Examples of output circuits 935, 1035, 1135, and 1235 are described. Circuit 1300 may include one or more aspects of circuits 900, 1000, 1100, and 1200.

[0182] Memory array 1305 can store data and can include a plurality of memory cells, which can be volatile memory cells, non-volatile memory cells, or a combination thereof. In some examples, memory array 1305 can be coupled to output circuitry 1335. For example, memory array 1305 can be coupled to data bus 1315, to which output circuitry 1335 is also coupled. Data bus 1315 can be a serial data bus or a parallel data bus. Memory controller 1310 can also be coupled to data bus 1315. Other components not shown in circuit 1300 can also be coupled to data bus 1315, such as one or more memory sensing components, row or column decoders, clock signals, or other output circuitry.

[0183] In some examples, the data bus 1315 may be coupled to four, eight, sixteen, or thirty-two output circuits 1335, and those output circuits 1335 may be collectively configured by the memory controller 1310 to each output binary sign signal symbols (collectively representing four, eight, sixteen, or thirty-two bits of information stored within the memory array 1305). These operating modes may be referred to as x4, x8 (or byte mode), x16, or x32 binary sign signal operating modes, respectively.

[0184] In some cases, data bus 1315 may be coupled to four, eight, sixteen, or thirty-two output circuits 1335, and those circuits may be collectively configured by memory controller 1310 to each output multi-symbol signal symbols (collectively representing eight, sixteen, thirty-two, or sixty-four bits of information stored within memory array 1305). These operating modes may be referred to as x4, x8, x16, or x32 multi-symbol signal operating modes, respectively.

[0185] In some examples, the memory controller 1310 may detect a period of inactivity (which may be referred to as idle time) or a period of output data rate below a threshold data rate for a duration greater than or equal to a threshold duration and then transmit a signal to switch operating modes. For example, the memory controller 1310 may monitor a symbol rate associated with one or more output pins (which may include identifying an associated clock rate), determine the data rate of the one or more output pins based on the symbol rate (e.g., based on the number of bits represented by each symbol, which may be known to the memory controller 1310 based on the current signaling pattern), compare the data rate to one or more threshold data rates, determine the length of time the data rate is above or below the threshold data rate, and adjust the signaling pattern at the one or more output pins between binary symbol signals or multi-symbol signal orders, or alternatively or additionally, adjust the number of active output pins to optimize the output data rate, the number of active output pins, or power consumption based on the observed conditions.

[0186] For example, the circuit 1300 can switch from operating eight output circuits 1335 to operating sixteen output circuits 1335. That is, a signaling mode that outputs multi-level signal symbols on a certain number of output pins 1325 can be disabled, and a signaling mode that outputs bi-level signal symbols on the same, different, or additional output pins 1325 can be enabled. In some examples, the circuit 1300 is capable of operating eight output circuits 1335 or sixteen output circuits 1335 on the same die (i.e., the same piece of silicon). In some cases, the circuit 1300 can act as an external master component to a controlled device, and the memory controller 1310 can adjust the signaling mode at one or more output pins between the order of binary symbol signals or multi-symbol signals in response to commands from the master component, or alternatively or additionally, adjust the number of active output pins.

[0187] In some examples, the memory controller 1310 can be configured to determine a first signaling mode for the circuit 1300 and configure the one or more output circuits 1335 to generate non-binary symbols each representing two or more bits output by the memory array 1305. For example, the first signaling mode can be an example of an x8 multi-symbol signaling mode of operation or an x16 multi-symbol signaling mode of operation. In some cases, the memory controller 1310 can be configured to determine a second signaling mode for the circuit 1300 and configure the one or more output circuits 1335 to generate binary symbols each representing less than two bits output by the memory array 1305.

[0188] For example, the second signaling mode may be an instance of a x8 binary symbol signaling mode of operation or a x16 binary symbol signaling mode of operation. In some cases, the first signaling mode and the second signaling mode may utilize the same symbol rate. In other examples, the first signaling mode and the second signaling mode may utilize different symbol rates. For example, a multi-symbol signaling (e.g., PAM4) mode of operation may utilize a symbol rate that is less than (half) the symbol rate used for a binary symbol signaling mode of operation, but provide the same data rate per pin while having improved robustness, reliability, or power consumption characteristics, or may utilize the same symbol rate but provide a greater (e.g., double) data rate per pin.

[0189] In some cases, the second signaling mode can be configured to support the full bandwidth of the memory device using half of the available I / O pins. By applying PAM4 signaling to half of the memory device's I / O pins, the same bandwidth can be achieved as using all I / O pins and NRZ signaling. This configuration can increase the number of memory dies that can be connected to the channel by reducing the I / O pin count per die. In some examples, eight I / O pins can be connected, while another eight can be unconnected, so mode switching may not be available. The memory device can operate the eight connected I / O pins in either PAM4 or NRZ mode.

[0190] In some cases, each output circuit 1335 may include a multiplexer. For example, memory controller 1310 may configure the multiplexers of at least eight output circuits 1335 to output a first output type during a first signaling mode. For example, the first output type may be a group of bits (e.g., a bit pair) and may correspond to a multi-symbol signal (e.g., PAM4) operating mode. In other examples, memory controller 1310 may configure the multiplexers of at least sixteen output circuits 1335 to output a second output type during a second signaling mode.

[0191] For example, the second output type can be a bit and can correspond to a binary symbol signal operating mode. The memory controller 1310 can also detect a data rate associated with the memory array 1305 over a certain duration and determine an operating mode based on the detected data rate (e.g., determining whether to output binary symbol signal symbols, multi-symbol signal symbols, or other types of symbols, determining the number of output pins 1325 through which to output symbols, or determining a symbol rate).

[0192] For example, if the data rate is above a threshold data rate, a first signaling mode may be determined that uses higher-order symbols (e.g., multi-symbol signals rather than binary symbol signals), a greater number of output pins 1325 (e.g., x16 rather than x8), a higher symbol rate, or a combination thereof, e.g., to support the higher data rate. As another example, if the data rate is below a threshold data rate, a second signaling mode may be determined that uses lower-order symbols (e.g., binary symbol signals rather than multi-symbol signals), a smaller number of output pins 1325 (e.g., x8 rather than x16), a lower symbol rate, or a combination thereof, e.g., to support the lower data rate while conserving power or improving the reliability or robustness of the output signal.

[0193] Figures 14 to 19 A memory device, waveforms, and a process for dynamically selecting a modulation scheme based on one or more parameters associated with the memory device are shown. For example, the memory device can dynamically switch between modulation schemes and, in some cases, frequencies, so that operating parameters such as bandwidth or power can be adapted or met. Because transmitting at different modulation schemes and frequencies varies the amount of bandwidth provided and power consumed, the memory device can select a combination of modulation scheme and frequency that provides sufficient bandwidth without consuming excessive power. Figures 14 to 19 The features and / or functions described may be comparable to those described in Figures 1 to 13 and Figures 20 to 22 Combinations of features and / or functionality of other aspects of the described memory devices.

[0194] Although described with reference to memory devices, the techniques described herein can be implemented by any type of device (e.g., the techniques described herein can be implemented by a CPU or GPU communicating with a modem or other peripheral device). The techniques described herein can be used for wireless communications (e.g., communications involving signals sent over the air), wired communications (e.g., communications involving signals sent over a solid medium), or both. In some cases, the techniques described herein can be used in wired systems on a substrate.

[0195] Figure 14 1400 according to various embodiments of the present invention. In some cases, the circuit 1400 may be a reference circuit. Figure 3 Thus, many features of circuit 1400 are similar to features of circuit 300, and some descriptions of certain features are not repeated in the figures.

[0196] Circuit 1400 may include one or more internal signal paths 1415-a through 1415-N coupling at least one memory die 1403 and memory controller 1401. Internal signal paths 1415 may be configured to transmit multi-symbol signals 1420 or binary symbol signals 1425, or both. Memory die 1403 may be a reference Figure 1 and 3 105, 305. The memory controller 1401 may be referenced to Figure 1 and 3 The example of memory controller 110, 310 described in FIG. 14 is a block diagram of a memory controller 110, 310. The signal path 1415 may be referenced to FIG. Figure 1 and 3 Examples of depicted signal paths 115, 315. In some cases, internal signal path 1415 can be an example of a data bus.

[0197] Memory controller 1401 can be coupled to (e.g., be in electronic communication with) host 1430, which may or may not be part of circuit 1400. Host 1430 can be a system-on-chip (SoC) or a processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU). Although shown as separate components, in some cases, host 1430 and memory controller 1401 can be the same component or can be part of a common SoC. Although described with reference to a memory interface, the techniques described herein can be implemented for non-memory interfaces (e.g., between non-memory components within a device, or between two devices).

[0198] Memory controller 1401 may include one or more driver circuits ("drivers") 1405. Driver 1405 may be in electronic communication with a signal path 1415 (e.g., a data bus) and may be configured to transmit (e.g., send or transmit) multi-level signals and / or binary-level signals over the one or more signal paths 1415 (e.g., a data bus). For example, driver 1405 may include circuitry that converts one or more bit streams into multi-level and / or binary-level signals. A bit stream may be a number of consecutive (e.g., serialized) bits representing a data set. In some cases, driver 1405 may include one or more drivers 1405 that are segmented (e.g., assigning a corresponding different number of legs of driver 1405 to each signal to be driven) to drive multiple (e.g., more than one) voltage levels on internal signal path 1415.

[0199] The driver 1405 may include an encoder 1440 coupled to (e.g., in electronic communication with) a driver circuit 1435. The encoder 1440 may be configured to receive one or more bit streams 1445 and convert (e.g., encode) the bit streams 1445 into one or more control signals 1450. The driver circuit 1435 may be configured to receive a control signal 1425 and drive a voltage on an internal signal path 1415 based on the control signal 1425. The voltage amplitude may represent one or more bits. Thus, a binary-level signal or a multi-level signal may be output by the driver circuit 1435 by varying the voltage amplitude driven on the internal signal path 1415. Whether a signal is transmitted as a binary-level signal or as a multi-level signal may be determined by the type of modulation scheme used to modulate the signal.

[0200] The type of modulation scheme used for transmission (e.g., the type of signal output by driver 1405) can be controlled by memory controller 1401 and can be based on operating parameters associated with memory controller 1401, host 1430, a device of which circuit 1400 is a part, or an application on the device. Because different modulation schemes consume different amounts of power and provide different bandwidths, memory controller 1401 can dynamically switch between modulation schemes to adjust the power consumed and the bandwidth provided for changing power constraints and bandwidth requirements (e.g., demand).

[0201] In addition to the driver 1405, the memory controller 1401 may also be in electronic communication with one or more clock circuits 1410. The clock circuit 1410 may be configured to generate clock pulses that can be used as a reference for the timing of other components. For example, the clock circuit 1410 may be configured to generate a first clock signal at a first frequency and a second clock signal at a second frequency. The term frequency may refer to the reciprocal of the pulse duration used to represent a symbol in binary level signaling or multi-level signaling. The first clock signal may represent a first clock rate, and the second clock signal may represent a second clock rate. In some cases, the memory controller 1401 may control the output of the clock circuit 1410 (e.g., the memory controller 1401 may control the frequency of the clock signal or the clock rate generated by the clock circuit).

[0202] Clock circuit 1410 may be in electronic communication with driver 1405. For example, driver 1405 or a sampling component in electronic communication with driver 1405 may sample clock pulses generated by clock circuit 1410. The sampled clock pulses may be used as a reference for transmitting multi-level and binary-level signals at a frequency determined by memory controller 1401. For example, driver 1405 or an associated component may reference the clock pulses output by clock circuit 1410 to determine the frequency at which to transmit binary-level or multi-level signals. Because transmitting at different frequencies consumes different amounts of power and provides different bandwidths, memory controller 1401 may dynamically select a frequency for transmitting to accommodate changing power constraints and bandwidth requirements. In some cases, memory controller 1401 may dynamically select a combination of modulation schemes and frequencies to accommodate changing power constraints and bandwidth requirements, or to accommodate some other operating parameter.

[0203] In one example, memory controller 1401 may receive a first set of data in a first number of bitstreams. For example, memory controller 1401 may receive the first number of bitstreams from a data array or a user input interface in electronic communication with memory controller 1401 (e.g., at encoder 1440). According to the techniques described herein, memory controller 1401 may generate a first signal having a first number of levels. The first signal may be a binary level signal (e.g., an NRZ signal, such as signal 1425) or a multi-level signal (e.g., a PAM4 signal, such as signal 1420). In some cases, the first signal may be based on the first number of bitstreams. For example, the first signal may represent a first set of data delivered via the first number of bitstreams. In some cases, the number of levels may be based on the first number of bitstreams. For example, the first number of levels may be twice the number of bitstreams. In some cases, the first number of bitstreams may be different from the first number of levels.

[0204] After receiving the first data set, memory controller 1401 may receive a second data set in a second number of bitstreams that is different from the first number of bitstreams. For example, memory controller 1401 may receive the first number of bitstreams from a data array or a user input interface in electronic communication with memory controller 1401. The first number of bitstreams may be the same as or different from the second number of bitstreams. In some cases, the first data set is associated with a first application, and the second data set may be associated with a second application.

[0205] According to the techniques described herein, memory controller 1401 can determine an operating parameter associated with a device of which memory controller 1401 is a part. For example, memory controller 1401 can determine an operating parameter associated with host 1430. The operating parameter can be a requirement, request, condition, metric, demand, or value. The determination of the operating parameter can be based on receiving the second data set, or it can be independent of receiving the second data set (e.g., the determination of the operating parameter can occur before receiving the second data set). The operating parameter can be a temperature parameter, a bandwidth parameter, a power parameter, a data rate parameter, or the like, or a combination thereof.

[0206] After determining the operating parameters, the memory controller may generate a second signal having a second number of levels different from the first number of levels. Generating the second signal may be based on the determined operating parameters and the second number of bitstreams. For example, the second signal may represent a second set of data delivered in the second bitstream, and / or the second number of levels may vary with the second number of bitstreams (e.g., may be twice the number of bitstreams). In some cases, the second number of bitstreams is different from the second number of levels.

[0207] In some cases, a first signal is transmitted on a channel (e.g., on internal signal path 1415) at a first frequency (e.g., a first clock frequency, a first pulse frequency, or a first data rate frequency), and a second signal is transmitted on the channel (or a different channel) at a second frequency (e.g., a second clock frequency, a second pulse frequency, or a second data rate frequency). Thus, the modulation scheme and frequency can be different for the two separate signals. The frequency can be based on a clock pulse output by clock circuit 1410. In other cases, a first signal is transmitted on a channel (e.g., on internal signal path 1415) at a first frequency, and a second signal is transmitted on the channel (or a different channel) at a first frequency (e.g., at the same frequency). Thus, the modulation scheme can be different for the two separate signals, but the frequency can be the same.

[0208] According to the techniques described herein, memory controller 1401 may be configured to transmit a first signal to memory die 1403. The first signal may be modulated using a first modulation scheme having a first number of levels. Memory controller 1401 may also be configured to determine operating parameters associated with a device of which memory controller 1401 and memory die 1403 are a part. Based on the determined operating parameters, memory controller 1401 may select a second modulation scheme different from the first modulation scheme. After selecting the second modulation scheme, memory controller 1401 may transmit a second signal to memory die 1403. The second signal may be modulated using a second modulation scheme, which may have a second number of levels different from the first number of levels.

[0209] In some cases, the memory controller 1401 may be configured to transmit the first signal based on a first frequency of a first clock signal generated by the clock circuit 1410. In these cases, the memory controller 1401 may also be configured to transmit the second signal based on a second frequency of a second clock signal and based on the determined operating parameters. The second frequency may be higher or lower than the first frequency.

[0210] In some cases, the operating parameter is a bandwidth parameter (e.g., a current bandwidth requirement) or a power parameter (e.g., a parameter indicating a current power consumption or conservation requirement). When the operating parameter is a power parameter, the memory controller 1401 can determine the power parameter by detecting whether an external power source is connected to a device of which the memory controller 1401 is a part. If the first modulation scheme is NRZ and the second modulation scheme is PAM4, then the second modulation scheme can be selected when an external power source connection is detected. Using PAM4 instead of NRZ can provide more bandwidth for communication. If the first modulation scheme is PAM4 and the second modulation scheme is NRZ, then the second modulation scheme can be selected when an external power source connection is not detected. Using NRZ instead of PAM4 can reduce power consumption (e.g., increase power conservation).

[0211] In some cases, determining the power parameter includes estimating the duration until the internal power supply reaches a threshold. Selection of the second modulation scheme can be based on the estimation. For example, if the estimation indicates that the internal power supply will be exhausted within a threshold (e.g., a short) time period, the memory controller 1401 can switch from PAM4 to NRZ to save power. If the estimation indicates that the internal power supply will not be exhausted within the threshold time period, the memory controller 1401 can switch from NRZ to PAM4 to provide more bandwidth for data communication.

[0212] In some examples, the operating parameter is the activation of an application on a device including the memory controller 1401. Some applications may define a relatively low data rate for the transfer of their application data to the memory array, while other applications may define a relatively high data rate. For example, a camera application may require a high data rate, especially when it is in burst mode (e.g., a mode that captures multiple photos in a short period of time). The camera application may also require a relatively high data rate when, for example, it is in video mode, playback mode, 4K continuous shooting mode, etc. Other applications that require high data rates may include media consumption applications, virtual reality applications, augmented reality applications, artificial intelligence applications, machine learning applications, and the like.

[0213] The operating parameters may be associated with the launch of an application. For example, a newly launched application may require a data rate greater than a threshold data rate. In this example, the operating parameters may instruct the application to enter a mode that requires a data rate greater than the threshold data rate. When the data rate requested or required by the application is greater than the threshold rate, the memory controller 1401 may select a multi-symbol modulation scheme (e.g., PAM4, PAM8, PAM16, etc.) as the second modulation scheme. When the data rate requested or required by the application is less than the threshold rate, the memory controller 1401 may select a dual-level modulation scheme (e.g., NRZ) as the second modulation scheme.

[0214] In some cases, memory controller 1401 can be configured to select a first number of memory cells in memory die 1403 to receive a first signal modulated using a first modulation scheme to represent a first set of data. In other words, the memory controller can be configured to modify the size of the pages in memory die 1403 based on the modulation scheme being used to encode the data.

[0215] In these cases, memory controller 1401 may also be configured to select a second number of memory cells in memory die 1403 for receiving a second signal modulated using a second modulation scheme to represent a second set of data. The second number of memory cells accessed using the second signal may be different from the first number of memory cells accessed using the first signal. For example, if the first signal is modulated using NRZ (e.g., the first signal is a binary-level signal) and the second signal is modulated using PAM4 (e.g., a multi-level signal), memory controller 1401 may select a small number of cells (e.g., a small page size) for receiving the first signal and a large number of cells (e.g., a larger page size) for receiving the second signal. In some cases, the first set of memory cells may be selected to be overwritten with new data (e.g., a third set of data) modulated using the second modulation scheme. In these cases, the new data may be modulated at a data rate different from the first data rate (e.g., the second data rate and / or the third data rate may be different from the first data rate and / or the second data rate).

[0216] In some examples, the operating parameter is a temperature parameter (e.g., the temperature value of a component of the same device as memory controller 1401). Because high temperatures can damage components or cause degraded performance, memory controller 1401 can select a modulation scheme for communication that prevents or mitigates these temperatures.

[0217] For example, the memory controller 1401 may determine the temperature parameter by detecting a temperature associated with a component of the memory controller 1401 or a device that includes the memory controller 1401. If the memory controller 1401 detects that the temperature associated with the component (e.g., the memory controller 1401) satisfies a temperature threshold (e.g., a high temperature threshold), the memory controller 1401 may select NRZ as the second modulation scheme to reduce the temperature. If the memory controller 1401 detects that the temperature associated with the component (e.g., the memory controller 1401) does not satisfy the temperature threshold (e.g., the temperature is below the high temperature threshold), the memory controller 1401 may select PAM4 as the second modulation scheme to provide more bandwidth without the risk of negative effects caused by high heat.

[0218] In some cases, an operating parameter is an indicator or value that indicates the ability of an external device to receive data. For example, an operating parameter may indicate that the external device is limited to a certain bandwidth, data rate, modulation scheme, or frequency. In these cases, memory controller 1401 may select a second modulation scheme based on the limitations of the external device. In some examples, an operating parameter is a communication metric or requirement requested by the external device. For example, an operating parameter may be a requested data rate, bandwidth, frequency, modulation scheme, voltage level, etc.

[0219] Thus, a device (e.g., a memory controller associated with a memory device) may select a second modulation scheme and / or frequency based on a request by an external device for one or more communication metrics or requirements (e.g., the second modulation scheme and / or frequency may be selected to comply with or satisfy the requested communication metrics or requirements). Additionally or alternatively, the operating parameter may be based on characteristics of the data represented by the second signal. Although described with reference to a single operating parameter, the memory controller 1401 may select a combination of a modulation scheme and frequency based on multiple operating factors. The operating parameter used as the basis for selection may be selected based on detection of a change in the operation or condition of the device or based on a request from another device.

[0220] According to the techniques described herein, memory controller 1401 can be configured to transmit a first signal on a signal path 1415 (e.g., a data bus) using a first driver 1405. The first signal can have a signal strength corresponding to one of a first number of levels representing a first data set. After determining operating parameters as described herein, memory controller 1401 can transmit a second signal on signal path 1415-a based on the determined operating parameters. The second signal can have a signal strength corresponding to one of a second number of levels representing a second data set, and the second number of levels can be different from the first number of levels. In some cases, the second signal is transmitted on signal path 1415-a using a second driver 1405 in electronic communication with memory controller 1401.

[0221] In some cases, a first signal is sent on a first data bus and a second signal is sent on a second data bus. The first signal can be transmitted at a first clock rate generated by clock circuit 1410 and the second signal can be transmitted at a second clock rate generated by clock circuit 1410. Alternatively, the signals can be transmitted at different clock rates derived from the clock rate generated by clock circuit 1410.

[0222] Figure 15 An exemplary diagram illustrating a waveform 1500 employed according to various examples of the present invention is shown. The amplitude of the waveform 1500, depicted as a voltage, is shown varying over time. The waveform 1500 may be transmitted between two different devices or between two components within a device. In the example of intra-device communication (e.g., communication within a single device), the waveform 1500 may be transmitted as described in detail in the accompanying drawings. Figure 14 The depicted memory controller 1401 generates and transmits (eg, transmits or sends). For example, waveform 1500 may be sent from the memory controller 1401 to the memory die 1403 within the device.

[0223] According to the techniques described herein, waveform 1500 may include a first signal 1505 and a second signal 1510. Although shown as a continuous waveform, waveform 1500 may be a discontinuous waveform (e.g., there may be a break between first signal 1505 and second signal 1510 during which no data is transmitted). First signal 1505 may be modulated using a first modulation scheme having a first number of levels, and second signal 1510 may be modulated using a first modulation scheme having a second number of levels. For example, first signal 1505 may be modulated using NRZ and second signal 1510 may be modulated using PAM4. Thus, a device may switch from transmitting using the NRZ modulation scheme to transmitting using the PAM4 modulation scheme (e.g., the device may switch modulation schemes). The switch may be based on operating parameters determined for the device or for a component of the device (e.g., a host, a memory controller, an SoC, a processor, etc.).

[0224] The first signal 1505 may be transmitted at a first frequency, which may be based on a clock frequency generated and sampled by the device. The first frequency may be related to a pulse duration 1515 (sometimes referred to as a symbol duration) of a pulse of the first signal 1505. A single symbol may be transmitted during a single pulse duration 1515. One or more data bits may be represented in each pulse duration 1515. For example, when NRZ is used to modulate the first signal 1505, the amplitude of the signal 1505 during the pulse duration 1515 may represent less than two data bits (e.g., a logic '0' or a logic '1'). Thus, starting from the trailing pulse (i.e., reading from left to right), the first signal 1505 may represent the data sequence: 1010010.

[0225] Second signal 1510 may also be transmitted at the first frequency. Thus, the modulation scheme can be switched without switching the frequency. However, second signal 1510 may represent a different number of bits per pulse duration 1515 than first signal 1505. For example, when PAM4 is used to modulate second signal 1510, the amplitude of signal 1510 during pulse duration 1515 may represent two data bits. Thus, starting from the trailing pulse (i.e., reading from left to right), second signal 1510 may represent the data sequence: 00101101000110110101.

[0226] In some cases, a change in an operating parameter may be detected. Based on the change, the device may select a first modulation scheme for transmitting a third signal (e.g., a signal following the second signal 1510). Thus, the device may transmit a third signal modulated using the first modulation scheme (e.g., NRZ) based on the selection of the first modulation scheme. In some cases, the first signal 1505 may be transmitted at a frequency different from the first frequency before the second signal 1510 is transmitted (e.g., the first signal 1505 may be transmitted at a first frequency for one period of time and then at another frequency for a subsequent period of time).

[0227] Because different modulation schemes provide varying bandwidths and consume different amounts of power, a device can switch modulation schemes to optimize performance, efficiency, and power savings. For example, if using NRZ at a first frequency consumes less power than using PAM4 at the same frequency, the device may generally use NRZ to save power and may switch to PAM4 to accommodate bandwidth demands above a certain threshold. Once the bandwidth demand drops below the threshold level, the device may switch back to NRZ. Although described with reference to NRZ and PAM4, the techniques described herein are applicable to any combination of pulse amplitude modulation, including PAM2 (e.g., NRZ), PAM4, PAM8, PAM16, and the like. The techniques described herein are also applicable to switching from PAM4 to NRZ. Additionally, although described with reference to two modulation schemes, any number of modulation schemes may be switched between.

[0228] In some cases, the device may switch frequencies based on operating parameters. In other cases, the device may select both modulation and frequency based on operating parameters. In these cases, two variables related to the encoded signal (modulation scheme and clock frequency) may be changed based on the operating parameters. For example, the device may determine that switching from NRZ to PAM4, but using the same frequency, provides excess bandwidth and / or consumes more power than the device can provide. In these cases, the device may switch the clock frequency of the encoded signal.

[0229] In some cases, a device can switch both the modulation scheme and clock frequency of the encoded signal. For example, a device can switch from using NRZ at a first frequency to using PAM4 at a second frequency lower than the first frequency. In another example, a device may determine that switching from NRZ to PAM4, while using the same frequency, does not provide sufficient bandwidth to support bandwidth requirements. In this case, the device can switch from using NRZ at a first frequency to using PAM4 at a second frequency higher than the first frequency. Thus, a device can adapt to changing operational constraints by customizing the modulation scheme and frequency used by the device for transmission.

[0230] Figure 16 An exemplary diagram illustrating a waveform 1600 employed according to various examples of the present invention. The waveform 1600 may be transmitted between two different devices or between internal components of a device. In an example of intra-device communication (e.g., communication within a single device), the waveform 1600 may be transmitted by a user as described in detail in FIG. Figure 14 The depicted memory controller 1401 generates and transmits (eg, transmits or sends). For example, waveform 1600 may be sent from the memory controller 1401 to the memory die 1403 within the device.

[0231] Waveform 1600 may include a first signal 1605 and a second signal 1610. First signal 1605 may be modulated using PAM4 (e.g., using a first modulation scheme having a first number of levels), and second signal 1610 may be modulated using NRZ (e.g., a second modulation scheme having a second number of levels). Thus, data represented by first signal 1605 may be transmitted using a first number of signal levels (e.g., four), and data represented by second signal 1610 may be transmitted using a second number of signal levels (e.g., two). The device may switch between the two modulation schemes based on determining, detecting, or identifying an operating parameter associated with the device (e.g., the activation of an application that requires or demands a data rate greater than a threshold data rate, or the activation of an application that consumes or provides data at a rate greater than a threshold rate). First signal 1605 may follow a previous signal modulated using a different modulation scheme (e.g., NRZ) than first signal 1605.

[0232] The first signal 1605 may be transmitted at a first frequency that serves as the basis for pulse duration 1615 (e.g., pulse duration 1615 may be inversely proportional to the first frequency), and the second signal 1610 may be transmitted at a second frequency that serves as the basis for pulse duration 1620 (e.g., pulse duration 1620 may be inversely proportional to the second frequency). Thus, the device may switch between modulation schemes and frequencies simultaneously. While the first frequency is shown as being greater than the second frequency, the reverse is also permitted (e.g., the second frequency may be greater than the first frequency). The device may determine or select the second frequency based on operating parameters associated with the device (e.g., based on detection of a battery power or charge level of the device below or above a predetermined threshold), or a component of the device (e.g., based on the temperature of the component), or an application of the device (e.g., based on the data rate requirements of the application).

[0233] Figure 17 An exemplary diagram illustrating a waveform 1700 employed according to various examples of the present invention. The waveform 1700 may be transmitted between two different devices or between internal components of a device. In an example of intra-device communication (e.g., communication within a single device), the waveform 1700 may be transmitted by a user as described in detail in FIG. Figure 14 The depicted memory controller 1401 generates and transmits (e.g., transmits or sends). For example, waveform 1700 can be sent from the memory controller 1401 to the memory die 1403 within the device. Waveform 1700 can be an example of a waveform transmitted when the device switches between multiple (e.g., different) modulation schemes and multiple frequencies (e.g., in response to changes in one or more operating parameters).

[0234] Waveform 1700 may include several signals modulated at different frequencies according to different modulation schemes. For example, waveform 1700 may include signal 1710 modulated according to a dual-level modulation scheme (e.g., NRZ), and signals 1705, 1715, and 1720 modulated according to a multi-level modulation scheme (e.g., PAM4). Signal 1705 may be transmitted at a first frequency f1 based on a pulse duration 1720. At time t1, the modulation scheme and frequency of waveform 1700 may be modified. For example, the modulation scheme may be changed from PAM4 to NRZ, and the frequency may be changed from f1 to f2. The modifications may be based on one or more operating parameters associated with the device or a component of the device. Thus, after t1, signal 1710 may be transmitted at a frequency f2 using an NRZ modulation scheme. Frequency f2 may be based on pulse duration 1725 (e.g., frequency f2 may be inversely proportional to pulse duration 1725). Although shown as f2>f1, the second frequency f2 may be less than f1.

[0235] At time t2, the modulation scheme and frequency of waveform 1700 may be modified again. For example, the modulation scheme may be switched from NRZ to PAM4, and the frequency may be switched from f2 to f3. The modifications may be based on one or more operating parameters associated with the device or its components. Thus, signal 1715 may be transmitted using a PAM4 modulation scheme at a frequency of f3. Frequency f3 may be based on pulse duration 1730, which may be longer than pulse duration 1725.

[0236] At time t3, the frequency of transmit waveform 1700 may be modified while maintaining the modulation scheme. For example, the modulation scheme may remain PAM4, and the frequency may be changed from f3 to f4. Prior to time t3, the device may determine that a change in operating parameters has occurred. The device may select frequency f4 based on the change in operating parameters. Thus, signal 1740 may be transmitted using PAM4 at frequency f4. Frequency f4 may be based on pulse duration 1735. At time t4, the frequency may be changed again from f4 to fn. In some cases, the modulation scheme is also changed. Frequency f4 may be the same as or different from frequencies f1, f2, f3, and f4.

[0237] Thus, different modulation schemes and frequencies can be used to generate and transmit different signals. The number of frequencies available for use or used can be a discrete number of frequencies (e.g., n frequencies) and can be predetermined or dynamically determined. The frequencies can be based on, for example, Figure 14 The clock rate or clock frequency generated by the depicted clock circuit 1410 may be determined by sampling the clock pulses generated by the clock circuit 1410, for example.

[0238] Selecting a particular combination of modulation scheme and frequency can allow a device to achieve a desired bandwidth (e.g., data rate) and / or power consumption level. For example, a device can determine the bandwidth provided and the power consumed by a particular combination of modulation scheme and frequency and compare those values to desired bandwidth and power consumption values (e.g., bandwidth thresholds and power consumption thresholds). The desired bandwidth can be based on the application having data to transmit, and the power consumption can be based on the power state of the device (e.g., the remaining battery charge of the device or whether the device is connected to an external power source). If the comparison results in a difference within the threshold, the device can select the modulation scheme and frequency for communication. If the comparison results in a difference outside the threshold, the device can select a different combination of modulation scheme and frequency for comparison.

[0239] In some cases, the process by which a device selects a modulation scheme and frequency for communication may involve the use of a lookup structure. For example, the lookup structure may include several entries (e.g., preconfigured modulation data) indicating the provided bandwidth and consumed power associated with different combinations of modulation schemes and frequencies. Thus, the device may compare the required bandwidth and / or power with the preconfigured modulation data to determine which combination of modulation scheme and frequency to use for communication. Although described with reference to bandwidth and power, the techniques described herein for selecting a modulation scheme and frequency may be based on bandwidth or power, or on one or more other parameters.

[0240] Figure 18 An exemplary diagram illustrating a process flow 1800 supporting variable modulation schemes according to various examples of the present invention. Features of process flow 1800 may be implemented or performed by a device (e.g., a memory controller associated with a memory device) or a component of the device, such as memory controller 110, an SoC, a processor, a GPU, etc. Although described with reference to NRZ and PAM4, aspects and features of process flow 1800 may be implemented using other combinations of modulation schemes, including binary-level modulation schemes and multi-level modulation schemes (e.g., QAM, PSK, etc.).

[0241] At 1805, a device may transmit a first signal modulated using a first modulation scheme (e.g., NRZ) at a first frequency. The first signal may represent a first data set, and the first modulation scheme may have a first number of levels (e.g., when the first modulation scheme is NRZ, the first modulation scheme may consist of two levels). The first signal may be transmitted between components of the device (e.g., between a memory controller and a memory array) or between the device and another device. In some examples, the first and second signals may be transmitted on the same channel at different times (e.g., via time multiplexing), on the same channel at overlapping times, on different channels at the same time (e.g., concurrently, simultaneously), on different channels at different times (e.g., non-simultaneously), or at overlapping times. At 1810, the device may determine operating parameters associated with the device or a component of the device (e.g., a host, SoC, processor, memory die, memory controller, etc.).

[0242] For example, the device may determine a power parameter associated with the device. The device may determine the power parameter by determining whether the device is connected to an external power supply (e.g., by determining whether the device is capable of drawing power from an external power source such as an outlet, a battery, a battery charger, and the like). If the device is detected as being connected to an external power source, the device may select a second modulation scheme (e.g., PAM4) different from the first modulation scheme based at least in part on the detection at 1815. The second modulation scheme may be used to modulate a second signal (which represents a second data set) and may have a second number of levels (e.g., four levels) different from the first number of levels.

[0243] If the device is not connected to an external power source, the device may determine at 1820 whether the device's battery life (e.g., the charge level of the battery) is greater than a threshold battery life (e.g., a threshold charge level). For example, the device may estimate the duration until the internal power source (e.g., the battery) reaches the threshold. If the device determines that the estimated duration is less than the threshold duration, the device may maintain transmission at the first frequency using NRZ at 1825. If the device determines that the duration is greater than the threshold duration (e.g., the device has more than x hours until the internal power source has y% remaining battery), the device may select PAM4 for communication of the second signal at 1815. Thus, the device may select the second modulation scheme based on the estimate of the duration until the internal power source reaches the threshold.

[0244] In some cases, the device may select a second frequency at 1830 for transmitting a second signal modulated using PAM4. The second frequency may be based on the determination made at 1810 and / or 1815. At 1835, the device may transmit the second signal modulated using PAM4 at the selected second frequency. Alternatively, the device may transmit the second signal modulated using PAM4 at the first frequency. The second signal may be transmitted between components of the device or between the device and another device. In some cases, the first signal and the second signal are transmitted by a memory controller. In other cases, the first signal and the second signal may be transmitted to the memory controller (e.g., sent from another component or passed to the memory controller).

[0245] Figure 19 An exemplary diagram illustrates a process flow 1900 supporting variable modulation schemes according to various examples of the present invention. Features of process flow 1900 may be implemented or performed by a device (e.g., a memory controller associated with a memory device) or a component of the device, such as memory controller 110, a SoC, a processor, a GPU, etc. Communication in process flow 1900 may occur between components of the device or between two different devices. Although described with reference to NRZ and PAM4, aspects and features of process flow 1900 may be implemented using any combination of modulation schemes (e.g., QAM, PSK, etc.).

[0246] At 1905, the device may transmit a first signal modulated according to a first modulation scheme (e.g., NRZ) at a first frequency. At 1910, the device may determine an operating parameter associated with the device or a component of the device. For example, the device may determine a bandwidth parameter. The bandwidth parameter may be associated with a particular application (e.g., an application associated with the second signal, such as an application that transmits or receives the second signal) and may indicate a bandwidth required, requested, or desired by the application. Thus, at 1910, the device may determine whether the bandwidth of the application is greater than a threshold bandwidth.

[0247] In some cases, the device may additionally or alternatively determine whether a bandwidth parameter associated with a first application is greater than a bandwidth parameter associated with a second application (e.g., a different application). The first application may be an application that is activated or ready to send data, and the second application may be an application that is closed or not ready to send data. In some cases, the second application is associated with a first set of data represented by the first signal, and the first application is associated with a second set of data represented by the second signal.

[0248] If the bandwidth parameter associated with the application is greater than the threshold bandwidth, or greater than the bandwidth parameter associated with the second application, the device may select a second modulation scheme (e.g., PAM4) that is different from the first modulation scheme at 1915. Thus, the selection is based at least in part on the determined bandwidth parameter. The second modulation scheme may have a second number of levels (e.g., four) that is different from the first number of levels. If the bandwidth parameter associated with the first application is less than the bandwidth parameter associated with the second application, or less than the bandwidth parameter associated with the second application, the device may determine at 1920 whether the launched application has a data rate (e.g., a target data rate or a desired data rate) that is greater than a threshold data rate. The term bandwidth may refer to the total amount of data that a device or component can transmit, while the term data rate may refer to the speed at which data is transmitted between two devices or components.

[0249] If the data rate is not greater than the threshold rate, the device may determine at 1925 to continue using the first modulation scheme (e.g., NRZ) at the first frequency. If the data rate is greater than the threshold rate, the device may select PAM4 for modulating the second signal at 1915. Optionally, the device may select a second frequency for transmitting the second signal at 1930. The second frequency may be different from the first frequency and may be selected based on a determined operating parameter (e.g., a bandwidth parameter or a data rate parameter). At 1935, the device may transmit the second signal modulated using the second modulation scheme (e.g., PAM4) at the second frequency. In some cases, the second signal may be transmitted at the first frequency (e.g., if 1930 is not performed).

[0250] It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and that other implementations are possible. Furthermore, examples from two or more of the methods described may be combined.

[0251] Figures 20 to 22 A memory device configured to multiplex data is described. In some multi-level modulation schemes, symbols may represent data from different sources or different types of data. For example, control data, storage data, metadata, or a combination thereof may be transmitted in a single symbol containing multiple symbols. To multiplex a signal, first data and second data may be multiplexed together into a data structure. The multi-symbol signal may be encoded with particular symbols based on a multiplexed data structure, with a modulation scheme having at least three levels. In some cases, multiple memory dies may receive the multi-symbol signal and may use only a portion of one or more of the symbols. For example, a first memory die may use the most significant bit of a symbol of the multi-symbol signal, and a second memory die may use the least significant bit of the same symbol of the multi-symbol signal. Reference Figures 20 to 22 The features and / or functions described may be comparable to those described in Figures 1 to 19 Combinations of features and / or functionality of other aspects of the described memory devices.

[0252] Figure 20 An example memory device 2000 according to various embodiments of the present invention is illustrated. The memory device 2000 may be a memory device 2000 as shown in FIG. Figure 1 2. An example of the described system 100. Memory device 2000 can include a memory controller 2005, a memory die 2010, a memory die 2015, a multiplexer 2020, a bus 2025, and a host 2030. In some examples, memory die 2010 can be referred to as a first memory die 2010 and memory die 2015 can be referred to as a second memory die 2015. In some examples, the first memory die 2010 and the second memory die 2015 can be coupled to a bus 2025.

[0253] In some examples, multiplexer 2020 may be coupled to bus 2025 and may be configured to multiplex the first data and the second data. Multiplexer 2020 may be configured to multiplex the first data and the second data into a signal modulated using a binary symbol modulation scheme or a multi-symbol modulation scheme. In some examples, memory controller 2005 may multiplex the first data and the second data. In other examples, the modulation scheme of the signal may include at least one of three levels. Each of first memory die 2010 and second memory die 2015 may be configured to use at least a portion of the signal.

[0254] For example, the first memory die 2010 may be configured to use at least the first data of the signal, and the second memory die 2015 may be configured to use at least the second data of the signal. Each of the first or second data may include, for example, metadata, control data, or storage data. In some examples, the metadata may include information about various aspects of the memory device 2000—for example, information about the power usage of the memory device 2000. Additionally or alternatively, for example, the metadata may include information about the storage data, the control data, or both. In other examples, the control data may include information about one or more operations of the memory device 2000—for example, information about a read operation or a write operation on one of the first memory die 2010 or the second memory die 2015. In other examples, the storage data may include information about the logical state of one or more memory cells of the first memory die 2010 or the second memory die 2015—for example, a logical "0" or a logical "1."

[0255] In some examples, the memory controller 2005 can receive signals associated with each of the first memory die 2010 and the second memory die 2015. In some examples, the signals can be received from the host 2030. The host 2030 can communicate with the memory controller 2005 through a communication channel 2035. In response to receiving the signals, the memory controller 2005 can determine whether the signals are associated with the first memory die 2010 or the second memory die 2015, for example.

[0256] In some examples, this determination may be based at least in part on the respective signal levels of the received signals. In some cases, this determination may be based on the type of modulation scheme used to encode the data in the signal (e.g., binary level or multi-level). In other examples, the memory controller 2005 may be operable to receive a first request associated with an operation to be performed on the first memory die 2010. This request may be, for example, a request to read data or write data to the first memory die 2010. In either case, the memory controller 2005 may be configured to transmit a signal to the first memory die 2010 and the second memory die 2015 based at least in part on the first request.

[0257] In other examples, the memory controller 2005 can transmit, for example, first data and second data based on respective data requests to the first memory die 2010 and the second memory die 2015. For example, the first memory die 2010 and the second memory die 2015 can transmit the first data request and the second data request, respectively, to the memory controller 2005. In some examples, the first data request and the second data request can be transmitted by the host 2030. The first data request can indicate to the memory controller 2005 that data be transmitted to the first memory die 2010—for example, the first data of the transmission signal.

[0258] Additionally or alternatively, the second data request may instruct the memory controller 2005 to transmit data to the second memory die 2015—for example, to transmit the second data of the signal. In some examples, the first data request and the second data request may be associated with a read operation or a write operation. For example, the first data request may be associated with a read command for the first memory die 2010. Thus, a read operation of one or more memory cells in the first memory die 2010 may occur in response to the first data request. In other examples, the second data request may be associated with a write command for the second memory die 2015. For example, a write operation to one or more memory cells in the second memory die 2015 may occur in response to the second data request. In either example, the memory controller 2005 may transmit the first data of the signal, the second data of the signal, or both in response to the first and second data requests.

[0259] In some examples, multiplexer 2020 can be configured to multiplex the first data and the second data into symbols of a multi-level signal. In other words, multiplexer 2020 can be configured to generate a single modulation symbol that includes data from two different sources. For example, a PAM4 modulation symbol can represent two data bits. The most significant bit of the modulation symbol can be based on the first data, and the least significant bit of the modulation symbol can be based on the second data.

[0260] Additionally or alternatively, for example, the most significant bit of the modulation symbol may be based on the second data, and the least significant bit of the modulation symbol may be based on the first data. The number of data sources that can be multiplexed into a single symbol may be based on the number of bits represented by the symbol. For example, a multi-level modulation scheme comprising eight levels may be configured to multiplex data from three sources because the symbol may represent three data bits.

[0261] Additionally or alternatively, for example, each of the first memory die 2010 and the second memory die 2015 may include a variety of packaging and / or cell configurations. For example, each of the first memory die 2010 and the second memory die 2015 may be different memory dies in a single package (e.g., different stacked memory dies, a package-on-package stack). In some examples, the second memory die 2015 may include a different type of memory or storage device than the first memory die 2010. In other examples, the first memory die 2010 may include at least one of FeRAM, DRAM, a NAND device, a NOR device, or a phase-change memory device. In other examples, the second memory die 2015 may include at least one of FeRAM, DRAM, a NAND device, a NOR device, or a phase-change memory device. Thus, in some examples, each of the first memory die 2010 and the second memory die 2015 may contain the same cell or device type, and in other examples, each of the first memory die 2010 and the second memory die 2015 may contain different cell or device types. In other words, although depicted as stacked dies, memory die 2010 and memory die 2015 can be physically distinct memory devices. For example, memory die 2010 can be an internal memory array (or storage device) for a device, and memory die 2015 can be a removable memory card. In these cases, either or both memory dies 2010 and 2015 can be flash memory devices.

[0262] In other examples, memory device 2000 may include a third memory die (not illustrated). The third memory die may be coupled to bus 2025 and may be configured to receive the multiplexed data. In some examples, the third memory die may be configured to decode the signal and discard the first data or the second data. In other examples, the third memory die may be a different memory die from first memory die 2010 and second memory die 2015. Additionally or alternatively, for example, the third memory die may be configured to use at least a portion of the signal for the first data and / or the second data.

[0263] In some examples, the memory controller 2005 can transmit the first data and the second data, for example, to the first memory die 2010 and the third memory die based on respective data requests. For example, the first memory die 2010 and the third memory die can transmit the first data request and the second data request, respectively, to the memory controller 2005. In some examples, the first data request and the second data request can be transmitted by the host 2030 as described above. The first data request can indicate to the memory controller 2005 that data be transmitted to the first memory die 2010—for example, the first data of the transmission signal.

[0264] Additionally or alternatively, for example, the second data request may instruct the memory controller 2005 to transmit data to the third memory die—for example, to transmit the second data of the signal. Thus, the memory controller 2005 may transmit the first data of the signal, the second data of the signal, or both in response to the first and second data requests.

[0265] Additionally or alternatively, for example, the third memory die may include a variety of packaging and / or cell configurations. For example, each of the first memory die 2010, the second memory die 2015, and the third memory die may be a different memory die in a single package (e.g., different stacked memory dies, a package-on-package stack). In other examples, the third memory die may include at least one of FeRAM, DRAM, a NAND device, a NOR device, or a phase change memory device. The third memory die may include the same cell or device type as the first memory die 2010 and the second memory die 2015, or a different cell or device type. Thus, each of the first memory die 2010, the second memory die 2015, and the third memory die may contain the same cell or device type, each may contain a different cell or device type, or a combination thereof.

[0266] In other examples, each of the first memory die 2010, the second memory die 2015, and the third memory die can be coupled to the bus 2025. In some examples, the memory controller 2005 can also be coupled to the bus 2025. The memory controller 2005 can be operable to identify first data, second data, and third data, which can include metadata, control data, or storage data.

[0267] The memory controller 2005 is operable to multiplex the first data, the second data, and the third data in a signal using a first modulation scheme having at least five levels (e.g., PAM8). In other examples, the memory controller 2005 is operable to transmit the signal to the first memory die 2010, the second memory die 2015, and the third memory die. In some examples, the first memory die 2010, the second memory die 2015, and the third memory die may each include at least one of FeRAM, DRAM, a NAND device, a NOR device, or a phase change memory device.

[0268] Figure 21 An example process flow diagram 2100 is shown in FIG. 2100 according to various embodiments of the present invention. Figure 20 One or more operations performed by the memory device 2000 described herein. The process flow diagram 2100 may include operations performed by a memory controller 2105, a multiplexer 2110, a host 2115, a memory die 2120, and a memory die 2125. In some examples, the memory controller 2105, the multiplexer 2110, the memory die 2120, and the memory die 2125 may be, respectively, as described in reference to FIG. Figure 20 Examples of memory controller 2005, multiplexer 2020, memory die 2010, and memory die 2015 are depicted.

[0269] At block 2130, the memory controller 2105 may identify the first data and the second data. In some examples, the first data or the second data may include the data described above with reference to Figure 20The first data and the second data may be metadata, control data, or stored data as described. In some examples, each of the first data and the second data may be configured to include metadata, control data, or stored data. This may exclude other types of data. After identifying the first data and the second data, the memory controller 2105 may immediately transmit an indication of the first data and the second data to the multiplexer 2110 via transmission 2135. In other examples, the memory controller 2105 may transmit the first data and the second data to the multiplexer 2110. In either case, at block 2140, the multiplexer 2110 may multiplex the first data and the second data. For example, the multiplexer 2110 may multiplex the first data and the second data so that they are represented by a single symbol of a multi-level modulation scheme that includes at least three unique symbols to represent the data. In other words, the multiplexer 2110 may multiplex the first data and the second data in a signal containing a signal strength corresponding to one of the at least three levels.

[0270] Upon multiplexing the first and second data, the multiplexer 2110 may transmit an indication of the multiplexed data to the memory controller 2105 via transmission 2145. In other examples, the multiplexer 2110 may transmit the multiplexed data to the memory controller 2105. In other examples, the multiplexer 2110 may pass the data to an encoder that modulates a signal based on the multiplexed data. In another example, the memory controller 2105 may transmit an indication to the multiplexer 2110 to transmit the multiplexed data to at least one of the first memory die 2120 or the second memory die 2125 (not illustrated).

[0271] Additionally or alternatively, for example, the memory controller 2105 may receive a signal from the memory die 2120, the memory die 2125, or both that indicates one or more characteristics of the respective die. For example, based on one or more characteristics of the signal (e.g., signal strength), the memory controller 2105 may first determine whether the signal is transmitted by the first memory die 2120 or the second memory die 2125. Because the first memory die 2120 may include FeRAM cells, DRAM cells, NAND devices, NOR devices, or phase change memory devices, as described above with reference to FIG. Figure 1 As discussed, the memory controller 2105 can determine the cell or device type based in part on a signal transmitted from the first memory die 2120 .

[0272] Additionally, because the second memory die 2125 can include different memory cells or memory devices than the first memory die 2120 , the memory controller 2105 can determine the cell type or device type based in part on a signal transmitted from the second memory die 2125 .

[0273] In any of the foregoing examples, the host can determine a first data request corresponding to the first memory die 2120 or the second memory die 2125 at block 2150. The data request can instruct the memory controller 2105 to transmit a multi-symbol signal representing multiplexed data to at least one of the first memory die 2120 and / or the second memory die 2125, for example.

[0274] After determining the first data request at block 2150, the host 2115 may, for example, transmit the data request or an indication of the data request to the memory controller 2105. This may occur via transmission 2155. Additionally or alternatively, the host 2115 may, for example, determine a second data request corresponding to the first memory die 2120 or the second memory die 2125 at block 2160. As stated above, relative to the first data request, the second data request may indicate to the memory controller 2105 that the multiplexed data is to be transmitted to at least one of the first memory die 2120 or the second memory die 2125. Upon determining the second data request at block 2160, the host 2115 may transmit the data request or an indication of the data request to the memory controller 2105. This may occur via transmission 2165.

[0275] At transmit 2170, the memory controller 2105 may transmit the first data and the second data to the first memory die 2120 and the second memory die 2125. In some examples, the memory controller 2105 may transmit the first data and the second data to the first memory die 2120 and the second memory die 2125 over a bus coupled to each of the first and second memory dies. In some examples, the second memory die 2125 may be or may include an external or removable memory device.

[0276] For example, upon insertion or activation, the memory controller 2105 may receive an indication of the presence of a second memory die 2125 comprising a removable storage device (not illustrated). In some examples, the removable storage device may be a Universal Flash Storage (UFS) device. In this example, the transmission of signals to the first memory die 2120 and the second memory die 2125 may be based in part on the indication transmitted to the memory controller 2105.

[0277] In some examples, memory die 2120 and memory die 2125 may receive a signal modulated using a first modulation scheme and may identify one or more bits represented by a symbol (e.g., one of three unique symbols). For example, one bit may be assigned to memory die 2120 and one bit may be assigned to memory die 2125. Consequently, memory die 2120 may discard the bit assigned to memory die 2125 and memory die 2125 may discard the bit assigned to memory die 2120. In other examples, each of memory die 2120 and memory die 2125 may partition data based on the type of data (e.g., control data). For example, memory die 2125 may decode the received signal and, based on the type of data, may discard the bits. Additionally or alternatively, for example, memory die 2120 may decode the received signal and may facilitate the transfer of specific data to memory die 2125.

[0278] In some examples, a memory die (e.g., memory die 2120 or memory die 2125) can decode symbols modulated using a multi-symbol modulation scheme and can determine the type of each bit represented by the decoded symbol. The memory die can perform one or more operations based on the type of data included in the symbol.

[0279] In other examples, the first data and the second data may be transmitted as a multiplexed signal having a signal strength corresponding to one of at least three levels. Figure 1 As discussed, the signal may be modulated using, for example, a pulse amplitude modulation (PAM) scheme. Immediately after transmitting the signal, at block 2175, the memory controller 2105 may be operable to initiate adjustment of the timing of the transmission of the signal to the first memory die 2120 and the second memory die 2125. When transmitting the signal, the memory controller 2105 may transmit the signal based on the timing of a system clock. In some examples, the system clock may be associated with (e.g., integrated with) the memory controller 2105. In other examples, the system clock may be external to the memory controller 2105. For example, the memory controller 2105 may transmit the signal during the rising edge of the system clock, the falling edge of the system clock, or both. The memory controller 2105 may then transmit the adjusted signal to each of the first memory die 2120 and the second memory die 2125 via transmission 2180.

[0280] For example, at block 2130, the memory controller 2105 may identify first and second data that each include control data. The memory controller 2105 may then transmit, for example, indications of the first and second control data to the multiplexer 2110 via transmission 2135. At block 2140, the multiplexer 2110 may multiplex the first and second data into a symbol of a multi-level signal containing at least three levels, and then transmit an indication of the multiplexed data to the memory controller 2105. At block 2150, the host 2115 may determine a first data request, which may correspond to a data request from the first memory die 2120.

[0281] Additionally, at block 2160, the host 2115 may determine a second data request, which may correspond to a data request from the second memory die 2125. Each of the data requests may be transmitted from the host 2115 to the memory controller 2105 at transmissions 2155 and 2165, respectively. Upon receiving the data requests, the memory controller 2105 may simultaneously transmit a multiplexed signal to each of the first memory die 2120 and the second memory die 2125 via transmission 2170. Based on the transmissions, at block 2175, the memory controller 2105 adjusts the communication of the multiplexed signal based on a clock cycle of the memory controller 2105 and may simultaneously transmit the adjusted signal to each of the first memory die 2120 and the second memory die 2125 via transmission 2180.

[0282] Figure 22 The process flow diagram 2200 is a flowchart illustrating various embodiments of the present invention. The process flow diagram 2200 can illustrate the process flow diagram of the embodiment of the present invention. Figure 20 One or more operations performed by the memory device 2000 described. The process flow diagram 2200 may include operations performed by the memory controller 2205, the multiplexer 2210, the host 2215, the memory die 2220, and the memory die 2225. In some examples, the memory controller 2205, the multiplexer 2210, the host 2215, the memory die 2220, and the memory die 2225 may be respectively as described in reference Figure 21 Examples of memory controller 2105, multiplexer 2110, host 2115, memory die 2120, and memory die 2125 are depicted.

[0283] At block 2230, the host 2215 may determine a first data request corresponding to the first memory die 2220 or the second memory die 2225. The first data request may indicate to the memory controller 2205, for example, to transfer data to one of the first or second memory die. After determining the first data request at block 2230, the host 2215 may transmit the data request or an indication of the data request to the memory controller 2205, for example. This may occur via transmission 2235.

[0284] Additionally or alternatively, for example, at block 2240, the host 2215 may determine a second data request corresponding to the first memory die 2220 or the second memory die 2225. As stated above, relative to the determination of the first data request, the determination of the second data request may indicate to the memory controller 2205 that data be transferred to one of the first or second memory die. In some examples, the determination of the first data request at block 2230 may correspond to the first memory die 2220, and the determination of the second data request at block 2240 may correspond to the second memory die 2225. After determining the second data request at block 2240, the host 2215 may transmit the second data request or an indication of the second data request to the memory controller 2205, for example, by transmitting 2245.

[0285] After transmitting each of the first and second data requests, or indications thereof, to the memory controller 2205, the memory controller 2205 may identify the first data at block 2250. The memory controller 2205 may, for example, identify the first data in response to the first or second data request determined at blocks 2230 and 2240, respectively. In some examples, identifying the first data includes identifying control data. Upon identifying the first data at block 2250, the multiplexer 2210 may receive an indication of the first data from the memory controller 2205. In other examples, the multiplexer 2210 may receive an indication of the first data from the memory controller 2205.

[0286] In either case, receipt of the identified data (or an indication thereof) may occur via transmission 2255. After receiving identification of the first data via transmission 2255, the memory controller 2205 may identify the second data at block 2260. The memory controller 2205 may identify the first data, for example, in response to the determined first or second data requests at blocks 2230 and 2240, respectively, or in response to identification of the first data at block 2250. In some examples, after identification of the second data at block 2260, the multiplexer 2210 may receive the identified second data or an indication of the identified second data from the memory controller 2205 via transmission 2265.

[0287] Upon receiving the identified first and second data, or indications thereof, the multiplexer 2210 may multiplex the identified first and second data at block 2270 so that they are represented by a single symbol of a multi-level modulation scheme that includes at least three unique symbols to represent the data. For example, the multiplexer 2210 may multiplex the identified first data. In other words, the multiplexer 2210 may multiplex the identified first and second data in a signal having a signal strength corresponding to one of the at least three levels.

[0288] After multiplexing the identified first data and the identified second data, the multiplexer 2210 may, for example, transmit an indication of the multiplexed data to the memory controller 2205 via transmission 2275. In other examples, the multiplexer 2210 may transmit the multiplexed data to the memory controller 2205. In another example, the memory controller 2205 may transmit an indication to the multiplexer 2210 to transmit the multiplexed data to at least one of the first memory die 2220 or the second memory die 2225 (not illustrated).

[0289] Additionally or alternatively, for example, the first memory die 2220, the second memory die 2225, or both may transmit a signal indicating one or more characteristics of the respective die to the memory controller 2205. For example, based on one or more characteristics of the signal (e.g., signal strength), the signal may indicate that it originated at one of the first memory die 2220 or the second memory die 2225. Because the first memory die 2220 may include FeRAM cells, DRAM cells, NAND devices, NOR devices, or phase change memory devices, as described above with reference to Figure 1 As discussed, the signal may indicate a cell or device type of the first memory die 2220. Additionally, because the second memory die 2225 may include different memory cells or memory devices than the first memory die 2220, the signal may indicate a cell type or device type of the second memory die 2225. In some examples, the multiplexer 2210 may multiplex the first and second data based on the cell type or device type of the first memory die 2220 and the second memory die 2225 at block 2270.

[0290] Via transmission 2280, first memory die 2220 and second memory die 2225 may receive multiplexed first and second data from memory controller 2205. In some examples, the multiplexed first and second data may be received via a bus (not illustrated) coupled to each of the first and second memory dies. In some examples, second memory die 2225 may be or may include an external or removable memory device. For example, when inserted or activated, second memory die 2225 may transmit an indication to memory controller 2205 indicating the insertion or activation of the device. In this example, the transmission of signals to first memory die 2220 and second memory die 2225 may be based in part on the indication transmitted to memory controller 2205.

[0291] In other examples, the first data and the second data may be received at the first memory die 2220 and the second memory die 2225 as a multiplexed signal having a signal strength corresponding to one of at least three levels. Figure 1 As discussed, the signal may be modulated using, for example, a PAM modulation scheme. Upon receiving the signal, at block 2285, the memory controller 2205 may adjust the timing of the transmission of the signal. The signals received at the first memory die 2220 and the second memory die 2225 may be based on the timing of a system clock. In some examples, the system clock may be associated with (e.g., integrated with) the memory controller 2205. In other examples, the system clock may be external to the memory controller 2205. For example, the memory controller 2205 may transmit the signal during a rising edge of the system clock, a falling edge of the system clock, or both. The first memory die 2220 and the second memory die 2225 may then receive the adjusted signals based on the system clock of the memory controller 2205 by transmitting 2290.

[0292] In some examples, memory die 2220 and memory die 2225 may receive a signal modulated using a first modulation scheme and may identify one or more bits represented by a symbol (e.g., one of three unique symbols). For example, one bit may be assigned to memory die 2220 and one bit may be assigned to memory die 2225. Consequently, memory die 2220 may discard the bit assigned to memory die 2225, and memory die 2225 may discard the bit assigned to memory die 2220. In other examples, each of memory die 2220 and memory die 2225 may partition data based on the type of data (e.g., control data). For example, memory die 2225 may decode the received signal and, based on the type of data, may discard the bits. Additionally or alternatively, for example, memory die 2220 may decode the received signal and may facilitate the transfer of specific data to memory die 2225.

[0293] For example, at block 2230, the host 2215 may determine a first data request, which may correspond to a data request from the first memory die 2220. Additionally, at block 2240, the host 2215 may determine a second data request, which may correspond to a data request from the second memory die 2225. Each of the data requests may be transmitted by the host 2215 to the memory controller 2205 at transmissions 2235 and 2245, respectively. Upon transmitting the memory requests to the memory controller 2205, the memory controller 2205 may recognize that the first and second data, each including control data.

[0294] This indication may occur at blocks 2250 and 2260, respectively. After identifying each of the first data and the second data, the identified data may be received by the multiplexer 2210 at transmissions 2255 and 2265, respectively. At block 2240, the multiplexer 2210 may multiplex the first data and the second data into symbols of a multi-level signal containing at least three levels, and then transmit an indication of the multiplexed data to the memory controller 2205. Based on this transmission, each of the first memory die 2220 and the second memory die 2225 may receive the multiplexed signal from the memory controller via transmission 2280. The multiplexed signal may be transmitted simultaneously to each of the first memory die 2220 and the second memory die 2225. Upon receiving the multiplexed signal, the memory controller 2205 may coordinate communication of the multiplexed signal based on the clock cycle of the memory controller 2205. The adjusted signal may then be received by each of the first memory die 2220 and the second memory die 2225 .

[0295] Figure 23 A block diagram 2300 illustrates a memory controller 2315 according to various embodiments of the present invention. The memory controller 2315 may be a reference Figure 1 10. Memory controller 2315 may include a biasing component 2320, a timing component 2325, an identification component 2330, a multiplexing component 2335, a transmitting component 2340, a receiving component 2345, a determining component 2350, and an adjusting component 2355. Each of these components may communicate with each other, directly or indirectly (e.g., via one or more buses).

[0296] In some examples, the identification component 2330 can identify the first data and the second data. The multiplexing component 2335 can multiplex the first data and the second data in the signal. In some examples, based on identifying the first data and the second data, the signal can be modulated using a first modulation scheme having at least three levels.

[0297] The transmit component 2340 can transmit the signal in a signal to a first memory die coupled to the bus and a second memory die coupled to the bus. In some cases, the signal can include a pulse amplitude modulated (PAM) signal.

[0298] In some examples, receiving component 2345 may receive a first data request associated with a first memory die from a host device or from another component of a common SoC. In other examples, receiving component 2345 may receive a second data request associated with a second memory die from a host. In some examples, a signal may be transmitted based on the first data request and the second data request. Additionally or alternatively, for example, receiving component 2345 may receive a signal from each of the first memory die and the second memory die. In other examples, receiving component 2345 may receive an indication of the presence of a second memory die comprising a removable storage device. In some examples, the transmission of signals to the first memory die and to the second memory die may be based on the indication. The removable storage device may be, for example, a Universal Flash Storage (UFS) device.

[0299] The determining component 2350 can determine whether one of the received signals was transmitted by the first memory die or the second memory die based on the respective signal levels of the signals from each of the first memory die and the second memory die. The adjusting component 2355 can adjust the timing of transmitting the signals to the first memory die and the second memory die based on the timing of the system clock of the memory controller coupled to the bus.

[0300] Some examples of the methods and apparatus described above may further include processes, features, means, or instructions for receiving, from a host, a first data request associated with a first memory die. Some examples of the methods and apparatus described above may further include processes, features, means, or instructions for receiving, from a host, a second data request associated with a second memory die, wherein transmitting the signal may be based at least in part on the first data request and the second data request.

[0301] In other examples, the methods and apparatus described above may further include a process, feature, means, or instructions for receiving a signal from each of the first memory die and the second memory die. Some examples of the methods and apparatus described above may further include a process, feature, means, or instructions for determining whether one of the received signals was transmitted by the first memory die or the second memory die based at least in part on respective signal levels of the signals from each of the first memory die and the second memory die. In some examples of the methods and apparatus described above, the signal comprises a pulse amplitude modulated (PAM) signal.

[0302] Some examples of the methods and apparatus described above may further include processes, features, means, or instructions for adjusting the timing of transmitting signals to the first memory die and the second memory die based at least in part on the timing of a system clock of a memory controller coupled to the bus. Some examples of the methods and apparatus described above may further include processes, features, means, or instructions for receiving an indication of the presence of a second memory die comprising a removable storage device, wherein the transmission of signals to the first memory die and to the second memory die may be based at least in part on the indication.

[0303] Figure 24 A block diagram 2400 illustrates a device 2405 according to an example of the present invention. The device 2405 may be as described above, for example, with reference to Figure 20 2405. The components of the memory device 2000 are described as examples of or include such components. The device 2405 may include components for two-way voice and data communications, including components for transmitting and receiving communications, including a memory controller 2415, a memory unit 2420, a basic input / output system (BIOS) component 2425, a processor 2430, an I / O controller 2435, and peripheral components 2440. These components may be in electronic communication via one or more buses, such as bus 2410.

[0304] Memory controller 2415 can operate one or more memory cells as described herein. In some cases, memory controller 2415 can include a row decoder, a column decoder, or both, as described herein (not shown). Memory cell 2420 can store information (i.e., in the form of logic states) as described herein.

[0305] The BIOS component 2425 is a software component that includes the BIOS operating as firmware that can initialize and run various hardware components. The BIOS component 2425 can also manage the flow of data between the processor and various other components, such as peripheral components, input / output control components, etc. The BIOS component 2425 can include a program or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0306] The processor 2430 may include an intelligent hardware device (e.g., a general-purpose processor, a DSP, a central processing unit (CPU), a microcontroller, an ASIC, an FPGA, a programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof). In some cases, the processor 2430 may be configured to operate the memory array using a memory controller. In other cases, the memory controller may be integrated into the processor 2430. The processor 2430 may be configured to execute computer-readable instructions stored in the memory to perform various functions as described in various examples herein.

[0307] I / O controller 2435 can manage input and output signals for device 2405. I / O controller 2435 can also manage peripheral devices that are not integrated into device 2405. In some cases, I / O controller 2435 can represent a physical connection or port to an external peripheral device. In some cases, I / O controller 2435 can utilize an operating system, such as or another known operating system. In other cases, I / O controller 2435 may represent or interact with a modem, keyboard, mouse, touch screen, or similar device. In some cases, I / O controller 2435 may be implemented as part of a processor. In some cases, a user may interact with device 2405 via I / O controller 2435 or via hardware components controlled by I / O controller 2435.

[0308] Peripheral components 2440 may include any input or output device, or an interface for such a device. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral device card slot (such as a Peripheral Component Interconnect (PCI) or Accelerated Graphics Port (AGP) card slot).

[0309] Input 2445 may represent a device or signal external to device 2405 that provides input to device 2405 or its components. This may include a user interface or an interface with other devices or between other devices. In some cases, input 2445 may be managed by I / O controller 2435 and may interact with device 2405 via peripheral components 2440. In some cases, input 2445 may be used to receive binary symbol signals from a host device, such as processor 2430 or device 2405 itself.

[0310] Output 2450 may also represent a device or signal external to device 2405 that is configured to receive output from device 2405 or any of its components. Examples of output 2450 may include a display, an audio speaker, a printing device, another processor, or a printed circuit board. In some cases, output 2450 may be a peripheral element that interfaces with device 2405 via peripheral components 2440. In some cases, output 2450 may be managed by I / O controller 2435.

[0311] The components of device 2405 may include circuitry designed to perform its functions. This may include various circuit elements configured to perform the functions described herein, such as wires, transistors, capacitors, inductors, resistors, amplifiers, or other active or inactive components. Device 2405 may be a computer, server, laptop, notebook, tablet, mobile phone, wearable electronic device, personal electronic device, or the like. Or device 2405 may be a portion or aspect of such a device. Device 2405 may support communication between various components via bus 2410 using one or more standardized protocols. For example, the various components of device 2405 may communicate using Gen-Z, CCIX, OpenCAPI, or the like.

[0312] Figure 25 An example flow chart illustrating a method 2500 according to an example of the present invention is shown. The operations of the method 2500 may be implemented by the memory device 2000 or its components as described herein. For example, the operations of the method 2500 may be implemented by the memory device 2000 or its components as described herein. Figure 23 and 24 The memory controller described herein performs. In some examples, the memory device 2000 may execute a set of codes to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the memory device 2000 may use dedicated hardware to perform aspects of the functions described below.

[0313] At 2505, the memory device 2000 may identify the first data and the second data. The operations of 2505 may be performed according to the methods described herein. In some examples, aspects of the operations of 2505 may be as described in reference to Figure 23 and 24 The described recognition component performs.

[0314] At 2510, the memory device 2000 may multiplex the first data and the second data in a signal modulated using a first modulation scheme having at least three levels based at least in part on identifying the first data and the second data. The operation of 2510 may be performed according to the methods described herein. In some examples, aspects of the operation of 2510 may be as described with reference to Figure 23 and 24 The multiplexing component described performs

[0315] At 2515, the memory device 2000 may transmit a signal in a signal to a first memory die coupled to a bus and a second memory die coupled to a bus. The operations of 2515 may be performed according to the methods described herein. In some examples, aspects of the operations of 2515 may be as described with reference to Figure 23 and 24 The described launch component executes.

[0316] In some cases, the method may include identifying first data and second data. In some cases, the method may also include transmitting a signal in a signal to a first memory die coupled to a bus and a second memory die coupled to the bus. In other cases, the method may include receiving a first data request associated with the first memory die from a host. Additionally or alternatively, for example, the method may include receiving a second data request associated with the second memory die from the host, wherein the transmitting signal is based at least in part on the first data request and the second data request.

[0317] In some cases, the method may include receiving a signal from each of a first memory die and a second memory die. In other cases, the method may include multiplexing the first data and the second data into a signal modulated using a first modulation scheme having at least three levels based at least in part on identifying the first data and the second data. In some cases, the signal comprises a pulse amplitude modulated (PAM) signal. Additionally or alternatively, for example, the method may include adjusting the timing of transmitting the signal to the first memory die and the second memory die based at least in part on the timing of a system clock of a memory controller coupled to the bus.

[0318] In some cases, the method may include receiving an indication of the presence of a second memory die comprising a removable storage device, wherein the transmission of signals to the first memory die and to the second memory die is based at least in part on the indication. In some cases, the removable storage device comprises a Universal Flash Storage (UFS) device. In other cases, the method may also include determining whether one of the received signals was transmitted by the first memory die or the second memory die based at least in part on respective signal levels of the signals from each of the first memory die and the second memory die.

[0319] An apparatus is described. In some examples, the apparatus may include: means for identifying first data and second data; means for multiplexing the first data and the second data in a signal modulated using a first modulation scheme having at least three levels based at least in part on identifying the first data and the second data; and means for transmitting the signal in the signal to a first memory die coupled to a bus and a second memory die coupled to the bus.

[0320] In some examples, the apparatus may include: means for receiving a first data request associated with a first memory die from a host; and means for receiving a second data request associated with a second memory die from the host, wherein transmitting the signal is based at least in part on the first data request and the second data request. In some examples, the apparatus may include: means for receiving a signal from each of the first memory die and the second memory die; and means for determining whether one of the received signals was transmitted by the first memory die or the second memory die based at least in part on respective signal levels of the signals from each of the first memory die and the second memory die.

[0321] In some examples, the signal comprises a pulse amplitude modulation (PAM) signal. In some examples, the apparatus may include means for adjusting the timing of transmitting the signal to the first memory die and the second memory die based at least in part on the timing of a system clock. In some examples, the apparatus may include means for receiving an indication of the presence of the second memory die comprising a removable storage device, wherein the transmission of the signal to the first memory die and to the second memory die is based at least in part on the indication. In some examples, the removable storage device comprises a universal flash storage (UFS) device. In some examples, at least one of the first data or the second data comprises metadata or control data.

[0322] Figure 26 2600. The operations of the method 2600 may be performed by the memory device 2000 or its components as described herein. For example, the operations of the method 2600 may be performed by the memory device 2000 or its components as described herein. Figure 23 and 24 The memory controller described herein performs. In some examples, the memory device 2000 may execute a set of codes to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the memory device 2000 may use dedicated hardware to perform aspects of the functions described below.

[0323] At 2605, the memory device 2000 may identify the first data and the second data. The operations of 2605 may be performed according to the methods described herein. In some examples, aspects of the operations of 2605 may be as described in reference to Figure 23 and 24 The described recognition component performs.

[0324] At 2610, the memory device 2000 may multiplex the first data and the second data in a signal modulated using a first modulation scheme having at least three levels based at least in part on identifying the first data and the second data. The operation of 2610 may be performed according to the methods described herein. In some examples, aspects of the operation of 2610 may be as described in reference to Figure 23 and 24 The multiplexing component described performs

[0325] At 2615, the memory device 2000 may transmit a signal in a signal to a first memory die coupled to a bus and a second memory die coupled to a bus. The operations of 2615 may be performed according to the methods described herein. In some examples, aspects of the operations of 2615 may be as described in reference to Figure 23 and 24 The described launch component executes.

[0326] At 2620, the memory device 2000 may receive a first data request associated with a first memory die from a host. The operations of 2620 may be performed according to the methods described herein. In some examples, aspects of the operations of 2620 may be as described with reference to Figure 23 and 24 The receiving component described performs the following.

[0327] At 2625, the memory device 2000 may receive a second data request associated with a second memory die from the host, wherein the transmitting signal is based at least in part on the first data request and the second data request. The operations of 2625 may be performed according to the methods described herein. In some examples, aspects of the operations of 2625 may be as described with reference to Figure 23 and 24 The receiving component described performs the following.

[0328] An apparatus is described. In some examples, the apparatus may include: a first memory die coupled to a bus; a second memory die coupled to the bus; means for identifying first data and second data, wherein at least one of the first data or the second data comprises control data; means for multiplexing the first data and the second data in a signal modulated using a first modulation scheme having at least three levels; and means for transmitting a signal to the first memory die and the second memory die.

[0329] In some examples, the apparatus may include means for receiving a first request from a host associated with an operation to be performed on a first memory die, wherein the means for transmitting a signal to the first memory die and the second memory die is based at least in part on the first request. In some examples, the second memory die is configured to use second data of the signal. In some examples, the apparatus may include: means for adjusting a timing of transmitting the signal to the first memory die and the second memory die based at least in part on the first request received from the host; and means for transmitting the signal to the first memory die and the second memory die based at least in part on the adjustment.

[0330] In some examples, the means for multiplexing the first data and the second data into symbols of the signal is based at least in part on timing of a system clock. In some examples, the first memory die and the second memory die each include at least one of a ferroelectric random access memory (FeRAM), a dynamic random access memory (DRAM), a NAND device, a NOR device, or a phase change memory device, wherein the first memory die includes a ferroelectric memory cell, a dynamic random access memory cell, or a NAND flash memory cell, and wherein the second memory die includes a general purpose flash memory device.

[0331] An apparatus is described. In some examples, the apparatus may include: a first memory die coupled to a bus; a second memory die coupled to the bus; a third memory die coupled to the bus; means for identifying first data, second data, and third data; means for multiplexing the first data, second data, and third data in a signal modulated using a first modulation scheme having at least five levels; and means for transmitting a signal to the first memory die, the second memory die, and the third memory die.

[0332] In some examples, at least one of the first data, the second data, or the third data includes metadata, control data, or storage data. In some examples, the first memory die, the second memory die, and the third memory die each include at least one of a ferroelectric random access memory (FeRAM), a dynamic random access memory (DRAM), a NAND device, a NOR device, or a phase change memory device.

[0333] It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, embodiments from two or more of the methods described may be combined.

[0334] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that the signal may represent a signal bus, where the bus may have multiple bit widths.

[0335] As used herein, the term "virtual ground" refers to a node of a circuit that is maintained at a voltage of approximately zero volts (0V) but is not directly connected to ground. Thus, the voltage of the virtual ground can fluctuate over time and return to approximately 0V in a steady state. A virtual ground can be implemented using various electronic circuit elements, such as a voltage divider consisting of an operational amplifier and resistors. Other implementations are also possible. A "virtual ground" or "virtual earth ground" means being connected to approximately 0V.

[0336] The terms "electronic communication" and "coupling" refer to a relationship between components that supports the flow of electrons between the components. This may include a direct connection between the components or may include intermediate components. Components that are in electronic communication or coupled with each other may actively exchange electrons or signals (e.g., in an energized circuit) or may not actively exchange electrons or signals (e.g., in a de-energized circuit), but may be configured and operable to exchange electrons or signals immediately after the circuit is energized. For example, two components that are physically connected via a switch (e.g., a transistor) may be in electronic communication or coupled regardless of the state of the switch (i.e., open or closed).

[0337] The term "isolation" refers to a relationship between components in which electrons are currently unable to flow between the components; if there is an open circuit between the components, the components are isolated from each other. For example, two components physically connected by a switch can be isolated from each other when the switch is open.

[0338] The devices discussed herein, including memory devices, can be formed on a semiconductor substrate, such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, or the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate, or a subregion of the substrate, can be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0339] The embodiments described herein in conjunction with the accompanying drawings describe example configurations and do not represent all examples that may be implemented or within the scope of the claims. As used herein, the term "exemplary" means "serving as an example, instance, or illustration" and does not mean "preferred" or "superior to other examples." The detailed description includes specific details for the purpose of providing an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0340] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dashed line and a second label, which distinguishes among similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label regardless of the second reference label.

[0341] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0342] The various illustrative blocks and modules described in connection with the present invention may be implemented or executed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a digital signal processor (DSP) and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0343] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope of the present invention and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may also be physically located at various locations, including being distributed so that parts of the functions are implemented at different physical locations. Furthermore, as used herein, including in the claims, the term "or" used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be understood as referring to a closed set of conditions. For example, without departing from the scope of the present invention, exemplary steps described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be equally interpreted as the phrase "based at least in part on."

[0344] Computer-readable media include non-transitory computer storage media and communication media including any media that facilitates transferring a computer program from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. For example, but not limited to, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or wireless technology (e.g., infrared, radio and microwave) is used to transmit software from a website, server or other remote source, then the coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or wireless technology (e.g., infrared, radio and microwave) is included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of the above are also included within the scope of computer-readable media.

[0345] The description herein is provided to enable one skilled in the art to make or use the present invention. Various modifications to the present invention will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present invention. Therefore, the present invention is not limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A volatile memory device comprising: bus; as well as a multiplexer, wherein the volatile memory device supports a plurality of pulse amplitude modulation (PAM) schemes, the plurality of pulse amplitude modulation (PAM) schemes including a non-return-to-zero (NRZ) scheme and a PAM3 scheme, and wherein the volatile memory device is operable to: generating, by the multiplexer, a single symbol of a pulse amplitude modulated signal, the pulse amplitude modulated signal comprising a first bit of a first type of metadata for a stored data set and a second bit of a second type of metadata for the stored data set, wherein the single symbol is generated based at least in part on a modulation scheme mode of the volatile memory device, wherein the pulse amplitude modulated signal is a PAM3 signal having three levels, and wherein the second type of metadata is different from the first type of metadata; as well as Based at least in part on generating the single symbol of the pulse amplitude modulated signal including the first bit of the first type of metadata and the second bit of the second type of metadata, the single symbol of the pulse amplitude modulated signal is transmitted over the bus.

2. The volatile memory device of claim 1, wherein the volatile memory device is operable to receive a request from a host device coupled to the volatile memory device. 3 . The volatile memory device of claim 2 , wherein the first bit of the first type of metadata and the second bit of the second type of metadata are associated with the request from the host device. 4 . The volatile memory device of claim 1 , wherein the first bit of the first type of metadata and the second bit of the second type of metadata are associated with a read operation.

5. The volatile memory device of claim 1, wherein the volatile memory device is coupled to a graphics processing unit (GPU).

6. The volatile memory device of claim 1, wherein the volatile memory device comprises a random access memory system. 7 . The volatile memory device of claim 1 , wherein the first bit of the first type of metadata has a different logic value than the second bit of the second type of metadata.

8. The volatile memory device of claim 1, wherein the first bit of the first type of metadata and the second bit of the second type of metadata are associated with a read command.

9. A method implemented by a volatile memory system, comprising: generating, at the volatile memory system supporting a plurality of pulse amplitude modulation (PAM) schemes, a single symbol of a pulse amplitude modulated signal, the plurality of pulse amplitude modulation (PAM) schemes including a non-return-to-zero (NRZ) scheme and a PAM3 scheme, the pulse amplitude modulated signal comprising a first bit of a first type of metadata for a stored data set and a second bit of a second type of metadata for the stored data set, wherein the single symbol is generated based at least in part on a modulation scheme mode of the volatile memory system, wherein the pulse amplitude modulated signal is a PAM3 signal having three levels, and wherein the second type of metadata is different from the first type of metadata; as well as Based at least in part on generating the single symbol of the pulse amplitude modulated signal including the first bit of the first type of metadata and the second bit of the second type of metadata, transmitting the single symbol of the pulse amplitude modulated signal on a bus coupled to the volatile memory system.

10. The method according to claim 9, further comprising: A request is received from a host device coupled to the volatile memory system.

11. The method of claim 10, wherein the first bit of the first type of metadata and the second bit of the second type of metadata are associated with the request from the host device. 12 . The method of claim 9 , wherein the first bit of the first type of metadata and the second bit of the second type of metadata are associated with a read operation.

13. The method of claim 9, wherein the volatile memory system is coupled to a graphics processing unit (GPU).

14. The method of claim 9, wherein the volatile memory system comprises a random access memory system.

15. A memory device comprising: A first volatile memory die storing a set of data, wherein the memory device supports a plurality of pulse amplitude modulation (PAM) schemes including a non-return-to-zero (NRZ) scheme and a PAM3 scheme, and wherein the memory device is operable to: generating a single symbol of a pulse amplitude modulated signal, the pulse amplitude modulated signal comprising a first bit of a first type of metadata for the data set and a second bit of a second type of metadata for the data set, wherein the single symbol is generated based at least in part on a modulation scheme pattern for the first volatile memory die, wherein the pulse amplitude modulated signal is a PAM3 signal having three levels, and wherein the second type of metadata is different from the first type of metadata; as well as Based at least in part on generating the single symbol of the pulse amplitude modulated signal including the first bit of the first type of metadata and the second bit of the second type of metadata, the single symbol of the pulse amplitude modulated signal is transmitted on a bus.

16. The memory device of claim 15, wherein the memory device is operable to: A request is received from a host device, and wherein the first bit of the first type of metadata and the second bit of the second type of metadata are associated with the request from the host device.

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