An RC-LIGBT device with integrated dual self-biased MOS and low turn-off loss

Abstract

The present invention relates to an RC-LIGBT device with integrated dual self-biased MOS and low turn-off loss, and belongs to the field of semiconductor technology. The LIGBT device of the present invention has the following structural and performance characteristics: (1) Both the reverse conducting MOS and the low turn-off loss MOS include N-base, P-base and N+ collector, and the metal gate is short-circuited with the N-base and N+ collector respectively through the polysilicon layer, without the need for additional gate signal control. (2) When conducting in the forward direction, there is no negative resistance effect; when conducting in the reverse direction, when V GS,RC >V TH , the reverse conducting MOS is automatically turned on, and the device realizes reverse conduction; at the turn-off time, the device meets V GS,FC >V TH , the low turn-off loss MOS is turned on, and electrons can be extracted through the low turn-off loss MOS, which reduces the turn-off time and reduces the turn-off loss.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to an RC-LIGBT device with integrated dual self-biased MOS and low turn-off loss. Background Art

[0002] IGBT (Insulated Gate Bipolar Transistor) is a bipolar semiconductor power device that combines MOSFET and BJT tubes. It has the advantages of low on-state voltage, low driving power consumption and high operating frequency. It is widely used in communication technology, new energy equipment and various consumer electronics fields, and is the core device of electronic power systems. Among them, LIGBT (Lateral Insulated Gate Bipolar Transistor) is easy to integrate on Si substrate, usually used in SOI-based power intelligent systems, and is a typical representative of bipolar semiconductor devices.

[0003] However, since LIGBT does not have the ability to conduct in the reverse direction, a reverse freewheeling diode is usually connected in parallel next to the LIGBT for protection in actual use. At the same time, in order to improve the integration of the device and reduce the manufacturing cost, people began to try to integrate the protective freewheeling diode inside the LIGBT, replace the P-Collector of the LIGBT with the N-Collector, and integrate a P-body / N-drift / N-Collector freewheeling diode inside the transistor, becoming a RC-LIGBT (Reverse-Conducting Lateral Insulated Gate Bipolar Transistor). This change not only enables the device to have reverse conduction capability, but also greatly reduces the size of the chip, which can reduce production costs.

[0004] Traditional LIGBT still has some disadvantages that cannot be ignored in use: for example, in the turn-off stage, there are a large number of carriers in the drift region that need to be extracted. Without additional carrier extraction channels, the carriers can only disappear through recombination, resulting in a long turn-off time and tail current, which affects the use of the device. At present, the structural optimization scheme of LIGBT can be summarized into the following three aspects:

[0005] 1. Anode optimization, the main purpose is to control the injection efficiency of anode holes;

[0006] 2. Cathode optimization, the main purpose is to increase the carrier concentration on the cathode side in the on-state;

[0007] 3. Drift region optimization, the main purpose is to improve the device's withstand voltage and increase the carrier extraction speed.

[0008] Therefore, in order to better promote the application of LIGBT, it is necessary to further improve LIGBT to optimize the various performances of LIGBT, thereby enhancing the reliability of LIGBT devices. Summary of the invention

[0009] In view of this, an object of the present invention is to provide an RC-LIGBT device with integrated dual self-biased MOS and low turn-off loss.

[0010] In order to achieve the above object, the present invention provides the following technical solutions:

[0011] An RC-LIGBT device with integrated dual self-biased MOS low turn-off loss, the device is divided into a LIGBT region, a reverse conducting MOS region and a low turn-off loss MOS region from left to right, the LIGBT region includes a P+ emitter 1, an N+ electron emitter 2, a P-body 3, an N-type drift region 4, a silicon dioxide insulating layer 5, a P-type substrate 6, an N-type buffer layer 7, a P+ collector 8, a collector 12, a gate 14, and an emitter 15;

[0012] Reverse conducting MOS region: N-base 11, P-base 10, N+ collector 9, and polysilicon connection layer 16 are arranged from left to right respectively; the upper side of the N-base 11 is flush with the upper side of the N-type buffer layer 7, the left side is completely covered by the N-type buffer layer 7, the right side is closely connected to the left side of the P-base 10, and the lower side is closely connected to the upper side of the P+ collector 8; the upper side of the P-base 10 is flush with the upper side of the N-type buffer layer 7, the right side is closely connected to the left side of the N+ collector 9, and the lower side is closely connected to the upper side of the P+ collector 8; the upper side of the N+ collector 9 is flush with the upper side of the N-type buffer layer 7, the right side is closely connected to the right side of the device, and the lower side is closely connected to the upper side of the P+ collector 8; the polysilicon connection layer 16 short-circuits the N-base 11 and the gate of the reverse conducting MOS, thereby realizing reverse conduction of the device;

[0013] Low turn-off loss MOS region: N-base 11, P-base 10, N+ collector 9, and polysilicon layer 13 are arranged from left to right respectively; the upper side of the N-base 11 is flush with the upper side of the N-type buffer layer 7, the left side is completely covered by the N-type buffer layer 7, the right side is closely connected to the left side of the P-base 10, and the lower side is closely connected to the upper side of the P+ collector 8; the upper side of the P-base 10 is flush with the upper side of the N-type buffer layer 7, the right side is closely connected to the left side of the N+ collector 9, and the lower side is closely connected to the upper side of the P+ collector 8; the upper side of the N+ collector 9 is flush with the upper side of the N-type buffer layer 7, the right side is closely connected to the right side of the device, and the lower side is closely connected to the upper side of the P+ collector 8; the polysilicon layer 13 short-circuits the N+ collector 9 with the gate of the reverse conducting MOS, thereby realizing low turn-off loss of the device;

[0014] LIGBT area: from left to right, P+ emitter 1, N+ electron emitter 2, emitter 15, P-body 3, gate 14, N-type drift region 4, silicon dioxide insulating layer 5, P-type substrate 6, N-type buffer layer 7, P+ collector 8, collector 12 are arranged respectively; P+ emitter 1 is located below emitter 15, its left side is flush with the left side of the device, its right side is closely connected to the left side of N+ electron emitter 2, and its lower side is connected to P-body 3; N+ electron emitter 2 is located below emitter 15 and gate 14, and its right side and lower side are completely covered by P-body 3; the upper side of P-body 3 is flush with the upper sides of P+ emitter 1 and N+ electron emitter 2 , the right side and the bottom side are completely covered by the N-type drift region 4; the upper side of the N-type drift region 4 is flush with the upper sides of the P+ emitter 1, the N+ electron emitter 2, the gate 14, the N-type buffer layer 7 and the P+ collector 8, and the bottom side is closely connected to the upper side of the silicon dioxide insulating layer 5, the left side is flush with the left side of the device, and the right side is flush with the right side of the device; the upper side of the N-type buffer layer 7 is flush with the upper side of the device, the right side is flush with the right side of the device, and the left side and the bottom side are completely covered by the N-type drift region 4; the P+ collector 8 is located on the bottom side of the collector 12, its upper side is flush with the upper side of the device, the right side is flush with the right side of the device, and the left side and the bottom side are completely covered by the N-type buffer layer 7, and the above structure constitutes a LIGBT bipolar device.

[0015] Optionally, the right side of the N-type buffer layer 7 in the LIGBT region is connected to the left side of the reverse conducting MOS region and the low turn-off loss MOS region N-base11.

[0016] Optional, in the forward conduction stage, there is no negative resistance effect; in the reverse conduction stage, when V GS,RC >V TH , the reverse conducting MOS is automatically turned on, and the device realizes reverse conduction; at the turn-off time, the device meets V GS,FC >V TH, the low turn-off loss MOS is turned on, and electrons can be extracted through the low turn-off loss MOS, reducing the turn-off loss.

[0017] Optionally, the material of the gate 14 includes doped polysilicon or aluminum.

[0018] The beneficial effects of the present invention are:

[0019] (1) When forward conducting, the device has no negative resistance effect;

[0020] (2) In reverse conduction, when V GS,RC >V TH , the reverse conducting MOS is automatically turned on, and the device achieves reverse conduction;

[0021] (3) At the turn-off time, the device meets V GS,FC >V TH , the low turn-off loss MOS is turned on, and electrons can be extracted through the low turn-off loss MOS, which reduces the turn-off time and reduces the turn-off loss;

[0022] (4) The threshold voltage of the MOS can be changed by changing the thickness of the gate oxide layer of the MOS, preferably, so that it can be automatically turned off or on without introducing an external driving circuit.

[0023] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0025] Figure 1 The present invention provides an RC-LIGBT device with integrated dual self-biased MOS and low turn-off loss;

[0026] Figure 2 A schematic diagram of the structure of an RC-LIGBT device with integrated reverse conducting MOS provided by the present invention;

[0027] Figure 3 A schematic diagram of the structure of a LIGBT device with integrated low turn-off loss MOS provided by the present invention;

[0028] Figure 4 An equivalent circuit diagram of an RC-LIGBT device with integrated dual self-biased MOS and low turn-off loss provided by the present invention;

[0029] Figure 5 For example 1, the concentration of the reverse conducting MOS LIGBT, the low turn-off loss MOS LIGBT and the traditional RC-LIGBT in the drift region is 2×10 15 cm -3 Comparison of forward conduction characteristics under ;

[0030] Figure 6 In Example 1, the concentration in the drift region is 2×10 15 cm -3 Forward conduction electron concentration distribution and current line distribution diagram when the device is forward-conducting; (a) is the electron current distribution diagram of Example 1 when the device is forward-conducting; (b) is the current line distribution diagram of Example 1 when the device is forward-conducting;

[0031] Figure 7 For example 1, the concentration of the reverse conducting MOS LIGBT, the low turn-off loss MOS LIGBT and the traditional RC-LIGBT in the drift region is 2×10 15 cm -3 Comparison of reverse conduction characteristics under ;

[0032] Figure 8 In Example 1, the concentration in the drift region is 2×10 15 cm -3 The reverse conduction electron concentration distribution and current line distribution diagram when conducting; (a) is the electron current distribution diagram of Example 1 when conducting in reverse; (b) is the current line distribution diagram of Example 1 when conducting in reverse;

[0033] Fig. 9 The drift region length L of the reverse conducting MOS LIGBT, the low turn-off loss MOS LIGBT and the traditional RC-LIGBT are shown in Example 1. D =The influence of the concentration change of the drift region under 18μm on the breakdown voltage of the device;

[0034] Fig.10 The turn-off characteristic curves of Example 1, a reverse conducting MOS LIGBT, a low turn-off loss MOS LIGBT and a traditional RC-LIGBT under a turn-on voltage drop of 0.9V;

[0035] Fig.11 The electron concentration distribution diagrams of Example 1, reverse conducting MOS LIGBT, low turn-off loss MOS LIGBT and traditional RC-LIGBT at turn-off time t1, t2, t3 and t4 respectively; (a) is the electron concentration distribution diagram at time t1; (b) is the electron concentration distribution diagram at time t2; (c) is the electron concentration distribution diagram at time t3; (d) is the electron concentration distribution diagram at time t4;

[0036] Fig.12The compromise relationship between the on-state voltage drop and the turn-off loss of the reverse conducting MOS LIGBT, the low turn-off loss MOS LIGBT and the traditional RC-LIGBT is shown in Example 1;

[0037] Fig.13 The forward conduction characteristics, reverse conduction characteristics and turn-off characteristics of the reverse conducting MOS and the low turn-off loss MOS in Example 1 when the gate oxide thickness is 8nm, 10nm and 20nm respectively; (a) is the effect of the change of the gate oxide layer on the forward conduction performance; (b) is the effect of the change of the gate oxide layer on the reverse conduction performance; (c) is the effect of the change of the gate oxide layer on the turn-off performance;

[0038] Fig.14 The forward conduction characteristics, reverse conduction characteristics and turn-off characteristics in Example 1 when the width ratios of the reverse conducting MOS and the low turn-off loss MOS are 3:1, 2:2 and 1:3 respectively; (a) is the effect of the change in MOS width on the forward conduction performance; (b) is the effect of the change in MOS width on the reverse conduction performance; (c) is the effect of the change in MOS width on the turn-off performance.

[0039] Fig.15 The N-base doping concentration in Example 1 is 1×10 16 cm -3 , 5×10 16 cm -3 , 8×10 16 cm -3 , 1×10 16 cm -3 and 2×10 16 cm -3 Forward conduction characteristics, reverse conduction characteristics and turn-off characteristics under ; (a) is the effect of change of N-base doping concentration on forward conduction performance; (b) is the effect of change of N-base doping concentration on reverse conduction performance; (c) is the effect of change of N-base doping concentration on turn-off performance.

[0040] Figure numerals: 1-P+ emitter, 2-N+ electron emitter, 3-P-body, 4-N-type drift region, 5-silicon dioxide insulating layer, 6-P-type substrate, 7-N-type buffer layer, 8-P+ collector, 9-N+ collector, 10-P-base, 11-N-base, 12-collector, 14-gate, 15-emitter, 16-polysilicon connection layer. DETAILED DESCRIPTION

[0041] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0042] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0043] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0044] Figure 1 This is an RC-LIGBT device with integrated dual self-biased MOS and low turn-off loss proposed by the present invention, and is a structural schematic diagram of Embodiment 1. The length L of the device d is 25 μm, and the cross-sectional views of AA' and BB' are given respectively;

[0045] Figure 2 A schematic diagram of the structure of an RC-LIGBT device with integrated reverse conducting MOS provided by the present invention. Compared with Example 1, the device only integrates reverse conducting MOS;

[0046] Figure 3 A schematic diagram of the structure of a LIGBT device with integrated low turn-off loss MOS provided by the present invention. Compared with Example 1, the device only integrates low turn-off loss MOS;

[0047] Figure 4The equivalent circuit diagram of the RC-LIGBT device with integrated dual self-biased MOS and low turn-off loss provided by the present invention. On the basis of the traditional LIGBT, the reverse conducting MOS and the low turn-off loss MOS are introduced;

[0048] Figure 5 For example 1, the concentration of the reverse conducting MOS LIGBT, the low turn-off loss MOS LIGBT and the traditional RC-LIGBT in the drift region is 2×10 15 cm -3 Comparison of forward conduction characteristics under the following conditions. When conducting forward, a positive voltage is applied to the collector. At this time, the low turn-off loss MOS is not turned on, and the reverse conducting MOS is turned on. The reverse conducting MOS LIGBT has the lowest conduction voltage drop, because the forward conduction mode at this time is equivalent to the traditional LIGBT. The forward conduction performance of the traditional RC-LIGBT is the worst, and there is a negative resistance effect, ΔV SB It is 2.22V, which seriously affects the reliability of the device;

[0049] Figure 6 In Example 1, the concentration in the drift region is 2×10 15 cm -3 The electron concentration distribution and current line distribution diagram of forward conduction. (a) is the electron current distribution diagram of Example 1 when forward conduction; (b) is the current line distribution diagram of Example 1 when forward conduction;

[0050] Figure 7 For example 1, the concentration of the reverse conducting MOS LIGBT, the low turn-off loss MOS LIGBT and the traditional RC-LIGBT in the drift region is 2×10 15 cm -3 Comparison of reverse conduction characteristics under ;

[0051] Figure 8 In Example 1, the concentration in the drift region is 2×10 15 cm -3 The reverse conduction electron concentration distribution and current line distribution diagram. (a) is the electron current distribution diagram of Example 1 during reverse conduction; (b) is the current line distribution diagram of Example 1 during reverse conduction;

[0052] Fig. 9 The drift region length L of the reverse conducting MOS LIGBT, the low turn-off loss MOS LIGBT and the traditional RC-LIGBT are shown in Example 1. D =The influence of the concentration change of the drift region under 18μm on the breakdown voltage of the device;

[0053] Fig.10The turn-off characteristic curves of Example 1, a reverse conducting MOS LIGBT, a low turn-off loss MOS LIGBT and a traditional RC-LIGBT under a turn-on voltage drop of 0.9V;

[0054] Fig.11 The electron concentration distribution diagrams of Example 1, reverse conducting MOS LIGBT, low turn-off loss MOS LIGBT and traditional RC-LIGBT at turn-off time t1, t2, t3 and t4 respectively; (a) is the electron concentration distribution diagram at time t1; (b) is the electron concentration distribution diagram at time t2; (c) is the electron concentration distribution diagram at time t3; (d) is the electron concentration distribution diagram at time t4;

[0055] Fig.12 The compromise relationship between the on-state voltage drop and the turn-off loss of the reverse conducting MOS LIGBT, the low turn-off loss MOS LIGBT and the traditional RC-LIGBT is shown in Example 1;

[0056] Fig.13 The forward conduction characteristics, reverse conduction characteristics and turn-off characteristics of the reverse conducting MOS and the low turn-off loss MOS in Example 1 when the gate oxide thickness is 8nm, 10nm and 20nm respectively; (a) is the effect of the change of the gate oxide layer on the forward conduction performance; (b) is the effect of the change of the gate oxide layer on the reverse conduction performance; (c) is the effect of the change of the gate oxide layer on the turn-off performance;

[0057] Fig.14 The forward conduction characteristics, reverse conduction characteristics and turn-off characteristics in Example 1 when the width ratios of the reverse conducting MOS and the low turn-off loss MOS are 3:1, 2:2 and 1:3 respectively; (a) is the effect of the change in MOS width on the forward conduction performance; (b) is the effect of the change in MOS width on the reverse conduction performance; (c) is the effect of the change in MOS width on the turn-off performance.

[0058] Fig.15 The N-base doping concentration in Example 1 is 1×10 16 cm -3 , 5×10 16 cm -3 , 8×10 16 cm -3 , 1×10 16 cm -3 and 2×10 16 cm -3 Forward conduction characteristics, reverse conduction characteristics and turn-off characteristics under ; (a) is the effect of change of N-base doping concentration on forward conduction performance; (b) is the effect of change of N-base doping concentration on reverse conduction performance; (c) is the effect of change of N-base doping concentration on turn-off performance.

[0059] Embodiment 1:

[0060] like Figure 1As shown, an RC-LIGBT device with integrated dual self-biased MOS and low turn-off loss is proposed in the embodiment of the present invention. The main structural feature is that the device is divided into a LIGBT region, a reverse conducting MOS region and a low turn-off loss MOS region from left to right. The LIGBT region includes a P+ emitter 1, an N+ electron emitter 2, a P-body 3, an N-type drift region 4, a silicon dioxide insulating layer 5, a P-type substrate 6, an N-type buffer layer 7, a P+ collector 8, a collector 12, a gate 14, and an emitter 15. Reverse conducting MOS region: N-base 11, P-base 10, N+ collector 9, and a polysilicon layer 13 are respectively arranged from left to right. The upper side of the N-base 11 is flush with the upper side of the N-type buffer layer 7, the left side is completely covered by the N-type buffer layer 7, the right side is closely connected to the left side of the P-base 10, and the lower side is closely connected to the upper side of the P+ collector 8. The upper side of P-base10 is flush with the upper side of N-type buffer layer 7, the right side is closely connected to the left side of N+ collector 9, and the lower side is closely connected to the upper side of P+ collector 8. The upper side of N+ collector 9 is flush with the upper side of N-type buffer layer 7, the right side is closely connected to the right side of the device, and the lower side is closely connected to the upper side of P+ collector 8. The polysilicon connection layer 16 short-circuits N-base11 with the gate of the reverse conducting MOS, realizing the reverse conduction of the device. Low turn-off loss MOS area: N-base11, P-base10, N+ collector 9, and polysilicon layer 13 are arranged from left to right. The upper side of N-base11 is flush with the upper side of N-type buffer layer 7, the left side is completely covered by N-type buffer layer 7, the right side is closely connected to the left side of P-base10, and the lower side is closely connected to the upper side of P+ collector 8. The upper side of P-base 10 is flush with the upper side of N-type buffer layer 7, the right side is closely connected to the left side of N+ collector 9, and the lower side is closely connected to the upper side of P+ collector 8. The upper side of N+ collector 9 is flush with the upper side of N-type buffer layer 7, the right side is closely connected to the right side of the device, and the lower side is closely connected to the upper side of P+ collector 8. The polysilicon layer 13 short-circuits N+ collector 9 with the gate of reverse-conducting MOS, achieving low turn-off loss of the device. LIGBT area: From left to right, P+ emitter 1, N+ electron emitter 2, emitter 15, P-body 3, gate 14, N-type drift region 4, silicon dioxide insulating layer 5, P-type substrate 6, N-type buffer layer 7, P+ collector 8, collector 12 are arranged respectively. P+ emitter 1 is located below emitter 15, its left side is flush with the left side of the device, its right side is closely connected to the left side of N+ electron emitter 2, and its lower side is connected to P-body 3. The N+ electron emitter 2 is located below the emitter 15 and the gate 14, and the right side and the bottom side are completely covered by the P-body 3. The upper side of the P-body 3 is flush with the upper sides of the P+ emitter 1 and the N+ electron emitter 2, and the right side and the bottom side are completely covered by the N-type drift region 4.The upper side of the N-type drift region 4 is flush with the upper sides of the P+ emitter 1, the N+ electron emitter 2, the gate 14, the N-type buffer layer 7 and the P+ collector 8, and the lower side is closely connected to the upper side of the silicon dioxide insulating layer 5, and the left side is flush with the left side of the device, and the right side is flush with the right side of the device. The upper side of the N-type buffer layer 7 is flush with the upper side of the device, the right side is flush with the right side of the device, and the left side and the lower side are completely covered by the N-type drift region 4. The P+ collector 8 is located on the lower side of the collector 12, and its upper side is flush with the upper side of the device, the right side is flush with the right side of the device, and the left side and the lower side are completely covered by the N-type buffer layer 7. The above structure constitutes a LIGBT bipolar device.

[0061] The length of the P+ emitter 1 is 1 μm, the width is 10 μm, the thickness is 1 μm, and the doping concentration is 1×10 19 cm -3 The length of the N+ electron emitter 2 is 1 μm, the width is 10 μm, the thickness is 1 μm, and the doping concentration is 1×10 19 cm -3 The length of P-body3 is 3μm, the width is 10μm, the thickness is 2μm, and the doping concentration is 8×10 16 cm -3 The length of the N-type drift region 4 is 18 μm, the width is 10 μm, the thickness is 5 μm, and the doping concentration is 2×10 15 cm -3 The length of the P-type substrate 6 is 25 μm, the width is 10 μm, the thickness is 2 μm, and the doping concentration is 1×10 15 cm -3 The length of the N-type buffer layer 7 is 4 μm, the width is 10 μm, the thickness is 2 μm, and the doping concentration is 5×10 16 cm -3 The length of the P+ collector 8 is 1 μm, the width is 10 μm, the thickness is 1.5 μm, and the doping concentration is 1×10 19 cm -3 The length of the N+ collector 9 is 1 μm, the width is 5 μm, the thickness is 1 μm, and the doping concentration is 1×10 19 cm -3 The length of P-base10 is 1 μm, the width is 5 μm, the thickness is 1 μm, and the doping concentration is 1×10 17 cm -3 The length of N-base11 is 1 μm, the width is 5 μm, the thickness is 1 μm, and the doping concentration is 5×10 16 cm -3 . Gate oxide thickness T of reverse conducting MOS and low turn-off loss MOS OX =20nm.

[0062] When forward conducting, there is no negative resistance effect; when reverse conducting, the reverse conducting MOS is turned on and the device achieves reverse conducting; at the turn-off moment, the low turn-off loss MOS is turned on and electrons can be extracted through the low turn-off loss MOS, which reduces the turn-off time and reduces the turn-off loss.

[0063] Using SENTAURUS simulation software, the LIGBT device of the proposed implementation case 1 is simulated as follows: Figure 1 The structure shown in the figure is subjected to performance simulation analysis, its mechanism is analyzed, and electrical simulation is performed. During the simulation process, the conventional RC-LIGBT device, the device of embodiment 1, the reverse conducting MOS LIGBT device (such as Figure 2 ) and low turn-off loss MOS LIGBT devices (such as Figure 3 The simulation parameters of the embodiment (as shown in FIG) are consistent, wherein the thickness of the N drift region is 5 μm, the carrier lifetime is 10 μs, and the ambient temperature is 300 K.

[0064] Figure 4 The figure shows an equivalent circuit diagram of an RC-LIGBT device with integrated dual self-biased MOS and low turn-off loss. On the basis of the traditional LIGBT, a reverse conducting MOS and a low turn-off loss MOS are introduced. When conducting in the forward direction, the low turn-off loss MOS is turned on, and the device has no negative resistance effect; when conducting in the reverse direction, the reverse conducting MOS is turned on, and the device achieves reverse conducting performance; at the turn-off moment, the low turn-off loss MOS is turned on, providing an extraction channel for electrons in the drift region, reducing the turn-off time, reducing the tail current, and reducing the turn-off loss of the device.

[0065] Figure 5 For example 1, the concentration of the reverse conducting MOS LIGBT, the low turn-off loss MOS LIGBT and the traditional RC-LIGBT in the drift region is 2×10 15 cm -3 Comparison of forward conduction characteristics under . During forward conduction, a positive voltage is applied to the collector. At this time, the low turn-off loss MOS is turned on, and the reverse conduction MOS is not turned on. The reverse conduction MOS LIGBT has the lowest conduction voltage drop, because the forward conduction mode at this time is equivalent to the traditional LIGBT. The forward conduction performance of the traditional RC-LIGBT is the worst, and there is a negative resistance effect, ΔV SB is 2.22V, which seriously affects the reliability of the device

[0066] Figure 6 In Example 1, the concentration in the drift region is 2×10 15 cm -3The forward conduction electron concentration distribution and current line distribution diagram. (a) The electron current distribution diagram of Example 1 during forward conduction (b) The current line distribution diagram of Example 1 during forward conduction. At this time, the turn-on status of the MOS can be more intuitively seen. The gate of the reverse conducting MOS is short-circuited with the N-base through the polysilicon layer, and the reverse conducting MOS cannot be turned on; the gate of the low turn-off loss MOS is short-circuited with the N+ collector through the polysilicon layer, and V GS,FC >V TH , the low turn-off loss MOS turns on automatically.

[0067] Figure 7 For example 1, the concentration of the reverse conducting MOS LIGBT, the low turn-off loss MOS LIGBT and the traditional RC-LIGBT in the drift region is 2×10 15 cm -3 The reverse conduction characteristics comparison chart below. When conducting in reverse, a positive voltage is applied to the emitter, at this time the low turn-off loss MOS is not turned on, and the reverse conducting MOS is turned on. The reverse conducting MOS LIGBT has the best reverse conducting performance, while the low turn-off loss MOS LIGBT has no reverse conducting capability.

[0068] Figure 8 In Example 1, the concentration in the drift region is 2×10 15 cm -3 The reverse conduction electron concentration distribution and current line distribution diagram. (a) The electron current distribution diagram of Example 1 during reverse conduction (b) The current line distribution diagram of Example 1 during reverse conduction. At this time, the turn-on status of the MOS can be more intuitively seen. The gate of the reverse conducting MOS is short-circuited with the N-base through the polysilicon layer, and V GS,RC >V TH , the reverse conducting MOS is automatically turned on; the gate of the low turn-off loss MOS is short-circuited with the N+ collector through polysilicon, and the low turn-off loss MOS is not turned on.

[0069] Fig. 9 The drift region length L of the reverse conducting MOS LIGBT, the low turn-off loss MOS LIGBT and the traditional RC-LIGBT are shown in Example 1. D = The influence of the change of drift region concentration on the breakdown voltage of the device at 18μm. As the concentration of the drift region gradually increases, the breakdown voltage of the device first increases and then decreases. 15 cm -3 The peak breakdown voltage is reached at .

[0070] Fig.10The figure is a turn-off characteristic curve of Example 1, reverse conducting MOS LIGBT, low turn-off loss MOS LIGBT and traditional RC-LIGBT at a turn-on voltage drop of 0.9 V. At this time, the low turn-off loss MOS is turned on to provide an extraction channel for electrons, so the turn-off performance of the low turn-off loss MOS LIGBT is the best, while the turn-off performance of the reverse conducting MOS LIGBT is the worst, because it has no electron extraction channel, and the electrons in the drift region can only disappear through recombination.

[0071] Fig.11 The electron concentration distribution diagrams of Example 1, reverse conducting MOS LIGBT, low turn-off loss MOS LIGBT and traditional RC-LIGBT at turn-off time t1, t2, t3 and t4 respectively (a) electron concentration distribution diagram at time t1 (b) electron concentration distribution diagram at time t2 (c) electron concentration distribution diagram at time t3 (d) electron concentration distribution diagram at time t4. The electron extraction of low turn-off loss MOS LIGBT is the fastest, while the electron extraction of reverse conducting MOS LIGBT is the slowest.

[0072] Fig.12 The trade-off relationship between the on-state voltage drop and the turn-off loss of the reverse conducting MOS LIGBT, the low turn-off loss MOS LIGBT and the traditional RC-LIGBT in Example 1 is shown. on =0.9V, the turn-off loss E of the new structure embodiment 1 off 76% lower than the traditional RC-LIGBT; at the same E off =0.47mJ / cm 2 Under the new structure, the conduction voltage drop V on This is a 50% decrease compared to traditional RC-LIGBT.

[0073] Fig.13 The forward conduction characteristics, reverse conduction characteristics and turn-off characteristics of the reverse conducting MOS and low turn-off loss MOS in Example 1 when the gate oxide thickness is 8nm, 10nm and 20nm respectively (a) The influence of the gate oxide change on the forward conduction performance (b) The influence of the gate oxide change on the reverse conduction performance (c) The influence of the gate oxide change on the turn-off performance. The thickness of the gate oxide layer is very important. If the thickness of the gate oxide layer is too low, it will affect the reliability of the device. If it is too high, it will make the MOS difficult to turn on. After comprehensive consideration, the gate oxide layer thickness T is finally set to ox Set to 20nm.

[0074] Fig.14Forward conduction characteristics, reverse conduction characteristics and turn-off characteristics when the width ratios of the reverse conducting MOS and the low turn-off loss MOS in Example 1 are 3:1, 2:2 and 1:3 respectively (a) Effect of MOS width change on forward conduction performance (b) Effect of MOS width change on reverse conduction performance (c) Effect of MOS width change on turn-off performance.

[0075] Fig.15 The N-base doping concentration in Example 1 is 1×10 16 cm -3 , 5×10 16 cm -3 , 8×10 16 cm -3 , 1×10 16 cm -3 and 2×10 16 cm -3 Forward conduction characteristics, reverse conduction characteristics and turn-off characteristics under (a) The effect of change of N-base doping concentration on forward conduction performance (b) The effect of change of N-base doping concentration on reverse conduction performance (c) The effect of change of N-base doping concentration on turn-off performance.

[0076] In summary, the present invention proposes an integrated dual self-biased MOS low turn-off loss RC-LIGBT device, the functional characteristics of which are that in the forward conduction stage, there is no negative resistance effect; in the reverse conduction stage, when V GS,RC >V TH , the reverse conducting MOS is automatically turned on, and the device realizes reverse conduction; at the turn-off time, the device meets V GS,FC >V TH , the low turn-off loss MOS is turned on, and electrons can be extracted through the low turn-off loss MOS, reducing the turn-off loss.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. An integrated dual self-biased MOS low turn-off loss RC-LIGBT device, characterized in that: The device is divided into a LIGBT region, a reverse conducting MOS region and a low turn-off loss MOS region from left to right, wherein the LIGBT region includes a P+ emitter (1), an N+ electron emitter (2), a P-body (3), an N-type drift region (4), a silicon dioxide insulating layer (5), a P-type substrate (6), an N-type buffer layer (7), a P+ collector (8), a collector (12), a gate (14) and an emitter (15); Reverse conducting MOS region: from left to right, an N-base (11), a P-base (10), an N+ collector (9), and a polysilicon connection layer (16) are arranged respectively; the upper side of the N-base (11) is flush with the upper side of the N-type buffer layer (7), the left side is completely covered by the N-type buffer layer (7), the right side is closely connected to the left side of the P-base (10), and the lower side is closely connected to the upper side of the P+ collector (8); the upper side of the P-base (10) is The upper side of the N-type buffer layer (7) is flush with the upper side of the N-type buffer layer (7), the right side is closely connected to the left side of the N+ collector (9), and the lower side is closely connected to the upper side of the P+ collector (8); the upper side of the N+ collector (9) is flush with the upper side of the N-type buffer layer (7), the right side is closely connected to the right side of the device, and the lower side is closely connected to the upper side of the P+ collector (8); the polysilicon connection layer (16) short-circuits the N-base (11) and the gate of the reverse conducting MOS, thereby realizing reverse conduction of the device; Low turn-off loss MOS region: from left to right, an N-base (11), a P-base (10), an N+ collector (9), and a polysilicon layer (13) are arranged respectively; the upper side of the N-base (11) is flush with the upper side of the N-type buffer layer (7), the left side is completely covered by the N-type buffer layer (7), the right side is closely connected to the left side of the P-base (10), and the lower side is closely connected to the upper side of the P+ collector (8); the P-base (10) The upper side is flush with the upper side of the N-type buffer layer (7), the right side is closely connected to the left side of the N+ collector (9), and the lower side is closely connected to the upper side of the P+ collector (8); the upper side of the N+ collector (9) is flush with the upper side of the N-type buffer layer (7), the right side is closely connected to the right side of the device, and the lower side is closely connected to the upper side of the P+ collector (8); the polysilicon layer (13) short-circuits the N+ collector (9) and the gate of the reverse-conducting MOS, thereby achieving low turn-off loss of the device; LIGBT region: from left to right, the P+ emitter (1), N+ electron emitter (2), emitter (15), P-body (3), gate (14), N-type drift region (4), silicon dioxide insulating layer (5), P-type substrate (6), N-type buffer layer (7), P+ collector (8), and collector (12) are arranged respectively; the P+ emitter (1) is located below the emitter (15), its left side is flush with the left side of the device, its right side is closely connected to the left side of the N+ electron emitter (2), and its lower side is connected to the P-body (3); the N+ electron emitter (2) is located below the emitter (15) and the gate (14), and its right side and lower side are completely covered by the P-body (3); the upper side of the P-body (3) is connected to the P+ emitter (1) and the N+ electron emitter (1). The upper side of the N-type drift region (4) is flush with the upper side of the P+ emitter (1), the N+ electron emitter (2), the gate (14), the N-type buffer layer (7) and the P+ collector (8), the lower side is closely connected to the upper side of the silicon dioxide insulating layer (5), the left side is flush with the left side of the device, and the right side is flush with the right side of the device; the upper side of the N-type buffer layer (7) is flush with the upper side of the device, the right side is flush with the right side of the device, and the left side and the lower side are completely covered by the N-type drift region (4); the P+ collector (8) is located on the lower side of the collector (12), the upper side of the P+ collector (8) is flush with the upper side of the device, the right side is flush with the right side of the device, and the left side and the lower side are completely covered by the N-type buffer layer (7), and the above structure constitutes a LIGBT bipolar device.

2. The RC-LIGBT device with integrated dual self-biased MOS and low turn-off loss according to claim 1, characterized in that: The right side of the LIGBT region N-type buffer layer (7) is connected to the left side of the reverse conducting MOS region and the low turn-off loss MOS region N-base (11).

3. The RC-LIGBT device with integrated dual self-biased MOS and low turn-off loss according to claim 1, characterized in that: In the forward conduction stage, there is no negative resistance effect; in the reverse conduction stage, when V GS,RC >V TH , the reverse conducting MOS is automatically turned on, and the device realizes reverse conduction; at the turn-off time, the device meets V GS,FC >V TH , the low turn-off loss MOS is turned on, and electrons can be extracted through the low turn-off loss MOS, reducing the turn-off loss.

4. The RC-LIGBT device with integrated dual self-biased MOS and low turn-off loss according to claim 1, characterized in that: The material of the gate (14) includes doped polysilicon or aluminum.

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