Manage and display data

Abstract

This document discloses a method for writing data to and reading data from one or more buffers. The method includes: determining a write rate for writing data to a first buffer; determining a read rate for reading data from the first buffer; determining a portion of the first buffer using the write rate and the read rate; writing data to the portion of the first buffer; starting to read data from the first buffer when the writing of data to the portion of the first buffer has been completed; and writing data to the remaining portion of the first buffer that is different from the portion of the first buffer. The portion of the first buffer is determined such that the reading of data from the first buffer does not exceed the writing of data into the first buffer.

Description

Background Technology

[0001] This invention generally relates to managing data, such as display data. In many computing systems, especially display systems, data is typically streamed via buffers: that is, a process of writing data to a buffer and a second process of reading data. Ideally, the read and write processes traverse the data as close as possible in time, such that there is as little latency as possible between the specific data being written and the data being read, and ideally, this time latency is constant. However, the read process is typically faster than the write process, which can cause the processes to lose synchronization and may cause the read process to attempt to read data that has not yet been written. It will be apparent that the buffer can ideally store previously written data, or can be at least partially empty (no data, which is different from data that is zero). When the buffer is written to, the write process overwrites what was previously there, whether there was no data or previously written data. Similarly, when reading from the buffer, the read process reads whatever data (or no data) it comes to, whether that data has already been written in the current write process or has been previously written.

[0002] In display systems, synchronization loss is typically mitigated by using multiple buffers, where one buffer is being written to while another is being read from, and once the write process is complete, the read process can only begin on a specific buffer. Typically, three buffers are provided to ensure no overlap, and once the write process has finished writing data to a given buffer, a flag indicating which buffer it will write to next is set. When the read process reaches the end of a given buffer, it proceeds to the next buffer based on the flag. However, this results in increased and unpredictable latency because an entire frame of display data must be written before the direction flag can be set, followed by an unknown length of time for the read process to catch up, ranging from the immediate time to reading the entire frame.

[0003] These increased and unpredictable delays are unacceptable in display and other streaming systems, especially as delays become more noticeable to users with technological advancements and updates. Therefore, the method of the present invention aims to address or at least mitigate these problems. Summary of the Invention

[0004] The invention is set forth in the independent claims and in the dependent claims.

[0005] In one aspect, the present invention provides a method for writing data to one or more buffers and reading data from one or more buffers, the method comprising:

[0006] Determine the write rate at which data is written to the first buffer;

[0007] Determine the read rate for reading data from the first buffer;

[0008] The portion of the first buffer is determined using the write rate and read rate;

[0009] Write the data into the first buffer portion;

[0010] Once the writing of data to a portion of the first buffer is complete, data reading from the first buffer begins.

[0011] as well as

[0012] Write the data into the remaining portion of the first buffer that is different from the portion of the first buffer;

[0013] The portion of the first buffer is configured such that reading data from the first buffer does not exceed writing data into the first buffer.

[0014] The first buffer can be a first-in-first-out (FIFO) buffer.

[0015] The method may also include:

[0016] Determine the write rate at which data is written to the second buffer;

[0017] Determine the read rate for reading data from the second buffer;

[0018] The portion of the second buffer is determined using the write rate and read rate;

[0019] Once the writing of data to the remaining portion of the first buffer is complete, data is written to the portion of the second buffer.

[0020] While writing data to the second buffer, continue reading data from the first buffer;

[0021] When the writing of data to a portion of the second buffer is complete, data is read from the second buffer; and data is written to the remaining portion of the second buffer that is different from the portion of the second buffer.

[0022] The second buffer portion is configured such that reading data from the second buffer does not exceed writing data into the second buffer.

[0023] The second buffer can be a first-in-first-out (FIFO) buffer.

[0024] The steps for determining the portion of the second buffer can be based on the ratio of the read rate of data read from the second buffer to the write rate of data written to the second buffer.

[0025] The step of determining a portion of the first buffer can be based on the ratio of the read rate of data read from the first buffer to the write rate of data written to the first buffer.

[0026] The first buffer portion can be calculated using the following formula:

[0027]

[0028] Where P is a portion, B is the size of the first buffer, and R is the read rate of reading data from the first buffer divided by the write rate of writing data to the first buffer.

[0029] The first buffer portion can be calculated using the following formula:

[0030]

[0031] Where P is a part, B is the buffer size of the first buffer, R is the read rate of reading data from the first buffer divided by the write rate of writing data to the first buffer, and C is a constant.

[0032] In one example, only the updated portion of the first buffer is written.

[0033] In a second aspect, the present invention provides a method for writing data to and reading data from a buffer, the method comprising:

[0034] Determine the write rate at which data is written to the buffer;

[0035] Determine the read rate at which data is read from the buffer;

[0036] Write the data to the buffer;

[0037] The write rate and read rate are used to determine when to begin reading data from the buffer, where the time is determined such that reading data from the buffer will not exceed writing data into the buffer; and

[0038] Data is read from the buffer at a predetermined time.

[0039] The buffer can be a first-in-first-out (FIFO) buffer.

[0040] In one example, only the updated portion of the buffer is written; and the time to start reading data from the buffer is calculated based on the time it takes for the write to the updated portion of the buffer to be completed.

[0041] In one example, all data in the buffer is read.

[0042] The data can be displayed data. The data can include tiles that display the data.

[0043] In a third aspect, the present invention provides a computing device including a plurality of frame buffers, wherein the computing device is configured to perform a method according to the first aspect or the second aspect.

[0044] In a fourth aspect, the present invention provides a system comprising:

[0045] Non-temporary memory for storing instructions; and

[0046] One or more hardware processors, coupled to and configured to execute instructions from the non-transitory memory to cause the system to perform operations, including:

[0047] Determine the write rate at which data is written to the first buffer;

[0048] Determine the read rate for reading data from the first buffer;

[0049] The portion of the first buffer is determined using the write rate and read rate;

[0050] Write the data into the first buffer portion;

[0051] Once the writing of data to a portion of the first buffer is complete, data reading from the first buffer begins; and

[0052] Write the data into the remaining portion of the first buffer that is different from the portion of the first buffer;

[0053] The portion of the first buffer is configured such that reading data from the first buffer does not exceed writing data into the first buffer.

[0054] In a fifth aspect, the present invention provides a system comprising:

[0055] Non-temporary memory for storing instructions; and

[0056] One or more hardware processors, coupled to and configured to execute instructions from the non-transitory memory to cause the system to perform operations, including:

[0057] Determine the write rate at which data is written to the buffer;

[0058] Determine the read rate at which data is read from the buffer;

[0059] Write the data to the buffer;

[0060] The write rate and read rate are used to determine when to begin reading data from the buffer, where the time is determined such that reading data from the buffer will not exceed writing data into the buffer; and

[0061] Data is read from the first buffer at a predetermined time.

[0062] In one example, a method for streaming data using a pair of buffers includes:

[0063] 1. Determine the relative rates (ratios) of the write and read processes;

[0064] 2. Determine the portion (part) of each buffer based on the ratio;

[0065] 3. The write process writes data into the first buffer until the end of the portion;

[0066] 4. The reading process receives a switching signal and begins reading the first buffer;

[0067] 5. The reading process repeatedly reads the first buffer until it receives another switching signal;

[0068] 6. When the write process has written data into the entire first buffer, the write process writes data into the second buffer until the end of the portion;

[0069] 7. The reading process receives another switching signal and begins reading the second buffer; and

[0070] 8. Once the write process has written the data into the entire second buffer, the process returns to step 3 above.

[0071] Repeat steps 3-8 until the data stream is complete.

[0072] This approach is advantageous because it coordinates the write and read processes based on the relative time spent writing and reading data from the buffer, respectively. Since a read process in a particular buffer begins once sufficient data has been written, there is reduced latency before data can be streamed to the endpoint. However, because data readiness is determined based on the relative rates of the write and read processes, the chance of reading stale data is advantageously reduced.

[0073] This method can be used in any streaming system, but it is advantageous when the data is display data and each of the two buffers is a frame buffer.

[0074] This ratio is advantageously determined by the following formula:

[0075]

[0076] Alternatively:

[0077]

[0078] This gives the same result for ratios, since the time required for a process is inversely proportional to the rate of the process, such that a process carried out at a rate of 2x will take half the time of a process carried out at a rate of x.

[0079] Therefore, this part can be determined by the second formula:

[0080]

[0081] The formula can be advantageously modified to allow for the addition of an offset to that portion, thereby allowing for a delay in the write process, such that the write process writes a constant amount beyond that portion before a signal is sent to the read process.

[0082] The size of this section and the buffer can be measured in any appropriate unit of measurement. For example:

[0083] Data volume in units such as bits, nibbles, bytes, and kilobytes.

[0084] • Number of pixels, tiles, slices, rows, etc.

[0085] Physical location in the memory region

[0086] It should also be understood that this method may include calculating the proportion of the buffer according to the following formula:

[0087]

[0088] In this case, the method may include using the ratio to calculate the time when data can begin to be read from the buffer, such that the read process will not exceed the write process.

[0089] Any system feature described herein can also be provided as a method feature, and vice versa. As used herein, device plus functional features can alternatively be represented according to their corresponding structures.

[0090] Any feature in one aspect of the invention may be applied to other aspects of the invention in any suitable combination. In particular, a method aspect may be applied to a system aspect, and vice versa. Furthermore, any, some, and / or all features in one aspect may be applied to any, some, and / or all features in any other aspect in any suitable combination.

[0091] It should also be understood that specific combinations of the various features described and defined in any aspect of the invention may be implemented and / or provided and / or used independently. Attached Figure Description

[0092] The embodiments will now be described by way of example only and with reference to the accompanying drawings, wherein:

[0093] Figure 1 An overview of the display system is shown;

[0094] Figure 2 The process of interacting with the buffer is shown;

[0095] Figure 3 The process is shown;

[0096] Figure 4 shows an example with a first write process rate;

[0097] Figure 5 shows an example with a second write process rate; and

[0098] Figure 6 A block diagram of the computer system is shown. Detailed Implementation

[0099] The abbreviations used in the attached diagrams and the following equations are as follows:

[0100] W: Write process

[0101] R: Reading process

[0102] • T: Time delay between read and write processes

[0103] ·T R Time required to read the entire buffer

[0104] ·T W Time required to write the entire buffer

[0105] Figure 1 An overview of an example system in which the methods of embodiments of the present invention can be used is shown. In this example, the system is a display system, including a host computing device

[11] that generates and transmits display data, the host computing device

[11] being connected to a display control device

[12] , the display control device

[12] preparing the received display data for display, and the display control device

[12] being connected to a display device

[13] . Naturally, this is merely an example, and embodiments of the present invention can be used in other streaming contexts, including contexts in which data is transmitted within a single device or in contexts in which data is received from or transmitted to multiple devices. Therefore, the connections between devices and components described in this figure can be via any internal, local, or network interface.

[0106] The host computing device

[11] contains an application

[14] that generates a frame stream of display data, such as as part of a video stream. The application

[14] runs in a processor

[14] connected to an encoder

[15] . The encoder

[15] compresses the display data in preparation for transmission across a limited bandwidth connection to a display control device

[12] . The encoder

[15] may also encrypt the data or perform any other processing required. The encoder

[15] is then connected to a frame buffer

[16] , which stores the data before transmission. A frame buffer may also exist between the application

[14] and the encoder

[15] , but it is not shown here.

[0107] The display control device

[12] includes a decoder

[17] that reverses the processing performed by the encoder

[15] , such as decompression. The decoder

[17] is connected to a frame buffer

[18] , which stores the decoded data before it is sent to the display device

[13] for display. Therefore, the frame buffer

[18] is connected to an output engine

[19] , which transmits the display data to the display device

[13] . A frame buffer may also exist that stores received data before it is decoded, but this is not shown here.

[0108] Streaming can be performed using any frame buffer in the system, and any such frame buffer can actually be implemented as two or more frame buffers. For the purposes of this description, streaming is performed using a frame buffer

[18] that stores the decoded data before it is sent to the display device

[13] .

[0109] Figure 2 The operation of a regular read and write process within a single buffer is shown.

[0110] The top arrow in the diagram represents the read process, and the arrows below represent the write process. The write process writes data to a buffer, and the read process subsequently reads the data. Ideally, there is a constant time delay between the write and read processes, as indicated by the arrow marked 'T', and the read process does not exceed the write process. However, if this does occur, the read process may output out-of-date data, which is problematic in scenarios such as... Figure 1 The display system shown may exhibit visual artifacts such as tearing, and the audio system may exhibit audio artifacts such as skipping. The time delay between the write and read processes is added to the system's total latency.

[0111] In reality, because the reading process is usually faster than the writing process, the time delay between the writing and reading processes cannot be maintained.

[0112] For example, the time required to read the entire buffer can be half the time required to write the entire buffer:

[0113]

[0114] In this scenario, if the read and write processes begin simultaneously, the buffer will have already been read twice by the time the write process has filled it.

[0115] Figure 3 It shows things like Figure 1 The process in the illustrated display system assumes that the buffer (to which the process is applied) is a frame buffer

[18] of a decoder

[17] connected to the display control device

[12] , which, as previously described, can be implemented as two or more buffers that can share a single memory region. This is merely one example; for instance, a similar approach could also be used for a frame buffer

[16] of an encoder

[15] connected to a host computing device

[11] .

[0116] At step S31, the decoder

[17] receives and decodes display data frames from the host computing device

[11] across the connection. Then, at step S32, it begins writing display data into the first frame buffer [18 / FB1]. At step S33, when it has been written up to a predetermined position in the frame buffer [18 / FB1], the decoder

[17] sends a signal to the output engine

[19] at step S34, indicating that it should begin the reading process, which begins at step S35.

[0117] The process is described in more detail again in Figures 4 and 5.

[0118] Figure 4 illustrates, for example, Figure 1 Examples of display systems, such as the one shown, in which

[0119]

[0120] As stated above.

[0121] Because of T R and T W The ratio between them is 2:1, therefore the predetermined point mentioned in step S33 is determined to be the point at which the write process has written 1 / 2 of the frame into the buffer

[18] —that is, if the buffer is the same size as the complete frame, then 1 / 2 of the buffer

[18] has been written. Therefore, in Figure 4a In step S41, the writing process writes the first half of the new frame—received in the step corresponding to S31 but not shown in Figure 4—into the first frame buffer [18 / FB1]. As previously stated, this is done by... Figure 4a The arrow marked W is shown in the first part.

[0122] If the first frame buffer [18 / FB1] is read at this point, the image output will consist of half new frame (sun) and half previous frame (cloud). This is an example of tearing. In contrast, in this example, the reading process is delayed; Figure 4a In this context, it is shown as reading the second frame buffer containing the complete previous frame (face) [18 / FB2], but the reading process may be inactive during step S41 if the frame being written is the first frame in the stream.

[0123] When the writing process has completed the first half of the frame, a signal is sent to the output engine

[19] at step S34. The output engine

[19] then begins reading the first frame buffer [18 / FB1], as indicated by the arrow marked R at step S42. This corresponds to... Figure 3 Step S35 in the process.

[0124] While a read process is being performed on the first frame buffer [18 / FB1], a write process continues to write the remaining portion of the data into the first frame buffer [18 / FB1]. This means that by the time the read process has reached the midpoint of the frame buffer [18 / FB1], the write process will have reached three-quarters of the way through, and so on, so that both processes reach the end of the frame together, but the read process will never overtake the write process.

[0125] When the write process has completed the first frame buffer [18 / FB1], it is in Figure 4b At step S43, the system moves to the second frame buffer [18 / FB2] to begin writing a new frame. This corresponds to returning to... Figure 3 Step S32.

[0126] As previously described regarding the first frame buffer [18 / FB1] at step S41, the write process writes the first half (heart) of the new frame into the second frame buffer [18 / FB2]. Simultaneously, a second read process is performed on the first frame buffer [18 / FB1], which is complete and therefore tearing is not required. As previously stated, when the write process has written the first half of the frame buffer [18 / FB2] (step S33), the decoder

[17] sends a signal to the output engine

[19] (step S34), and the output engine

[19] begins reading the second frame buffer [18 / FB2] at step S44, again corresponding to... Figure 3 Step S35. As previously stated, while a read process is being performed on the second frame buffer [18 / FB2], the write process continues and completes the frame, and the read process cannot exceed it because the start time of the read process is determined based on the relative speed of the two processes.

[0127] When the writing process has been completed and the data has been written to the second frame buffer [18 / FB2], it returns to the first frame buffer [18 / FB1] and repeats the process from step S41, which again corresponds to step S32.

[0128] The signal that triggers the transition of the read process between frame buffers [18 / FB1 / 18 / FB2] is in Figure 4b The signal is described as being provided by the decoder

[17] . However, it could also be an external signal, clock signal, or any other suitable external or internal signal from, for example, a display device

[13] indicating its expectation of a new frame. This signal is independent of the progress of the reading process through the buffer, so that if there is a delay in the reading process for any reason, that delay will not propagate through the system; the reading process can be sent at any time to the beginning of the ready frame, unlike a conventional system in which the reading process must proceed sequentially through all complete frames.

[0129] Therefore, this version of the method will produce output on the display device

[13] , such as Figure 4c The output shown is as follows: At step S41, the face is shown. Then, the read process switches to the first frame buffer [18 / FB1], so the sun is shown at step S42. At step S43, the read process reads the first frame buffer [18 / FB1] a second time, so the sun is shown again; this repetition occurs when the read process is faster than the write process. At step S44, the read process switches to the second frame buffer [18 / FB2] again, so the heart is shown. It will be shown again in the next iteration, and so on.

[0130] This method is not limited to a 2:1 ratio between the read and write rates and can be extended to any ratio. Figure 5 illustrates further iterations of the method, where...

[0131]

[0132] This means that the reading process is three times faster than the writing process. Therefore, the frame buffer

[18] cannot be divided uniformly because the ratio between the reading and writing rates is 2:1. However, the following ratio can be used to calculate the predetermined stages:

[0133]

[0134] That is, 2 / 3 of the process through the buffer

[18] . This can be calculated at the start of each new display session, or it can be hardcoded, for example, at manufacturing time or hardcoded into the display driver. In practice, “2 / 3 of the process through the buffer

[18] ” can be implemented based on the amount of data: for example, in a buffer holding 3GB of data, once 2GB of data has been written, the reading process can begin:

[0135]

[0136] Alternatively, "2 / 3 of the process through the buffer

[18] " can be implemented based on the position in the frame: for example, if the frame contains 60 tiles, then 40 tiles have already been written:

[0137]

[0138] It should also be understood that this portion is not necessarily a contiguous area of ​​the buffer's memory. For example, when the read process will begin after 40 tiles have been written, the 40 tiles can be any combination of tiles to be written to the buffer. Furthermore, although in the example above, the read process has been described as starting once the write process has completed a defined proportion of the frame buffer being written, the size of the frame buffer, or the number of tiles, this method can alternatively be based on T. R With T W The ratio is used to calculate when the read process will start, so that the read process will not exceed the write process, and the read process can start at the calculated time, regardless of the amount of data actually written to the buffer by the write process.

[0139] At step S51, corresponding to step S32 as described above, the decoder

[17] writes the data (sun) into the first third of the first frame buffer [18 / FB1], while the output engine

[19] reads the entire second frame buffer [18 / FB2] (which in this example contains the existing frame (face)). At step S52, the decoder

[17] continues to write the second third of the frame into the first frame buffer [18 / FB1], while the output engine

[19] again reads the entire second frame buffer [18 / FB2].

[0140] At the end of step S52, two-thirds of the frame buffer [18 / FB1] has been written, therefore the write process has been completed. Figure 3 The predetermined stage at step S33. Therefore, at step S34, the decoder

[17] sends a signal to the output engine

[19] to begin reading the first frame buffer [18 / FB1], and the output engine

[19] in Figure 5bThe reading of the first frame buffer [18 / FB1] begins at step S53 (corresponding to step S35). As previously described, during the time it takes for the reading process to complete in the first frame buffer [18 / FB1], the writing process has already written the remainder of the frame into the first frame buffer [18 / FB1].

[0141] At step S54, corresponding to a return to step S32, the decoder

[17] begins writing the next frame (heart) into the second frame buffer [18 / FB2], while the output engine

[19] reads the first frame buffer [18 / FB1] for the second time. The output engine

[19] in Figure 5c At step S55, the first frame buffer [18 / FB1] is read for the third time, while the write process writes the second third of the new frame into the second frame buffer [18 / FB2]. At the end of this stage, the predetermined point has been reached, corresponding to step S33, so a signal is sent to the output engine

[19] (step S34) to indicate that it should begin reading the second frame buffer [18 / FB2], which is completed at step S56 (corresponding to step S35). During step S56, the decoder

[17] also completes writing the frame into the second frame buffer [18 / FB2] as previously described.

[0142] The output obtained is in Figure 5d The diagram shows that at step S51, the initial frame, the face, is shown from the second frame buffer [18 / FB2]. It continues to exist at step S52 until the output engine

[19] switches to reading from the first frame buffer [18 / FB1] at S53, thus showing the sun. At steps S54 and S55, the output engine

[19] continues reading from the first frame buffer [18 / FB1] while the decoder

[17] writes the first two-thirds of the frame into the second frame buffer [18 / FB2], then the output engine

[19] switches to reading from the second frame buffer [18 / FB2], and the heart is shown at step S56. As before, this results in repetition due to the nature of the system where the reading process is faster than the writing process.

[0143] The above description assumes the entire frame is updated. However, in some systems, only a portion of the data (e.g., only the part of the frame displaying the data that has changed compared to previous frames, sometimes referred to as a "dirty rectangle") can be updated at a time. This means the amount and location of data written to the frame buffer can change with each frame. While the write process can still scan down the frame buffer in the usual way and update only where appropriate, as described above regarding the read process, the write process only accesses and updates the appropriate locations, and the read process may be more efficient for this limited write by starting as quickly as possible, as in contrast to a full write.

[0144] In many conventional systems, the read process will still read the entire buffer, regardless of which parts have been updated, therefore T R The time required to update the write buffer will be fixed. However, the time required to update the write buffer will depend on how much the buffer has been updated. This information is known during the write process and can be used to determine when to begin the read process.

[0145] For example, if the buffer is divided into N rows of data to be read sequentially from 0 to N-1, then the time it takes to read a given row n can be described as t. r,n It can be determined by the following formula:

[0146]

[0147] That is, the time to read line n is the time when the reading process starts plus the time offset based on the value of n and the time required to read the entire buffer, divided by the total number of lines.

[0148] Assuming the update portion consists of M rows of data to be written sequentially within the range from 0 to M-1, the time it takes for the write function to complete for a given row m can be described as t. w,m It can be determined by a similar formula:

[0149]

[0150] That is, the time it takes for the write process to complete writing row m is the start time of the write process plus the time offset based on the value of m and the time required to write the entire buffer, divided by the total number of rows.

[0151] The M rows in the updated portion can actually be divided into multiple updated portions, and even a single updated portion may not start at the beginning of the buffer. Therefore, it is necessary to map each row m to row n in the buffer, depending on the row's position in the buffer:

[0152] n = f(m)

[0153] Each updated row in the updated portion is associated with a row in the buffer.

[0154] Then choose the start time of the reading process, such that it is approximated as:

[0155]

[0156] Therefore, in one example, where:

[0157] ·m=0

[0158] ·f(m)=n=3

[0159] ·N=8

[0160] ·T R =x

[0161] ·T W =2x

[0162]

[0163] therefore

[0164]

[0165] Of course, the inequality must be determined for each value of m in the updated portion or for all updated portions to produce the final value.

[0166] The start time of the reading process can then be chosen to maintain this inequality, eliminating the need to maintain a precise ratio between the size of the already updated buffer portion and the start time of the reading process. This calculation can be performed on a per-frame basis by the device that determines the start time of the reading process as described above (the decoder

[17] in the example above).

[0167] Therefore, in these cases, if it is known that the write process is not writing the entire frame, the number of parts used in this method can be reduced; for example, if it is known that only the latter half of the frame in the system described in Figure 4 is being updated, the read process can begin simultaneously with the write process, as would essentially be the cases shown in steps S42 and S44. Using this method can reduce the predictability of the system, but it can also reduce the latency caused by double buffering and allow the system to be used efficiently with partial updates.

[0168] Figure 6 This is a block diagram of a computer system

[600] suitable for implementing one or more embodiments of the present disclosure, including a host device

[11] or a display control device

[12] . In various implementations, the host device

[11] may include a mobile cellular phone, a personal computer (PC), a laptop computer, a wearable computing device, etc., suitable for wireless communication, and each of the host device

[11] and the display control device

[12] may include a network computing device. Therefore, it should be understood that these devices [12, 13] may be implemented as a computer system

[600] in such a way as to...

[0169] The computer system

[600] includes a bus

[612] or other communication mechanism for transmitting information data, signals, and information between various components of the computer system

[600] . These components include input / output (I / O) components

[604] that process user actions, such as keypad / keyboard selection keys, selecting one or more buttons or links, and sending corresponding signals to the bus

[612] . The I / O components

[604] may also include output components, such as a display

[602] and cursor controls

[608] (such as a keyboard, keypad, mouse, etc.). Optional audio input / output components

[606] may also be included to allow the user to input information using speech by converting audio signals. The audio I / O components

[606] allow the user to hear audio. A transceiver or network interface

[620] transmits and receives signals between the computer system

[600] and other devices via a network

[622] . In one embodiment, the transmission is wireless, but other transmission media and methods may also be suitable. The processor

[614] (which may be a microcontroller, digital signal processor (DSP), or other processing unit) processes these various signals, such as for display on the computer system

[600] or for transmission to other devices via a communication link

[624] . The processor

[614] may also control the transmission of information such as cookies or IP addresses to other devices.

[0170] The computer system

[600] also includes system memory components

[610] (e.g., RAM), static storage components

[616] (e.g., ROM), and / or disk drives

[618] (e.g., solid-state drives, hard disk drives). The computer system

[600] performs specific operations by the processor

[614] and other components by executing one or more sequences of instructions contained in the system memory components

[610] . For example, the processor

[614] may be used to perform the functions of the application

[14] of the host device

[11] .

[0171] Executable logic for performing any of the described functions may be encoded in a computer-readable medium, which may refer to any medium that participates in providing instructions to a processor

[614] for execution. Such a medium may take many forms, including but not limited to non-volatile media, volatile media, and transmission media. In various implementations, non-volatile media include optical discs or magnetic disks, volatile media include dynamic memory, such as system memory components

[610] , and transmission media include coaxial cables, copper wires, and optical fibers, including wires containing a bus

[612] . In one embodiment, the logic is encoded in a non-transitory computer-readable medium, such as a magnetic disk or optical disc or other magnetic / optical storage medium, or flash memory or other solid-state memory (e.g., integrated into a device or in the form of a memory card). In one example, the transmission medium may take the form of sound waves or light waves, such as those generated during radio wave, optical, and infrared data communications.

[0172] In various embodiments of this disclosure, the execution of a sequence of instructions for practicing this disclosure may be performed by a computer system

[600] . In various other embodiments of this disclosure, multiple computer systems

[600] coupled to a network (e.g., such as a LAN, WLAN, PTSN, and / or various other wired or wireless networks, including telecommunications, mobile, and cellular telephone networks) via a communication link

[624] may execute sequences of instructions to practice this disclosure in a coordinated manner with each other.

[0173] The above embodiments and examples should be understood as illustrative examples. Where applicable, the various embodiments provided in this disclosure may be implemented using hardware, software, or a combination of hardware and software. Furthermore, where applicable, the various hardware and / or software components described herein may be combined into composite components including software, hardware, and / or both, without departing from the spirit of this disclosure. Where applicable, the various hardware and / or software components described herein may be divided into sub-components including software, hardware, or both, without departing from the scope of this disclosure. Additionally, where applicable, it is contemplated that software components may be implemented as hardware components, and vice versa.

[0174] The software (such as program code and / or data) according to this disclosure may be stored on one or more computer-readable media. It is also contemplated that the software identified herein may be implemented using one or more general-purpose or special-purpose computers and / or computer systems, networked and / or otherwise. Where applicable, the order of the various steps described herein may be changed, combined into compound steps, and / or divided into sub-steps to provide the features described herein.

[0175] The various features and steps described herein can be implemented as a system comprising one or more memories storing the various information described herein and one or more processors coupled to the one or more memories and networks, wherein the one or more processors are operable to perform the steps as described herein, as a non-transitory machine-readable medium comprising a plurality of machine-readable instructions, which, when executed by the one or more processors, are adapted to cause the one or more processors to perform methods including the steps described herein and methods executed by one or more devices (such as hardware processors, user equipment, servers, and other devices described herein).

Claims

1. A method of writing data to and reading data from one or more buffers, the method comprising: determining a write rate at which data is to be written into a first buffer; determining a read rate at which data is to be read from the first buffer; using the write rate and the read rate to determine a portion of the first buffer; writing only an updated portion of data into the portion of the first buffer and not performing any data reads while writing data into the portion of the first buffer; when writing of data to the portion of the first buffer has completed, beginning to read data from the first buffer and simultaneously beginning to write data into a remaining portion of the first buffer different from the portion of the first buffer; wherein the portion of the first buffer is determined such that reading of data from the first buffer does not exceed writing of data into the first buffer.

2. The method of claim 1, wherein the first buffer is a first-in-first-out (FIFO) buffer.

3. The method of claim 1, the method further comprising: determining a write rate at which data is to be written into a second buffer; determining a read rate at which data is to be read from the second buffer; using the write rate and the read rate to determine a portion of the second buffer; when writing of data to the remaining portion of the first buffer has completed, writing data into the portion of the second buffer; continuing to read data from the first buffer while writing data into the portion of the second buffer; when writing of data to the portion of the second buffer is complete, beginning to read data from the second buffer; and writing data into a remaining portion of the second buffer different from the portion of the second buffer; wherein the portion of the second buffer is determined such that reading of data from the second buffer does not exceed writing of data into the second buffer.

4. The method of claim 3, wherein the second buffer is a first-in-first-out (FIFO) buffer.

5. The method of claim 3, wherein the step of determining the portion of the second buffer is based on a ratio of the read rate at which data is read from the second buffer to the write rate at which data is written to the second buffer.

6. The method of claim 1, wherein the step of determining the portion of the first buffer is based on a ratio of the read rate at which data is read from the first buffer to the write rate at which data is written to the first buffer.

7. The method of claim 1, wherein the portion of the first buffer is calculated using the following formula: P = B * R / (B + R) where P is the portion, B is a size of the first buffer, and R is the read rate at which data is read from the first buffer divided by the write rate at which data is written to the first buffer.

8. The method of claim 6, wherein the portion of the first buffer is calculated using the following formula: P = B * R / (B + R) where P is the portion, B is a size of the first buffer, and R is the read rate at which data is read from the first buffer divided by the write rate at which data is written to the first buffer. ​ ​ where P is the portion, B is a buffer size of the first buffer, R is the read rate from the first buffer divided by the write rate to the first buffer, and C is a constant.

9. A method of writing data to a buffer and reading data from a buffer, the method comprising: determining a write rate at which data is written into the buffer; determining a read rate at which data is read from the buffer; starting to write an updated portion of data into the buffer; using the write rate and the read rate to determine a time at which to start reading data from the buffer, wherein the time is determined such that the reading of data from the buffer will not exceed the writing of data into the buffer; and starting to read data from the buffer at the determined time; wherein the time at which to start reading data from the buffer is calculated based on a time at which writing the updated portion of data to the buffer will be complete.

10. The method of claim 9, wherein the buffer is a first-in-first-out (FIFO) buffer.

11. The method of claim 9, wherein all of the data in the buffer is read.

12. The method of claim 9, wherein the data is display data.

13. The method of claim 12, wherein the data comprises tiles of display data.

14. A computing device comprising a plurality of frame buffers, wherein the computing device is configured to perform the method of any one of claims 1 to 13.

15. A computer system comprising: a non-transitory memory storing instructions; and one or more hardware processors coupled to the non-transitory memory and configured to execute the instructions from the non-transitory memory to cause the computer system to perform operations comprising: determining a write rate at which data is written into a first buffer; determining a read rate at which data is read from the first buffer; using the write rate and the read rate to determine a portion of the first buffer; writing only an updated portion of data into the portion of the first buffer and not performing any data reads while writing data into the portion of the first buffer; starting to read data from the first buffer when writing of data to the portion of the first buffer has completed and concurrently starting to write data into a remaining portion of the first buffer different from the portion of the first buffer; wherein the portion of the first buffer is determined such that the reading of data from the first buffer does not exceed the writing of data into the first buffer.

16. A computer system comprising: a non-transitory memory storing instructions; and one or more hardware processors coupled to the non-transitory memory and configured to execute the instructions from the non-transitory memory to cause the computer system to perform operations comprising: determining a write rate at which data is written into a buffer; determining a read rate at which data is to be read from the buffer; starting to write an updated portion of data into the buffer; using the write rate and the read rate to determine a time at which to start reading data from the buffer, wherein the time is determined such that the reading of data from the buffer will not exceed the writing of data into the buffer; and starting to read data from the buffer at the determined time; wherein the time at which to start reading data from the buffer is calculated based on a time at which the writing of the updated portion of data into the buffer will be completed.

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