Three-dimensional memory devices including backside trench support structures and methods of forming the same

Abstract

A three-dimensional memory device includes a tier stack located over a substrate and laterally spaced apart from one another by backside trenches. Each of the tier stacks includes a respective alternating stack of insulating layers and electrically conductive layers. Memory openings vertically extend through respective ones of the alternating stacks and are filled with respective memory opening fill structures. Each of the memory opening fill structures includes a respective vertical semiconductor channel and a respective vertical memory element stack. Each backside trench fill structure includes a respective row of backside trench bridge structures that are farther from the substrate than a farthest one of the electrically conductive layers. The backside trench bridge structures can provide structural support during replacement processes that form the electrically conductive layers.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to the field of semiconductor devices, and particularly to three-dimensional memory devices including backside trench support structures and methods of forming the same. BACKGROUND

[0002] Three-dimensional vertical NAND strings each having one bit are disclosed in T. Endoh et al., “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell,” IEDM Proc. (2001) 33-36. SUMMARY

[0003] According to aspects of the present disclosure, there is provided a three-dimensional memory device comprising: a tier stack located above a substrate and laterally spaced apart from one another by backside trenches extending laterally along a first horizontal direction, wherein each tier stack of the tier stack comprises a respective alternating stack of insulating layers and electrically conductive layers; memory openings extending vertically through respective ones of the alternating stacks and filled with respective memory opening fill structures, wherein each memory opening fill structure of the memory opening fill structures comprises a respective vertical semiconductor channel and a respective vertical memory element stack; and backside trench fill structures located within respective ones of the backside trenches, wherein each backside trench fill structure of the backside trench fill structures comprises a respective row of backside trench bridge structures laterally spaced apart from one another along the first horizontal direction and further from the substrate than a furthest one of the electrically conductive layers.

[0004] According to another aspect of the present disclosure, a method of forming a three-dimensional memory device is provided, the method comprising: forming an alternating stack of insulating layers and sacrificial material layers over a substrate; forming memory openings through the alternating stack; forming memory opening fill structures in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical semiconductor channel and a respective vertical memory element stack; forming a contact level dielectric layer over the alternating stack; forming backside trenches laterally extending through the contact level dielectric layer and the alternating stack along a first horizontal direction to form a layer stack comprising respective patterned portions of the contact level dielectric layer and respective patterned portions of the alternating stack, the layer stack being laterally spaced apart from one another by the backside trenches; forming a row of backside trench bridge structures laterally spaced apart from one another within each of the backside trenches along the first horizontal direction, wherein the backside trench bridge structures are farther from the substrate than a farthest patterned portion of the sacrificial material layers; and replacing the patterned portions of the sacrificial material layers with electrically conductive layers. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 is a schematic vertical cross-sectional view of an exemplary structure after formation of at least one peripheral device, a semiconductor material layer, and a gate dielectric layer in accordance with an embodiment of the present disclosure.

[0006] Figure 2 is a schematic vertical cross-sectional view of an exemplary structure after formation of an alternating stack of insulating layers and sacrificial material layers in accordance with an embodiment of the present disclosure.

[0007] Figure 3 is a schematic vertical cross-sectional view of an exemplary structure after formation of a stepped platform and a back-directed stepped dielectric material portion in accordance with an embodiment of the present disclosure.

[0008] Figure 4A is a schematic vertical cross-sectional view of an exemplary structure after formation of memory openings and support openings in accordance with an embodiment of the present disclosure.

[0009] Figure 4B is a top-down view of the exemplary structure of Figure 4A is a plane of the cross-section of Figure 4A .

[0010] Figures 5A-5H is a sequence of schematic vertical cross-sectional views of an exemplary structure during formation of memory opening fill structures, an optional dielectric core, and drain regions within memory openings located within the exemplary structure during formation thereof in accordance with an embodiment of the present disclosure.

[0011] Figure 6 is a schematic vertical cross-sectional view of an exemplary structure after forming memory stack structures and support pillar structures, in accordance with an embodiment of the present disclosure.

[0012] Figure 7A is a schematic vertical cross-sectional view of an exemplary structure after forming backside trenches and source regions, in accordance with an embodiment of the present disclosure.

[0013] Figure 7B is a partial perspective top-down view of the exemplary structure of Figure 7A is a plane of the schematic vertical cross-sectional view of Figure 7A

[0014] Figure 8 is a schematic vertical cross-sectional view of an exemplary structure after forming a sacrificial fill material layer, in accordance with an embodiment of the present disclosure.

[0015] Figure 9A is a schematic vertical cross-sectional view of an exemplary structure after forming a sacrificial backside trench fill structure, in accordance with an embodiment of the present disclosure.

[0016] Figure 9B is a partial perspective top-down view of the exemplary structure of Figure 9A is a plane of the schematic vertical cross-sectional view of Figure 9A

[0017] Figure 10A is a schematic vertical cross-sectional view of an exemplary structure after forming a hardmask layer and a patterned photoresist layer, in accordance with an embodiment of the present disclosure.

[0018] Figure 10B is a partial perspective top-down view of the exemplary structure of Figure 10A is a plane of the schematic vertical cross-sectional view of Figure 10A

[0019] Figure 11A is a schematic vertical cross-sectional view of an exemplary structure after forming recessed cavities in upper portions of the sacrificial backside trench fill structure, in accordance with an embodiment of the present disclosure.

[0020] Figure 11B is a partial perspective top-down view of the exemplary structure of Figure 11A is a plane of the schematic vertical cross-sectional view of Figure 11A

[0021] Figure 12 is a schematic vertical cross-sectional view of an exemplary structure after forming a dielectric fill material layer, in accordance with an embodiment of the present disclosure.

[0022] ​​​​Figure 13A is a vertical cross-sectional view of an exemplary structure after formation of a sacrificial trench bridge structure in accordance with an embodiment of the present disclosure.

[0023] Figure 13B is Figure 13A is a partial perspective top-down view of an exemplary structure of Figure 13A is a plane of the schematic vertical cross-sectional view of Figure 13C Figure 13A is a partial perspective top-down view of an alternative embodiment of an exemplary structure of

[0024] Figure 14A is a schematic vertical cross-sectional view of an exemplary structure after formation of a backside cavity by removal of a sacrificial backside trench fill structure in accordance with an embodiment of the present disclosure.

[0025] Figure 14B is Figure 14A is a partial perspective top-down view of an exemplary structure of Figure 14A is a plane of the schematic vertical cross-sectional view of

[0026] Figure 15 is a schematic vertical cross-sectional view of an exemplary structure after formation of a backside recess in accordance with an embodiment of the present disclosure.

[0027] Figures 16A-16D is a sequential vertical cross-sectional view of a region of an exemplary structure during formation of a conductive layer in accordance with an embodiment of the present disclosure.

[0028] Figure 17 is Figure 16D is a schematic vertical cross-sectional view of an exemplary structure at a processing step of

[0029] Figure 18A is a schematic vertical cross-sectional view of an exemplary structure after removal of conductive material from within a backside trench in accordance with an embodiment of the present disclosure.

[0030] Figure 18B is Figure 18A is a partial perspective top-down view of an exemplary structure of Figure 18A is a plane of the schematic vertical cross-sectional view of

[0031] Figure 19A is a schematic vertical cross-sectional view of an exemplary structure after formation of an insulating spacer for each backside trench in accordance with an embodiment of the present disclosure.

[0032] Figure 19B is Figure 19A is a partial perspective top-down view of an exemplary structure of Figure 19A is a plane of the schematic vertical cross-sectional view of​

[0033] Figure 19C is a vertical cross-sectional view of the exemplary structure taken along vertical plane C-C’ of Figure 19B

[0034] Figure 20A is a schematic vertical cross-sectional view of an exemplary structure after forming backside contact via structures of each backside trench according to embodiments of the present disclosure.

[0035] Figure 20B is a partial perspective top-down view of the exemplary structure of Figure 20A Figure 20A

[0036] Figure 20C is a vertical cross-sectional view of the exemplary structure taken along vertical plane C-C’ of Figure 20B

[0037] Figure 21A is a schematic vertical cross-sectional view of an exemplary structure after forming additional contact via structures according to embodiments of the present disclosure.

[0038] Figure 21B is a top-down view of the exemplary structure of Figure 21A Figure 21A

[0039] Figure 21C is a top-down view of an alternative configuration of the exemplary structure. DETAILED DESCRIPTION

[0040] As described above, the present disclosure relates to three-dimensional memory devices including backside trench support structures that reduce or prevent stack tilting or collapse during replacement of sacrificial material layers with electrically conductive layers, methods of fabrication thereof, aspects thereof described below. Embodiments of the present disclosure can be used to form various structures, including multilevel memory structures, non-limiting examples of which include semiconductor devices such as three-dimensional memory array devices including multiple NAND memory strings.

[0041] The drawings are not drawn to scale. Where multiple instances of an element are shown in the drawings, multiple instances of the element can be repeated unless explicitly described or otherwise clearly indicated otherwise. Numerical designations such as “first,” “second,” and “third” are merely used to identify like elements and different numerical designations can be employed throughout the specification and claims of the present disclosure. The term “at least one” element means all possibilities including the possibility of a single element and the possibility of multiple elements.

[0042] ​​​​​​The same reference numbers can indicate the same elements or like elements. Elements having the same reference numbers are assumed to have the same composition and the same function unless otherwise indicated. “Contact between” elements means direct contact between elements that share an edge or surface unless otherwise indicated. Two or more elements are “separated from” each other if they are not in direct contact with each other. As used herein, a first element that is “on” a second element can be on an outer side of a surface of the second element or on an inner side of the second element. As used herein, a first element is “directly on” a second element if there is physical contact between a surface of the first element and a surface of the second element. As used herein, a first element is “electrically connected to” a second element if there is an electrically conductive path between the first element and the second element that is composed of at least one electrically conductive material. As used herein, a “prototype” structure or “in-process” structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component thereof.

[0043] As used herein, a “layer” refers to a portion of material that includes a region having a thickness. A layer can extend over the entirety of an underlying or overlying structure, or can have a

[0044] Reference is made to Figure 1 FIG. 1 shows an exemplary structure according to embodiments of the present disclosure, which can be used, for example, to fabricate a device structure containing vertical NAND memory devices. The exemplary structure includes a substrate (9, 10), which can be a semiconductor substrate. The substrate can include a substrate semiconductor layer 9 and an optional semiconductor material layer 10. The substrate semiconductor layer 9 can be a semiconductor wafer or a semiconductor material layer, and can include at least one elemental semiconductor material (e.g., single crystal silicon wafer or layer), at least one III-V compound semiconductor material, at least one II- VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. The substrate can have a major surface 7, which can be, for example, a topmost surface of the substrate semiconductor layer 9. The major surface 7 can be a semiconductor surface. In one embodiment, the major surface 7 can be a single crystalline semiconductor surface, such as a single crystalline semiconductor surface.

[0045] As used herein, a “semiconductor material” refers to a material that has a resistivity in the range from 1.0 x 10 -6 S / cm to 1.0 x 10 5Materials with electrical conductivity in the range of S / cm. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the absence of electrical dopants of 1.0 × 10⁻⁶ S / cm. -6 S / cm up to 1.0×10 5 Materials with conductivity in the range of S / cm are produced, and materials with conductivity from 1.0 S / cm to 1.0 × 10⁻⁶ S / cm can be produced with appropriate doping agents. 5 Doped materials with electrical conductivity in the range of S / cm. As used herein, “electrical dopant” refers to a p-type dopant that adds holes to the valence band of the band structure, or an n-type dopant that adds electrons to the conduction band of the band structure. As used herein, “conductive material” refers to a material with conductivity greater than 1.0 × 10⁻⁶ S / cm. 5 Materials with a conductivity of S / cm. As used herein, "insulating material" or "dielectric material" refers to a material with a conductivity of less than 1.0 × 10⁻⁶ S / cm. -6 Materials with an electrical conductivity of S / cm. As used herein, "heavily doped semiconductor material" refers to a material doped with an electrically conductive agent at a sufficiently high atomic concentration to become a conductive material (i.e., having a conductivity greater than 1.0 × 10⁻⁶ S / cm) when formed into a crystalline material or converted into a crystalline material by an annealing process (e.g., starting from an initial amorphous state). 5 Semiconductor materials with a conductivity of S / cm. "Doped semiconductor materials" can be heavily doped semiconductor materials, or can include those exhibiting a conductivity of 1.0 × 10⁻⁶ S / cm. -6 S / cm up to 1.0×10 5 Semiconductor materials with electrical dopant concentrations (i.e., p-type and / or n-type dopant) in the range of S / cm. "Intrinsic semiconductor material" refers to a semiconductor material undoped with electrical dopants. Therefore, a semiconductor material can be semiconductor or conductive, and can be intrinsic or doped. Doped semiconductor materials can be semiconductor or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material comprising at least one metallic element. All conductivity measurements were performed under standard conditions.

[0046] At least one semiconductor device 700 of the peripheral circuit can be formed on a portion of the substrate semiconductor layer 9. The at least one semiconductor device can include, for example, a field effect transistor. The at least one shallow trench isolation structure 720 can be formed, for example, by etching a portion of the substrate semiconductor layer 9 and depositing a dielectric material therein. A gate dielectric layer, at least one gate conductor layer, and a gate cap dielectric layer can be formed over the substrate semiconductor layer 9 and can be subsequently patterned to form at least one gate structure (750, 752, 754, 758), each of which can include a gate dielectric 750, a gate electrode (752, 754), and a gate cap dielectric 758. The gate electrode (752, 754) can include a stack of a first gate electrode portion 752 and a second gate electrode portion 754. At least one gate spacer 756 can be formed around the at least one gate structure (750, 752, 754, 758) by depositing and anisotropically etching a dielectric liner. An active region 730 can be formed in an upper portion of the substrate semiconductor layer 9, for example, by introducing electrical dopants with the at least one gate structure (750, 752, 754, 758) as a mask structure. Additional masks can be employed as desired. The active region 730 can include source and drain regions of a field effect transistor. A first dielectric liner 761 and a second dielectric liner 762 can be optionally formed. Each of the first and second dielectric liners (761, 762) can include a silicon oxide layer, a silicon nitride layer, and / or a dielectric metal oxide layer. As used herein, silicon oxide includes silicon dioxide as well as non-stoichiometric silicon oxides having more or less than two oxygen atoms for each silicon atom. Silicon dioxide is preferred. In an illustrative example, the first dielectric liner 761 can be a silicon oxide layer and the second dielectric liner 762 can be a silicon nitride layer. The at least one semiconductor device of the peripheral circuit can comprise a driver circuit of a subsequently formed memory device, which can include at least one NAND device.

[0047] A dielectric material such as silicon oxide can be deposited over the at least one semiconductor device and can be subsequently planarized to form a planarized dielectric layer 770. In one embodiment, a planarized top surface of the planarized dielectric layer 770 can be coplanar with top surfaces of the dielectric liners (761, 762). Subsequently, the planarized dielectric layer 770 and the dielectric liners (761, 762) can be removed from an area to physically expose a top surface of the substrate semiconductor layer 9. As used herein, a surface is "physically exposed" if the surface is in physical contact with a vacuum or a gas phase material such as air.

[0048] The optional semiconductor material layer 10, if present, can be formed on the top surface of the substrate semiconductor layer 9 by deposition of single crystalline semiconductor material (e.g., by selective epitaxy) before or after formation of the at least one semiconductor device 700. The deposited semiconductor material can be the same as or different from the semiconductor material of the substrate semiconductor layer 9. The deposited semiconductor material can be any material that can be used for the substrate semiconductor layer 9, as described above. The single crystalline semiconductor material of the semiconductor material layer 10 can be epitaxially aligned with the single crystalline structure of the substrate semiconductor layer 9. Portions of the deposited semiconductor material that are above the top surface of the planarization dielectric layer 170 can be removed, e.g., by chemical mechanical planarization (CMP). In this case, the semiconductor material layer 10 can have a top surface that is coplanar with the top surface of the planarization dielectric layer 770.

[0049] The region (i.e., area) of the at least one semiconductor device 700 is referred to herein as a peripheral device region 200. The region in which the memory array is subsequently formed is referred to herein as a memory array region 100. A contact region 300 for a subsequently formed stepped platform of conductive layers can be provided between the memory array region 100 and the peripheral device region 200.

[0050] In one alternative embodiment, the peripheral device region 200 containing the at least one semiconductor device 700 for peripheral circuitry can be located under the memory array region 100 in CMOS under array configuration. In another alternative embodiment, the peripheral device region 200 can be located on a separate substrate that is subsequently bonded to the memory array region 100.

[0051] Reference Figure 2 A stack of an alternating plurality of first material layers (which can be insulating layers 32) and second material layers (which can be sacrificial material layers 42) is formed over a top surface of a substrate (9, 10). As used herein, a “material layer” refers to a layer that includes a material throughout its entirety. As used herein, an alternating plurality of first elements and second elements refers to a structure in which instances of the first elements and instances of the second elements alternate. Each instance of the first element that is not an end element of the alternating plurality of elements is adjoined on both sides by two instances of the second element, and each instance of the second element that is not an end element of the alternating plurality of elements is adjoined on both ends by two instances of the first element. The first elements can have the same thickness therebetween, or can have different thicknesses. The second elements can have the same thickness therebetween, or can have different thicknesses. The alternating plurality of first material layers and second material layers can begin with an instance of the first material layer or an instance of the second material layer, and can end with an instance of the first material layer or an instance of the second material layer. In one embodiment, the instances of the first elements and the instances of the second elements can form a cell that is periodically repeated within the alternating plurality of elements.

[0052] Each first material layer includes a first material, and each second material layer includes a second material that is different from the first material. In one embodiment, each first material layer can be an insulating layer 32, and each second material layer can be a sacrificial material layer. In this case, the stack can include a plurality of alternating insulating layers 32 and sacrificial material layers 42, and the prototype stack comprises alternating layers of insulating layers 32 and sacrificial material layers 42.

[0053] The plurality of alternating stacks is referred to herein as an alternating stack (32, 42). In one embodiment, the alternating stack (32, 42) can include insulating layers 32 comprised of a first material and sacrificial material layers 42 comprised of a second material, where the second material is different from the material of the insulating layers 32. The first material of the insulating layers 32 can be at least one insulating material. Thus, each insulating layer 32 can be a layer of insulating material. Insulating materials that can be used for the insulating layers 32 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the insulating layers 32 can be silicon oxide.

[0054] The second material of the sacrificial material layers 42 is a sacrificial material that is selectively removable with respect to the first material of the insulating layers 32. As used herein, the removal of the first material is “selective with respect to” the second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the “selectivity” of the removal process for the first material with respect to the second material.

[0055] The sacrificial material layers 42 can include an insulating material, a semiconducting material, or a conductive material. The second material of the sacrificial material layers 42 can be subsequently replaced with a conductive electrode that can function as, for example, a control gate electrode of a vertical NAND device. Non-limiting examples of the second material include silicon nitride, amorphous semiconducting material (such as amorphous silicon), and poly crystalline semiconducting material (such as poly silicon). In one embodiment, the sacrificial material layers 42 can be spacer material layers comprising silicon nitride or a semiconducting material including at least one of silicon and germanium.

[0056] In one embodiment, the insulating layers 32 can comprise silicon oxide, and the sacrificial material layers can comprise silicon nitride sacrificial material layers. The first material of the insulating layers 32 can be deposited, for example, by chemical vapor deposition (CVD). If silicon oxide is used for the insulating layers 32, for example, tetraethyl orthosilicate (TEOS) can be employed as a precursor material for the CVD process. The second material of the sacrificial material layers 42 can be formed, for example, by CVD or atomic layer deposition (ALD).

[0057] The sacrificial material layers 42 can be suitably patterned so that portions of electrically conductive material subsequently formed by replacing the sacrificial material layers 42 can be used as electrically conductive electrodes, such as control gate electrodes of a subsequently formed unit three-dimensional NAND string memory device. The sacrificial material layers 42 can comprise portions having a strip shape extending substantially parallel to the major surface 7 of the substrate.

[0058] The thickness of the insulating layers 32 and the sacrificial material layers 42 can be in a range from 20 nm to 50 nm, although lesser and greater thicknesses can be used for each insulating layer 32 and each sacrificial material layer 42. The number of repetitions of pairs of insulating layers 32 and sacrificial material layers (e.g., control gate electrodes or sacrificial material layers) 42 can be in a range from 2 to 1,024, and typically in a range from 8 to 256, although greater numbers of repetitions can also be employed. The top and bottom gate electrodes in the stack can be used as select gate electrodes. In one embodiment, each sacrificial material layer 42 in the alternating stack (32, 42) can have a uniform thickness that is substantially constant within each respective sacrificial material layer 42.

[0059] Although the present disclosure is described with embodiments in which the spacer material layers are sacrificial material layers 42 that are subsequently replaced with electrically conductive layers, embodiments in which the sacrificial material layers are formed as electrically conductive layers are expressly contemplated herein. In such cases, the step of replacing the spacer material layers with electrically conductive layers can be omitted.

[0060] Optionally, an insulating cap layer 70 can be formed over the alternating stack (32, 42). The insulating cap layer 70 comprises a dielectric material that is different from the material of the sacrificial material layers 42. In one embodiment, the insulating cap layer 70 can comprise a dielectric material as described above that can be used for the insulating layers 32. The insulating cap layer 70 can have a greater thickness than each insulating layer 32. The insulating cap layer 70 can be deposited, for example, by chemical vapor deposition. In one embodiment, the insulating cap layer 70 can be a silicon oxide layer.

[0061] Reference Figure 3At a peripheral region of the alternating stack (32, 42), referred to herein as a terrace region, a stepped surface is formed. As used herein, a“stepped surface” refers to a set of surfaces that includes at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface is adjoined to a first vertical surface that extends upward from a first edge of the horizontal surface, and is adjoined to a second vertical surface that extends downward from a second edge of the horizontal surface. A stepped cavity is formed within the volume, portions of the alternating stack (32, 42) are removed from the volume by forming the stepped surface. A“stepped cavity” refers to a cavity having a stepped surface.

[0062] The terrace region is formed in a contact region 300 between a memory array region 100 and a peripheral device region 200, which contains at least one semiconductor device for peripheral circuitry. The stepped cavity can have various stepped surfaces, such that the horizontal cross-sectional shape of the stepped cavity varies stepwise as a function of vertical distance from a top surface of the substrate (9, 10). In one embodiment, the stepped cavity can be formed by repeatedly performing a set of processing steps. The set of processing steps can include, for example, a first type of etch process that vertically increases the cavity depth by one or more levels, and a second type of etch process that laterally expands a region to be vertically etched in a subsequent etch process of the first type. As used herein, a“level” including an alternating plurality of structures is defined as the relative position of a pair of a first material layer and a second material layer within the structure.

[0063] Each sacrificial material layer 42 within the alternating stack (32, 42) except for the topmost sacrificial material layer 42 extends laterally farther than any overlying sacrificial material layer 42 within the alternating stack (32, 42) in the terrace region. The terrace region includes stepped surfaces of the alternating stack (32, 42) that extend continuously from the bottommost layer within the alternating stack (32, 42) to the topmost layer within the alternating stack (32, 42).

[0064] Each vertical stair of the stepped surface can have one or more pairs of heights of insulating layers 32 and sacrificial material layers. In one embodiment, each vertical stair can have a single pair of heights of insulating layers 32 and sacrificial material layers 42. In another embodiment, multiple “columns” of stairs can be formed along the first horizontal direction hd1 such that each vertical stair has multiple pairs of heights of insulating layers 32 and sacrificial material layers 42, and the number of columns can be at least the number of the multiple pairs. Each column of stairs can be vertically offset from one another such that each of the sacrificial material layers 42 has a physically exposed top surface in a respective column of stairs. In an exemplary example, two columns of stairs are formed for each block of memory stack structures to be subsequently formed such that one column of stairs provides a physically exposed top surface for odd-numbered sacrificial material layers 42 (as counted from the bottom) and another column of stairs provides a physically exposed top surface for even-numbered sacrificial material layers (as counted from the bottom). Configurations with three columns, four columns, or more columns of stairs with respective sets of vertical offsets can also be employed in the physically exposed surfaces of the sacrificial material layers 42. Each sacrificial material layer 42 has a greater lateral extent than any overlying sacrificial material layer 42 in at least one direction such that each physically exposed surface of any sacrificial material layer 42 does not have an overhang. In one embodiment, the vertical stairs within each column of stairs can be arranged along a first horizontal direction hd1 and the columns of stairs can be arranged along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1. In one embodiment, the first horizontal direction hd1 can be perpendicular to the boundary between the memory array region 100 and the contact region 300.

[0065] A backward stepped dielectric material portion 65 (i.e., an insulative fill material portion) can be formed in the stepped cavity by depositing a dielectric material therein. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed from above the top surface of the insulative cap layer 70, e.g., by chemical mechanical planarization (CMP). The remaining portions of the deposited dielectric material that fill the stepped cavity constitute the backward stepped dielectric material portion 65. As used herein, a “backward stepped” element refers to an element that has a stepped surface and a horizontal cross-sectional area that monotonically increases as a function of vertical distance from a top surface of a substrate on which the element is present. If silicon oxide is used for the backward stepped dielectric material portion 65, the silicon oxide of the backward stepped dielectric material portion 65 can or can not be doped with a dopant, such as B, P, and / or F.

[0066] Optionally, drain-select-level isolation structures 72 can be formed through the insulative cap layer 70 and a subset of the sacrificial material layers 42 at the drain-select level. The drain-select-level isolation structures 72 can be formed, for example, by forming drain-select-level isolation trenches and filling the drain-select-level isolation trenches with a dielectric material such as silicon oxide. Excess portions of the dielectric material can be removed from above the top surface of the insulative cap layer 70.

[0067] Referring to Figure 4A and Figure 4B A photoresist material stack (not shown), including at least a photoresist layer, can be formed over the insulative cap layer 70 and the back-kicked dielectric material portion 65 and can be photopatterned to form openings therein. The openings include a first set of openings formed over the memory array region 100 and a second set of openings formed over the contact region 300. The pattern in the photoresist material stack can be transferred through the insulative cap layer 70 or the back-kicked dielectric material portion 65 and through the alternating stack (32, 42) by at least one anisotropic etch that employs the patterned photoresist material stack as an etch mask. Portions of the alternating stack (32, 42) under the openings in the patterned photoresist material stack are etched to form memory openings 49 and support openings 19. As used herein, a “memory opening” refers to a structure in which a memory element such as a memory stack structure is subsequently formed therein. As used herein, a “support opening” refers to a structure in which a support structure (such as a support pillar structure) that mechanically supports other elements is subsequently formed. The memory openings 49 are formed through the entirety of the insulative cap layer 70 and the alternating stack (32, 42) in the memory array region 100. The support openings 19 are formed through the back-kicked dielectric material portion 65 and portions of the alternating stack (32, 42) that are below the stepped surface in the contact region 300.

[0068] The memory openings 49 extend through the entirety of the alternating stack (32, 42). The support openings 19 extend through a subset of layers within the alternating stack (32, 42). The chemical attributes of the anisotropic etch processes used to etch through the materials of the alternating stack (32, 42) can alternate to optimize etching of the first material and the second material in the alternating stack (32, 42). The anisotropic etching can be, for example, a series of reactive ion etches. The sidewalls of the memory openings 49 and the support openings 19 can be substantially vertical or can be tapered. The patterned photoresist material stack can be subsequently removed, for example, by ashing.

[0069] The memory openings 49 and the support openings 19 can extend from a top surface of the alternating stack (32, 42) at least to a horizontal plane that includes a topmost surface of the semiconductor material layer 10. In one embodiment, an over-etch of the semiconductor material layer 10 can be optionally performed after the top surface of the semiconductor material layer 10 is physically exposed at the bottom of each memory opening 49 and each support opening 19. The over-etch can be performed before or after the removal of the photoresist material stack. In other words, a recessed surface of the semiconductor material layer 10 can be vertically offset from an un-recessed top surface of the semiconductor material layer 10 by a recess depth. The recess depth can be in a range from, for example, 1 nm to 50 nm, although lesser and greater depths can also be employed. The over-etch is optional and can be omitted. If the over-etch is not performed, the bottom surfaces of the memory openings 49 and the support openings 19 can be coplanar with the topmost surface of the semiconductor material layer 10.

[0070] Each of the memory openings 49 and the support openings 19 can include a sidewall (or sidewalls) that extends substantially perpendicular to the topmost surface of the substrate. A two-dimensional array of memory openings 49 can be formed in the memory array region 100. A two-dimensional array of support openings 19 can be formed in the contact region 300. The substrate semiconductor layer 9 and the semiconductor material layer 10 collectively constitute a substrate (9, 10), which can be a semiconductor substrate. Alternatively, the semiconductor material layer 10 can be omitted, and the memory openings 49 and the support openings 19 can extend to a top surface of the substrate semiconductor layer 9.

[0071] Figures 5A-5H Structural variations in the memory openings 49 are shown that are one of the memory openings 49 in the example structures of Figure 4A and Figure 4B The same structural variations occur simultaneously in each other memory opening 49 and each support opening 19.

[0072] Referring to Figure 5A , memory openings 49 are shown in the example device structures of Figure 4A and Figure 4B The memory openings 49 extend through the insulating cap layer 70, the alternating stack (32, 42), and optionally into an upper portion of the semiconductor material layer 10. In this process step, each support opening 19 can extend through the backside stepped dielectric material portion 65, a subset of the layers in the alternating stack (32, 42), and optionally through an upper portion of the semiconductor material layer 10. A recess depth of a bottom surface of each memory opening relative to a top surface of the semiconductor material layer 10 can be in a range from 0 nm to 30 nm, although greater recess depths can also be employed. Optionally, the sacrificial material layer 42 can be laterally recessed, for example, by an isotropic etch to form lateral recesses (not shown).

[0073] Referring to Figure 5B An optional pedestal channel portion (e.g., epitaxial pedestal) 11 can be formed, for example, by selective epitaxy at a bottom portion of each memory opening 49 and each support opening 19. Each pedestal channel portion 11 includes single-crystal semiconductor material that is epitaxially aligned with the single-crystal semiconductor material of the semiconductor material layer 10. In one embodiment, the pedestal channel portion 11 can be doped with electrical dopants of the same conductivity type as the semiconductor material layer 10. In one embodiment, a top surface of each pedestal channel portion 11 can be formed above a horizontal plane that includes a top surface of the sacrificial material layer 42. In this case, at least one source select gate electrode can be subsequently formed by replacing each sacrificial material layer 42 that is located below a horizontal plane that includes a top surface of the pedestal channel portion 11 with a respective conductive material layer. The pedestal channel portion 11 can be a portion of a transistor channel that will subsequently extend between a source region that will be subsequently formed in the substrate (9, 10) and a drain region that will be subsequently formed in an upper portion of the memory opening 49. A memory cavity 49’ is present in an unfilled portion of the memory opening 49 above the pedestal channel portion 11. In one embodiment, the pedestal channel portion 11 can include single-crystal silicon. In one embodiment, the pedestal channel portion 11 can have a doping of a first conductivity type that is the same as a conductivity type of the semiconductor material layer 10 that contacts the pedestal channel portion. If the semiconductor material layer 10 is not present, the pedestal channel portion 11 can be formed directly on the substrate semiconductor layer 9, which can have a doping of the first conductivity type.

[0074] Referring to Figure 5C A layer stack including the blocking dielectric layer 52, the memory material layer 54, the tunneling dielectric layer 56, and the optional sacrificial cap material layer 601 can be sequentially deposited in the memory opening 49.

[0075] The blocking dielectric layer 52 can include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer can include a dielectric metal oxide layer that consists essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material that includes at least one metallic element and at least oxygen. The dielectric metal oxide can consist essentially of at least one metallic element and oxygen, or can consist essentially of at least one metallic element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer 52 can include a dielectric metal oxide having a dielectric constant that is greater than 7.9 (i.e., having a dielectric constant that is greater than that of silicon nitride).

[0076] Non-limiting examples of dielectric metal oxides include aluminum oxide (AI2O3), hafnium oxide (HfO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), silicates thereof, nitrogen-doped compounds thereof, alloys thereof, and stacks thereof. The dielectric metal oxide layer can be deposited, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), liquid-source misted chemical deposition, or combinations thereof. The thickness of the dielectric metal oxide layer can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed. Subsequently, the dielectric metal oxide layer can serve as a dielectric material portion that blocks stored charge from leaking to the control gate electrode. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide. In one embodiment, the blocking dielectric layer 52 can include multiple dielectric metal oxide layers having different material compositions.

[0077] Alternatively or additionally, the blocking dielectric layer 52 can include a dielectric semiconductor compound, such as silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof. In one embodiment, the blocking dielectric layer 52 can include silicon oxide. In this case, the dielectric semiconductor compound of the blocking dielectric layer 52 can be formed by a conformal deposition method, such as low pressure chemical vapor deposition, atomic layer deposition, or combinations thereof. The thickness of the dielectric semiconductor compound can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed. Alternatively, the blocking dielectric layer 52 can be omitted, and a backside blocking dielectric layer can be formed after forming a backside recess on a surface of a subsequently to be formed memory film.

[0078] Subsequently, a memory material layer 54 can be formed. In one embodiment, the memory material layer 54 can be a continuous layer or a patterned discrete portion of a charge trapping material including a dielectric charge trapping material (e.g., which can be silicon nitride). Alternatively, the memory material layer 54 can include a continuous layer or a patterned discrete portion of an electrically conductive material (such as doped polysilicon or a metallic material) that is patterned into a plurality of electrically isolated portions (e.g., floating gates) by being formed as the sacrificial material layer 42 within the lateral recesses. In one embodiment, the memory material layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer 42 and the insulating layer 32 can have vertically coinciding sidewalls, and the memory material layer 54 can be formed as a single continuous layer.

[0079] In another implementation, the sacrificial material layers 42 can be laterally recessed relative to the sidewalls of the insulating layers 32, and a combination of deposition and anisotropic etching processes can be employed to form the memory material layers 54 as a plurality of vertically spaced-apart memory material portions. While the disclosure is described with an implementation in which the memory material layers 54 are a single continuous layer, implementations in which the memory material layers 54 are replaced by a plurality of vertically spaced-apart memory material portions, which can be charge-trapping material portions or electrically isolated conductive material portions, are expressly contemplated herein.

[0080] In one implementation, each vertical memory element stack includes a stack of vertically charge storage material portions that hold a charge therein when programmed, or a stack of vertical ferroelectric memory elements that hold an electric polarization therein when programmed. In the case of using a stack of vertical ferroelectric memory elements, the memory material layers 54 can include a continuous ferroelectric material layer or a plurality of discrete vertically separated ferroelectric material portions. The ferroelectric material can include hafnium oxide in an orthorhombic phase doped with, for example, silicon, aluminum, or zirconium.

[0081] The memory material layers 54 can be formed as a single memory material layer of uniform composition, or can include a stack of multiple memory material layers. The multiple memory material layers, if employed, can include a plurality of spaced-apart floating gate material layers that include conductive material (e.g., a metal such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and alloys thereof, or a metal silicide such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or combinations thereof) and / or semiconductor material (e.g., a polycrystalline or amorphous semiconductor material including at least one elemental semiconductor element or at least one compound semiconductor material). Alternatively or additionally, the memory material layers 54 can include insulating charge-trapping material, such as one or more silicon nitride segments. Alternatively, the memory material layers 54 can include conductive nanoparticles, such as metal nanoparticles, which can be, for example, ruthenium nanoparticles. The memory material layers 54 can be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing charge therein. The thickness of the memory material layers 54 can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.

[0082] The tunneling dielectric layer 56 includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the mode of operation of the unit three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 can include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides such as aluminum oxide and hafnium oxide, dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 can include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which stack is commonly referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 can include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.

[0083] The optional sacrificial cap material layer 601 includes a sacrificial material that is selective to the material of the tunneling dielectric layer 56 and that can be subsequently removed. In one embodiment, the sacrificial cap material layer 601 can include a semiconductor material such as amorphous silicon. The sacrificial cap material layer 601 can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the sacrificial cap material layer 601 can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. A memory cavity 49' is formed in the volume of each memory opening 49 that is not filled with the deposited material layers (52, 54, 56, 601).

[0084] Referring to Figure 5D , the optional sacrificial cap material layer 601, the tunneling dielectric layer 56, the memory material layer 54, the blocking dielectric layer 52 are sequentially anisotropically etched by at least one anisotropic etch process. Portions of the sacrificial cap material layer 601, the tunneling dielectric layer 56, the memory material layer 54, and the blocking dielectric layer 52 that are located above the top surface of the insulating cap layer 70 can be removed by the at least one anisotropic etch process. In addition, horizontal portions of the sacrificial cap material layer 601, the tunneling dielectric layer 56, the memory material layer 54, and the blocking dielectric layer 52 at the bottom of each memory cavity 49' can be removed to form an opening in the remaining portions thereof. Each of the sacrificial cap material layer 601, the tunneling dielectric layer 56, the memory material layer 54, and the blocking dielectric layer 52 can be etched by a respective anisotropic etch process that employs a respective etch chemistry that can be the same or different for the various material layers.

[0085] Each remaining portion of the sacrificial capping material layer 601 can have a tubular configuration. The memory material layers 54 can comprise charge trapping material, ferroelectric material, or floating gate material. In one embodiment, each memory material layer 54 can comprise a vertical stack of charge storage regions that store charge when programmed. In one embodiment, the memory material layers 54 can be memory material layers in which each portion adjacent to the sacrificial material layers 42 constitutes a charge storage region.

[0086] The surface of the base channel portion 11 (or the surface of the semiconductor material layer 10 in the case where the base channel portion 11 is not employed) can be physically exposed under the openings through the sacrificial capping material layer 601, the tunneling dielectric layer 56, the memory material layer 54, and the blocking dielectric layer 52. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity 49’ can be vertically recessed such that the recessed semiconductor surface under the memory cavity 49’ is vertically offset from the topmost surface of the base channel portion 11 (or the semiconductor material layer 10 in the case where the base channel portion 11 is not employed) by a recessed distance. The tunneling dielectric layer 56 is over the memory material layer 54. The set of blocking dielectric layers 52, memory material layers 54, and tunneling dielectric layers 56 in the memory openings 49 constitute a memory film 50 that includes a plurality of charge storage regions (as embodied by the memory material layers 54) that are insulated from surrounding material by the blocking dielectric layers 52 and the tunneling dielectric layers 56. In one embodiment, the sacrificial capping material layer 601, the tunneling dielectric layer 56, the memory material layer 54, and the blocking dielectric layer 52 can have vertically coincident sidewalls. The sacrificial capping material layer 601, which is selective to the material of the tunneling dielectric layer 56, can be subsequently removed. In the case where the sacrificial capping material layer 601 comprises a semiconductor material, a wet etch process employing hot trimethyl-2-hydroxyethylammonium hydroxide (“hot TMY”) or tetramethylammonium hydroxide (TMAH) can be performed to remove the sacrificial capping material layer 601. Alternatively, the sacrificial capping material layer 601 can be left in the final device.

[0087] Reference Figure 5Esemiconductor material layer 10 (if the base channel portion 11 is omitted), and directly on the tunneling dielectric layer 56. The semiconductor channel layer 60L includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II- VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel layer 60L includes amorphous silicon or polysilicon. The semiconductor channel layer 60L can have a dopant of a first conductivity type, which is the same as the conductivity type of the semiconductor material layer 10 and the base channel portion 11. The semiconductor channel layer 60L can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel layer 60L can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. The semiconductor channel layer 60L can partially fill the memory cavity 49’ in each memory opening, or can completely fill the cavity in each memory opening.

[0088] Referring to Figure 5F In the case where the memory cavity 49’ in each memory opening is not completely filled by the semiconductor channel layer 60L, a dielectric core layer 62L can be deposited in the memory cavity 49’ to fill any remaining portion of the memory cavity 49’ within each memory opening. The dielectric core layer 62L includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer 62L can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD) or by a self-planarizing deposition process such as spin-on.

[0089] Referring to Figure 5G The horizontal portions of the dielectric core layer 62L can be removed, e.g., by a recess etch process, such that each remaining portion of the dielectric core layer 62L is within a respective memory opening 49 and has a respective top surface that is below a horizontal plane that includes a top surface of the insulating cap layer 70. Each remaining portion of the dielectric core layer 62L constitutes a dielectric core 62.

[0090] Referring to Figure 5H A doped semiconductor material having a dopant of a second conductivity type can be deposited within each recessed region above the dielectric core 62. The deposited semiconductor material can have a dopant of a second conductivity type that is opposite to the first conductivity type. For example, if the first conductivity type is p-type, then the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material can be in a range from 5.0 x 1019 / cm3to 2.0 x 1020 / cm3, although lesser and greater dopant concentrations can also be employed. 18 / cm 3 / cm 21 / cm 3within the range of 1 x 1016atoms / cm3to 1 x 1021atoms / cm3, but smaller and larger dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon.

[0091] Excess portions of the deposited semiconductor material of the horizontal portions of the doped semiconductor material of the second conductivity type and the semiconductor channel layer 60L can be removed (e.g., by a chemical mechanical planarization (CMP) or a recess etch process) from above the horizontal plane including the top surface of the insulating cap layer 70. Each remaining portion of the doped semiconductor material of the second conductivity type constitutes a drain region 63. Each remaining portion of the semiconductor channel layer 60L of the first conductivity type constitutes a vertical semiconductor channel 60.

[0092] The tunneling dielectric layer 56 is surrounded by the memory material layer 54 and laterally surrounds a portion of the vertical semiconductor channel 60. Each set of contiguous blocking dielectric layer 52, memory material layer 54, and tunneling dielectric layer 56 collectively constitutes a memory film 50, which can store an electrical charge or a ferroelectric polarization with a macroscopic retention time. In some embodiments, no blocking dielectric layer 52 can be present in the memory film 50 at this step, and the blocking dielectric layer can be formed subsequently after the formation of the backside recess. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device, such as a retention time exceeding 24 hours.

[0093] Each combination of the memory film 50 and the vertical semiconductor channel 60 within the memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of a semiconductor channel, a tunneling dielectric layer, a plurality of memory elements embodied as portions of the memory material layer 54, and optionally a blocking dielectric layer 52. Each combination of the base channel portion 11 (if present), the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 is referred to herein as a memory opening fill structure 58. Each combination of the base channel portion 11 (if present), the memory film 50, the vertical semiconductor channel 60, the dielectric core 62, and the drain region 63 within each support opening 19 fills the respective support opening 19 and constitutes a support pillar structure.

[0094] Referring to Figure 6 , an example structure is shown after formation of the memory opening fill structures 58 and the support pillar structures 20 within the memory openings 49 and the support openings 19, respectively. The instances of the memory opening fill structures 58 can be formed within each memory opening 49 of the structure of Figure 4A and Figure 4B . The instances of the support pillar structures 20 can be formed within each support opening 19 of the structure of Figure 4A and Figure 4B .

[0095] Each memory stack structure 55 includes a vertical semiconductor channel 60 and a memory film 50. The memory film 50 can include a tunneling dielectric layer 56 laterally surrounding the vertical semiconductor channel 60 and a vertical stack of a charge storage or ferroelectric region (e.g., including a portion of a memory material layer 54) laterally surrounding the tunneling dielectric layer 56 and optionally a blocking dielectric layer 52. While the present disclosure is described using the illustrated configuration for the memory stack structure, the methods of the present disclosure can be applied to alternative memory stack structures including different layer stacks or structures for the memory film 50 and / or for the vertical semiconductor channel 60.

[0096] Referring to Figure 7A and Figure 7B A contact-level dielectric layer 73 can be formed over the alternating stack (32, 42) of insulating layers 32 and sacrificial material layers 42 and over the memory stack structures 55 and support pillar structures 20. The contact-level dielectric layer 73 includes a dielectric material that is different from the dielectric material of the sacrificial material layers 42. For example, the contact-level dielectric layer 73 can include silicon oxide. The contact-level dielectric layer 73 can have a thickness in a range from 50 nm to 500 nm, although lesser and greater thicknesses can also be employed.

[0097] A photoresist layer (not shown) can be applied over the contact-level dielectric layer 73 and lithographically patterned to form openings in regions between clusters of the memory stack structures 55. The pattern in the photoresist layer can be transferred through the contact-level dielectric layer 73, the alternating stack (32, 42), and / or the backside stepped dielectric material portions 65 using anisotropic etching to form backside trenches 79 that extend vertically from a top surface of the contact-level dielectric layer 73 to a top surface of the substrate (9, 10) and laterally through the memory array region 100 and the contact region 300.

[0098] In one embodiment, the backside trenches 79 can laterally extend along a first horizontal direction hd1 and can be laterally spaced apart from one another along a second horizontal direction (e.g., a bit line direction) hd2 that is perpendicular to the first horizontal direction hd1. The memory stack structures 55 can be arranged in rows that extend along the first horizontal direction (e.g., a word line direction) hd1. The drain-select-level isolation structures 72 can laterally extend along the first horizontal direction hd1. Each backside trench 79 can have a uniform width that is invariant along the longitudinal direction (i.e., along the first horizontal direction hd1). Each drain-select-level isolation structure 72 can have a uniform vertical cross-sectional profile along a vertical plane that is perpendicular to the first horizontal direction hd1 that does not vary with translation along the first horizontal direction hd1. Multiple rows of memory stack structures 55 can be located between an adjacent pair of backside trenches 79 and drain-select-level isolation structures 72 or between an adjacent pair of drain-select-level isolation structures 72.

[0099] In one embodiment, the backside trenches 79 can include source contact openings in which source contact via structures can be subsequently formed. The photoresist layer can be removed, e.g., by ashing. Generally, the backside trenches 79 extending laterally along the first horizontal direction hd1 can be formed through the contact-level dielectric layer 73 and the alternating stack (32, 42). As formed at processing step of FIG. 2A, the alternating stack (32, 42) is divided by the backside trenches 79 into a plurality of alternating stacks (32, 42) laterally spaced apart along the second horizontal direction hd2. Figure 3 The layer stacks (32, 42, 70, 73) are formed, each of the layer stacks including a respective patterned portion of the contact-level dielectric layer 73 and a respective patterned portion of the alternating stack (32, 42), as formed at processing step of FIG. 2B and laterally spaced apart from one another by the backside trenches 79. Figure 3 The layer stacks (32, 42, 70, 73) are formed, each of the layer stacks including a respective patterned portion of the contact-level dielectric layer 73 and a respective patterned portion of the alternating stack (32, 42), as formed at processing step of FIG. 2B and laterally spaced apart from one another by the backside trenches 79.

[0100] Dopants of the second conductivity type can be implanted into the physically exposed surface portions of the substrate (9, 10) at the bottoms of the backside trenches (which can be surface portions of the semiconductor material layer 10) by an ion implantation process. The source regions 61 can be formed at the surface portions of the semiconductor material layer 10 under each of the backside trenches 79. Each of the source regions 61 is formed in a surface portion of the substrate (9, 10) under a respective backside trench 79. Due to the straggling of the implanted dopant atoms during the implantation process and the lateral diffusion of the implanted dopant atoms during a subsequent activation anneal process, each of the source regions 61 can have a lateral extent that is greater than the lateral extent of the overlying backside trench 79.

[0101] The upper portions of the semiconductor material layer 10 extending between the source regions 61 and the plurality of pedestal channel portions 11 constitute horizontal semiconductor channels 59 for a plurality of field effect transistors. The horizontal semiconductor channels 59 are connected to the plurality of vertical semiconductor channels 60 by the respective pedestal channel portions 11. Each of the horizontal semiconductor channels 59 contacts the source region 61 and the plurality of pedestal channel portions 11.

[0102] Referring to Figure 8 The sacrificial fill material layer 161L can be formed in the backside trenches 79 and over the layer stacks (32, 42, 70, 73) by conformal deposition of a sacrificial fill material. In one embodiment, the sacrificial fill material includes a semiconductor material, a carbon-containing material, or a polymeric material. For example, the sacrificial fill material can include amorphous silicon, polysilicon, a silicon-germanium alloy, amorphous carbon, diamond-like carbon (DLC), or a silicon-based polymeric material.

[0103] Referring to Figure 9A and Figure 9BA planarization process can be performed to remove horizontal portions of the sacrificial fill material layer 1611 overlying a horizontal plane of top surfaces of the contact-level dielectric layers 73. The planarization process can employ a recess etch process and / or a chemical mechanical polishing (CMP) process. Each remaining portion of the sacrificial fill material layer 161L filling a respective backside trench 79 constitutes a sacrificial backside trench fill structure 161.

[0104] Referring to Figure 10A and Figure 10B An optional hardmask layer 162 can be deposited over the contact-level dielectric layers 73 and the sacrificial backside trench fill structures 161. The hardmask layer 162 includes a dielectric material that is different from the dielectric material of the contact-level dielectric layers 73. For example, the contact-level dielectric layers 73 can include silicon oxide, and the hardmask layer 162 can include silicon nitride. The thickness of the hardmask layer 162 can be in a range from 10 nm to 200 nm, although lesser and greater thicknesses can also be employed.

[0105] A photoresist layer 167 can be applied over the hardmask layer 162 and can be lithographically patterned to form a pattern of discrete openings through the photoresist layer 167. The pattern of openings in the photoresist layer 167 can include multiple rows of discrete openings overlying respective ones of the sacrificial backside trench fill structures 161. In particular, a row of discrete rectangular-shaped openings extending (e.g., elongated) along a second horizontal direction hd2 and spaced apart along a first horizontal direction hd1 can be formed over each of the sacrificial backside trench fill structures 161 through the photoresist layer 167. In one embodiment, each row of discrete openings can include a periodic one-dimensional array of rectangular openings. The width of each opening along the first horizontal direction hd1 can be in a range from 100 nm to 2,000 nm, and the pitch of the openings along the first horizontal direction hd1 can be in a range from 200 nm to 10,000 nm, although lesser and greater dimensions can also be employed.

[0106] Referring to Figure 11A and Figure 11BAn anisotropic etch process can be performed to transfer a pattern of openings in the photoresist layer 167 through the hardmask layer 162 to an upper portion of the sacrificial backside trench fill structures 161. The anisotropic etch process can include a first anisotropic etch step that etches a material of the hardmask layer 162 selective to a material of the contact level dielectric layer 73 and a second anisotropic etch step that etches a material of the sacrificial backside trench fill structures 161 selective to a material of the contact level dielectric layer 73. A duration of the second anisotropic etch step can be selected such that a recessed surface of the sacrificial backside trench fill structures 161 is formed above a horizontal plane that includes a top surface of the topmost sacrificial material layer 42 within each layer stack (32, 42, 70, 73). A row of recessed cavities 169 is formed within each backside trench 79 and is located above a respective one of the sacrificial backside trench fill structures 161. The recessed cavities 169 can be laterally spaced apart within each of the sacrificial backside trench fill structures 161 along a first horizontal direction hd1.

[0107] Referring to Figure 12 The photoresist layer 167 can be removed, e.g., by ashing. A dielectric fill material layer 164L can be deposited within the recessed cavities 169 and deposited above the hardmask layer 162. The dielectric fill material layer 164L can include a dielectric material, such as silicon oxide.

[0108] Referring to Figure 13A And Figure 13B The dielectric fill material layer 164L can be planarized to remove portions of the dielectric fill material layer 164L above a horizontal plane that includes a top surface of the hardmask layer 162. For example, a chemical mechanical polishing (CMP) process or a recess etch process can be employed. The dielectric fill material layer 164L can then be recessed, e.g., by performing an isotropic recess etch process, such as a wet etch process, to remove portions of the dielectric fill material layer that overlie a horizontal plane that includes a top surface of the contact level dielectric layer 73. The hardmask layer 162, which is selective to a material of the contact level dielectric layer 73 and a remaining portion of the dielectric fill material layer 164L, can then be removed. For example, if the hardmask layer 162 includes silicon nitride and if the contact level dielectric layer 73 and the dielectric fill material layer 164L include silicon oxide, a wet etch process employing hot phosphoric acid can be employed to remove the hardmask layer 162. Each remaining portion of the dielectric fill material layer 164L constitutes a backside trench bridge structure 164 that fills a volume of a respective one of the recessed cavities 169.

[0109] A row of backside trench bridge structures 164 can be formed within each backside trench 79. Within each of the backside trenches 79, the backside trench bridge structures 164 within a row of backside trench bridge structures 164 are laterally spaced apart from one another along a first horizontal direction hd1. In one embodiment, a bottom surface of the backside trench bridge structures 164 is farther from the substrate (9, 10) than a farthest patterned portion of the patterned portions of the sacrificial material layer 42 is from the substrate (9, 10). In one embodiment, a top surface of the backside trench bridge structures 164 can be coplanar or can be substantially coplanar with a top surface of the contact-level dielectric layer 73.

[0110] The backside trench bridge structures 164 in different trenches 79 are shown aligned along a second horizontal direction hd2 in Figure 13B However, in an alternative embodiment shown in Figure 13C The backside trench bridge structures 164 in different trenches 79 are shown aligned along a second horizontal direction hd2 in

[0111] Referring to Figure 14A and 14B The sacrificial backside trench fill structures 161 can be removed selectively to the materials of the backside trench bridge structures 164 and the layer stack (32, 42, 70, 73) by an isotropic etch process. The isotropic etch process etches the material of the sacrificial backside trench fill structures 161 selective to the dielectric materials of the backside trench bridge structures 164 and the layer stack (32, 42, 70, 73). For example, if the sacrificial backside trench fill structures 161 comprise a semiconductor material, such as amorphous silicon, the isotropic etch process can comprise a wet etch process employing hot trimethyl-2-hydroxyethylammonium hydroxide (“hot TMY”) or tetramethylammonium hydroxide (TMAH). In one embodiment, the sacrificial backside trench fill structures 161 can comprise an undoped semiconductor material or a lightly-doped semiconductor material, and the wet etch process employing hot TMY or TMAH can etch the undoped or lightly-doped semiconductor material of the sacrificial backside trench fill structures 161 selective to the heavily-doped semiconductor material of the source regions 61.

[0112] Alternatively or additionally, the sacrificial backside trench fill structures 161 can comprise a silicon-germanium alloy to provide a higher etch rate relative to the semiconductor material of the source regions 61. Optionally, a thin surface oxide layer (not shown) can be formed over each source region 61 prior to deposition of the sacrificial fill material layer 161L to facilitate selective removal of the sacrificial backside trench fill structures 161.

[0113] A backside cavity 79’ is formed in each volume from which the sacrificial backside trench fill structure 161 is removed. Each row of backside trench bridge structures 164 located within the upper portion of the backside trench 79 provides a configuration of parallel bridges connecting upper regions of adjacent pairs of layer stacks (32, 42, 70, 73) laterally spaced apart along the second horizontal direction hd2. The backside trench bridge structures 164 provide structural support to the layer stacks (32, 42, 70, 73) during subsequent processing steps in which backside recesses are formed therein, and the sacrificial material layers 42 within the layer stacks (32, 42, 70, 73) are replaced with conductive layers. The bridge structures reduce tilting and collapse of the layer stacks.

[0114] Referring to Figure 15 and Figure 16A An etchant can be introduced into the backside cavities 79’ for example employing an etching process that selectively etches the second material of the sacrificial material layers 42 relative to the first material of the insulating layers 32. Backside recesses 43 are formed in the volumes from which the sacrificial material layers 42 are removed. The removal of the second material of the sacrificial material layers 42 can be selective to the first material of the insulating layers 32, the material of the backside stepped dielectric material portions 65, the semiconductor material of the semiconductor material layers 10, and the outermost material of the memory films 50. In one embodiment, the sacrificial material layers 42 can comprise silicon nitride, and the material of the insulating layers 32 and the backside stepped dielectric material portions 65 can be selected from silicon oxide and a dielectric metal oxide. The backside trench bridge structures 164 do not block access to the backside recesses 43 from the backside trench 79 because the bottom surfaces of the backside trench bridge structures 164 are farther from the substrate (9, 10) than the farthest backside recesses in the backside recesses 43.

[0115] The etching process that removes the second material selective to the first material and the outermost layer of the memory films 50 can be a wet etching process using a wet etching solution, or can be a vapor phase (dry) etching process in which an etchant is introduced into the backside trench 79 in the vapor phase. For example, if the sacrificial material layers 42 comprise silicon nitride, the etching process can be a wet etching process in which the exemplary structure is immersed into a wet etching bath comprising phosphoric acid that etches silicon nitride selective to silicon oxide, silicon, and various other materials employed in the art. The support pillar structures 20, the backside stepped dielectric material portions 65, and the memory stack structures 55 provide structural support when the backside recesses 43 are present within the volumes previously occupied by the sacrificial material layers 42.

[0116] Each backside recess 43 can be a laterally extending cavity having a lateral dimension that is greater than a vertical extent of the cavity. In other words, a lateral dimension of each backside recess 43 can be greater than a height of the backside recess 43. The plurality of backside recesses 43 can be formed in a volume of the second material of the sacrificial material layer 42 removed therefrom. The memory openings in which the memory stack structures 55 are formed are referred to herein as frontside openings or frontside cavities, in contrast to the backside recesses 43. In one embodiment, the memory array region 100 includes an array of monolithic three-dimensional NAND strings having a plurality of device levels disposed above the substrate (9, 10). In this case, each backside recess 43 can define a space for receiving a respective word line of the array of monolithic three-dimensional NAND strings.

[0117] Each of the plurality of backside recesses 43 can extend substantially parallel to a top surface of the substrate (9, 10). The backside recesses 43 can be vertically defined by a top surface of the underlying insulating layer 32 and a bottom surface of the overlying insulating layer 32. In one embodiment, each backside recess 43 can have a uniform height throughout. Generally, the backside recesses 43 can be formed by removing a patterned portion of the sacrificial material layer 42 (which is a patterned portion of the sacrificial material layer formed at a processing step such as Figure 3 Figure 3 the processing step of FIG. 1C) that is selective to the insulating layer 32 (which is an insulating layer formed at a processing step such as

[0118] ​The optional base channel portions 11 and physically exposed surface portions of the semiconductor material layer 10 can be converted to dielectric material portions by thermally converting and / or plasma converting the semiconductor material. For example, a surface portion of each base channel portion 11 can be converted to a tubular dielectric spacer 116 and each physically exposed surface portion of the semiconductor material layer 10 can be converted to a planar dielectric portion 616 using thermal conversion and / or plasma conversion. In one embodiment, each tubular dielectric spacer 116 can be topologically homeomorphic to a torus, i.e., generally ring-shaped. As used herein, an element is topologically homeomorphic to a torus if the shape of the element can be continuously stretched without breaking a hole or forming a new hole into the shape of a torus. The tubular dielectric spacer 116 comprises a dielectric material that includes the same semiconductor elements as the base channel portion 11 and additionally includes at least one non-metallic element such as oxygen and / or nitrogen such that the material of the tubular dielectric spacer 116 is a dielectric material. In one embodiment, the tubular dielectric spacer 116 can comprise a dielectric oxide, a dielectric nitride, or a dielectric oxynitride of the semiconductor material of the base channel portion 11. Likewise, each planar dielectric portion 616 comprises a dielectric material that includes the same semiconductor elements as the semiconductor material layer and additionally includes at least one non-metallic element such as oxygen and / or nitrogen such that the material of the planar dielectric portion 616 is a dielectric material. In one embodiment, the planar dielectric portion 616 can comprise a dielectric oxide, a dielectric nitride, or a dielectric oxynitride of the semiconductor material of the semiconductor material layer 10.

[0119] Referring to Figure 16B A backside blocking dielectric layer 44 can optionally be formed. The backside blocking dielectric layer 44, if present, comprises a dielectric material that functions as a control gate dielectric for a control gate to be subsequently formed in the backside recess 43. The backside blocking dielectric layer 44 is optional in the presence of the blocking dielectric layer 52 within each memory opening. The backside blocking dielectric layer 44 is present in the case where the blocking dielectric layer 52 is omitted.

[0120] The backside blocking dielectric layer 44 can be formed in the backside recess 43 and on the sidewalls of the backside trench 79. The backside blocking dielectric layer 44 can be formed directly on the horizontal surfaces of the insulating layer 32 and the sidewalls of the memory stack structure 55 within the backside recess 43. The formation of the tubular dielectric spacer 116 and the planar dielectric portion 616 is optional prior to the formation of the backside blocking dielectric layer 44, if the backside blocking dielectric layer 44 is formed. In one embodiment, the backside blocking dielectric layer 44 can be formed by a conformal deposition process such as atomic layer deposition (ALD). The backside blocking dielectric layer 44 can consist essentially of aluminum oxide. The thickness of the backside blocking dielectric layer 44 can be in a range from 1 nm to 15 nm, such as from 2 nm to 6 nm, although lesser and greater thicknesses can also be employed.

[0121] The dielectric material of the backside blocking dielectric layer 44 can be a dielectric metal oxide such as aluminum oxide, a dielectric oxide of at least one transition metal element, a dielectric oxide of at least one lanthanide element, a dielectric oxide of a combination of aluminum, at least one transition metal element, and / or at least one lanthanide element. Alternatively or additionally, the backside blocking dielectric layer 44 can include a silicon oxide layer. The backside blocking dielectric layer 44 can be deposited by a conformal deposition method such as chemical vapor deposition or atomic layer deposition. The backside blocking dielectric layer 44 is formed on the sidewalls of the backside trenches 79, the horizontal surfaces and sidewalls of the insulating layers 32, the portions of the sidewall surfaces of the memory stack structures 55 that are physically exposed to the backside recesses 43, and the top surfaces of the planar dielectric portions 616. A backside cavity 79’ is present within the portion of each backside trench 79 that is not filled with the backside blocking dielectric layer 44.

[0122] Reference is made to Figure 16C A conductive material can be deposited in the backside recesses 43 by providing at least one reactant gas into the backside recesses 43 through the backside trenches 79. A metal blocking layer 46A can be deposited in the backside recesses 43. The metal blocking layer 46A includes a conductive metal material that can function as a diffusion barrier layer and / or adhesion promotion layer for a subsequently deposited metal fill material. The metal blocking layer 46A can include a conductive metal nitride material such as TiN, TaN, WN, or a stack thereof, or can include a conductive metal carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metal blocking layer 46A can be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal blocking layer 46A can be in a range from 2 nm to 8 nm, such as from 3 nm to 6 nm, although lesser and greater thicknesses can also be employed. In one embodiment, the metal blocking layer 46A can consist essentially of a conductive metal nitride such as TiN.

[0123] Reference is made to Figure 16D and Figure 17The metal fill material is deposited in the plurality of backside recesses 43, on sidewalls of the at least one backside trench 79, and over the top surface of the contact level dielectric layer 73 to form a metal fill material layer 46B. The metal fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metal fill material layer 46B can be substantially composed of at least one elemental metal. The at least one elemental metal of the metal fill material layer 46B can be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metal fill material layer 46B can be substantially composed of a single elemental metal. In one embodiment, the metal fill material layer 46B can be deposited with a fluorine-containing precursor gas such as WF6. In one embodiment, the metal fill material layer 46B can be a tungsten layer that includes residual level fluorine atoms as impurities. The metal fill material layer 46B is spaced apart from the insulating layers 32 and the memory stack structures 55 by a metal barrier layer 46A, which is a metal barrier layer that blocks diffusion of fluorine atoms therethrough.

[0124] The plurality of conductive layers 46 can be formed in the plurality of backside recesses 43, and a continuous metal material layer 46L can be formed on sidewalls of each backside trench 79 and over the contact level dielectric layer 73. Each conductive layer 46 includes a portion of the metal barrier layer 46A and a portion of the metal fill material layer 46B located between a pair of vertically adjacent dielectric material layers such as a pair of insulating layers 32. The continuous metal material layer 46L includes a continuous portion of the metal barrier layer 46A and a continuous portion of the metal fill material layer 46B located in the backside trench 79 or over the contact level dielectric layer 73.

[0125] Each sacrificial material layer 42 can be replaced by a conductive layer 46. A backside cavity 79’ is present in a portion of each backside trench 79 that is not filled with the backside barrier dielectric layer 44 and the continuous metal material layer 46L. The tubular dielectric spacer 116 laterally surrounds the base channel portion 11. The bottommost conductive layer 46 laterally surrounds each tubular dielectric spacer 116 when the conductive layer 46 is formed.

[0126] Referring to Figure 18A and Figure 18B The deposited metal material of the continuous conductive material layer 46L is etched back from the sidewalls of each backside trench 79 and from over the contact level dielectric layer 73 by performing an isotropic etch process that etches at least one conductive material of the continuous conductive material layer 46L. Each remaining portion of the deposited metal material in the backside recess 43 constitutes a conductive layer 46. Each conductive layer 46 can be a conductive line structure. Thus, the sacrificial material layer 42 is replaced by the conductive layer 46.

[0127] Each conductive layer 46 can function as a combination of a plurality of control gate electrodes located at a same level and word lines electrically interconnected (i.e., electrically shorted) to the plurality of control gate electrodes located at the same level. The plurality of control gate electrodes within each conductive layer 46 are control gate electrodes for vertical memory devices including memory stack structures 55. In other words, each conductive layer 46 can be a word line functioning as a common control gate electrode for a plurality of vertical memory devices.

[0128] In one embodiment, the removal of the continuous conductive material layer 46L can be selective to the material of the backside blocking dielectric layer 44. In this case, a horizontal portion of the backside blocking dielectric layer 44 can be present at the bottom of each backside trench 79. In another embodiment, the removal of the continuous conductive material layer 46L can be non-selective to the material of the backside blocking dielectric layer 44, or the backside blocking dielectric layer 44 can not be employed. The planar dielectric portion 616 can be removed during the removal of the continuous conductive material layer 46L. A backside cavity 79’ is present within each backside trench 79. Each backside cavity 79’ extends continuously along the first horizontal direction hd1 under the respective row of backside trench bridge structures 164.

[0129] Referring to Figures 19A-19C A layer of insulating material can be formed in the backside trenches 79 and over the contact level dielectric layer 73 by a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The layer of insulating material includes an insulating material such as silicon oxide, silicon nitride, a dielectric metal oxide, an organosilicate glass, or a combination thereof. In one embodiment, the layer of insulating material can include silicon oxide. The layer of insulating material can be formed, for example, by low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The thickness of the layer of insulating material can be in a range from 1.5 nm to 60 nm, although lesser and greater thicknesses can also be employed.

[0130] If the backside blocking dielectric layer 44 is present, the layer of insulating material can be formed directly on a surface of the backside blocking dielectric layer 44 and directly on the sidewalls of the conductive layer 46. If the backside blocking dielectric layer 44 is not employed, the layer of insulating material can be formed directly on the sidewalls of the insulating layer 32 and directly on the sidewalls of the conductive layer 46.

[0131] An anisotropic etch is performed to remove horizontal portions of the layer of insulating material from over the contact level dielectric layer 73 and the bottom of each backside trench 79. Each remaining portion of the layer of insulating material constitutes an insulating spacer 74. A backside cavity 79’ is present within a volume surrounded by each insulating spacer 74. Each of the insulating spacers 74 contacts a bottom surface and sidewalls of the respective row of backside trench bridge structures 164 located in the same backside trench 79.

[0132] A top surface of the source region 61 can be physically exposed at a bottom of each backside trench 79. A bottommost conductive layer 46 provided when forming the conductive layers 46 within the alternating stack (32, 46) can comprise a select gate electrode of a field effect transistor. Each source region 61 is formed in an upper portion of the substrate (9, 10). A semiconductor channel (59, 11, 60) extends between each source region 61 and a respective set of drain regions 63. The semiconductor channel (59, 11, 60) comprises a vertical semiconductor channel 60 of the memory stack structure 55.

[0133] Referring to Figures 20A-20C A backside contact via structure 76 can be formed within each backside cavity 79'. Each contact via structure 76 can fill a respective cavity 79'. The contact via structure 76 can be formed by depositing at least one conductive material in the remaining unfilled volume of the backside trench 79, i.e., the backside cavity 79'. For example, the at least one conductive material can comprise a conductive liner 76A and a conductive fill material portion 76B. The conductive liner 76A can comprise a conductive metal liner, such as TiN, TaN, WN, TiC, TaC, WC, alloys thereof, or stacks thereof. The thickness of the conductive liner 76A can be in a range from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed. The conductive fill material portion 76B can comprise a metal or a metal alloy. For example, the conductive fill material portion 76B can comprise W, Cu, Al, Co, Ru, Ni, alloys thereof, or stacks thereof.

[0134] The contact level dielectric layer 73 overlying the alternating stack (32, 46) can be used as a stop layer to planarize the at least one conductive material. If a chemical mechanical planarization (CMP) process is employed, the contact level dielectric layer 73 can be used as a CMP stop layer. Each remaining continuous portion of the at least one conductive material in the backside trench 79 constitutes a backside contact via structure 76. Each backside contact via structure 76 extends through the alternating stack (32, 46) and contacts a top surface of a respective source region 61. If a backside blocking dielectric layer 44 is employed, each backside contact via structure 76 can contact a sidewall of the backside blocking dielectric layer 44.

[0135] Generally, the backside contact via structures 76 can be formed within each of the backside trenches 79 after forming the insulating spacers 74 by depositing and planarizing at least one electrically conductive material in the volume of the backside trenches 79 that is not filled with the insulating spacers 74. In one embodiment, each of the backside contact via structures 76 includes a foot that protrudes upward from a horizontal plane that includes a bottom surface of the backside trench bridge structure 164 between adjacent backside trench bridge structures 164 in the same backside trench 79. In one embodiment, the foot of each backside trench via structure 76 can have a top surface that lies within a horizontal plane that includes a top surface of the backside trench bridge structure 164. Thus, the backside trench via structures 76 do not lie above or on the top surface of the backside trench bridge structure 164.

[0136] Alternatively, the above-described insulating material layer can be formed in the backside trenches 79 to completely fill the entire volume of the backside trenches 79 and can consist essentially of at least one dielectric material. In this alternative embodiment, the source regions 61 and the backside trench via structures 76 can be omitted, and horizontal source lines (e.g., direct strap contacts) can contact one side of the lower portion of the semiconductor channels 60.

[0137] Referring to Figure 21A and Figure 21B , additional contact via structures (88, 86, 8P) can be formed through the contact level dielectric layer 73 and, optionally, through the back-directed stepped dielectric material portion 65. For example, drain contact via structures 88 can be formed through the contact level dielectric layer 73 over each of the drain regions 63. Wordline contact via structures 86 can be formed on the conductive layer 46 through the contact level dielectric layer 73 and through the back-directed stepped dielectric material portion 65. Peripheral device contact via structures 8P can be formed directly on the respective nodes of the peripheral devices through the back-directed stepped dielectric material portion 65.

[0138] Figure 21C An alternative configuration of the exemplary structure according to an alternative embodiment is shown. In this embodiment, the bridge structures 164 are in the contact region 300 but not in the memory array region 100. In another alternative embodiment, the planarization step to form the backside contact via structures 76 removes more material than shown in Figures 20A-20C to remove the entire remaining bridge structure 164. In this alternative embodiment, the bridge structures 164 are temporary structures that are not retained in the final memory device shown in Figures 21A-21C

[0139] ​As the bridge structures 164 reduce the tilt and pattern distortion of the layer stacks, they also reduce potential shorting between the drain contact via structures 88 and the backside contact via structures 76 due to pattern distortion. The formation of the bridge structures 164 is also relatively simple and does not significantly negatively impact subsequent process steps.

[0140] Referring to all of the drawings and in accordance with various embodiments of the present disclosure, a three-dimensional memory device is provided that includes: layer stacks (32, 46, 70, 73) located above a substrate (9, 10) and laterally spaced apart from one another by backside trenches 79 that extend laterally along a first horizontal direction hd1, wherein each of the layer stacks (32, 46, 70, 73) includes a respective alternating stack of insulating layers 32 and electrically conductive layers 46; memory openings 49 that vertically extend through respective ones of the alternating stacks (32, 46) and are filled with respective memory opening fill structures 58, wherein each of the memory opening fill structures 58 includes a respective vertical semiconductor channel 60 and a respective vertical memory element stack (such as a portion of a memory material layer 54 located at a horizontal level of an electrically conductive layer 46); and backside trench fill structures (74, 76, 164) located within respective ones of the backside trenches 79, wherein each of the backside trench fill structures (74, 76, 164) includes a respective row of backside trench bridge structures 164 that are laterally spaced apart from one another along the first horizontal direction hd1 and are farther from the substrate (9, 10) than a farthest one of the electrically conductive layers 46 is from the substrate (9, 10).

[0141] In one embodiment, each of the layer stacks (32, 46, 70, 73) includes a respective contact level dielectric layer 73 overlying the respective alternating stack (32, 46) and contacting sidewalls of two rows of backside trench bridge structures 164. In one embodiment, a top surface of a backside trench bridge structure 164 is located within a same horizontal plane as a top surface of a contact level dielectric layer 73. In one embodiment, each of the memory opening fill structures 58 includes a drain region 63 that contacts a top end of a respective one of the vertical semiconductor channels 60; and a drain contact via structure 88 that vertically extends through a respective one of the contact level dielectric layers 73 and contacts a top surface of a respective one of the drain regions 63.

[0142] In one embodiment, each of the backside trench bridge structures 164 includes a pair of first sidewalls parallel to the first horizontal direction hd1 and a pair of second sidewalls perpendicular to the first horizontal direction hd2 (and parallel to the second horizontal direction hd2). In one embodiment, the backside trench bridge structures include a dielectric material, such as silicon oxide (e.g., undoped silicate glass or doped silicate glass).

[0143] In one embodiment, each of the backside trench fill structures (74, 76, 164) includes a backside contact via structure 76 that includes at least one electrically conductive material and that extends continuously below the respective row of backside trench bridge structures 164. In one embodiment, the backside contact via structure 76 includes a caster that protrudes upward from a horizontal plane that includes a bottom surface of the respective row of backside trench bridge structures 164 between the backside trench bridge structures 164 located in a same backside trench 79. In one embodiment, the caster of the backside trench via structure 76 has a top surface that is located within a horizontal plane that includes a top surface of the respective row of backside trench bridge structures 164, and the backside trench via structure 76 is not located above or on the top surface of the backside trench bridge structures 164.

[0144] In one embodiment, the electrically conductive layer 46 does not extend directly below the backside trench bridge structures 164. This allows the backside trenches 79 to electrically separate adjacent memory blocks located in a respective tier stack. Thus, word lines of adjacent memory blocks can be controlled individually.

[0145] In one embodiment, each of the backside trench fill structures (74, 76, 164) includes an insulating spacer 74 that laterally surrounds the backside contact via structure 76 and contacts sidewalls of a respective pair of tier stacks (32, 46, 70, 73) in the tier stacks (32, 46, 70, 73). In one embodiment, the substrate (9, 10) includes a semiconductor material layer 10 having a first conductivity type and a doping of source regions 61 embedded in the semiconductor material layer 10 and having a doping of a second conductivity type; and the backside contact via structure 76 contacts a top surface of a respective one of the source regions 61.

[0146] In one embodiment, each of the alternating stacks (32, 46) includes a platform region, where each conductive layer 46 within the alternating stack (32, 46) other than the topmost conductive layer 46 extends laterally farther than any overlying conductive layer 46 within the alternating stack (32, 46); the platform region includes stepped surfaces of the alternating stack (32, 46) that extend continuously from a bottommost layer within the alternating stack (32, 46) to a topmost layer within the alternating stack (32, 46); and the support pillar structure 20 extends through the stepped surfaces and through a back-stepped dielectric material portion 65 overlying the stepped surfaces.

[0147] In one embodiment, the three-dimensional memory device includes a three-dimensional NAND memory device; the conductive layers 46 include respective word lines of the three-dimensional NAND memory device or are electrically connected to respective word lines of the three-dimensional NAND memory device; and each vertical memory element stack includes a stack of vertical charge storage material portions that hold electrical charge therein when programmed or a stack of vertical ferroelectric memory elements that hold a ferroelectric polarization therein when programmed.

[0148] While specific preferred embodiments are mentioned, it is to be understood that the present disclosure is not limited thereto. Those skilled in the art will appreciate that various modifications can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed among all embodiments that are not alternatives to each other. Unless explicitly stated otherwise, the word "comprising" or "including" contemplates all embodiments where the words "consisting essentially of or the words "consisting of are substituted for the word "comprising" or "including." Embodiments are shown in the present disclosure employing particular structures and / or configurations, it is understood that the present disclosure can be practiced in any other compatible structure and / or configuration that is functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise deemed impossible by one of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated by reference in their entirety.

Claims

1. A three-dimensional memory device, comprising: a stack of layers located over a substrate and laterally spaced apart from one another by backside trenches that extend laterally along a first horizontal direction, wherein each stack of layers of the stack of layers comprises a respective alternating stack of insulating layers and electrically conductive layers; memory openings that extend vertically through respective ones of the alternating stacks and that are filled with respective memory opening fill structures, wherein each of the memory opening fill structures comprises a respective vertical semiconductor channel and a respective vertical stack of memory elements; and backside trench fill structures located within respective ones of the backside trenches, wherein: each of the backside trench fill structures comprises a respective row of backside trench bridge structures that are laterally spaced apart from one another along the first horizontal direction, and a bottom surface of the backside trench bridge structures is farther from the substrate than a distance of a farthest one of the electrically conductive layers from the substrate.

2. The three-dimensional memory device of Claim 1, wherein each stack of layers of the stack of layers comprises a respective contact-level dielectric layer that overlies the respective alternating stack and that contacts sidewalls of two rows of backside trench bridge structures.

3. The three-dimensional memory device of Claim 2, wherein a top surface of the backside trench bridge structures is located within a same horizontal plane as a top surface of the contact-level dielectric layer.

4. The three-dimensional memory device of Claim 2, wherein: each of the memory opening fill structures comprises a drain region that contacts a top end of a respective one of the vertical semiconductor channels; and a drain contact via structure extends vertically through a respective one of the contact-level dielectric layers and contacts a top surface of a respective one of the drain regions.

5. The three-dimensional memory device of Claim 1, wherein each of the backside trench bridge structures comprises a pair of first sidewalls that are parallel to the first horizontal direction and a pair of second sidewalls that are perpendicular to the first horizontal direction.

6. The three-dimensional memory device of Claim 1, wherein the backside trench bridge structures comprise a dielectric material.

7. The three-dimensional memory device of Claim 1, wherein each of the backside trench fill structures comprises a backside contact via structure that comprises at least one electrically conductive material and that extends continuously beneath the respective row of backside trench bridge structures.

8. The three-dimensional memory device of Claim 7, wherein the backside contact via structure comprises casters that protrude upward from a horizontal plane comprising bottom surfaces of the respective row of backside trench bridge structures between backside trench bridge structures located in a same backside trench.

9. The three-dimensional memory device of Claim 8, wherein the caster of the backside-trench-via structure has a top surface that lies within a horizontal plane that includes a top surface of the respective row of backside-trench-bridge structures, and the backside-trench-via structure does not lie above or on a top surface of the backside-trench-bridge structure.

10. The three-dimensional memory device of Claim 7, wherein each of the backside-trench-fill structures comprises an insulative spacer laterally surrounding the backside-contact-via structure and contacting sidewalls of a respective pair of layer stacks in the layer stack.

11. The three-dimensional memory device of Claim 7, wherein: the substrate comprises a layer of semiconductor material having a first conductivity type and source regions embedded in the layer of semiconductor material and having a second conductivity type of doping; and the backside-contact-via structures contact top surfaces of respective ones of the source regions.

12. The three-dimensional memory device of Claim 1, wherein the electrically-conductive layers do not directly extend under the backside-trench-bridge structures.

13. The three-dimensional memory device of Claim 1, wherein: the three-dimensional memory device comprises a three-dimensional NAND memory device; the electrically-conductive layers comprise respective word lines of the three-dimensional NAND memory device or are electrically connected to respective word lines of the three-dimensional NAND memory device; and each vertical memory element stack comprises a stack of vertical charge storage material portions that hold electrical charge therein when programmed or a stack of vertical ferroelectric memory elements that hold a ferroelectric polarization therein when programmed.

14. A method of forming a three-dimensional memory device, the method comprising: forming an alternating stack of insulative layers and sacrificial material layers over a substrate; forming memory openings through the alternating stack; forming memory opening fill structures in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical semiconductor channel and a respective vertical memory element stack; forming a contact-level dielectric layer over the alternating stack; forming backside trenches laterally extending through the contact-level dielectric layer and the alternating stack along a first horizontal direction to form layer stacks comprising respective patterned portions of the contact-level dielectric layer and respective patterned portions of the alternating stack that are laterally spaced apart from one another by the backside trenches; forming a row of backside-trench-bridge structures laterally spaced apart from one another within each of the backside trenches along the first horizontal direction, wherein a bottom surface of the backside-trench-bridge structures is farther from the substrate than a farthest patterned portion of the patterned portions of the sacrificial material layers; and replacing the patterned portions of the sacrificial material layers with electrically-conductive layers.

15. The method of Claim 14, further comprising: forming sacrificial backside-trench-fill structures in the backside trenches; forming a row of recessed cavities laterally spaced apart along the first horizontal direction within each of the sacrificial backside trench fill structures; forming the backside trench bridge structures in the recessed cavities; and forming backside cavities below the backside trench bridge structures by removing the sacrificial backside trench fill structures selective to the backside trench bridge structures and the layer stack.

16. The method of claim 15, wherein: the sacrificial backside trench fill structures comprise a semiconductor material, a carbon-containing material, or a polymeric material; the backside trench bridge structures comprise a dielectric material; and the sacrificial backside trench fill structures are removed by an isotropic etch process that etches a material of the sacrificial backside trench fill structures selective to the dielectric material of the backside trench bridge structures.

17. The method of claim 14, further comprising: forming backside recesses by removing the patterned portions of the sacrificial material layer selective to patterned portions of the insulating layer that pass through the backside trenches; depositing at least one conductive material in the backside recesses by providing a reactant into the backside recesses through the backside trenches, wherein portions of the at least one conductive material deposited in the backside recesses comprise the conductive layer; and removing portions of the at least one conductive material deposited in the backside trenches.

18. The method of claim 14, further comprising forming insulating spacers within each of the backside trenches by conformally depositing a layer of insulating material and anisotropically etching the layer of insulating material after forming the conductive layer, wherein each of the insulating spacers contacts a bottom surface and sidewalls of a respective row of backside trench bridge structures.

19. The method of claim 18, further comprising forming backside contact via structures within each of the backside trenches by depositing and planarizing at least one conductive material in volumes of the backside trenches not filled with the insulating spacers after forming the insulating spacers.

20. The method of claim 19, wherein: each of the backside contact via structures comprises a caster that protrudes upward from a horizontal plane comprising a bottom surface of the backside trench bridge structures between the backside trench bridge structures located in a same backside trench, and the casters of the backside trench via structures have top surfaces located within a horizontal plane comprising a top surface of the backside trench bridge structures.

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