Array substrate and display device

Abstract

An array substrate is provided. The array substrate includes first spacers (PS1) arranged in a first array and second spacers (PS2) arranged in a second array. Each row of second spacers (PS2) in the second array is between two corresponding rows of first spacers (PS1) in the first array. Each column of second spacers (PS2) in the second array is between two corresponding columns of first spacers (PS1) in the first array. Each row of first spacers (PS1) in the first array is between two corresponding rows of second spacers (PS2) in the second array. Each column of first spacers (PS1) in the first array is between two corresponding columns of second spacers (PS2) in the second array. A corresponding one of the first spacers (PS1) is between the second sub-pixel aperture and the third sub-pixel aperture. A corresponding one of the second spacers (PS2) is between the third sub-pixel aperture and the fourth sub-pixel aperture.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently a hot topic in flat panel display research. Unlike thin-film transistor liquid crystal displays (TFT-LCDs), which use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control illuminance. An OLED display panel includes multiple pixel units configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to a gate line in each row and a drain terminal connected to a data line in each column. When the row in which the pixel unit is selected is turned on, a switching transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line through the switching transistor to the driving transistor, causing the driving transistor to output a current corresponding to the data voltage to the OLED device. This drives the OLED device to emit light of a corresponding brightness. Summary of the Invention

[0003] In one aspect, this disclosure provides an array substrate, comprising: a substrate; a pixel defining layer on the substrate, the pixel defining layer defining a sub-pixel opening; a spacer layer located on a side of the pixel defining layer away from the substrate; a plurality of light-emitting elements in a plurality of sub-pixels, wherein the plurality of light-emitting elements includes a first light-emitting element in each first sub-pixel, a second light-emitting element in each second sub-pixel, a third light-emitting element in each third sub-pixel, and a fourth light-emitting element in each fourth sub-pixel; and a first sub-pixel opening, a second sub-pixel opening, a third sub-pixel opening, and a fourth sub-pixel opening extending through the pixel defining layer, wherein a first light-emitting layer of the first light-emitting element, a second light-emitting layer of the second light-emitting element, a third light-emitting layer of the third light-emitting element, and a fourth light-emitting layer of the fourth light-emitting element are respectively connected to the first light-emitting element through the first sub-pixel opening, the second sub-pixel opening, the third sub-pixel opening, and the fourth sub-pixel opening. The light source includes a first anode of a light-emitting element, a second anode of a second light-emitting element, a third anode of a third light-emitting element, and a fourth anode of a fourth light-emitting element; wherein the spacer layer includes a first spacer arranged in a first array and a second spacer arranged in a second array; the first array and the second array are interleaved; each row of second spacers in the second array is between two corresponding rows of first spacers in the first array; each column of second spacers in the second array is between two corresponding columns of first spacers in the first array; each row of first spacers in the first array is between two corresponding rows of second spacers in the second array; each column of first spacers in the first array is between two corresponding columns of second spacers in the second array; a corresponding first spacer in the first spacer is between a second sub-pixel opening and a third sub-pixel opening; and a corresponding second spacer in the second spacer is between a third sub-pixel opening and a fourth sub-pixel opening.

[0004] Optionally, the plurality of sub-pixels are arranged in an array of multiple rows along a first direction and multiple columns along a second direction; each row has a first spacer along the first direction; each row has a second spacer along the first direction; each column has a first spacer along the second direction; and each column has a second spacer along the second direction; two adjacent first spacers in each row are spaced apart by twice the distance between first anodes, the first anode distance being the distance along the first direction and between the centers of two adjacent third anodes of two adjacent third light-emitting elements along the first direction; two adjacent second spacers in each row are spaced apart by twice the distance between first anodes; two adjacent first spacers in each column are spaced apart by three times the distance between second anodes, the second anode distance being the distance along the second direction and between the centers of two adjacent third anodes of two adjacent third light-emitting elements along the second direction; and two adjacent second spacers in each column are spaced apart by three times the distance between second anodes.

[0005] Optionally, the array substrate further includes: a first light-emitting layer located on the side of the first anode of the first light-emitting element away from the substrate; a second light-emitting layer located on the side of the second anode away from the substrate; a third light-emitting layer located on the side of the third anode away from the substrate; and a fourth light-emitting layer located on the side of the fourth anode away from the substrate; wherein the orthographic projection of the third light-emitting layer on the substrate partially overlaps with the orthographic projection of the corresponding first spacer on the substrate; the orthographic projection of the second light-emitting layer on the substrate partially overlaps with the orthographic projection of the corresponding first spacer on the substrate; a first edge of the third light-emitting layer passing through the corresponding first spacer is substantially parallel to a first centerline of the corresponding first spacer; and a second edge of the second light-emitting layer passing through the corresponding first spacer is substantially parallel to the first centerline of the corresponding first spacer.

[0006] Optionally, the first edge is spaced apart from the first center line by a first distance along a direction perpendicular to the first center line; the second edge is spaced apart from the first center line by a second distance along the direction perpendicular to the first center line; and the average value of the first distance along the first edge is substantially the same as the average value of the second edge along the second distance.

[0007] Optionally, the orthographic projection of the third light-emitting layer on the substrate partially overlaps with the orthographic projection of the corresponding second spacer on the substrate; the orthographic projection of the fourth light-emitting layer on the substrate partially overlaps with the orthographic projection of the corresponding second spacer on the substrate; the third edge of the third light-emitting layer passing through the corresponding second spacer is substantially parallel to the second center line of the corresponding second spacer; and the fourth edge of the fourth light-emitting layer passing through the corresponding second spacer is substantially parallel to the second center line of the corresponding second spacer.

[0008] Optionally, the third edge is spaced a third distance from the second center line along a direction perpendicular to the second center line; the fourth edge is spaced a fourth distance from the second center line along the same direction perpendicular to the second center line; and the average value of the third distance along the third edge is substantially the same as the average value of the fourth distance along the fourth edge.

[0009] Optionally, the array substrate further includes a plurality of pixel driving circuits respectively in the plurality of sub-pixels, the plurality of pixel driving circuits being configured to drive the plurality of light-emitting elements respectively; wherein, each of the plurality of pixel driving circuits includes a plurality of transistors and a storage capacitor, the storage capacitor including a first capacitor electrode, a second capacitor electrode electrically connected to a corresponding voltage supply line, and an insulating layer between the first capacitor electrode and the second capacitor electrode; wherein, the array substrate includes: a semiconductor material layer on the substrate; and node connection lines located in the same layer as the corresponding voltage supply lines, the node connection lines being connected to the first capacitor electrode through a first via and to the semiconductor material layer through a second via; wherein, in the corresponding first sub-pixel, the plurality of pixel driving circuits are configured to drive the plurality of light-emitting elements respectively. The orthographic projection of the first anode of the first light-emitting element on the substrate at least partially overlaps with the orthographic projection of the node connection line in the corresponding first sub-pixel on the substrate; the orthographic projection of the second anode of the second light-emitting element in the corresponding second sub-pixel on the substrate at least partially overlaps with the orthographic projection of the node connection line in the corresponding second sub-pixel on the substrate; the orthographic projection of the third anode of the third light-emitting element in the corresponding third sub-pixel on the substrate at least partially overlaps with the orthographic projection of the node connection line in the corresponding third sub-pixel on the substrate; and the orthographic projection of the fourth anode of the fourth light-emitting element in the corresponding fourth sub-pixel on the substrate at least partially overlaps with the orthographic projection of the node connection line in the corresponding fourth sub-pixel on the substrate.

[0010] Optionally, the plurality of transistors includes a driving transistor; the orthographic projection of the first anode in a corresponding first sub-pixel onto the substrate covers the orthographic projection of a portion of the node connection line in the corresponding first sub-pixel at the location connected to the first capacitor electrode onto the substrate; the orthographic projection of the second anode in a corresponding second sub-pixel onto the substrate covers the orthographic projection of a portion of the node connection line in the corresponding second sub-pixel at the location connected to the first capacitor electrode onto the substrate; the orthographic projection of the third anode in a corresponding third sub-pixel onto the substrate covers the orthographic projection of a portion of the node connection line in the corresponding third sub-pixel at the location connected to the first capacitor electrode onto the substrate; and the orthographic projection of the fourth anode in a corresponding fourth sub-pixel onto the substrate covers the orthographic projection of a portion of the node connection line in the corresponding fourth sub-pixel at the location connected to the first capacitor electrode onto the substrate.

[0011] Optionally, the orthographic projection of the third anode on the substrate covers the orthographic projection of the source of the third transistor in the corresponding third sub-pixel on the substrate, overlaps with the orthographic projection portion of the active layer of the third transistor in the corresponding third sub-pixel on the substrate, and overlaps with the orthographic projection portion of the active layer of the third transistor in the corresponding fourth sub-pixel on the substrate.

[0012] Optionally, the orthographic projection of the first anode on the substrate partially overlaps with the source of the third transistor in the corresponding first sub-pixel on the substrate, and partially overlaps with the orthographic projection of the active layer of the third transistor in the corresponding first sub-pixel on the substrate.

[0013] Optionally, the orthographic projection of the fourth anode on the substrate overlaps with the orthographic projection of the source of the third transistor in the corresponding second sub-pixel on the substrate, and also overlaps with the orthographic projection of the active layer of the third transistor in the corresponding second sub-pixel on the substrate.

[0014] Optionally, the array substrate further includes: a gate insulating layer located on the side of the semiconductor material layer away from the substrate; an insulating layer located on the side of the gate insulating layer away from the substrate; an interlayer dielectric layer located on the side of the insulating layer away from the gate insulating layer; a relay electrode layer located on the side of the interlayer dielectric layer away from the insulating layer; a first planarization layer located on the side of the relay electrode layer away from the interlayer dielectric layer; an anode contact pad layer located on the side of the first planarization layer away from the interlayer dielectric layer; a second planarization layer located on the side of the anode contact pad layer away from the first planarization layer; and a pixel defining layer. A first sub-pixel is defined by a pixel defining layer on the side of the second planarization layer away from the substrate. Each anode is located on the side of the second planarization layer away from the first planarization layer, and each light-emitting layer is located on the side of each anode away from the second planarization layer. In each first sub-pixel, the first anode is connected to a first anode contact pad via a first via extending through the second planarization layer, the first anode contact pad is connected to a first relay electrode via a second via extending through the first planarization layer, and the first relay electrode is connected to a third via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer. In each first sub-pixel, the drain of the fifth transistor; in each second sub-pixel, the second anode is connected to the second anode contact pad via a fourth via extending through the second planarization layer, the second anode contact pad is connected to the second relay electrode via a fifth via extending through the first planarization layer, and the second relay electrode is connected to the drain of the fifth transistor in each second sub-pixel via a sixth via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer; in each third sub-pixel, the third anode is connected to the third anode contact pad via a seventh via extending through the second planarization layer, and the third anode contact pad is connected to the drain of the fifth transistor in each second sub-pixel via a sixth via extending through the first planarization layer. An eighth via of the planarization layer is connected to a third relay electrode, which is connected to the drain of a fifth transistor in each third sub-pixel via a ninth via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer; and in each fourth sub-pixel, the fourth anode is connected to a fourth anode contact pad via a tenth via extending through the second planarization layer, the fourth anode contact pad is connected to a fourth relay electrode via an eleventh via extending through the first planarization layer, and the fourth relay electrode is connected to the drain of a fifth transistor in each fourth sub-pixel via a twelfth via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer.

[0015] Optionally, the orthographic projection of a portion of the first anode contact pad in the second via on the substrate does not substantially overlap with the orthographic projection of a portion of the first anode in the first via on the substrate, and also does not substantially overlap with the orthographic projection of a portion of the first relay electrode in the third via on the substrate; the orthographic projection of a portion of the second anode contact pad in the fifth via on the substrate does not substantially overlap with the orthographic projection of a portion of the second anode in the fourth via on the substrate, and also does not substantially overlap with the orthographic projection of a portion of the second relay electrode in the sixth via on the substrate. The orthographic projection of a portion of the third anode contact pad in the eighth via on the substrate does not substantially overlap with the orthographic projection of a portion of the third anode in the seventh via on the substrate, and does not substantially overlap with the orthographic projection of a portion of the third relay electrode in the ninth via on the substrate; and the orthographic projection of a portion of the fourth anode contact pad in the eleventh via on the substrate does not substantially overlap with the orthographic projection of a portion of the fourth anode in the tenth via on the substrate, and does not substantially overlap with the orthographic projection of a portion of the fourth relay electrode in the twelfth via on the substrate.

[0016] Optionally, the ratio of the number of subpixels to the number of spacers is in the range of 28:1 to 20:1.

[0017] Optionally, the average area occupied by a corresponding first spacer in the first spacers is 80 μm. 2 Up to 120μm 2 Within the range; the average occupied area of ​​the corresponding second spacer in the second spacer is 80 μm. 2 Up to 120μm 2 Within the range; the average occupied area of ​​a corresponding sub-pixel among the plurality of sub-pixels is 1400μm. 2 Up to 2000μm 2 Within the range; and the percentage of the total occupied area of ​​the first spacer and the second spacer to the total occupied area of ​​the plurality of sub-pixels is in the range of 0.15% to 0.35%.

[0018] Optionally, in a counter-clockwise or clockwise direction, each third anode is adjacent to a first corresponding fourth anode, a first corresponding first anode, a first corresponding second anode, a second corresponding first anode, a second corresponding fourth anode, a second corresponding second anode, and a third corresponding first anode, respectively; the shortest distance between each third anode and any one of the first corresponding fourth anode, the first corresponding first anode, the first corresponding second anode, the second corresponding first anode, the virtual line, or the third corresponding first anode is in the range of 2.0 μm to 22 μm, the virtual line passes through the collinear edges from the second corresponding fourth anode and the second corresponding second anode, respectively; and the shortest distance between each third anode and the first corresponding fourth anode is less than the shortest distance between each third anode and the third corresponding first anode, less than the shortest distance between each third anode and the first corresponding first anode, less than the shortest distance between each third anode and the second corresponding first anode, less than the shortest distance between each third anode and the virtual line, wherein the virtual line passes through the collinear edges from the second corresponding fourth anode and the second corresponding second anode, respectively, and is less than the shortest distance between each third anode and the first corresponding second anode.

[0019] Optionally, the shortest distance between each third anode and the first corresponding fourth anode is in the range of 2.0 μm to 5.0 μm; the shortest distance between each third anode and the first corresponding first anode is in the range of 8.0 μm to 20.0 μm; the shortest distance between each third anode and the first corresponding second anode is in the range of 5.0 μm to 15.0 μm; the shortest distance between each third anode and the second corresponding first anode is in the range of 7.0 μm to 17.0 μm; the shortest distance between each third anode and the virtual line passing through the collinear edges from the second corresponding fourth anode and the second corresponding second anode is in the range of 5.0 μm to 16.0 μm; and the shortest distance between each third anode and the third corresponding first anode is in the range of 9.0 μm to 22.0 μm.

[0020] Optionally, in a counter-clockwise or clockwise direction, each first anode is adjacent to a first corresponding second anode, a first corresponding fourth anode, a first corresponding third anode, a second corresponding second anode, a second corresponding third anode, a second corresponding fourth anode, and a third corresponding third anode, respectively; the shortest distance between each first anode and any one of the first corresponding second anode, the first corresponding fourth anode, the first corresponding third anode, the second corresponding second anode, the second corresponding third anode, the second corresponding fourth anode, or the third corresponding third anode is in the range of 3.0 μm to 25 μm; and the shortest distance between each first anode and the second corresponding fourth anode is less than the shortest distance between each first anode and the second corresponding second anode, less than the shortest distance between each first anode and the first corresponding fourth anode, less than the shortest distance between each first anode and the first corresponding third anode, less than the shortest distance between each first anode and the second corresponding third anode, and less than the shortest distance between each first anode and the first corresponding second anode, and the shortest distance between each first anode and the second corresponding third anode is greater than the shortest distance between each first anode and the third corresponding third anode.

[0021] Optionally, the shortest distance between each first anode and the first corresponding second anode is in the range of 3.0 μm to 14.0 μm; the shortest distance between each first anode and the first corresponding fourth anode is in the range of 10.0 μm to 24.0 μm; the shortest distance between each first anode and the first corresponding third anode is in the range of 9.0 μm to 21.0 μm; the shortest distance between each first anode and the second corresponding second anode is in the range of 11.0 μm to 25.0 μm; the shortest distance between each first anode and the second corresponding third anode is in the range of 8.0 μm to 20.0 μm; the shortest distance between each first anode and the second corresponding fourth anode is in the range of 2.5 μm to 7.5 μm; and the shortest distance between each first anode and the third corresponding third anode is in the range of 7.0 μm to 16.0 μm.

[0022] Optionally, in a counterclockwise or clockwise direction, each fourth anode is adjacent to a corresponding second anode, a first corresponding third anode, a first corresponding first anode, a second corresponding third anode, and a second corresponding first anode; the shortest distance between each fourth anode and any one of the first corresponding first anode, the second corresponding third anode, or the second corresponding first anode is in the range of 2.0 μm to 25.0 μm; and the shortest distance between each fourth anode and the second corresponding first anode is greater than the shortest distance between each fourth anode and the first corresponding first anode, and is also greater than the shortest distance between each fourth anode and the second corresponding third anode.

[0023] Optionally, the distance between each fourth anode and the corresponding second anode, along a virtual line passing through the collinear edges of the respective fourth anodes and the respective second anodes, is in the range of 10.0 μm to 25.0 μm; the shortest distance between the first corresponding third anode and the virtual line passing through the collinear edges of the respective fourth anodes and the respective second anodes is in the range of 6.0 μm to 15.0 μm; the shortest distance between the protrusion of the first corresponding first anode closest to each fourth anode and the virtual line passing through the collinear edges of the respective fourth anodes and the respective second anodes is in the range of 5.0 μm to 16.0 μm; the shortest distance between each fourth anode and the first corresponding first anode is in the range of 2.5 μm to 7.5 μm; the shortest distance between each fourth anode and the second corresponding third anode is in the range of 2.0 μm to 5.0 μm; and the shortest distance between each fourth anode and the second corresponding first anode is in the range of 10.0 μm to 25.0 μm.

[0024] Optionally, the shortest distance between the first via and the first sub-pixel opening is in the range of 9.0 μm to 15.0 μm; the shortest distance between the fourth via and the second sub-pixel opening is in the range of 2.0 μm to 6.0 μm; the shortest distance between the seventh via and the third sub-pixel opening is in the range of 4.5 μm to 10.5 μm; and the shortest distance between the tenth via and the fourth sub-pixel opening is in the range of 2.0 μm to 6.0 μm.

[0025] Optionally, the ratio of the number of subpixels to the number of spacers is in the range of 48:1 to 15:1.

[0026] Optionally, the first centerline has a first tilt angle in the range of 40 to 80 degrees relative to the first direction; and the second centerline has a second tilt angle in the range of 10 to 50 degrees relative to the first direction.

[0027] Optionally, the orthographic projection of a corresponding first spacer on the substrate at least partially overlaps with the orthographic projection of the second anode on the substrate; and the orthographic projection of a corresponding second spacer on the substrate at least partially overlaps with the orthographic projection of the fourth anode on the substrate.

[0028] Optionally, the plurality of sub-pixels are arranged in an array of multiple rows along a first direction and multiple columns along a second direction; each row has a first spacer along the first direction; each row has a second spacer along the first direction; each column has a first spacer along the second direction; and each column has a second spacer along the second direction, wherein a first virtual line along the first direction passes through a corresponding one of the first spacers and the fourth via; and a second virtual line along the first direction passes through a corresponding one of the second spacers and the tenth via.

[0029] Optionally, the first through hole, the second through hole, and the third through hole are arranged in a direction substantially parallel to the second direction; the fourth through hole, the fifth through hole, and the sixth through hole are arranged in a direction substantially parallel to the second direction; the eighth through hole and the ninth through hole are arranged in a direction substantially parallel to the second direction; the tenth through hole, the eleventh through hole, and the twelfth through hole are arranged in a direction substantially parallel to the second direction; and the seventh through hole and the eighth through hole are arranged in a direction with an inclination angle greater than 15 degrees relative to the second direction.

[0030] Optionally, the first anode contact pad has a first portion connected to the first anode through the first through-hole and a second portion connected to the first relay electrode through the second through-hole; the first anode contact pad has a substantially rectangular shape, and the first portion and the second portion are arranged in a direction substantially parallel to the second direction; the second anode contact pad has a third portion connected to the second anode through the fourth through-hole and a fourth portion connected to the second relay electrode through the fifth through-hole; the second anode contact pad has a substantially rectangular shape, and the third portion and the fourth portion are arranged in a direction substantially parallel to the second direction; the first... The three-anode contact pad has a fifth portion connected to the third anode through the seventh through-hole and a sixth portion connected to the third relay electrode through the eighth through-hole; the third anode contact pad has a substantially dumbbell-shaped shape, and the fifth and sixth portions are arranged at an angle greater than 15 degrees relative to the second direction; the fourth anode contact pad has a seventh portion connected to the fourth anode through the tenth through-hole and an eighth portion connected to the fourth relay electrode through the eleventh through-hole; and the fourth anode contact pad has a substantially rectangular shape, and the seventh and eighth portions are arranged in a direction substantially parallel to the second direction.

[0031] In another aspect, this disclosure provides a display device including an array substrate described herein or manufactured by the methods described herein, and an integrated circuit connected to the array substrate. Attached Figure Description

[0032] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0033] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure.

[0034] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0035] Figure 2B This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0036] Figure 3A This is a diagram illustrating the structure of a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0037] Figure 3B This is a schematic diagram illustrating the sub-pixel arrangement of a plurality of subpixels in an array substrate according to some embodiments of the present disclosure.

[0038] Figure 3C It is shown Figure 3A A diagram showing the structure of the semiconductor material layers in multiple sub-pixels of the array substrate.

[0039] Figure 3D It is shown Figure 3A A diagram showing the structure of the first conductive layer in multiple sub-pixels of the array substrate.

[0040] Figure 3E It is shown Figure 3A A diagram showing the structure of the second conductive layer in multiple sub-pixels of the array substrate.

[0041] Figure 3F It is shown Figure 3A A diagram showing the structure of the first signal line layer in multiple sub-pixels of the array substrate.

[0042] Figure 3G It is shown Figure 3A A diagram showing the structure of the second signal line layer in multiple sub-pixels of the array substrate.

[0043] Figure 3H It is shown Figure 3A A diagram showing the structure of the anode in multiple sub-pixels of the array substrate.

[0044] Figure 4A It is along Figure 3A A cross-sectional view of line A-A' in the diagram.

[0045] Figure 4B It is along Figure 3A A cross-sectional view of line B-B' in the diagram.

[0046] Figure 4C It is along Figure 3A A cross-sectional view of line C-C' in the diagram.

[0047] Figure 4D It is along Figure 3A A cross-sectional view of the D-D' line in the diagram.

[0048] Figure 5A This is a diagram illustrating the arrangement of spacers in an array substrate according to some embodiments of the present disclosure.

[0049] Figure 5B This is a schematic diagram illustrating the arrangement of spacers among a plurality of sub-pixels in an array substrate according to some embodiments of the present disclosure.

[0050] Figure 6A The following illustration shows the use of a third photomask to form a third light-emitting layer in an array substrate according to some embodiments of the present disclosure.

[0051] Figure 6B The following illustration shows the formation of a second light-emitting layer in an array substrate using a second photomask according to some embodiments of the present disclosure.

[0052] Figure 6C The present disclosure illustrates the use of a fourth photomask to form a fourth light-emitting layer in an array substrate according to some embodiments thereof.

[0053] Figure 6D The first light-emitting layer is formed in an array substrate using a first mask template according to some embodiments of the present disclosure.

[0054] Figure 6E The relative positions of the boundaries of the openings of the first, second, third, and fourth masks relative to the corresponding first spacers in the array substrate are shown in some embodiments of the present disclosure.

[0055] Figure 6F The relative positions of the light-emitting layers with respect to corresponding first spacers in the array substrate are shown in some embodiments according to this disclosure.

[0056] Figure 6G It revolves around Figure 6F An enlarged view of the area corresponding to the first spacer in the image.

[0057] Figure 6H It is along Figure 6F A cross-sectional view of the L-L' line in the diagram.

[0058] Figure 6I The following illustrations show how a second and a fourth light-emitting layer are formed in an array substrate using the same photomask according to some embodiments of the present disclosure.

[0059] Figure 7A The following illustration shows the use of a third photomask to form a third light-emitting layer in an array substrate according to some embodiments of the present disclosure.

[0060] Figure 7B The following illustration shows the formation of a second light-emitting layer in an array substrate using a second photomask according to some embodiments of the present disclosure.

[0061] Figure 7C The present disclosure illustrates the use of a fourth photomask to form a fourth light-emitting layer in an array substrate according to some embodiments thereof.

[0062] Figure 7D The first light-emitting layer is formed in an array substrate using a first mask template according to some embodiments of the present disclosure.

[0063] Figure 7EThe relative positions of the boundaries of the openings of the first, second, third, and fourth masks relative to the corresponding second spacers in the array substrate are shown in some embodiments of the present disclosure.

[0064] Figure 7F The relative positions of the light-emitting layer with respect to a corresponding second spacer in the array substrate are shown in some embodiments according to this disclosure.

[0065] Figure 7G It revolves around Figure 7F An enlarged view of the area corresponding to the second spacer in the diagram.

[0066] Figure 7H The following illustrations show how a second and a fourth light-emitting layer are formed in an array substrate using the same photomask according to some embodiments of the present disclosure.

[0067] Figure 8A This is a diagram illustrating the anode, first signal line layer, and semiconductor material layer in an array substrate according to some embodiments of the present disclosure.

[0068] Figure 8B It is along Figure 8A A cross-sectional view of the E-E' line in the diagram.

[0069] Figure 8C It is along Figure 8A A cross-sectional view of line F-F' in the diagram.

[0070] Figure 8D It is along Figure 8A A cross-sectional view of the G-G' line in the diagram.

[0071] Figure 8E This is a diagram illustrating the anode, first signal line layer, and semiconductor material layer in an array substrate according to some embodiments of the present disclosure.

[0072] Figure 8F This is a diagram illustrating the anode, first signal line layer, and semiconductor material layer in an array substrate according to some embodiments of the present disclosure.

[0073] Figure 9A This is a diagram illustrating the anode, first signal line layer, second signal line layer, and semiconductor material layer in an array substrate according to some embodiments of the present disclosure.

[0074] Figure 9B It is along Figure 9A A cross-sectional view of the H-H' line in the diagram.

[0075] Figure 9C It is along Figure 9A A cross-sectional view of line I-I' in the diagram.

[0076] Figure 9DIt is along Figure 9A A cross-sectional view of line J-J' in the diagram.

[0077] Figure 9E It is along Figure 9A A cross-sectional view of the K-K' line in the diagram.

[0078] Figure 10 The relative positions between subpixel openings and vias in an array substrate are shown in some embodiments according to this disclosure.

[0079] Figure 11 A partial structure of a voltage supply line according to some embodiments of the present disclosure is shown.

[0080] Figure 12 The detailed structure of an anti-interference block according to some embodiments of the present disclosure is shown.

[0081] Figure 13 The diagram schematically shows several repeating units arranged in two repeating unit groups.

[0082] Figure 14 Structural differences between the second and fourth anodes according to some embodiments of the present disclosure are shown. Detailed Implementation

[0083] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0084] This disclosure provides, in particular, an array substrate and a display device that substantially overcomes one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides an array substrate. In some embodiments, the array substrate includes a substrate; a pixel defining layer on the substrate defining sub-pixel openings; a spacer layer located on a side of the pixel defining layer remote from the substrate; and a plurality of light-emitting elements, each located in one of the plurality of sub-pixels. Optionally, the plurality of light-emitting elements includes a first light-emitting element in each first sub-pixel, a second light-emitting element in each second sub-pixel, a third light-emitting element in each third sub-pixel, and a fourth light-emitting element in each fourth sub-pixel. Optionally, the spacer layer includes a first spacer arranged in a first array and a second spacer arranged in a second array; the first array and the second array are staggered. Optionally, each row of the second array has a second spacer between two corresponding rows of the first array; each column of the second array has a second spacer between two corresponding columns of the first array; each row of the first array has a first spacer between two corresponding rows of the second array; each column of the first array has a first spacer between two corresponding columns of the second array; a corresponding first spacer is between the second anode of the second light-emitting element and the third anode of the third light-emitting element; and a corresponding second spacer is between the third anode and the fourth anode of the fourth light-emitting element.

[0085] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 1 The array substrate comprises an array of subpixels Sp. Each subpixel includes an electronic component, such as a light-emitting element. In one example, the light-emitting element is driven by a pixel driving circuit PDC. The array substrate includes multiple gate lines GL, multiple data lines DL, multiple voltage supply lines Vdd (e.g., high voltage supply lines), and multiple second voltage supply lines (e.g., low voltage supply lines Vss). The emission of light from each subpixel in the subpixel Sp is driven by the pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input to the pixel driving circuit PDC connected to the anode of the light-emitting element through a corresponding one of the multiple voltage supply lines Vdd; a low voltage signal (e.g., a VSS signal) is input to the cathode of the light-emitting element through a corresponding one of the multiple second voltage supply lines (e.g., a low voltage supply line Vss). The voltage difference between the high voltage signal (e.g., the VDD signal) and the low voltage signal (e.g., the VSS signal) is a driving voltage ΔV, which drives the light-emitting element to emit light.

[0086] Various suitable pixel driving circuits can be used in this array substrate. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, and 8T2C. In some embodiments, each pixel driving circuit in the plurality of pixel driving circuits is a 7T1C driving circuit. Various suitable light-emitting elements can be used in this array substrate. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro OLEDs. Optionally, the light-emitting element is a micro OLED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0087] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. Referring to FIG2, in some embodiments, the pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a corresponding one of a plurality of first reset control signal lines rst1, a source connected to a corresponding one of a plurality of first reset signal lines Vint1, and a drain connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a gate line GL, a source connected to a data line DL, and a drain connected to the source of the driving transistor Td; and a third transistor T3 having a gate connected to the gate line GL and a source connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td. The gate and drain of a transistor are connected to the drain of a driving transistor Td; a fourth transistor T4 has its gate connected to a corresponding one of a plurality of light-emitting control signal lines em, its source connected to a voltage supply line Vdd, and its drain connected to the source of the driving transistor Td and the drain of the second transistor T2; a fifth transistor T5 has a gate connected to a corresponding one of a plurality of light-emitting control signal lines em, a source connected to the drain of the driving transistor Td and the drain of the third transistor T3, and a drain connected to the anode of the light-emitting element LE; and a sixth transistor T6 has a gate connected to a corresponding one of a plurality of second reset control signal lines rst2, a source connected to a corresponding one of a plurality of second reset signal lines Vint2, and a drain connected to the drain of the fifth transistor and the anode of the light-emitting element LE. The second capacitor electrode Ce2 is connected to the voltage supply line Vdd and the source of the fourth transistor T4.

[0088] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the source of the third transistor T3. The second node N2 is connected to the drain of the fourth transistor T4, the drain of the second transistor T2, and the source of the driving transistor Td. The third node N3 is connected to the drain of the driving transistor Td, the drain of the third transistor T3, and the source of the fifth transistor T5. The fourth node N4 is connected to the drain of the fifth transistor T5, the drain of the sixth transistor T6, and the anode of the light-emitting element LE.

[0089] Figure 3A This is a diagram illustrating the structure of a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. Figure 3B This is a schematic diagram illustrating the sub-pixel arrangement of a plurality of subpixels in an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 3A and Figure 3B In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes a corresponding first sub-pixel sp1, a corresponding second sub-pixel sp2, a corresponding third sub-pixel sp3, and a corresponding fourth sub-pixel sp4. Optionally, each pixel of the array substrate includes a corresponding first sub-pixel sp1, a corresponding second sub-pixel sp2, a corresponding third sub-pixel sp3, and a corresponding fourth sub-pixel sp4. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in the format S1-S2-S3-S4, where S1 represents each first sub-pixel sp1, S2 represents each second sub-pixel sp2, S3 represents each third sub-pixel sp3, and S4 represents each fourth sub-pixel sp4. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, where C1 represents each first sub-pixel sp1 of a first color, C2 represents each second sub-pixel sp2 of a second color, C3 represents each third sub-pixel sp3 of a third color, and C4 represents each fourth sub-pixel sp4 of a fourth color. In another example, the S1-S2-S3-S4 format is the C1-C2-C3-C2' format, where C1 represents each first sub-pixel sp1 of the first color, C2 represents each second sub-pixel sp2 of the second color, C3 represents each third sub-pixel sp3 of the third color, and C2' represents each fourth sub-pixel sp4 of the second color. In yet another example, the C1-C2-C3-C2' format is the RGBG format, where each first sub-pixel sp1 is a red sub-pixel, each second sub-pixel sp2 is a green sub-pixel, each third sub-pixel sp3 is a blue sub-pixel, and each fourth sub-pixel sp4 is a green sub-pixel.

[0090] like Figure 3Aand Figure 3B As shown, in some embodiments, the smallest repeating unit of a plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel sp1, a corresponding second sub-pixel sp2, a corresponding third sub-pixel sp3, and a corresponding fourth sub-pixel sp4. Figure 3A The diagram shows a total of four sub-pixels, consisting of multiple sub-pixels sp arranged adjacent to each other. Each of the corresponding first sub-pixel sp1, corresponding second sub-pixel sp2, corresponding third sub-pixel sp3, and corresponding fourth sub-pixel sp4 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a driving transistor Td.

[0091] Figure 3C It is shown Figure 3A A diagram showing the structure of the semiconductor material layers in multiple sub-pixels of the array substrate. Figure 3D It is shown Figure 3A A diagram showing the structure of the first conductive layer in multiple sub-pixels of the array substrate. Figure 3E It is shown Figure 3A A diagram showing the structure of the second conductive layer in multiple sub-pixels of the array substrate. Figure 3F It is shown Figure 3A A diagram showing the structure of the first signal line layer in multiple sub-pixels of the array substrate. Figure 3G It is shown Figure 3A A diagram showing the structure of the second signal line layer in multiple sub-pixels of the array substrate. Figure 3H It is shown Figure 3A A diagram showing the structure of the anode in multiple sub-pixels of the array substrate. Figure 4A It is along Figure 3A A cross-sectional view of line A-A' in the diagram.

[0092] Figure 4B It is along Figure 3A A cross-sectional view of line B-B' in the diagram. Figure 4C It is along Figure 3A A cross-sectional view of line C-C' in the diagram. Figure 4D It is along Figure 3A A cross-sectional view of line D-D' in the diagram. (Reference) Figures 3A to 3H and Figures 4A to 4DIn some embodiments, the array substrate includes a substrate BS, a semiconductor material layer SML on the substrate BS, a gate insulating layer GI located on the side of the semiconductor material layer SML away from the substrate BS, a first conductive layer located on the side of the gate insulating layer GI away from the semiconductor material layer SML, an insulating layer IN located on the side of the first conductive layer away from the gate insulating layer GI, a second conductive layer located on the side of the insulating layer IN away from the first conductive layer, an interlayer dielectric layer ILD located on the side of the second conductive layer away from the insulating layer IN, a first signal line layer located on the side of the interlayer dielectric layer ILD away from the second conductive layer, a first planarization layer PLN1 located on the side of the signal line layer away from the interlayer dielectric layer ILD, a second signal line layer located on the side of the first planarization layer PLN1 away from the first signal line layer, a second planarization layer PLN2 located on the side of the second signal line layer away from the first planarization layer PLN1, and an anode layer located on the side of the second planarization layer PLN2 away from the second signal line layer.

[0093] Reference Figure 2A , Figure 3A as well as Figure 3C In some embodiments, the semiconductor material layer has an integral structure in each sub-pixel. Figure 3C In the image, the first sub-pixel on the left is marked, indicating the area corresponding to multiple transistors in the pixel driving circuit. These transistors include the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the driving transistor Td. Figure 3BIn the diagram, the sub-pixels on the right are labeled with markers indicating the components of each of the multiple transistors in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a source S1, and a drain D1. The second transistor T2 includes an active layer ACT2, a source S2, and a drain D2. The third transistor T3 includes an active layer ACT3, a source S3, and a drain D3. The fourth transistor T4 includes an active layer ACT4, a source S4, and a drain D4. The fifth transistor T5 includes an active layer ACT5, a source S5, and a drain D5. The sixth transistor T6 includes an active layer ACT6, a source S6, and a drain D6. The driving transistor Td includes an active layer ACTd, a source Sd, and a drain Dd. In one example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), sources (S1, S2, S3, S4, S5, S6, and Sd), and drains (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each sub-pixel are part of the overall structure in that sub-pixel. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), sources (S1, S2, S3, S4, S5, S6, and Sd), and drains (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are in the same layer.

[0094] Reference Figure 2A , Figure 3A , Figure 3D , Figure 4A as well as Figure 4B In some embodiments, the first conductive layer includes multiple gate lines GL, multiple first reset control signal lines rst1, multiple light emission control signal lines em, multiple second reset control signal lines rst2, and a first capacitor electrode Ce1 for a storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first conductive layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the multiple gate lines GL, multiple first reset control signal lines rst1, multiple light emission control signal lines em, multiple second reset control signal lines rst2, and the first capacitor electrode Ce1 are located in the same layer.

[0095] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, multiple gate lines GL and the first capacitor electrode Ce1 are located in the same layer when they are formed by one or more steps of the same patterning process performed on the same material layer. In another example, multiple gate lines GL and the first capacitor electrode Ce1 can be formed in the same layer by simultaneously performing the steps of forming multiple gate lines GL and forming the first capacitor electrode Ce1. The term "same layer" does not always mean that the thickness or height of the layer is the same in a cross-sectional view.

[0096] Reference Figure 2A , Figure 3A and Figure 3E In some embodiments, the second conductive layer includes multiple first reset signal lines Vint1, a second capacitor electrode Ce2 of a storage capacitor Cst, an anti-interference block IPB, and multiple second reset signal lines Vint2. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second conductive layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the multiple first reset signal lines Vint1, the multiple second reset signal lines Vint2, the anti-interference block IPB, and the second capacitor electrode Ce2 are located in the same layer. Reference Figure 2A , Figure 3A , Figure 3D and Figure 4B In some embodiments, the anti-interference block IPB is in the same layer as the second capacitor electrode Ce2. A corresponding one of the plurality of voltage supply lines Vdd is connected to the anti-interference block IPB via a third main via v3. Optionally, the third main via v3 extends through the interlayer dielectric layer ILD.

[0097] Reference Figure 2A , Figure 3A , Figure 3C and Figure 3FIn some embodiments, the first signal line layer includes multiple voltage supply lines Vdd, node connection lines Cln, second connection lines Cl2, and third connection lines Cl3. Node connection lines Cln connect a first capacitor electrode Ce1 to the source of a third transistor T3 in a respective sub-pixel. Second connection lines Cl2 connect a corresponding one of a plurality of first reset signal lines Vint1 to the source of a first transistor T1 in the corresponding sub-pixel. Third connection lines Cl3 connect a corresponding one of a plurality of second reset signal lines Vint2 to the source of a sixth transistor T6 in the corresponding sub-pixel. In some embodiments, the first signal line layer also includes a relay electrode RE in a corresponding sub-pixel sp. The relay electrode connects the source of a fifth transistor T5 in a corresponding sub-pixel sp to an anode contact pad in the corresponding sub-pixel sp. Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the signal line layer. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials used to manufacture the first signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, multiple voltage supply lines Vdd, multiple data lines DL, node connection lines Cln, second connection lines Cl2, third connection lines Cl3, and relay electrodes RE are located in the same layer.

[0098] Figure 4C It is along Figure 3A A cross-sectional view of line C-C' in the diagram. (Refer to...) Figure 2A , Figure 3A , Figure 3F and Figure 4C In some embodiments, the second connection line Cl2 connects a corresponding one of the plurality of first reset signal lines Vint1 to the source S1 of the first transistor T1 in each sub-pixel. The corresponding one of the plurality of first reset signal lines Vint1 is configured to provide a reset signal to the source S1 of the first transistor T1 in each sub-pixel via the second connection line Cl2. Optionally, the second connection line Cl2 is connected to the corresponding one of the plurality of first reset signal lines Vint1 via a fifth main via v5 extending through the interlayer dielectric layer ILD. Optionally, the second connection line Cl2 is connected to the source S1 of the first transistor T1 in each sub-pixel via a sixth main via v6 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0099] Figure 4D It is along Figure 3A A cross-sectional view of line D-D' in the diagram. (Refer to...) Figure 2A , Figure 3A , Figure 3F and Figure 4D In some embodiments, a third connection line Cl3 connects a corresponding one of the plurality of second reset signal lines Vint2 to the source S6 of a sixth transistor T6 in each sub-pixel. The corresponding one of the plurality of second reset signal lines Vint2 is configured to provide a reset signal to the source S6 of the sixth transistor T6 in each sub-pixel via the second connection line Cl2. Optionally, the third connection line Cl3 is connected to a corresponding one of the plurality of second reset signal lines Vint2 via a seventh main via v7 extending through the interlayer dielectric layer ILD. Optionally, the third connection line Cl3 is connected to the source S6 of the sixth transistor T6 in each sub-pixel via an eighth main via v8 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0100] Reference Figure 2A , Figure 3A and Figure 3G In some embodiments, the second signal line layer includes multiple data lines DL. Optionally, the second signal line layer also includes an anode contact pad ACP in each of the multiple sub-pixels sp. The anode contact pad ACP is electrically connected to the source of a fifth transistor T5 in each of the multiple sub-pixels sp via a relay electrode in each of the multiple sub-pixels sp. Reference Figure 2A , Figure 3A , Figure 3F , Figure 3G and Figure 4B In some embodiments, each of the multiple data lines DL is connected to the connection portion CP through a via v4-1 extending through the first planarization layer PLN-1, and the connection portion CP is connected to the source S2 of the second transistor through a via v4-2 extending through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI.

[0101] Reference Figure 2A , Figure 3A , Figure 3D , Figure 3E and Figure 4AIn some embodiments, except for the via region H in which a portion of the second capacitor electrode Ce2 is not present, the orthographic projection of the second capacitor electrode Ce2 onto the substrate BS completely covers the orthographic projection of the first capacitor electrode Ce1 onto the substrate BS with a margin. In some embodiments, the signal line layer includes a node connection line Cln located on the side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. The node connection line Cln is in the same layer as multiple voltage supply lines Vdd and multiple data lines DL. Optionally, the array substrate also includes a first main via v1 in the via region H and extending through the interlayer dielectric layer ILD and the insulating layer IN. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first main via v1. In some embodiments, the first capacitor electrode Ce1 is located on the side of the gate insulating layer IN away from the substrate BS. Optionally, the array substrate also includes a first main via v1 and a second main via v2. The first main via v1 is located in the via region H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second main via v2 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first main via v1 and to the semiconductor material layer SML through the second main via v2. Optionally, the node connection line Cln is connected to the source S3 of the third transistor, such as... Figure 4A As shown.

[0102] refer to Figure 2A , Figure 3A , Figure 3E and Figure 4B In some embodiments, the anti-interference block IPB and the second capacitor electrode Ce2 are in the same layer. A corresponding one of the plurality of voltage supply lines Vdd is connected to the anti-interference block IPB through a third main via v3. Optionally, the third main via v3 extends through the interlayer dielectric layer ILD. Optionally, the orthographic projection of the anti-interference block IPB on the substrate BS partially overlaps with the orthographic projection of a corresponding one of the plurality of voltage supply lines Vdd on the substrate BS. Optionally, the orthographic projection of the anti-interference block IPB on the substrate BS at least partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor T3 on the substrate BS. Optionally, the orthographic projection of the anti-interference block IPB on the substrate BS at least partially overlaps with the orthographic projection of the drain D1 of the first transistor T1 on the substrate BS. Optionally, a portion of the orthographic projection of the anti-interference block IPB on the substrate BS and a portion of the orthographic projection of a corresponding one of the plurality of voltage supply lines on the substrate BS jointly overlap with a portion of the orthographic projection of the active layer ACT3 of the third transistor T3 on the substrate BS.

[0103] As used herein, an active layer refers to an assembly of a transistor comprising at least a portion of a semiconductor material layer, the orthographic projection of which onto the substrate overlaps with the orthographic projection of the gate onto the substrate. As used herein, a source refers to an assembly of a transistor connected to one side of the active layer, and a drain refers to an assembly of a transistor connected to the other side of the active layer. In the case of a dual-gate transistor (e.g., the third transistor T3), an active layer refers to an assembly of a transistor comprising a first portion of a semiconductor material layer, a second portion of a semiconductor material layer, and a third portion between the first and second portions, the orthographic projection of which onto the substrate overlaps with the orthographic projection of the first gate onto the substrate, and the orthographic projection of which onto the substrate overlaps with the orthographic projection of the second gate onto the substrate. In the case of a dual-gate transistor, a source refers to an assembly of a transistor connected to the side of the first portion away from the third portion, and a drain refers to an assembly of a transistor connected to the side of the second portion away from the third portion.

[0104] refer to Figure 2A , Figure 3A and Figure 3H In some embodiments, the array substrate includes a first anode AD1 in each first sub-pixel sp1, a second anode AD2 in each second sub-pixel sp2, a third anode AD3 in each third sub-pixel sp3, and a fourth anode AD4 in each fourth sub-pixel sp4. The first anode AD1, second anode AD2, third anode AD3, and fourth anode AD4 are respectively the anodes of a first light-emitting element, a second light-emitting element, a third light-emitting element, and a fourth light-emitting element in each first sub-pixel sp1, each second sub-pixel sp2, each third sub-pixel sp3, and each fourth sub-pixel sp4. In some embodiments, the array substrate further includes a pixel defining layer PDL located on the side of the first anode AD1, second anode AD2, third anode AD3, and fourth anode AD4 away from the second planarization layer PLN2. The array substrate also includes a first sub-pixel opening SA1, a second sub-pixel opening SA2, a third sub-pixel opening SA3, and a fourth sub-pixel opening SA4 extending through the pixel defining layer PDL. In some embodiments, each first sub-pixel sp1 is a red sub-pixel, and the first anode AD1 is the anode of the red sub-pixel; each second sub-pixel sp2 is a first green sub-pixel, and the second anode AD2 is the anode of the first green sub-pixel; each third sub-pixel sp3 is a blue sub-pixel, and the third anode AD3 is the anode of the blue sub-pixel; each fourth sub-pixel sp4 is a second green sub-pixel, and the fourth anode AD4 is the anode of the second green sub-pixel.

[0105] In some embodiments, the array substrate further includes a plurality of spacers located on the side of the second planarization layer away from the substrate. The spacers are configured to space the fine metal mask from the array substrate during the process of depositing the light-emitting material onto the array substrate. By providing the spacers, damage to the pixel driving circuitry caused by the fine metal mask during deposition can be effectively avoided. Figure 5A This is a schematic diagram illustrating the arrangement of spacers among a plurality of sub-pixels in an array substrate according to some embodiments of the present disclosure. Reference Figure 5A In some embodiments, the multiple spacers include first spacers PS1 arranged in a first array and second spacers PS2 arranged in a second array. The first array and the second array are staggered. Each row of second spacers PS2 in the second array is located between two corresponding rows of first spacers PS1 in the first array. Each column of second spacers PS2 in the second array is located between two corresponding columns of first spacers PS1 in the first array. Each row of first spacers PS1 in the first array is located between two corresponding rows of second spacers PS2 in the second array. Each column of first spacers PS1 in the first array is located between two corresponding columns of second spacers PS2 in the second array.

[0106] like Figure 5A As shown, two adjacent first spacers in each row's first spacer PS1 are separated by eight sub-pixels; two adjacent second spacers in each row's second spacer PS2 are separated by eight sub-pixels; two adjacent first spacers in each column's first spacer PS1 are separated by six sub-pixels; and two adjacent second spacers in each column's second spacer PS2 are separated by six sub-pixels. Optionally, the ratio of the number of sub-pixels to the number of spacers is in the range of 48:1 to 15:1, for example, 48:1 to 40:1, 40:1 to 35:1, 35:1 to 30:1, 30:1 to 25:1, 25:1 to 20:1, or 20:1 to 15:1. Optionally, the ratio of the number of sub-pixels to the number of spacers is in the range of 28:1 to 20:1, for example, 27:1 to 21:1, 26:1 to 22:1, or 25:1 to 23:1. Optionally, as... Figure 5A As shown, the ratio of the number of sub-pixels to the number of spacers is 24:1.

[0107] Figure 5B This is a diagram illustrating the arrangement of spacers in an array substrate according to some embodiments of the present disclosure. Figure 5B The positions of multiple spacers in the array substrate relative to the anode are shown. (Reference) Figure 5BIn some embodiments, each first spacer in the first spacer PS1 is located between the second anode AD2 and the third anode AD3; and each second spacer in the second spacer PS2 is located between the third anode AD3 and the fourth anode AD4. Optionally, each first spacer in the first spacer PS1 is located between the second sub-pixel opening SA2 and the third sub-pixel opening SA3; and each second spacer in the second spacer PS2 is located between the third sub-pixel opening SA3 and the fourth sub-pixel opening SA4. In one example, each first sub-pixel sp1 is a red sub-pixel, and the first anode AD1 is the anode of the red sub-pixel; each second sub-pixel sp2 is a first green sub-pixel, and the second anode AD2 is the anode of the first green sub-pixel; the third sub-pixel sp3 is a blue sub-pixel, and each third anode AD3 is the anode of the blue sub-pixel; each fourth sub-pixel sp4 is a second green sub-pixel, and the fourth anode AD4 is the anode of the second green sub-pixel. In another example, each of the first spacers in the first spacer PS1 is located between the second anode AD2 of the first green sub-pixel and the third anode AD3 of the blue sub-pixel; and each of the second spacers in the second spacer PS2 is located between the third anode AD3 of the blue sub-pixel and the fourth anode AD4 of the second green sub-pixel. In another example, each of the first spacers in the first spacer PS1 is located between the second sub-pixel opening SA2 of the first green sub-pixel and the third sub-pixel opening SA3 of the blue sub-pixel; and each of the second spacers in the second spacer PS2 is located between the third sub-pixel opening SA3 of the blue sub-pixel and the fourth sub-pixel opening SA4 of the second green sub-pixel.

[0108] In some embodiments, the average occupied area of ​​each of the first spacers in the first spacer PS1 is 10 μm. 2 Up to 500μm 2 Within the range, for example, 10μm 2 Up to 50μm 2 50μm 2 Up to 100μm 2 100μm 2 Up to 150μm 2 150μm 2 Up to 200μm 2 200μm 2 Up to 250μm 2 250μm 2 Up to 300μm 2 300μm 2 Up to 350μm 2 350μm 2 Up to 400μm 2 400μm 2 Up to 450μm 2or 450μm 2 Up to 500μm 2 Furthermore, the average area occupied by each of the second spacers in the second spacer PS2 is 10 μm. 2 Up to 500μm 2 Within the range, for example, 10μm 2 Up to 50μm 2 50μm 2 Up to 100μm 2 100μm 2 Up to 150μm 2 150μm 2 Up to 200μm 2 200μm 2 Up to 250μm 2 250μm 2 Up to 300μm 2 300μm 2 Up to 350μm 2 350μm 2 Up to 400μm 2 400μm 2 Up to 450μm 2 or 450μm 2 Up to 500μm 2 Optionally, the average area occupied by each of the first spacers in the first spacer PS1 is 80 μm. 2 Up to 120μm 2 Within the range, for example, 80μm 2 Up to 90μm 2 90μm 2 Up to 100μm 2 100μm 2 Up to 110μm 2 or 110μm 2 Up to 120μm 2 Furthermore, the average area occupied by each second spacer in the second spacer PS2 is 80 μm. 2 Up to 120μm 2 Within the range, for example, 80μm 2 Up to 90μm 2 90μm 2 Up to 100μm 2 100μm 2 Up to 110μm 2 or 110μm 2 Up to 120μm 2 Optionally, the average area occupied by each first spacer in the first spacer PS1 is 100 μm. 2Furthermore, the average area occupied by each second spacer in the second spacer PS2 is 100 μm. 2 Optionally, the average area occupied by each sub-pixel in the plurality of sub-pixels is 1400 μm. 2 Up to 2000μm 2 Within the range, for example, 1400μm 2 Up to 1500μm 2 1500μm 2 Up to 1600μm 2 1600μm 2 Up to 1700μm 2 1700μm 2 Up to 1800μm 2 1800μm 2 Up to 1900μm 2 Or 1900μm 2 Up to 2000μm 2 Optionally, the average area occupied by each sub-pixel in the plurality of sub-pixels is 1676μm. 2 Optionally, the percentage of the total occupied area of ​​the first spacer PS1 and the second spacer PS2 relative to the total occupied area of ​​the plurality of sub-pixels is in the range of 0.01% to 1%, for example, 0.01% to 0.05%, 0.05% to 0.1%, 0.1% to 0.15%, 0.15% to 0.20%, 0.20% to 0.25%, 0.25% to 0.30%, 0.30% to 0.35%, or 0.35%. The percentage of the total occupied area of ​​the first spacer PS1 and the second spacer PS2 relative to the total occupied area of ​​the plurality of sub-pixels is in the range of 0.15% to 0.35%, for example, 0.15% to 0.20%, 0.20% to 0.25%, 0.25% to 0.30%, or 0.30% to 0.35%. Alternatively, the percentage of the total occupied area of ​​the first spacer PS1 and the second spacer PS2 relative to the total occupied area of ​​the plurality of sub-pixels is in the range of 0.15% to 0.35%, for example, 0.15% to 0.20%, 0.20% to 0.25%, 0.25% to 0.30%, or 0.30% to 0.35%. Optionally, the percentage of the total occupied area of ​​the first spacer PS1 and the second spacer PS2 relative to the total occupied area of ​​the plurality of sub-pixels is 0.25%.

[0109] The inventors of this disclosure have discovered, unexpectedly and surprisingly, that the arrangement and distribution of spacers in this array substrate can effectively reduce or prevent contamination by spacer residues during the deposition of luminescent materials, while still effectively preventing damage to the pixel driving circuitry. Furthermore, the ratio of the number of sub-pixels to the number of spacers in a typical array substrate can be reduced from a typical value of, for example, 8:1, to a value equal to or greater than 20:1. Additionally, the percentage of the total area occupied by spacers relative to the total area occupied by multiple sub-pixels can be reduced from a typical value of, for example, 2%, to a value equal to or less than 0.35%.

[0110] refer to Figure 5A and Figure 5B In some embodiments, multiple sub-pixels sp are arranged in an array of multiple rows along a first direction DR1 and multiple columns along a second direction DR2. Each row has a first spacer PS1 along the first direction DR1. Each row has a second spacer PS2 along the first direction DR1. Each column has a first spacer PS1 along the second direction DR2. Each column has a second spacer PS2 along the second direction DR2.

[0111] refer to Figure 5A and Figure 5B In some embodiments, two adjacent first spacers in each row of first spacers are spaced apart by twice the first anode distance IAD1, which is the distance along the first direction DR1 and between the centers of the two most adjacent third anodes of the two most adjacent third light-emitting elements along the first direction DR1. Optionally, two adjacent second spacers in each row of second spacers are spaced apart by twice the first anode distance IAD1. In some embodiments, two adjacent first spacers in each column of first spacers are spaced apart by three times the second anode distance IAD2, which is the distance along the second direction DR2 and between the centers of the two most adjacent third anodes of the two most adjacent third light-emitting elements along the second direction DR2. Optionally, two adjacent second spacers in each column of second spacers are spaced apart by three times the second anode distance IAD2.

[0112] refer to Figure 5A and Figure 5B In some embodiments, the orthographic projection of each of the first spacers in the first spacers PS1 onto the substrate at least partially overlaps with the orthographic projection of the second anode AD2 onto the substrate. Optionally, the orthographic projection of each of the second spacers PS2 onto the substrate at least partially overlaps with the orthographic projection of the fourth anode AD4 onto the substrate.

[0113] refer to Figure 5A and Figure 5BIn some embodiments, a first virtual line along the first direction DR1 passes through a corresponding one and a fourth through hole V2-1 in the first spacer PS1. Optionally, a second virtual line VL2 along the first direction DR1 passes through a corresponding one and a tenth through hole V4-1 in the second spacer PS2.

[0114] Figure 6A The following illustration shows the use of a third photomask to form a third light-emitting layer in an array substrate according to some embodiments of the present disclosure. Figure 6B The following illustration shows the formation of a second light-emitting layer in an array substrate using a second photomask according to some embodiments of the present disclosure. Figure 6C The present disclosure illustrates the use of a fourth photomask to form a fourth light-emitting layer in an array substrate according to some embodiments thereof. Figure 6D The first light-emitting layer is formed in an array substrate using a first mask template according to some embodiments of the present disclosure. Figure 6E The diagram illustrates the relative positions of the boundaries of the openings of the first, second, third, and fourth photomasks relative to corresponding first spacers in the array substrate, according to some embodiments of the present disclosure. Reference Figures 6A to 6E After forming the spacers (first spacer PS1 and second spacer PS2), a mask (e.g., a pure metal mask) is placed on the spacers to deposit luminescent material on top of the anode. In one example, the first mask MK1 is used to form a first luminescent layer on the first anode AD1 of the first sub-pixel. Figure 6D The second mask MK2 is used to form a second light-emitting layer on the second anode AD2 of the second sub-pixel. Figure 6B The fourth mask MK4 is used to form the fourth light-emitting layer on the fourth anode AD2 of the fourth sub-pixel. Figure 6C The third mask MK3 is used to form the third light-emitting layer on the third anode AD3 of the third sub-pixel. Figure 6A ). Figure 6D and Figure 6E The first boundary of the opening BA1 of the first mask template MK1 is shown. Figure 6B and Figure 6E The second boundary of the opening BA2 of the second mask template MK2 is shown. Figure 6C and Figure 6E The fourth boundary of the opening BA4 of the fourth mask template MK4 is shown. Figure 6D and Figure 6E The third boundary of the opening BA3 of the third mask template MK3 is shown.

[0115] like Figure 6AAs shown, the orthographic projection of a portion of the third boundary of the opening BA3 of the third mask MK3 onto the substrate substantially overlaps with the orthographic projection of the first centerline ML1 of the corresponding first spacer PS1. The first centerline ML1 has a first tilt angle α relative to the first direction DR1. As used herein, the term "substantially overlaps" means that the two orthographic projections overlap each other by at least 50%, such as at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 99%, or 100%.

[0116] like Figure 6B As shown, the orthographic projection of a portion of the second boundary of the opening BA2 of the second mask MK2 onto the substrate substantially overlaps with the orthographic projection of the first centerline ML1 of the corresponding first spacer PS1. The first centerline ML1 has a first tilt angle α relative to the first direction DR1.

[0117] refer to Figure 6A , Figure 6B and Figure 6E In some embodiments, the orthographic projection of a portion of the third boundary of the opening BA3 of the third mask MK3 onto the substrate substantially overlaps with the orthographic projection of the first centerline ML1 of the corresponding first spacer PS1, and the orthographic projection of a portion of the second boundary of the opening BA2 of the second mask MK2 onto the substrate substantially overlaps with the orthographic projection of the first centerline ML1 of the corresponding first spacer PS1. The first centerline ML1 has a first tilt angle α relative to the first direction DR1. Optionally, the first tilt angle α is in the range of 40 degrees to 80 degrees, for example, 40 degrees to 50 degrees, 50 degrees to 60 degrees, 60 degrees to 70 degrees, or 70 degrees to 80 degrees. Optionally, the first tilt angle α is 60 degrees.

[0118] Figure 6F The relative positions of the light-emitting layers with respect to corresponding first spacers in the array substrate are shown in some embodiments according to this disclosure. Reference Figure 6FIn some embodiments, the array substrate further includes a first light-emitting layer EM1 located on the side of the first anode AD1 away from the substrate; a second light-emitting layer EM2 located on the side of the second anode AD2 away from the substrate; a third light-emitting layer EM3 located on the side of the third anode AD3 away from the substrate; and a fourth light-emitting layer EM4 located on the side of the fourth anode AD4 away from the substrate. In one example, the first sub-pixel is a red sub-pixel, the first anode AD1 is the anode of the red sub-pixel, and the first light-emitting layer EM1 is a red light-emitting layer; the second sub-pixel is a first green sub-pixel, the second anode AD2 is the anode of the first green sub-pixel, and the second light-emitting layer EM2 is a green light-emitting layer; the third sub-pixel is a blue sub-pixel, the third anode AD3 is the anode of the blue sub-pixel, and the third light-emitting layer EM3 is a blue light-emitting layer; the fourth sub-pixel is a second green sub-pixel, the fourth anode AD4 is the anode of the second green sub-pixel, and the fourth light-emitting layer EM4 is also a green light-emitting layer.

[0119] Figure 6G It revolves around Figure 6F An enlarged view of the area corresponding to the first spacer. (Reference) Figure 6F and Figure 6G In some embodiments, the orthographic projection of the third light-emitting layer EM3 onto the substrate partially overlaps with the orthographic projection of the corresponding first spacer PS1 onto the substrate; the orthographic projection of the second light-emitting layer EM2 onto the substrate partially overlaps with the orthographic projection of the corresponding first spacer PS1 onto the substrate. The first edge E1 of the third light-emitting layer EM3 passing through the corresponding first spacer PS1 is substantially parallel to the first centerline ML1 of the corresponding first spacer PS1; and the second edge E2 of the second light-emitting layer EM2 passing through the corresponding first spacer PS1 is substantially parallel to the first centerline ML1 of the corresponding first spacer PS1. As used herein, the term "substantially parallel" means that the angle between the two lines is in the range of 0 degrees to about 15 degrees, for example, 0 degrees to about 5 degrees, 5 degrees to about 10 degrees, or 10 degrees to about 15 degrees.

[0120] Optionally, the first edge E1 is spaced from the first center line ML1 by a first distance d1 along a direction perpendicular to the first center line ML1; and the second edge E2 is spaced from the first center line ML1 by a second distance d2 along a direction perpendicular to the first center line ML1. Optionally, the average value of the first distance d1 along the first edge E1 is substantially the same as the average value of the second distance d2 along the second edge E2. As used herein, the term "substantially the same" means that the difference between the two values ​​does not exceed 10% of a base value (e.g., one of the two values), such as not exceeding 8%, 6%, 4%, 2%, 1%, 0.5%, 0.1%, 0.05%, and 0.01% of the base value. Optionally, the first edge E1 substantially overlaps with the first center line ML1. Optionally, the second edge E2 substantially overlaps with the first center line ML1.

[0121] Figure 6H It is along Figure 6F A cross-sectional view of the L-L' line in the diagram. (Refer to...) Figure 6H In some embodiments, the display panel includes a substrate BS (e.g., a flexible substrate) in the display area; and a semiconductor material layer SML on the substrate BS (see also...). Figure 3C ); Gate insulating layer GI, located on the side of semiconductor material layer SML away from the substrate BS; insulating layer IN, located on the side of gate insulating layer GI away from the substrate BS; interlayer dielectric layer ILD, located on the side of insulating layer IN away from the gate insulating layer GI; relay electrode layer (e.g., such as Figure 6H The corresponding second relay electrode RE2 and the corresponding third relay electrode RE3 shown are located on the side of the interlayer dielectric layer ILD away from the insulating layer IN; the first planarization layer PLN1 is located on the side of the relay electrode layer away from the interlayer dielectric layer ILD; the anode contact pad layer (e.g., as shown) Figure 6H The corresponding second anode contact pad ACP2 and the corresponding third anode contact pad ACP3 shown are located on the side of the first planarization layer PLN1 away from the interlayer dielectric layer ILD; the second planarization layer PLN2 is located on the side of the anode contact pad layer away from the first planarization layer PLN1; the pixel defining layer PDL defines the sub-pixel opening and is located on the side of the second planarization layer PLN2 away from the substrate BS; the spacer layer (e.g., such as...) Figure 6H The corresponding one of the first spacers PS1 shown is located on the side of the pixel-defining layer PDL away from the second planarization layer PLN2; the anode layer (e.g., as shown) Figure 6HThe second anode (AD2 and the third anode (AD3) shown in the diagram are located on the side of the second planarization layer PLN2 away from the first planarization layer PLN1; and the light-emitting layer (e.g., the second light-emitting layer EM2 and the third light-emitting layer EM3) is located on the side of the anode layer away from the second planarization layer PLN2; and the cathode layer CD is located on the side of the light-emitting layer away from the anode layer.

[0122] Figure 6I The illustration shows the formation of a second and a fourth light-emitting layer in an array substrate using the same photomask according to some embodiments of the present disclosure. Reference Figure 6I In one example, the same mask MK24 is used to form a second emissive layer on the second anode AD2 of the second sub-pixel, and a fourth emissive layer is formed on the fourth anode AD4 of the fourth sub-pixel. Figure 6B ). Figure 6I The second boundary of opening BA2 of the same mask MK24 and the fourth boundary of opening BA4 of the same mask MK24 are shown.

[0123] Figure 7A The following illustration shows the use of a third photomask to form a third light-emitting layer in an array substrate according to some embodiments of the present disclosure. Figure 7B The following illustration shows the formation of a second light-emitting layer in an array substrate using a second photomask according to some embodiments of the present disclosure. Figure 7C The present disclosure illustrates the use of a fourth photomask to form a fourth light-emitting layer in an array substrate according to some embodiments thereof. Figure 7D The first light-emitting layer is formed in an array substrate using a first mask template according to some embodiments of the present disclosure. Figure 7E The diagram illustrates the relative positions of the boundaries of the openings of the first, second, third, and fourth photomasks relative to corresponding second spacers in the array substrate, according to some embodiments of the present disclosure. Reference Figures 7A to 7E After forming the spacers (first spacer PS1 and second spacer PS2), a mask (e.g., a pure metal mask) is placed on the spacers to deposit luminescent material on top of the anode. In one example, the first mask MK1 is used to form a first luminescent layer on the first anode AD1 of the first sub-pixel. Figure 7D The second mask MK2 is used to form a second light-emitting layer on the second anode AD2 of the second sub-pixel. Figure 7B The third mask MK3 is used to form the third light-emitting layer on the third anode AD3 of the third sub-pixel. Figure 7A ), and the fourth mask MK4 is used to form the fourth light-emitting layer on the fourth anode AD4 of the fourth sub-pixel ( Figure 7C ). Figure 7D and Figure 7E The first boundary of the opening BA1 of the first mask template MK1 is shown. Figure 7B and Figure 7E The second boundary of the opening BA2 of the second mask template MK2 is shown. Figure 7C and Figure 7E The fourth boundary of the opening BA4 of the fourth mask template MK4 is shown. Figure 7D and Figure 7E The third boundary of the opening BA3 of the third mask template MK3 is shown.

[0124] like Figure 7A As shown, the orthographic projection of a portion of the third boundary of the opening BA3 of the third mask MK3 onto the substrate substantially overlaps with the orthographic projection of the second centerline ML2 of the corresponding second spacer PS2. The second centerline ML2 has a second tilt angle β relative to the first direction DR1.

[0125] like Figure 7C As shown, the orthographic projection of a portion of the fourth boundary of the opening BA4 of the fourth mask MK4 onto the substrate substantially overlaps with the orthographic projection of the second centerline ML2 of the corresponding second spacer PS2. The second centerline ML2 has a second tilt angle β relative to the first direction DR1.

[0126] refer to Figure 7A , Figure 7B and Figure 7E In some embodiments, the orthographic projection of a portion of the third boundary of the opening BA3 of the third mask MK3 onto the substrate substantially overlaps with the orthographic projection of the second centerline ML2 of the corresponding second spacer PS2, and the orthographic projection of a portion of the fourth boundary of the opening BA4 of the fourth mask MK4 onto the substrate substantially overlaps with the orthographic projection of the second centerline ML2 of the corresponding second spacer PS2. The second centerline ML2 has a second tilt angle β relative to the first direction DR1. Optionally, the second tilt angle β is in the range of 10 degrees to 50 degrees, for example, 10 degrees to 20 degrees, 20 degrees to 30 degrees, 30 degrees to 40 degrees, or 40 degrees to 50 degrees. Optionally, the second tilt angle β is 30 degrees.

[0127] Figure 7F The relative positions of the light-emitting layers with respect to corresponding second spacers in the array substrate are shown in some embodiments according to this disclosure. Reference Figure 7FIn some embodiments, the array substrate further includes a first light-emitting layer EM1 located on the side of the first anode AD1 away from the substrate; a second light-emitting layer EM2 located on the side of the second anode AD2 away from the substrate; a third light-emitting layer EM3 located on the side of the third anode AD3 away from the substrate; and a fourth light-emitting layer EM4 located on the side of the fourth anode AD4 away from the substrate. In one example, the first sub-pixel is a red sub-pixel, the first anode AD1 is the anode of the red sub-pixel, and the first light-emitting layer EM1 is a red light-emitting layer; the second sub-pixel is a first green sub-pixel, the second anode AD2 is the anode of the first green sub-pixel, and the second light-emitting layer EM2 is a green light-emitting layer; the third sub-pixel is a blue sub-pixel, the third anode AD3 is the anode of the blue sub-pixel, and the third light-emitting layer EM3 is a blue light-emitting layer; the fourth sub-pixel is a second green sub-pixel, the fourth anode AD4 is the anode of the second green sub-pixel, and the fourth light-emitting layer EM4 is also a green light-emitting layer.

[0128] Figure 7G It revolves around Figure 7F An enlarged view of the area corresponding to the second spacer. (Reference) Figure 7F and Figure 7G In some embodiments, the orthographic projection of the third light-emitting layer EM3 onto the substrate partially overlaps with the orthographic projection of the corresponding second spacer PS2 onto the substrate; the orthographic projection of the fourth light-emitting layer EM4 onto the substrate partially overlaps with the orthographic projection of the corresponding second spacer PS2 onto the substrate. The third edge E3 of the third light-emitting layer EM3 passing through the corresponding second spacer PS2 is substantially parallel to the second centerline ML2 of the corresponding second spacer PS2; and the fourth edge E4 of the fourth light-emitting layer EM4 passing through the corresponding second spacer PS2 is substantially parallel to the second centerline ML2 of the corresponding second spacer PS2.

[0129] Optionally, the third edge E3 is spaced from the second center line ML2 by a third distance d3 along a direction perpendicular to the second center line ML2; the fourth edge E4 is spaced from the second center line ML2 by a fourth distance d4 along a direction perpendicular to the second center line ML2. Optionally, the average value of the third distance d3 along the third edge E3 is substantially the same as the average value of the fourth distance d4 along the fourth edge E4. Optionally, the third edge E3 substantially overlaps with the second center line ML2. Optionally, the fourth edge E4 substantially overlaps with the second center line ML2.

[0130] Figure 7H This illustration shows how, in some embodiments according to this disclosure, a second and a fourth light-emitting layer are formed in an array substrate using the same photomask. (Refer to...) Figure 7HIn one example, the same mask MK24 is used to form a second light-emitting layer on the second anode AD2 of the second sub-pixel and a fourth light-emitting layer on the fourth anode AD4 of the fourth sub-pixel. Figure 7H The second boundary of opening BA2 of the same mask MK24 and the fourth boundary of opening BA4 of the same mask MK24 are shown.

[0131] In some embodiments, the orthographic projection of each anode in each sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the first node in each sub-pixel onto the substrate. (Refer to...) Figure 2A , Figures 3A to 3H as well as Figure 4A In some embodiments, the orthographic projection of the first anode AD1 in each first sub-pixel sp1 onto the substrate BS at least partially overlaps with the orthographic projection of the node connection line Cln in each first sub-pixel sp1 onto the substrate BS; the orthographic projection of the second anode AD2 in each second sub-pixel sp2 onto the substrate BS at least partially overlaps with the orthographic projection of the node connection line Cln in each second sub-pixel sp2 onto the substrate BS; the orthographic projection of the third anode AD3 in each third sub-pixel sp3 onto the substrate BS at least partially overlaps with the orthographic projection of the node connection line Cln in each third sub-pixel sp3 onto the substrate BS; and the orthographic projection of the fourth anode AD4 in each fourth sub-pixel sp4 onto the substrate BS at least partially overlaps with the orthographic projection of the node connection line Cln in each fourth sub-pixel sp4 onto the substrate BS.

[0132] Optionally, the orthographic projection of the first anode AD1 in each first sub-pixel sp1 onto the substrate BS at least partially overlaps with the orthographic projection of the first capacitor electrode Ce1 in each first sub-pixel sp1 onto the substrate BS; the orthographic projection of the second anode AD2 in each second sub-pixel sp2 onto the substrate BS at least partially overlaps with the orthographic projection of the first capacitor electrode Ce1 in each second sub-pixel sp2 onto the substrate BS; the orthographic projection of the third anode AD3 in each third sub-pixel sp3 onto the substrate BS at least partially overlaps with the orthographic projection of the first capacitor electrode Ce1 in each third sub-pixel sp3 onto the substrate BS; and the orthographic projection of the fourth anode AD4 in each fourth sub-pixel sp4 onto the substrate BS at least partially overlaps with the orthographic projection of the first capacitor electrode Ce1 in each fourth sub-pixel sp4 onto the substrate BS.

[0133] Optionally, the orthographic projection of the first anode AD1 in each first sub-pixel sp1 onto the substrate BS at least partially overlaps with the orthographic projection of the second capacitor electrode Ce2 in each first sub-pixel sp1 onto the substrate BS; the orthographic projection of the second anode AD2 in each second sub-pixel sp2 onto the substrate BS at least partially overlaps with the orthographic projection of the second capacitor electrode Ce2 in each second sub-pixel sp2 onto the substrate BS; the orthographic projection of the third anode AD3 in each third sub-pixel sp3 onto the substrate BS at least partially overlaps with the orthographic projection of the second capacitor electrode Ce2 in each third sub-pixel sp3 onto the substrate BS; and the orthographic projection of the fourth anode AD4 in each fourth sub-pixel sp4 onto the substrate BS at least partially overlaps with the orthographic projection of the second capacitor electrode Ce2 in each fourth sub-pixel sp4 onto the substrate BS.

[0134] Optionally, the orthographic projection of the first anode AD1 in each first sub-pixel sp1 onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACTd of the driving transistor Td in each first sub-pixel sp1 onto the substrate BS; the orthographic projection of the second anode AD2 in each second sub-pixel sp2 onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACTd of the driving transistor Td in each second sub-pixel sp2 onto the substrate BS; the orthographic projection of the third anode AD3 in each third sub-pixel sp3 onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACTd of the driving transistor Td in each third sub-pixel sp3 onto the substrate BS; and the orthographic projection of the fourth anode AD4 in each fourth sub-pixel sp4 onto the substrate BS at least partially overlaps with the orthographic projection of the active layer ACTd of the driving transistor Td in each fourth sub-pixel sp4 onto the substrate BS.

[0135] Optionally, the orthographic projection of the first anode AD1 in each first sub-pixel sp1 onto the substrate BS covers the orthographic projection of a portion of the node connection line Cln in each first sub-pixel sp1 at the position connected to the first capacitor electrode Ce1 onto the substrate BS; the orthographic projection of the second anode AD2 in each second sub-pixel sp2 onto the substrate BS covers the orthographic projection of a portion of the node connection line Cln in each second sub-pixel sp2 at the position connected to the first capacitor electrode Ce1 onto the substrate BS; the orthographic projection of the third anode AD3 in each third sub-pixel sp3 onto the substrate BS covers the orthographic projection of a portion of the node connection line Cln in each third sub-pixel sp3 at the position connected to the first capacitor electrode Ce1 onto the substrate BS; and the orthographic projection of the fourth anode AD4 in each fourth sub-pixel sp4 onto the substrate BS covers the orthographic projection of a portion of the node connection line Cln in each fourth sub-pixel sp4 at the position connected to the first capacitor electrode Ce1 onto the substrate BS.

[0136] In this array substrate, the orthographic projection of the anodes at least partially overlaps with the nodes of the pixel driving circuits, and the loads between the anodes in each sub-pixel and between the pixel driving circuits can remain consistent with each other, thereby improving the uniformity of image display.

[0137] Figure 8A This is a diagram illustrating the anode, first signal line layer, and semiconductor material layer in an array substrate according to some embodiments of the present disclosure. Figure 8B It is along Figure 8A A cross-sectional view of line E-E' in the diagram. (Reference) Figure 8A and Figure 8B In some embodiments, the orthographic projection of the third anode AD3 on the substrate BS at least partially overlaps with the orthographic projection of the third transistor in the corresponding third sub-pixel on the substrate BS, and at least partially overlaps with the orthographic projection of the third transistor in the corresponding fourth sub-pixel adjacent to the corresponding third sub-pixel on the substrate BS. Optionally, the orthographic projection of the third anode AD3 on the substrate BS covers the orthographic projection of the source S3 of the third transistor in the corresponding third sub-pixel on the substrate BS, partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor in the corresponding third sub-pixel on the substrate BS, and partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor in the corresponding fourth sub-pixel on the substrate BS.

[0138] Figure 8C It is along Figure 8A A cross-sectional view of line F-F' in the diagram. (Reference) Figure 8A and Figure 8CIn some embodiments, the orthographic projection of the first anode AD1 on the substrate BS at least partially overlaps with the orthographic projection of the third transistor in the corresponding first sub-pixel on the substrate BS. Optionally, the orthographic projection of the first anode AD1 on the substrate BS partially overlaps with the orthographic projection of the source S3 of the third transistor in the corresponding first sub-pixel on the substrate BS, and also partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor in the corresponding first sub-pixel on the substrate BS.

[0139] In this array substrate, the orthographic projection of the anodes at least partially overlaps with the active layer of the third transistor. Because the anodes are typically made of reflective materials, they can prevent ultraviolet radiation from hitting the active layer, thereby protecting the transistor.

[0140] Figure 8D It is along Figure 8A A cross-sectional view of line G-G' in the diagram. (Refer to...) Figure 8A and Figure 8D In some embodiments, the orthographic projection of the fourth anode AD4 onto the substrate BS at least partially overlaps with the orthographic projection of the third transistor in the corresponding second sub-pixel onto the substrate BS. Optionally, the orthographic projection of the fourth anode AD4 onto the substrate BS partially overlaps with the orthographic projection of the source S3 of the third transistor in the corresponding second sub-pixel onto the substrate BS, and also partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor in the corresponding second sub-pixel onto the substrate BS.

[0141] refer to Figure 8AIn a counter-clockwise direction, each third anode RAD3 is adjacent to the first corresponding fourth anode RAD4-1, the first corresponding first anode RAD1-1, the first corresponding second anode RAD2-1, the second corresponding first anode RAD1-2, the second corresponding fourth anode RAD4-2, the second corresponding second anode RAD2-2, and the third corresponding first anode RAD1-3, respectively. Optionally, in a clockwise direction, each third anode RAD3 is adjacent to the first corresponding fourth anode RAD4-1, the first corresponding first anode RAD1-1, the first corresponding second anode RAD2-1, the second corresponding first anode RAD1-2, the second corresponding fourth anode RAD4-2, the second corresponding second anode RAD2-2, and the third corresponding first anode RAD1-3, respectively. Optionally, the shortest distance between each third anode RAD3 and any one of the first corresponding fourth anode RAD4-1, the first corresponding first anode RAD1-1, the first corresponding second anode RAD2-1, the second corresponding first anode RAD1-2, the virtual line VL, or the third corresponding first anode RAD1-3 is 2.Within the range of 0 μm to 22 μm, the virtual line VL passes through the collinear edges of the second corresponding fourth anode RAD4-2 and the second corresponding second anode RAD2-2, respectively. Optionally, the shortest distance between each third anode RAD3 and the first corresponding fourth anode RAD4-1 is less than the shortest distance between each third anode RAD3 and the third corresponding first anode RAD1-3, less than the shortest distance between each third anode RAD3 and the first corresponding first anode RAD1-1, less than the shortest distance between each third anode RAD3 and the second corresponding first anode RAD1-2, less than the shortest distance between each third anode RAD3 and the virtual line passing through the collinear edges of the second corresponding fourth anode RAD4-2 and the second corresponding second anode RAD2-2, and less than the shortest distance between each third anode RAD3 and the first corresponding second anode RAD2-1. Optionally, the shortest distance between each third anode RAD3 and the third corresponding first anode RAD1-3 is greater than the shortest distance between each third anode RAD3 and the first corresponding first anode RAD1-1, the shortest distance between each third anode RAD3 and the first corresponding first anode RAD1-1 is greater than the shortest distance between each third anode RAD3 and the second corresponding first anode RAD1-2, the shortest distance between each third anode RAD3 and the second corresponding first anode RAD1-2 is greater than the shortest distance between each third anode RAD3 and the virtual line passing through the collinear edges from the second corresponding fourth anode RAD4-2 and the second corresponding second anode RAD2-2 respectively, the shortest distance between each third anode RAD3 and the virtual line is greater than the shortest distance between each third anode RAD3 and the first corresponding second anode RAD2-1, and the shortest distance between each third anode RAD3 and the first corresponding second anode RAD2-1 is greater than the shortest distance between each third anode RAD3 and the first corresponding fourth anode RAD4-1. Optionally, the shortest distance b1 between each third anode RAD3 and the first corresponding fourth anode RAD4-1 is in the range of 2.0 μm to 5.0 μm (e.g., 2.0 μm to 2.5 μm, 2.5 μm to 3.0 μm, 3.0 μm to 3.5 μm, 3.5 μm to 4.0 μm, 4.0 μm to 4.5 μm, 4.5 μm to 5.0 μm, or optionally 4.0 μm); ... The shortest distance b2 between the first anodes RAD1-1 is in the range of 8.0 μm to 20.0 μm (e.g., 8.0 μm to 9.0 μm, 9.0 μm to 10.0 μm, 10.0 μm to 11.0 μm, 11.0 μm to 12.0 μm, 12.0 μm to 13.0 μm, 13.0 μm to 14.0 μm, 14.0 μm to 15.0 μm, 15.0 μm to 16.0 μm, 16.0 μm to 17.0 μm).0 μm, 17.0 μm to 18.0 μm, 18.0 μm to 19.0 μm, 19.0 μm to 20.0 μm, or optionally 13.7 μm); the shortest distance b3 between each third anode RAD3 and the first corresponding second anode RAD2-1 is in the range of 5.0 μm to 15.0 μm (e.g., 5.0 μm to 6.0 μm, 6.0 μm to 7.0 μm, 7.0 μm to 8.0 μm, 8.0 μm to 9.0 μm, 9.0 μm to 10.0 μm, 10.0 μm to 11.0 μm, 11.0 μm to 12.0 μm, 12.0 μm to 13.0 μm, 13.0 μm to 14.0 μm, 14.0 μm to 15.0 μm). 15.0 μm, or optionally 9.5 μm); the shortest distance b4 between each third anode RAD3 and the second corresponding first anode RAD1-2 is in the range of 7.0 μm to 17.0 μm (e.g., 7.0 μm to 8.0 μm, 8.0 μm to 9.0 μm, 9.0 μm to 10.0 μm, 10.0 μm to 11.0 μm, 11.0 μm to 12.0 μm, 12.0 μm to 13.0 μm, 13.0 μm to 14.0 μm, 14.0 μm to 15.0 μm, 15.0 μm to 16.0 μm, 16.0 μm to 17.0 μm, or optionally 9.5 μm); each third anode RAD3 and passing through respectively from The shortest distance b5 between the virtual lines of the collinear edges of the second corresponding fourth anode RAD4-2 and the second corresponding second anode RAD2-2 is in the range of 5.0 μm to 16.0 μm (e.g., 5.0 μm to 6.0 μm, 6.0 μm to 7.0 μm, 7.0 μm to 8.0 μm, 8.0 μm to 9.0 μm, 9.0 μm to 10.0 μm, 10.0 μm to 11.0 μm, 11.0 μm to 12.0 μm, 12.0 μm to 13.0 μm, 13.0 μm to 14.0 μm, 14.0 μm to 15.0 μm, 15.0 μm to 16.0 μm, or optionally 10.0 μm); and each third anode RAD3 The shortest distance b6 between the first anode RAD1-3 and the third corresponding anode is in the range of 9.0 μm to 22.0 μm (e.g., 9.0 μm to 10.0 μm, 10.0 μm to 11.0 μm, 11.0 μm to 12.0 μm, 12.0 μm to 13.0 μm, 13.0 μm to 14.0 μm, 14.0 μm to 15.0 μm, 15.0 μm to 16.0 μm, 16.0 μm to 17.0 μm, 17.0 μm to 18.0 μm, 18.0 μm to 19.0 μm, 19.0 μm to 20.0 μm, 20.0 μm to 21.0 μm, 21.0 μm to 22.0 μm, or optionally 14.8 μm).

[0142] Figure 8EThis is a diagram illustrating the anode, first signal line layer, and semiconductor material layer in an array substrate according to some embodiments of the present disclosure. (See reference...) Figure 8EIn a counter-clockwise direction, each first anode RAD1 is adjacent to the first corresponding second anode RAD2-1, the first corresponding fourth anode RAD4-1, the first corresponding third anode RAD3-1, the second corresponding second anode RAD2-2, the second corresponding third anode RAD3-2, the second corresponding fourth anode RAD4-2, and the third corresponding third anode RAD3-3, respectively. Optionally, in a clockwise direction, each first anode RAD1 is adjacent to the first corresponding second anode RAD2-1, the first corresponding fourth anode RAD4-1, the first corresponding third anode RAD3-1, the second corresponding second anode RAD2-2, the second corresponding third anode RAD3-2, the second corresponding fourth anode RAD4-2, and the third corresponding third anode RAD3-3, respectively. Optionally, the shortest distance between each of the first anode RAD1 and any one of the first corresponding second anode RAD2-1, the first corresponding fourth anode RAD4-1, the first corresponding third anode RAD3-1, the second corresponding second anode RAD2-2, the second corresponding third anode RAD3-2, the second corresponding fourth anode RAD4-2, or the third corresponding third anode RAD3-3 is 3.Within the range of 0 μm to 25 μm. Optionally, the shortest distance between each first anode RAD1 and the second corresponding fourth anode RAD4-2 is less than the shortest distance between each first anode RAD1 and the second corresponding second anode RAD2-2, less than the shortest distance between each first anode RAD1 and the first corresponding fourth anode RAD4-1, less than the shortest distance between each first anode RAD1 and the first corresponding third anode RAD3-1, less than the shortest distance between each first anode RAD1 and the second corresponding third anode RAD3-2, less than the shortest distance between each first anode RAD1 and the third corresponding third anode RAD3-3, and less than the shortest distance between each first anode RAD1 and the first corresponding second anode RAD2-1. Optionally, the shortest distance between each first anode RAD1 and the second corresponding second anode RAD2-2 is greater than the shortest distance between each first anode RAD1 and the first corresponding fourth anode RAD4-1, the shortest distance between each first anode RAD1 and the first corresponding fourth anode RAD4-1 is greater than the shortest distance between each first anode RAD1 and the first corresponding third anode RAD3-1, and the shortest distance between each first anode RAD1 and the first corresponding third anode RAD3-1 is greater than the shortest distance between each first anode RAD1 and the second corresponding third anode RAD3-2. The shortest distance between each first anode RAD1 and the second corresponding third anode RAD3-2 is greater than the shortest distance between each first anode RAD1 and the third corresponding third anode RAD3-3, the shortest distance between each first anode RAD1 and the third corresponding third anode RAD3-3 is greater than the shortest distance between each first anode RAD1 and the first corresponding second anode RAD2-1, and the shortest distance between each first anode RAD1 and the first corresponding second anode RAD2-1 is greater than the shortest distance between each first anode RAD1 and the second corresponding fourth anode RAD4-2. Optionally, the shortest distance r1 between each first anode RAD1 and the first corresponding second anode RAD2-1 is in the range of 3.0 μm to 14.0 μm (e.g., 3.0 μm to 4.0 μm, 4.0 μm to 5.0 μm, 5.0 μm to 6.0 μm, 6.0 μm to 7.0 μm, 7.0 μm to 8.0 μm, 8.0 μm to 9.0 μm, 9.0 μm to 10.0 μm, 10.0 μm to...). The shortest distance r2 between each first anode RAD1 and the first corresponding fourth anode RAD4-1 is in the range of 10.0 μm to 24.0 μm (e.g., 10.0 μm to 10.5 μm, 10.5 μm to 11.5 μm, 11.5 μm to 12.0 μm, 12.0 μm to 13.0 μm, 13 μm to 14.0 μm, or optionally 7.85 μm); the shortest distance r2 between each first anode RAD1 and the first corresponding fourth anode RAD4-1 is in the range of 10.0 μm to 24.0 μm (e.g., 10.0 μm to 10.5 μm, 10.5 μm to 11.5 μm, 11.5 μm to 12.0 μm).5 μm, 12.5 μm to 13.5 μm, 13.5 μm to 14.5 μm, 14.5 μm to 15.5 μm, 15.5 μm to 16.5 μm, 16.5 μm to 17.5 μm, 17.5 μm to 18.5 μm, 18.5 μm to 19.5 μm, 19.5 μm to 20.5 μm, 20.5 μm to 21.5 μm, 21.5 μm to 22.5 μm, 22.5 μm to 23.5 μm, 23.5 μm to 24 μm, or optionally 16.6 μm); the shortest distance r3 (same as b6) between each first anode RAD1 and the first corresponding third anode RAD3-1 is in the range of 9.0 μm to 21.0 μm (e.g., 9.0 μm). μm to 10.0μm, 10.0μm to 11.0μm, 11.0μm to 12.0μm, 12.0μm to 13.0μm, 13.0μm to 14.0μm, 14.0μm to 15.0μm, 15.0μm to 16.0μm, 16.0μm to 17.0μm, 17.0μm to 18.0μm, 18.0μm to 19.0μm, 19.0μm to 20.0μm, 20.0μm to 21.0μm, or optionally 14.8μm); the shortest distance r4 between each first anode RAD1 and the second corresponding second anode RAD2-2 is in the range of 11.0μm to 25.0μm (e.g., 11.0μm to 12.0μm, 1 2.0 μm to 13.0 μm, 13.0 μm to 14.0 μm, 14.0 μm to 15.0 μm, 15.0 μm to 16.0 μm, 16.0 μm to 17.0 μm, 17.0 μm to 18.0 μm, 18.0 μm to 19.0 μm, 19.0 μm to 20.0 μm, 20.0 μm to 21.0 μm, 21.0 μm to 22.0 μm, 22.0 μm to 23.0 μm, 23.0 μm to 24.0 μm, 24.0 μm to 25.0 μm, or optionally 18.2 μm); the shortest distance r5 (same as b2) between each first anode RAD1 and the second corresponding third anode RAD3-2 is 8.0 μm to 20.0 μm. Within the range (e.g., 8.0 μm to 9.0 μm, 9.0 μm to 10.0 μm, 10.0 μm to 11.0 μm, 11.0 μm to 12.0 μm, 12.0 μm to 13.0 μm, 13.0 μm to 14.0 μm, 14.0 μm to 15.0 μm, 15.0 μm to 16.0 μm, 16.0 μm to 17.0 μm, 17.0 μm to 18.0 μm, 18.0 μm to 19.0 μm, 19.0 μm to 20.0 μm, or optionally 13.7 μm); the shortest distance r6 between each first anode RAD1 and the second corresponding fourth anode RAD4-2 is in the range of 2.5 μm to 7.5 μm (e.g., 2.5 μm to 3.5 μm).The shortest distance r7 (same as b4) between each first anode RAD1 and the corresponding third anode RAD3-3 is in the range of 7.0 μm to 16.0 μm (e.g., 7.0 μm to 8.0 μm, 8.0 μm to 9.0 μm, 9.0 μm to 10.0 μm, 10.0 μm to 11.0 μm, 11.0 μm to 12.0 μm, 12.0 μm to 13.0 μm, 13.0 μm to 14.0 μm, 14.0 μm to 15.0 μm, 15.0 μm to 16.0 μm, or optionally 9.5 μm).

[0143] Figure 8F This is a diagram illustrating the anode, first signal line layer, and semiconductor material layer in an array substrate according to some embodiments of the present disclosure. (See reference...) Figure 8FIn a counter-clockwise direction, each fourth anode RAD4 is adjacent to the corresponding second anode RAD2, the first corresponding third anode RAD3-1, the first corresponding first anode RAD1-1, the second corresponding third anode RAD3-2, and the second corresponding first anode RAD1-2, respectively. Optionally, in a clockwise direction, each fourth anode RAD4 is adjacent to the corresponding second anode RAD2, the first corresponding third anode RAD3-1, the first corresponding first anode RAD1-1, the second corresponding third anode RAD3-2, and the second corresponding first anode RAD1-2, respectively. Optionally, the shortest distance between each fourth anode RAD4 and any one of the first corresponding first anode RAD1-1, the second corresponding third anode RAD3-2, or the second corresponding first anode RAD1-2 is in the range of 2.0 μm to 25.0 μm. Optionally, the shortest distance between each fourth anode RAD4 and the second corresponding first anode RAD1-2 is greater than the shortest distance between each fourth anode RAD4 and the first corresponding first anode RAD1-1, and is also greater than the shortest distance between each fourth anode RAD4 and the second corresponding third anode RAD3-2. Optionally, the distance g1 between each fourth anode RAD4 and the corresponding second anode RAD2, and along a virtual line VL passing through the collinear edges of each fourth anode RAD4 and the corresponding second anode RAD2, is in the range of 10.0 μm to 25.0 μm (e.g., 10.0 μm to 10.5 μm, 10.5 μm to 11.5 μm, 11.5 μm to 12.5 μm, 12.5 μm to 13.5 μm, 13.5 μm to 14.5 μm, 14.5 μm to 15.5 μm, 15.5 μm to 16.5 μm, 16.5 μm to 17.5 μm, 17.5 μm to 18.5 μm, 18.5 μm to 19.5 μm, 19.5 μm to 20.5 μm, 20.5 μm to 21.5 μm, 21.5 μm to 22. 0.5μm, 22.5μm to 23.5μm, 23.5μm to 24.5μm, 24.5μm to 25.0μm or optionally 16.3μm); the shortest distance g3 (same as b5) between the first corresponding third anode RAD3-1 and the virtual line VL passing through the collinear edges from the respective fourth anode RAD4 and the corresponding second anode RAD2 is 6.0μm to 15.0 μm (e.g., 6.0 μm to 7.0 μm, 7.0 μm to 8.0 μm, 8.0 μm to 9.0 μm, 9.0 μm to 10.0 μm, 10.0 μm to 11.0 μm, 11.0 μm to 12.0 μm, 12.0 μm to 13.0 μm, 13.0 μm to 14.0 μm, 14.0 μm to 15.0 μm, or optionally 10 μm).Within the range of 0 μm; the shortest distance g4 between the protrusion PP of the first corresponding first anode RAD1-1 closest to each of the fourth anodes and the virtual line VL passing through the collinear edges from each of the fourth anodes RAD4 and the corresponding second anode RAD2 is in the range of 5.0 μm to 16.0 μm (e.g., 5.0 μm to 6.0 μm, 6.0 μm to 7.0 μm, 7.0 μm to 8.0 μm, 8.0 μm to 9.0 μm, 9.0 μm to 10.0 μm, 10.0 μm to 11.0 μm, 11.0 μm to 12.0 μm, 12.0 μm to 13.0 μm). The minimum distance g5 (same as r6) between each fourth anode RAD4 and the first corresponding first anode RAD1-1 is in the range of 2.5μm to 7.5μm (e.g., 2.5μm to 3.5μm, 3.5μm to 4.5μm, 4.5μm to 5.5μm, 5.5μm to 6.5μm, 6.5μm to 7.5μm, or optionally 5.0μm); each fourth anode RAD4 and the second corresponding third anode RAD1-1 The shortest distance g6 between 3-2 (same as b1) is in the range of 2.0 μm to 5.0 μm (e.g., 2.0 μm to 2.5 μm, 2.5 μm to 3.0 μm, 3.0 μm to 3.5 μm, 3.5 μm to 4.0 μm, 4.0 μm to 4.5 μm, 4.5 μm to 5.0 μm, or optionally 4.0 μm); and the shortest distance g7 between each fourth anode RAD4 and the second corresponding first anode RAD1-2 (same as r2) is in the range of 10.0 μm to 25.0 μm (e.g., 10.0 μm to 10.5 μm, 10.5 μm to 11. 5 μm, 11.5 μm to 12.5 μm, 12.5 μm to 13.5 μm, 13.5 μm to 14.5 μm, 14.5 μm to 15.5 μm, 15.5 μm to 16.5 μm, 16.5 μm to 17.5 μm, 17.5 μm to 18.5 μm, 18.5 μm to 19.5 μm, 19.5 μm to 20.5 μm, 20.5 μm to 21.5 μm, 21.5 μm to 22.5 μm, 22.5 μm to 23.5 μm, 23.5 μm to 24.5 μm, 24.5 μm to 25.0 μm, or optionally 16.6 μm).

[0144] The shortest distance g1 in this array substrate is greater than the shortest distance in a typical array substrate. By increasing the shortest distance g1, the distribution of the illumination center of the pixels on the array substrate can be made more uniform.

[0145] Figure 9AThis is a diagram illustrating the anode, first signal line layer, second signal line layer, and semiconductor material layer in an array substrate according to some embodiments of the present disclosure. Figure 9B It is along Figure 9A A cross-sectional view of the H-H' line in the diagram. Figure 9C It is along Figure 9A A cross-sectional view of line I-I' in the diagram. Figure 9D It is along Figure 9A A cross-sectional view of line J-J' in the diagram. Figure 9E It is along Figure 9A A cross-sectional view of the K-K' line. (See reference) Figures 9A to 9E In some embodiments, in each first sub-pixel sp1, the first anode AD1 is connected to the first anode contact pad ACP1 via a first via V1-1 extending through the second planarization layer PLN-2, the first anode contact pad ACP1 is connected to the first relay electrode RE1 via a second via V1-2 extending through the first planarization layer PLN-1, and the first relay electrode RE1 is connected to the fifth transistor in each first sub-pixel sp1 via a third via V1-3 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. The drain of the second anode is D5; in each second sub-pixel sp2, the second anode AD2 is connected to the second anode contact pad ACP2 through a fourth via V2-1 extending through the second planarization layer PLN-2, the second anode contact pad ACP2 is connected to the second relay electrode RE2 through a fifth via V2-2 extending through the first planarization layer PLN-1, and the second relay electrode RE2 is connected to the drain of the fifth transistor in each second sub-pixel sp2 through a sixth via V2-3 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. D5; In each third sub-pixel sp3, the third anode AD3 is connected to the third anode contact pad ACP3 through the seventh via V3-1 extending through the second planarization layer PLN-2, the third anode contact pad ACP3 is connected to the third relay electrode RE3 through the eighth via V3-2 extending through the first planarization layer PLN-1, and the third relay electrode RE3 is connected to the drain D5 of the fifth transistor in each third sub-pixel sp3 through the ninth via V3-3 extending through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI; In each of the fourth sub-pixels sp4, the fourth anode AD4 is connected to the fourth anode contact pad ACP4 via a tenth via V4-1 extending through the second planarization layer PLN-2, the fourth anode contact pad ACP4 is connected to the fourth relay electrode RE4 via an eleventh via V4-2 extending through the first planarization layer PLN-1, and the fourth relay electrode RE4 is connected to the drain D5 of the fifth transistor in each of the fourth sub-pixels sp4 via a twelfth via V4-3 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0146] like Figures 9B to 9E As shown, in some embodiments, the orthographic projection of a portion of the first anode contact pad ACP1 in the second via V1-2 onto the substrate BS is substantially non-overlapping with the orthographic projection of a portion of the first anode AD1 in the first via V1-1 onto the substrate BS; and substantially non-overlapping with the orthographic projection of a portion of the first relay electrode RE1 in the third via V1-3 onto the substrate BS; the orthographic projection of a portion of the second anode contact pad ACP2 in the fifth via V2-2 onto the substrate BS is substantially non-overlapping with the orthographic projection of a portion of the second anode AD2 in the fourth via V2-1 onto the substrate BS; and substantially non-overlapping with the orthographic projection of a portion of the second relay electrode RE2 in the third via V2-3 onto the substrate BS. The orthographic projections of a portion of the third anode contact pad ACP3 in the eighth via V3-2 onto the substrate BS are substantially non-overlapping with the orthographic projections of a portion of the third anode AD3 in the seventh via V3-1 onto the substrate BS; and substantially non-overlapping with the orthographic projections of a portion of the third relay electrode RE3 in the ninth via V3-3 onto the substrate BS; and substantially non-overlapping with the orthographic projections of a portion of the fourth anode contact pad ACP4 in the eleventh via V4-2 onto the substrate BS; and substantially non-overlapping with the orthographic projections of a portion of the fourth anode AD4 in the tenth via V4-1 onto the substrate BS. As used herein, the term "substantially non-overlapping" means that two orthographic projections do not overlap by at least 90% (e.g., at least 92%, at least 94%, at least 96%, at least 98%, at least 99%, and 100%).

[0147] Optionally, the orthographic projection of the second through-hole V1-2 on the substrate BS is substantially non-overlapping with the orthographic projection of the first through-hole V1-1 on the substrate BS; and substantially non-overlapping with the orthographic projection of the third through-hole V1-3 on the substrate BS; the orthographic projection of the fifth through-hole V2-2 on the substrate BS is substantially non-overlapping with the orthographic projection of the fourth through-hole V2-1 on the substrate BS; and substantially non-overlapping with the orthographic projection of the third through-hole V2-3 on the substrate BS; the orthographic projection of the eighth through-hole V3-2 on the substrate BS is substantially non-overlapping with the orthographic projection of the seventh through-hole V3-1 on the substrate BS; and substantially non-overlapping with the orthographic projection of the ninth through-hole V3-3 on the substrate BS; the orthographic projection of the eleventh through-hole V4-2 on the substrate BS is substantially non-overlapping with the orthographic projection of the tenth through-hole V4-1 on the substrate BS; and substantially non-overlapping with the orthographic projection of the twelfth through-hole V4-3 on the substrate BS. By having the above-mentioned non-overlapping through-holes, the problem of open circuits can be substantially avoided. Furthermore, compared to other array substrates, the second planarization layer PLN2 can be formed to have a substantially flatter surface.

[0148] Figure 10 The relative positions between sub-pixel openings and vias in an array substrate are shown in some embodiments according to this disclosure. Reference Figure 10 In some embodiments, the array substrate includes a first anode AD1 in each first sub-pixel sp1, a second anode AD2 in each second sub-pixel sp2, a third anode AD3 in each third sub-pixel sp3, and a fourth anode AD4 in each fourth sub-pixel sp4. The first anode AD1, second anode AD2, third anode AD3, and fourth anode AD4 are respectively the anodes of a first light-emitting element, a second light-emitting element, a third light-emitting element, and a fourth light-emitting element in each first sub-pixel sp1, each second sub-pixel sp2, each third sub-pixel sp3, and each fourth sub-pixel sp4. In some embodiments, the array substrate further includes a pixel defining layer PDL located on the side of the first anode AD1, second anode AD2, third anode AD3, and fourth anode AD4 away from the second planarization layer PLN2. The array substrate also includes a first sub-pixel opening SA1, a second sub-pixel opening SA2, a third sub-pixel opening SA3, and a fourth sub-pixel opening SA4 extending through the pixel defining layer PDL. Optionally, the first light-emitting layer of the first light-emitting element, the second light-emitting layer of the second light-emitting element, the third light-emitting layer of the third light-emitting element, and the fourth light-emitting layer of the fourth light-emitting element are respectively connected to the first anode AD1 of the first light-emitting element, the second anode AD2 of the second light-emitting element, the third anode AD3 of the third light-emitting element, and the fourth anode AD4 of the fourth light-emitting element through the first sub-pixel opening SA1, the second sub-pixel opening SA2, the third sub-pixel opening SA3, and the fourth sub-pixel opening SA4, respectively.

[0149] In some embodiments, the shortest distance between the edge of the first anode (excluding the edge with the first via) and the opening of the first sub-pixel is different. Optionally, the shortest distance between the edge of the third anode (excluding the edge with the seventh via) and the opening of the third sub-pixel is different. Optionally, the shortest distance between the edge of the fourth anode (excluding the edge with the tenth via) and the opening of the fourth sub-pixel is different.

[0150] In some embodiments, the shortest distance d1 between the first via V1-1 and the first sub-pixel opening SA1 is in the range of 9.0 μm to 15.0 μm, for example, 9.0 μm to 10.0 μm, 10.0 μm to 11.0 μm, 11.0 μm to 12.0 μm, 12.0 μm to 13.0 μm, 13.0 μm to 14.0 μm, or 14.0 μm to 15.0 μm. Optionally, the shortest distance d1 is 11.7 μm. In some embodiments, the shortest distance d2 between the fourth via V2-1 and the second sub-pixel opening SA2 is in the range of 2.0 μm to 6.0 μm, for example, 2.0 μm to 3.0 μm, 3.0 μm to 4.0 μm, 4.0 μm to 5.0 μm, or 5.0 μm to 6.0 μm. Optionally, the shortest distance d2 is 3.7 μm. In some embodiments, the shortest distance d3 between the seventh via V3-1 and the third sub-pixel opening SA3 is in the range of 4.5 μm to 10.5 μm, for example, 4.5 μm to 5.5 μm, 5.5 μm to 6.5 μm, 6.5 μm to 7.5 μm, 7.5 μm to 8.5 μm, 8.5 μm to 9.5 μm, or 9.5 μm to 10.5 μm. Optionally, the shortest distance d3 is 7.4 μm. In some embodiments, the shortest distance d4 between the tenth via V4-1 and the fourth sub-pixel opening SA4 is in the range of 2.0 μm to 6.0 μm, for example, 2.0 μm to 3.0 μm, 3.0 μm to 4.0 μm, 4.0 μm to 5.0 μm, or 5.0 μm to 6.0 μm. Optionally, the shortest distance d4 is 3.4 μm. By separating the individual vias and sub-pixel openings, enhanced surface uniformity of each anode can be achieved.

[0151] refer to Figure 10In some embodiments, the first through hole V1-1, the second through hole V1-2, and the third through hole V1-3 are arranged along a direction substantially parallel to the second direction DR2; the fourth through hole V2-1, the fifth through hole V2-2, and the sixth through hole V2-3 are arranged along a direction substantially parallel to the second direction DR2; the eighth through hole V3-2 and the ninth through hole V3-3 are arranged along a direction substantially parallel to the second direction DR2; and the tenth through hole V4-1, the eleventh through hole V4-2, and the twelfth through hole V4-3 are arranged along a direction substantially parallel to the second direction DR2. However, the seventh through hole V3-1 and the eighth through hole V3-2 are arranged along a direction with an inclination angle greater than 15 degrees relative to the second direction DR2.

[0152] refer to Figure 10 , Figure 3G and Figures 9A to 9E In some embodiments, the first anode contact pad ACP1 has a first portion connected to the first anode AD1 through a first through-hole V1-1 and a second portion connected to the first relay electrode RE1 through a second through-hole V1-2; the first anode contact pad ACP1 has a generally rectangular shape, wherein the first and second portions are arranged along a direction substantially parallel to the second direction DR2. Optionally, the second anode contact pad ACP2 has a third portion connected to the second anode AD2 through a fourth through-hole V2-1 and a fourth portion connected to the second relay electrode RE2 through a fifth through-hole V2-2; the second anode contact pad ACP2 has a generally rectangular shape, wherein the third and fourth portions are arranged along a direction substantially parallel to the second direction DR2. Optionally, the third anode contact pad ACP3 has a fifth portion connected to the third anode AD3 through a seventh through-hole V3-1 and a sixth portion connected to the third relay electrode RE3 through an eighth through-hole V3-2; the third anode contact pad ACP3 has a generally dumbbell-shaped shape, wherein the fifth and sixth portions are arranged along a direction at an angle greater than 15 degrees relative to the second direction DR2. Optionally, the fourth anode contact pad ACP4 has a seventh portion connected to the fourth anode AD4 through a tenth through-hole V4-1 and an eighth portion connected to the fourth relay electrode RE4 through an eleventh through-hole V4-2; the fourth anode contact pad ACP4 has a generally rectangular shape, wherein the seventh and eighth portions are arranged along a direction that is generally parallel to the second direction DR2.

[0153] Figure 11 A partial structure of a voltage supply line according to some embodiments of the present disclosure is shown. Reference Figure 11In some embodiments, the voltage supply line Vdd includes a first parallel portion PA1, a second parallel portion PA2, a third parallel portion PA3, a first inclined portion INP1 connecting the first parallel portion PA1 and the second parallel portion PA2 along a first inclined direction IDR1, and a second inclined portion INP2 connecting the second parallel portion PA2 and the third parallel portion PA3 along a second inclined direction IDR2. The first parallel portion PA1, the second parallel portion PA2, and the third parallel portion PA3 each extend along a direction substantially parallel to the second direction DR2. The first inclined portion INP1 extends along a first inclined angle α1 relative to the first direction DR1. The second inclined portion INP2 extends along a second inclined angle α2 relative to the first direction DR2. Optionally, the first inclined angle α1 and the second inclined angle α2 are supplementary angles, for example, α1 + α2 = 180°. The first connecting portion INP1 extends along a direction substantially parallel to the first inclined direction IDR1. The second connecting portion INP2 extends along a direction substantially parallel to the second inclined direction IDR2. As used herein, the term "substantially parallel" means an angle ranging from 0 degrees to approximately 45 degrees, such as 0 degrees to approximately 5 degrees, 0 degrees to approximately 10 degrees, 0 degrees to approximately 15 degrees, 0 degrees to approximately 20 degrees, 0 degrees to approximately 25 degrees, and 0 degrees to approximately 30 degrees. Optionally, the first parallel portion PA1 and the third parallel portion PA3 are substantially aligned, for example, along the second direction DR2.

[0154] Reference Figure 11 , Figure 3A , Figure 4B The first connecting portion INP1, the second parallel portion PA2, and the second connecting portion INP2 together surround one side of the connecting portion CP. The connecting portion CP is connected to one of the multiple data lines DL through a via v4-1 extending through the first planarization layer PLN-1, and is connected to the source S2 of the second transistor through a via v4-2 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0155] Figure 12 The detailed structure of an anti-interference block according to some embodiments of the present disclosure is shown. Reference Figure 3A , Figure 4B and Figure 12 In some embodiments, the anti-interference block IPB further includes a base B, a first arm AM1, and a second arm AM2. A voltage supply line Vdd is connected to the base B via a third main via v3. Optionally, the first arm AM1 includes a first end portion TP1 and a first connecting bridge portion CP1 connecting the base B and the first end portion TP1. Optionally, the second arm AM2 includes a second end portion TP2 and a second connecting bridge portion CP2 connecting the base B and the second end portion TP2.

[0156] Optionally, the first end portion TP1 and the first connecting bridge portion CP1 are arranged along a direction substantially parallel to the second direction DR2. Optionally, the second end portion TP2 and the second connecting bridge portion CP2 are arranged along a direction substantially parallel to the second direction DR2. Optionally, the longitudinal side of the base B is arranged along a direction substantially parallel to the first direction DR1, and the transverse side of the base B is arranged along a direction substantially parallel to the second direction DR2.

[0157] Optionally, base B has a basic rectangular shape. Optionally, the first end portion TP1 has a basic rectangular shape. Optionally, the second end portion TP2 has a basic rectangular shape. Optionally, the first connecting bridge portion CP1 has a pseudo-half trapezoidal shape. Optionally, the second connecting bridge portion CP2 has a pseudo-trapezoidal shape.

[0158] To more clearly illustrate the shape and size relationships of the subpixel aperture, anode, and light-emitting functional layer, see below. Figure 13 The diagram shows the planar structure. Figure 13 Several repeating units arranged in two groups of repeating units are schematically shown. For clarity, Figure 13 The two second sub-pixels, two third sub-pixels, and four first sub-pixels on the left schematically illustrate the structure of the sub-pixel openings, the structure of the anode, and the structure of the light-emitting functional layer; Figure 13 The two second sub-pixels, two third sub-pixels, and four first sub-pixels on the right only show the light-emitting functional layer and sub-pixel openings. (See image.) Figure 13 As shown, the first sub-pixel includes a corresponding sub-pixel opening, an anode 411, and a light-emitting functional layer 611; the second sub-pixel includes a corresponding sub-pixel opening, an anode 412, and a light-emitting functional layer 612; and the third sub-pixel includes a corresponding sub-pixel opening, an anode 413, and a light-emitting functional layer 613. In each sub-pixel (first sub-pixel, second sub-pixel, and third sub-pixel), the area of ​​the light-emitting functional layer is the largest, the area of ​​the anode is smaller than the area of ​​the light-emitting functional layer, and the area of ​​the sub-pixel opening is the smallest. The orthographic projection of the sub-pixel opening onto the plane defined by the first direction DR1 and the second direction DR2 falls within the orthographic projection of the anode onto that plane. The orthographic projections of the anodes of the first sub-pixel, the second sub-pixel, and the third sub-pixel onto that plane fall within the orthographic projections of the respective light-emitting functional layers in the corresponding first sub-pixel, the corresponding second sub-pixel, and the corresponding third sub-pixel onto that plane.

[0159] like Figure 13As shown, the two opposite edges of the opening of the pixel-defining layer of the two first sub-pixels in the first sub-pixel pair extend along the first direction DR1, that is, the two opposite edges are parallel to each other, and the distance between the two edges is equal at different positions, thereby ensuring the maximum light-emitting area.

[0160] For example, such as Figure 13 As shown, the subpixel openings of any two adjacent subpixels among the first, second, and third subpixels have approximately parallel opposing edges, and the perpendicular bisector of one edge of the opposing edges passes through the other edge. In some examples, the length of the line connecting the centers of the two opposing edges is the minimum distance between the two opposing edges. On either side of the center, the space between the two opposing edges can gradually increase. For example, the maximum space between two opposing edges can be 1.5 times the minimum distance between the two opposing edges.

[0161] like Figure 13 As shown in the right-hand diagram of the sub-pixel with the anode not shown, in each of the second sub-pixel 12 and the third sub-pixel 13, the light-emitting functional layer includes annular portions 1220 and 1320 located on the pixel defining layer surrounding the corresponding sub-pixel opening; in the first sub-pixel pair (two first sub-pixels 11), the light-emitting functional layer 611 includes annular portion 1120 located on the pixel defining layer surrounding the corresponding sub-pixel opening of the two first sub-pixels and a connecting portion 1130 located on the pixel defining layer between the two sub-pixel openings (see...). Figure 13 (The dashed box between the two first sub-pixels). In each of the first, second, and third sub-pixels, the annular portion of the luminescent functional layer has equal widths (i.e., Pg1, Pg2, and Pg3) at different locations. For example, width Pg1 is equal to widths Pg2 and Pg3, respectively.

[0162] Furthermore, it should be noted that in a repeating unit, two first sub-pixels 11 form a sub-pixel pair, and the light-emitting functional layers of the two first sub-pixels 11 can be formed through a mask opening. When the light-emitting functional layers of the two first sub-pixels 11 are formed by a single opening, the difficulty of manufacturing the FMM is reduced, and the manufacturing efficiency is improved. In this case, at least the annular portion and the connecting portion of the light-emitting functional layers of the first sub-pixel pair are continuous layer structures. Figure 13As shown, the annular portion 1120 and the connecting portion 1130 of the light-emitting functional layer of the first sub-pixel pair may have a planar shape of "θ". In some embodiments, the light-emitting functional layers of the two first sub-pixels are integrally formed and distributed on the pixel defining layer and in the sub-pixel opening, and the light-emitting functional layers on the pixel defining layer and in the sub-pixel opening of the pixel defining layer are also interconnected. However, embodiments according to this disclosure are not limited to this, and the light-emitting functional layers on the pixel defining layer and in the sub-pixel opening of the pixel defining layer may also be disconnected from each other.

[0163] Furthermore, the anodes of the two first sub-pixels in the first sub-pixel pair are spaced apart from each other; therefore, the two first sub-pixels can be driven independently.

[0164] In addition, such as Figure 13 As shown, the anode needs to be connected to the underlying drive circuit via a via; therefore, an anode via 52 needs to be provided in the planarization layer. Figure 13 In the repeating unit at the upper left corner, the anode of the lower first sub-pixel of the first sub-pixel pair is connected to the first anode via 5211 via a connecting electrode 400; the anode of the second sub-pixel 12 is connected to the third anode via 5213 via a connecting electrode 400; and the anode of the third sub-pixel 13 is connected to the fourth anode via 5214 via a connecting electrode 400. The three anode vias (5211, 5213, and 5214) are substantially on a straight line parallel to the first direction DR1. That is, all three anode vias are formed on the lower side of the repeating unit group above and arranged on a straight line parallel to the first direction DR1. Furthermore, for the upper first sub-pixel 11 in the first sub-pixel pair, its anode is connected to the upper second anode via 5212 via a connecting electrode 400. For example, see reference... Figure 13 The connection of the first sub-pixel above the first sub-pixel pair in the lower left corner of the center. That is, for each repeating unit group, the second sub-pixel, the third sub-pixel, and the anodized via of the first sub-pixel located below the first sub-pixel pair are located below the repeating unit group and are substantially on the same straight line. The anodized via of the first sub-pixel above the first sub-pixel pair in the repeating unit group is located above the repeating unit group and is on the same straight line as the anodized vias of the second and third sub-pixels of the repeating unit group adjacent to the upper side of that repeating unit group.

[0165] For example, such as Figure 13As shown, the spacing between the anode vias 5213 and 5214 of adjacent second and third sub-pixels is greater than the spacing between adjacent anode vias 5211 and 5213. In this case, the anode via 5212 of the first sub-pixel in the next repeating unit group can be disposed between the anode vias 5213 and 5214.

[0166] For example, the anode access holes arranged along a straight line are arranged in the order of anode access hole 5211, anode access hole 5213, anode access hole 5212 and anode access hole 5214.

[0167] Despite Figure 13 The anodes 411, 412, and 413 and the connecting electrode 400 use different shading patterns, but the anodes 411, 412, and 413 can be integrally formed with their respective connecting electrodes, i.e., formed as a single structure. For example, each connecting electrode can be formed simultaneously with its corresponding connecting electrode by depositing a conductive layer (e.g., a metal layer) and patterning it.

[0168] In addition, such as Figure 13 As shown, the connection electrode (connection electrode) 400 of each sub-pixel electrically connected to the anode can overlap with the light-emitting functional layer, or can protrude beyond the area of ​​the light-emitting functional layer, which can be arbitrarily adjusted according to the position of the via hole.

[0169] In some embodiments, the light-emitting functional layer 60 may include a hole transport layer, a light-emitting layer, and an electron transport layer, but is not limited thereto. For example, the hole transport layer may have different thicknesses for different sub-pixels. For example, the hole transport layer of the second sub-pixel may have the smallest thickness, the hole transport layer of the third sub-pixel may have the largest thickness, and the thickness of the hole transport layer of the first sub-pixel may be in between. For example, different hole transport layers of different sub-pixels may be made of the same material but have different thicknesses; therefore, the entire thin layer of the hole transport layer may be deposited first using an aperture mask, and then deposited separately using pure metal masks (FMM) for the third and first sub-pixels to achieve their respective hole transport layer thicknesses. For the light-emitting layer, each light-emitting layer is obtained by depositing it separately using individual evaporation masks. For the electron transport layer, an aperture mask may also be used for evaporation. Therefore, five FMM evaporation mask processes may be used in the fabrication of the light-emitting diode pixel. For example, some layers of the light-emitting functional layer may be integrally formed for multiple sub-pixels, for example, by depositing these layers using the aforementioned aperture mask. However, for clarity, the shape and size of the light-emitting functional layer described in this application are all portions of the patterned light-emitting functional layer formed by each subpixel or subpixel pair of the FMM.

[0170] In some embodiments, a cathode, a lithium fluoride layer, a light extraction layer, and a lithium fluoride layer may be further disposed on the light-emitting functional layer 60. For example, the cathode may be formed of a transparent conductive material (such as ITO). The introduction of lithium fluoride can better modify the ITO surface, reduce the formation of interface defect states, and improve the stability of the device. This light extraction layer can improve the light extraction efficiency of the light-emitting diode.

[0171] In addition, such as Figure 13 As shown, in the same repeating unit group, the light-emitting functional layers of adjacent sub-pixels on the first direction DR1 are adjacent to each other. That is, there may be no space between two adjacent light-emitting functional layers on the first direction DR1. For example, in order to ensure that the light-emitting functional layers in the sub-pixel openings fabricated by the FMM process are as uniform as possible, and considering the process margin, the FMM openings used to fabricate the light-emitting functional layers are as large as possible, but the light-emitting functional layers of adjacent sub-pixels of different colors should preferably not overlap to avoid color mixing. Therefore, the FMM openings can be designed according to the adjacentity of the light-emitting functional layers of adjacent sub-pixels. However, in actual processes, due to process errors and other reasons, the shadow areas of the layers formed by the FMM may have a certain overlap or interval, and the light-emitting functional layers formed by adjacent sub-pixels may have overlapping parts. However, through process control, the size of the overlapping part can be less than 1 / 10 or even less than 1 / 20 of the size of the light-emitting functional layer. In addition, as mentioned above, the edge of the sub-pixel opening of each pixel has an equal distance from the edge of the light-emitting functional layer, for example, Pg1 = Pg2 = Pg3. Therefore, in the first direction DR1, the boundary lines of the light-emitting functional layers of two adjacent sub-pixels are located in the middle of the interval between the sub-pixel openings of the two adjacent sub-pixels. In this case, the shape of the light-emitting functional layer of each sub-pixel can be calculated. For example, the area of ​​the light-emitting functional layer of the first sub-pixel pair is larger than the area of ​​the light-emitting functional layer of the second sub-pixel, and the area of ​​the light-emitting functional layer of the second sub-pixel is larger than the area of ​​the light-emitting functional layer of the third sub-pixel. For example, the first sub-pixel is a green sub-pixel, the second sub-pixel is a blue sub-pixel, and the third sub-pixel is a red sub-pixel. Furthermore, in the second direction DR2, the light-emitting functional layers of adjacent first and second sub-pixels are adjacent to each other, the light-emitting functional layers of adjacent third and first sub-pixel pairs are spaced apart from each other, and the light-emitting functional layers of adjacent third and second sub-pixels are spaced apart from each other. Furthermore, as from... Figure 13As can be seen, the spacing between the light-emitting functional layers of adjacent third and second sub-pixels in the second direction DR2 is greater than the spacing between the light-emitting functional layers of adjacent third and first sub-pixel pairs in the second direction DR2. In the second direction DR2, the size of the light-emitting functional layer of a first sub-pixel pair is larger than the size of the light-emitting functional layer of a second sub-pixel, and also larger than the size of the light-emitting functional layer of a third sub-pixel; in the first direction DR1, the size of the light-emitting functional layer of a first sub-pixel pair and the size of the light-emitting functional layer of a second sub-pixel are both larger than the size of the light-emitting functional layer of a third sub-pixel. Designing the shape and area of ​​the light-emitting functional layers according to the above rules simplifies the process and maximizes the light-emitting area.

[0172] For example, such as Figure 13 As shown, the minimum distance between the sub-pixel openings of the two first sub-pixels in a first sub-pixel pair is less than the minimum distance between any two of the sub-pixel openings of the first sub-pixel pair, the second sub-pixel opening, and the third sub-pixel opening. For example, the minimum distance between the sub-pixel opening of the first sub-pixel pair and the sub-pixel opening of the second sub-pixel is the first distance, the minimum distance between the sub-pixel opening of the first sub-pixel pair and the sub-pixel opening of the third sub-pixel is the second distance, the minimum distance between the sub-pixel opening of the second sub-pixel and the sub-pixel opening of the third sub-pixel is the third distance, and the minimum distance between the sub-pixel openings of the two first sub-pixels in the first sub-pixel pair is the fourth distance. The first, second, and third distances are all greater than the fourth distance. For example, the difference between the first and second distances is less than 20% of the first distance, and the difference between the first and third distances is less than 20% of the first distance. At full high definition (FHD) resolution, the distance between the subpixel apertures of adjacent subpixels can be 22 to 25 μm; at quarter full definition (QHD) resolution, the distance between the subpixel apertures of adjacent subpixels can be 19.7 to 21.5 μm. For example, the above distances can be in the range of 18 to 26 μm. The distance between adjacent subpixels as described above refers to the distance between subpixels of different colors. For two subpixels in a first subpixel pair, the distance between the subpixel apertures can be 15 μm at full high definition (FHD) resolution and 14 μm at quarter full definition (QHD) resolution. For example, the distance between the subpixel apertures of two first subpixels can be in the range of 13 to 16 μm. Furthermore, the minimum size of the subpixel aperture for each subpixel is 8 μm. That is, the size of the subpixel aperture for each subpixel is greater than or equal to 8 μm.

[0173] For subpixel openings with different colors, the second subpixel has the largest opening area, the first subpixel has the smallest opening area, and the third subpixel's opening area is in between. Optionally, the first subpixel is a green subpixel, the second subpixel is a blue subpixel, and the third subpixel is a red subpixel.

[0174] Furthermore, for example, the minimum distance between the anodes of the two first sub-pixels in a first sub-pixel pair can be in the range of 8 to 15 μm. In this case, a wire with a linewidth of approximately 5 μm can be positioned between the anodes of the two first sub-pixels.

[0175] The design structure of the aforementioned light-emitting functional layer and sub-pixel openings can take into account the display effects of sub-pixels of various colors and achieve the most compact arrangement.

[0176] In some embodiments, two of the corresponding first sub-pixel, second sub-pixel, third sub-pixel, and fourth sub-pixel are sub-pixels of the same color (e.g., green). In one example, the corresponding second sub-pixel sp2 and the corresponding fourth sub-pixel sp4 are sub-pixels of the same color (e.g., green). In some embodiments, two of the first, second, third, and fourth light-emitting elements are light-emitting elements of the same color (e.g., green). In one example, the second and fourth light-emitting elements are light-emitting elements of the same color (e.g., green). In some embodiments, the anodes of the two light-emitting elements of the same color have different areas or different shapes. In one example, the second anode AD2 and the fourth anode AD4 have different areas or different shapes.

[0177] Figure 14 Structural differences between the second and fourth anodes according to some embodiments of the present disclosure are shown. Figure 14 The diagram illustrates a second anode AD2, a fourth anode AD4, and the overlap of the second anode AD2 and the fourth anode AD4. In some embodiments, the second anode AD2 includes a first main portion MP1 and a first additional portion EP1; the fourth anode AD4 includes a second main portion MP2, a second additional portion EP2, a third additional portion EP3, a fourth additional portion EP4, and a fifth additional portion EP5.

[0178] In some embodiments, the first main body portion MP1 is a combination of a rectangular portion and a triangular portion, and the second main body portion MP2 is a combination of a rectangular portion and a triangular portion. Optionally, the first main body portion MP1 and the second main body portion MP2 have substantially the same shape (and size). Optionally, the first additional portion EP1 is adjacent to the triangular portion of the first main body portion MP1. Optionally, the second additional portion EP2 is adjacent to the side of the rectangular portion of the second main body portion MP2 away from the triangular portion of the second main body portion MP2. Optionally, the third additional portion EP3 is adjacent to the triangular portion of the second main body portion MP2. Optionally, the third additional portion EP3 connects a fourth additional portion EP4 to the second main body portion MP2, and the fourth additional portion EP4 connects a fifth additional portion EP5 to the third additional portion EP3.

[0179] Optionally, the second additional portion EP2, the second main portion MP2, the third additional portion EP3, the fourth additional portion EP4, and the fifth additional portion EP5 are arranged sequentially along a direction substantially parallel to the second direction DR2. Optionally, the fourth additional portion EP4 extends along a direction forming a third tilt angle γ with respect to the second direction DR2 that is greater than zero.

[0180] In another aspect, this disclosure provides a display panel comprising an array substrate manufactured as described herein or by the methods described herein, and a counter substrate facing the array substrate. Optionally, the display panel is an organic light-emitting diode (OLED) display panel. Optionally, the display panel is a micro-LED display panel.

[0181] In another aspect, the present invention provides a display device comprising an array substrate manufactured as described herein or by the methods described herein, and one or more integrated circuits connected to the array substrate.

[0182] In another aspect, this disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a plurality of light-emitting elements in a plurality of sub-pixels; and forming a plurality of pixel driving circuits in the plurality of sub-pixels, configured to drive the plurality of light-emitting elements respectively. Optionally, forming the plurality of light-emitting elements includes forming a first light-emitting element in each first sub-pixel, a second light-emitting element in each second sub-pixel, a third light-emitting element in each third sub-pixel, and a fourth light-emitting element in each fourth sub-pixel. Optionally, forming each pixel driving circuit in the plurality of pixel driving circuits includes forming a plurality of transistors and forming a storage capacitor. Optionally, forming the storage capacitor includes forming a first capacitor electrode, forming a second capacitor electrode electrically connected to a corresponding voltage supply line, and forming an insulating layer. An insulating layer is formed between the first capacitor electrode and the second capacitor electrode. Optionally, forming the array substrate includes: forming a semiconductor material layer on the substrate; and forming node connection lines located in the same layer as the corresponding voltage supply lines. The node connection lines are formed to connect to the first capacitor electrode through a first main via and to connect to the semiconductor material layer through a second main via. Optionally, the orthographic projection of the first anode of the first light-emitting element in the corresponding first sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the node connection line in the corresponding first sub-pixel onto the substrate; the orthographic projection of the second anode in the corresponding second sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the node connection line in the corresponding second sub-pixel onto the substrate; the orthographic projection of the third anode in the corresponding third sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the node connection line in the corresponding third sub-pixel onto the substrate; and the orthographic projection of the fourth anode in the corresponding fourth sub-pixel sp4 onto the substrate at least partially overlaps with the orthographic projection of the node connection line in the corresponding fourth sub-pixel onto the substrate.

[0183] In some embodiments, forming the plurality of transistors includes forming driving transistors. Optionally, the orthographic projection of the first anode in a corresponding first sub-pixel onto the substrate covers the orthographic projection of a portion of the node connection line in the corresponding first sub-pixel at the location connected to the first capacitor electrode onto the substrate; the orthographic projection of the second anode in a corresponding second sub-pixel onto the substrate covers the orthographic projection of a portion of the node connection line in the corresponding second sub-pixel at the location connected to the first capacitor electrode Ce1 onto the substrate; the orthographic projection of the third anode in a corresponding third sub-pixel onto the substrate covers the orthographic projection of a portion of the node connection line in the corresponding third sub-pixel at the location connected to the first capacitor electrode Ce1 onto the substrate; and the orthographic projection of the fourth anode in a corresponding fourth sub-pixel onto the substrate covers the orthographic projection of a portion of the node connection line in the corresponding fourth sub-pixel at the location connected to the first capacitor electrode Ce1 onto the substrate.

[0184] In some embodiments, the orthographic projection of the third anode onto the substrate at least partially overlaps with the orthographic projection of the third transistor in the corresponding third sub-pixel onto the substrate, and at least partially overlaps with the orthographic projection of the third transistor in the corresponding fourth sub-pixel onto the substrate, the corresponding fourth sub-pixel being adjacent to the corresponding third sub-pixel.

[0185] In some embodiments, the orthographic projection of the third anode on the substrate covers the orthographic projection of the source of the third transistor in the corresponding third sub-pixel on the substrate, overlaps with the orthographic projection portion of the active layer of the third transistor in the corresponding third sub-pixel on the substrate, and overlaps with the orthographic projection portion of the active layer of the third transistor in the corresponding fourth sub-pixel on the substrate.

[0186] In some embodiments, the orthographic projection of the first anode onto the substrate at least partially overlaps with the orthographic projection of the third transistor in the corresponding first sub-pixel onto the substrate.

[0187] In some embodiments, the orthographic projection of the first anode on the substrate partially overlaps with the orthographic projection of the source of the third transistor in the corresponding first sub-pixel on the substrate, and partially overlaps with the orthographic projection of the active layer of the third transistor in the corresponding first sub-pixel on the substrate.

[0188] In some embodiments, the orthographic projection of the fourth anode onto the substrate at least partially overlaps with the orthographic projection of the third transistor in the corresponding second sub-pixel onto the substrate.

[0189] In some embodiments, the orthographic projection of the fourth anode on the substrate partially overlaps with the orthographic projection of the source of the third transistor in the corresponding second sub-pixel on the substrate, and partially overlaps with the orthographic projection of the active layer of the third transistor in the corresponding second sub-pixel on the substrate.

[0190] In some embodiments, the method further includes: forming a gate insulating layer located on the side of the semiconductor material layer away from the substrate; forming an insulating layer located on the side of the gate insulating layer away from the substrate; forming an interlayer dielectric layer located on the side of the insulating layer away from the gate insulating layer; forming a relay electrode layer located on the side of the interlayer dielectric layer away from the insulating layer; forming a first planarization layer located on the side of the relay electrode layer away from the interlayer dielectric layer; forming an anode contact pad layer located on the side of the first planarization layer away from the interlayer dielectric layer; and forming a second planarization layer located on the side of the anode contact pad layer away from the first planarization layer. Optionally, a pixel defining layer is formed on the side of the second planarization layer away from the substrate; a spacer layer is formed on the side of the pixel defining layer away from the second planarization layer; and each anode is formed on the side of the second planarization layer away from the first planarization layer; and each light-emitting layer is formed on the side of the each anode away from the second planarization layer. Optionally, in each first sub-pixel, the first anode is formed to be connected to a first anode contact pad via a first via extending through the second planarization layer, the first anode contact pad is connected to a first relay electrode via a second via extending through the first planarization layer, and the first relay electrode is connected to the drain of a fifth transistor in each first sub-pixel via a third via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer. Optionally, in each second sub-pixel, the second anode is formed to be connected to a second anode contact pad via a fourth via extending through the second planarization layer, the second anode contact pad is connected to a second relay electrode via a fifth via extending through the first planarization layer, and the second relay electrode is connected to the drain of a fifth transistor in each second sub-pixel via a sixth via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer. Optionally, in each third sub-pixel, the third anode is formed to be connected to the third anode contact pad via a seventh via extending through the second planarization layer, the third anode contact pad is connected to the third relay electrode via an eighth via extending through the first planarization layer, and the third relay electrode is connected to the drain of the fifth transistor in each third sub-pixel via a ninth via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer.Optionally, in each fourth sub-pixel, the fourth anode is formed to be connected to the fourth anode contact pad through a tenth via extending through the second planarization layer, the fourth anode contact pad is connected to the fourth relay electrode through an eleventh via extending through the first planarization layer, and the fourth relay electrode is connected to the drain of the fifth transistor in each fourth sub-pixel through a twelfth via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer.

[0191] In some embodiments, the orthographic projection of a portion of the first anode contact pad in the second via on the substrate does not substantially overlap with the orthographic projection of a portion of the first anode in the first via on the substrate, and also does not substantially overlap with the orthographic projection of a portion of the first relay electrode in the third via on the substrate; the orthographic projection of a portion of the second anode contact pad in the fifth via on the substrate does not substantially overlap with the orthographic projection of a portion of the second anode in the fourth via on the substrate, and also does not substantially overlap with the orthographic projection of a portion of the second relay electrode in the third via on the substrate. The orthographic projection of a portion of the third anode contact pad in the eighth via on the substrate does not substantially overlap with the orthographic projection of a portion of the third anode in the seventh via on the substrate, and does not substantially overlap with the orthographic projection of a portion of the third relay electrode in the ninth via on the substrate; and the orthographic projection of a portion of the fourth anode contact pad in the eleventh via on the substrate does not substantially overlap with the orthographic projection of a portion of the fourth anode in the tenth via on the substrate, and does not substantially overlap with the orthographic projection of a portion of the fourth relay electrode in the twelfth via on the substrate.

[0192] In some embodiments, each third anode is adjacent to a first corresponding fourth anode, a first corresponding first anode, a first corresponding second anode, a second corresponding first anode, a second corresponding fourth anode, a second corresponding second anode, and a third corresponding first anode, respectively, in a counter-clockwise direction. Optionally, each third anode is adjacent to a first corresponding fourth anode, a first corresponding first anode, a first corresponding second anode, a second corresponding first anode, a second corresponding fourth anode, a second corresponding second anode, and a third corresponding first anode, respectively, in a clockwise direction. Optionally, the shortest distance between each third anode and any one of the first corresponding fourth anode, the first corresponding first anode, the first corresponding second anode, the second corresponding first anode, the virtual line, or the third corresponding first anode is in the range of 2.0 μm to 22 μm, and the virtual line passes through the collinear edges of the second corresponding fourth anode and the second corresponding second anode, respectively. Optionally, the shortest distance between each third anode and the first corresponding fourth anode is less than the shortest distance between each third anode and the third corresponding first anode, less than the shortest distance between each third anode and the first corresponding first anode, less than the shortest distance between each third anode and the second corresponding first anode, less than the shortest distance between each third anode and the virtual line passing through the collinear edges of the second corresponding fourth anode and the second corresponding second anode, and less than the shortest distance between each third anode and the first corresponding second anode. Optionally, the shortest distance between each third anode and the third corresponding first anode is greater than the shortest distance between each third anode and the first corresponding first anode, the shortest distance between each third anode and the first corresponding first anode is greater than the shortest distance between each third anode and the second corresponding first anode, the shortest distance between each third anode and the second corresponding first anode is greater than the shortest distance between each third anode and the virtual line passing through the collinear edges of the second corresponding fourth anode and the second corresponding second anode, the shortest distance between each third anode and the virtual line is greater than the shortest distance between each third anode and the first corresponding second anode, and the shortest distance between each third anode and the first corresponding second anode is greater than the shortest distance between each third anode and the first corresponding fourth anode.Optionally, the shortest distance between each third anode and the first corresponding fourth anode is in the range of 2.0 μm to 5.0 μm; the shortest distance between each third anode and the first corresponding first anode is in the range of 8.0 μm to 20.0 μm; the shortest distance between each third anode and the first corresponding second anode is in the range of 5.0 μm to 15.0 μm; the shortest distance between each third anode and the second corresponding first anode is in the range of 7.0 μm to 17.0 μm; the shortest distance between each third anode and the virtual line passing through the collinear edges from the second corresponding fourth anode and the second corresponding second anode is in the range of 5.0 μm to 16.0 μm; and the shortest distance between each third anode and the third corresponding first anode is in the range of 9.0 μm to 22.0 μm.

[0193] In some embodiments, each first anode is adjacent to a first corresponding second anode, a first corresponding fourth anode, a first corresponding third anode, a second corresponding second anode, a second corresponding third anode, a second corresponding fourth anode, and a third corresponding third anode, respectively, in a counter-clockwise direction. Optionally, each first anode is adjacent to a first corresponding second anode, a first corresponding fourth anode, a first corresponding third anode, a second corresponding second anode, a second corresponding third anode, a second corresponding fourth anode, and a third corresponding third anode, respectively, in a clockwise direction. Optionally, the shortest distance between each first anode and any one of the first corresponding second anode, the first corresponding fourth anode, the first corresponding third anode, the second corresponding second anode, the second corresponding third anode, the second corresponding fourth anode, or the third corresponding third anode is in the range of 3.0 μm to 25 μm. Optionally, the shortest distance between each first anode and the second corresponding fourth anode is less than the shortest distance between each first anode and the second corresponding second anode, less than the shortest distance between each first anode and the first corresponding fourth anode, less than the shortest distance between each first anode and the first corresponding third anode, less than the shortest distance between each first anode and the second corresponding third anode, less than the shortest distance between each first anode and the third corresponding third anode, and less than the shortest distance between each first anode and the first corresponding second anode. Optionally, the shortest distance between each first anode and the corresponding second anode is greater than the shortest distance between each first anode and the corresponding fourth anode, the shortest distance between each first anode and the corresponding fourth anode is greater than the shortest distance between each first anode and the corresponding third anode, the shortest distance between each first anode and the corresponding third anode is greater than the shortest distance between each first anode and the corresponding third anode, the shortest distance between each first anode and the corresponding third anode is greater than the shortest distance between each first anode and the corresponding third anode, the shortest distance between each first anode and the corresponding second anode is greater than the shortest distance between each first anode and the corresponding fourth anode.Optionally, the shortest distance between each first anode and its corresponding second anode is in the range of 3.0 μm to 14.0 μm; the shortest distance between each first anode and its corresponding fourth anode is in the range of 10.0 μm to 24.0 μm; the shortest distance between each first anode and its corresponding third anode is in the range of 9.0 μm to 21.0 μm; the shortest distance between each first anode and its corresponding second anode is in the range of 11.0 μm to 25.0 μm; the shortest distance between each first anode and its corresponding third anode is in the range of 8.0 μm to 20.0 μm; the shortest distance between each first anode and its corresponding fourth anode is in the range of 2.5 μm to 7.5 μm; and the shortest distance between each first anode and its corresponding third anode is in the range of 7.0 μm to 16.0 μm.

[0194] In some embodiments, each fourth anode is adjacent to a corresponding second anode, a first corresponding third anode, a first corresponding first anode, a second corresponding third anode, and a second corresponding first anode in a counter-clockwise direction. Optionally, each fourth anode is adjacent to a corresponding second anode, a first corresponding third anode, a first corresponding first anode, a second corresponding third anode, and a second corresponding first anode in a clockwise direction. Optionally, the shortest distance between each fourth anode and any one of the first corresponding first anode, the second corresponding third anode, or the second corresponding first anode is in the range of 2.0 μm to 25.0 μm. Optionally, the shortest distance between each fourth anode and the second corresponding first anode is greater than the shortest distance between each fourth anode and the first corresponding first anode, and is also greater than the shortest distance between each fourth anode and the second corresponding third anode. Optionally, the distance between each fourth anode and the corresponding second anode, along a virtual line passing through the collinear edges of the respective fourth anodes and the respective second anodes, is in the range of 10.0 μm to 25.0 μm; the shortest distance between the first corresponding third anode and the virtual line passing through the collinear edges of the respective fourth anodes and the respective second anodes is in the range of 6.0 μm to 15.0 μm; the shortest distance between the protrusion of the first corresponding first anode closest to each fourth anode and the virtual line passing through the collinear edges of the respective fourth anodes and the respective second anodes is in the range of 5.0 μm to 16.0 μm; the shortest distance between each fourth anode and the first corresponding first anode is in the range of 2.5 μm to 7.5 μm; the shortest distance between each fourth anode and the second corresponding third anode is in the range of 2.0 μm to 5.0 μm; and the shortest distance between each fourth anode and the second corresponding first anode is in the range of 10.0 μm to 25.0 μm.

[0195] In some embodiments, the method further includes forming a first sub-pixel opening, a second sub-pixel opening, a third sub-pixel opening, and a fourth sub-pixel opening, respectively extending through the pixel defining layer. The first light-emitting layer of the first light-emitting element, the second light-emitting layer of the second light-emitting element, the third light-emitting layer of the third light-emitting element, and the fourth light-emitting layer of the fourth light-emitting element are formed to be connected to the first anode of the first light-emitting element, the second anode of the second light-emitting element, the third anode of the third light-emitting element, and the fourth anode of the fourth light-emitting element, respectively, through the first sub-pixel opening, the second sub-pixel opening, the third sub-pixel opening, and the fourth sub-pixel opening, respectively. Optionally, the shortest distance between the first via and the first sub-pixel opening is in the range of 9.0 μm to 15.0 μm; the shortest distance between the fourth via and the second sub-pixel opening is in the range of 2.0 μm to 6.0 μm; the shortest distance between the seventh via and the third sub-pixel opening is in the range of 4.5 μm to 10.5 μm; and the shortest distance between the tenth via and the fourth sub-pixel opening is in the range of 2.0 μm to 6.0 μm.

[0196] In some embodiments, the orthographic projection of the first anode in each first sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the first capacitor electrode in each first sub-pixel onto the substrate; the orthographic projection of the second anode in each second sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the first capacitor electrode in each second sub-pixel onto the substrate; the orthographic projection of the third anode in each third sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the first capacitor electrode in each third sub-pixel onto the substrate; and the orthographic projection of the fourth anode in each fourth sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the first capacitor electrode in each fourth sub-pixel onto the substrate; the orthographic projection of the first anode in each first sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the second capacitor electrode in each first sub-pixel onto the substrate; the orthographic projection of the second anode in each second sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the second capacitor electrode in each second sub-pixel onto the substrate; in each third sub-pixel... The orthographic projection of the third anode in each sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the second capacitor electrode in each third sub-pixel onto the substrate; and the orthographic projection of the fourth anode in each fourth sub-pixel sp4 onto the substrate at least partially overlaps with the orthographic projection of the second capacitor electrode in each fourth sub-pixel onto the substrate; and the orthographic projection of the first anode in each first sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor in each first sub-pixel onto the substrate; the orthographic projection of the second anode in each second sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor in each second sub-pixel onto the substrate; the orthographic projection of the third anode in each third sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor in each third sub-pixel onto the substrate; and the orthographic projection of the fourth anode in each fourth sub-pixel sp4 onto the substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor in each fourth sub-pixel onto the substrate.

[0197] In some embodiments, the method further includes forming a spacer layer located on the side of the pixel defining layer away from the substrate. Optionally, forming the spacer layer includes forming first spacers arranged in a first array and forming second spacers arranged in a second array; the first array and the second array are formed to be staggered. Optionally, each row of second spacers in the second array is formed between two corresponding rows of first spacers in the first array; each column of second spacers in the second array is formed between two corresponding columns of first spacers in the first array; each row of first spacers in the first array is formed between two corresponding rows of second spacers in the second array; each column of first spacers in the first array is formed between two corresponding columns of second spacers in the second array; a corresponding first spacer of the first spacers is formed between the second anode of the second light-emitting element and the third anode of the third light-emitting element; and a corresponding second spacer of the second spacers is formed between the third anode and the fourth anode of the fourth light-emitting element.

[0198] In some embodiments, two adjacent first spacers in each row of first spacers are separated by eight sub-pixels; two adjacent second spacers in each row of second spacers are separated by eight sub-pixels; two adjacent first spacers in each column of first spacers are separated by six sub-pixels; and two adjacent second spacers in each column of second spacers are separated by six sub-pixels.

[0199] In some embodiments, the plurality of sub-pixels are formed as an array of multiple rows along a first direction and multiple columns along a second direction; each row has a first spacer along the first direction; each row has a second spacer along the first direction; each column has a first spacer along the second direction; and each column has a second spacer along the second direction.

[0200] In some embodiments, the method further includes forming a first light-emitting layer located on the side of the first anode of the first light-emitting element away from the substrate; forming a second light-emitting layer located on the side of the second anode away from the substrate; forming a third light-emitting layer located on the side of the third anode away from the substrate; and forming a fourth light-emitting layer located on the side of the fourth anode away from the substrate; optionally, the orthographic projection of the third light-emitting layer on the substrate partially overlaps with the orthographic projection of a corresponding first spacer on the substrate; the orthographic projection of the second light-emitting layer on the substrate partially overlaps with the orthographic projection of the corresponding first spacer on the substrate; a first edge of the third light-emitting layer passing through the corresponding first spacer is substantially parallel to a first centerline of the corresponding first spacer; and a second edge of the second light-emitting layer passing through the corresponding first spacer is substantially parallel to the first centerline of the corresponding first spacer.

[0201] In some embodiments, the first edge is spaced apart from the first center line by a first distance along a direction perpendicular to the first center line; the second edge is spaced apart from the first center line by a second distance along the same direction perpendicular to the first center line; and the average value of the first distance along the first edge and the average value of the second distance along the second edge are substantially the same. Optionally, the first edge substantially overlaps with the first center line. Optionally, the second edge substantially overlaps with the first center line.

[0202] In some embodiments, the orthographic projection of the third light-emitting layer on the substrate partially overlaps with the orthographic projection of the corresponding second spacer on the substrate; the orthographic projection of the fourth light-emitting layer on the substrate partially overlaps with the orthographic projection of the corresponding second spacer on the substrate; the third edge of the third light-emitting layer passing through the corresponding second spacer is substantially parallel to the second centerline of the corresponding second spacer; and the fourth edge of the fourth light-emitting layer passing through the corresponding second spacer is substantially parallel to the second centerline of the corresponding second spacer.

[0203] In some embodiments, the third edge is spaced a third distance from the second center line along a direction perpendicular to the second center line; the fourth edge is spaced a fourth distance from the second center line along the same direction perpendicular to the second center line; and the average value of the third distance along the third edge and the average value of the fourth distance along the fourth edge are substantially the same. Optionally, the third edge substantially overlaps with the second center line. Optionally, the fourth edge substantially overlaps with the second center line.

[0204] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. An array substrate, comprising: Substrate; A pixel defining layer on the substrate, the pixel defining layer defining a sub-pixel opening; A spacer layer located on the side of the pixel defining layer away from the substrate, wherein the spacer layer includes a first spacer disposed in a first array and a second spacer disposed in a second array; Adjacent spacers along the column direction are spaced apart by a column distance; Adjacent spacers along the row direction are spaced apart by a row distance; The column distance is greater than the row distance; The second sub-pixel opening, the third sub-pixel opening, and the fourth sub-pixel opening extend through the pixel defining layer, wherein the second light-emitting layer, the third light-emitting layer, and the fourth light-emitting layer are respectively connected to the second anode, the third anode, and the fourth anode through the second sub-pixel opening, the third sub-pixel opening, and the fourth sub-pixel opening; A corresponding first spacer in the first spacer is located between the second sub-pixel opening and the third sub-pixel opening; and a corresponding second spacer in the second spacer is located between the third sub-pixel opening and the fourth sub-pixel opening; It also includes multiple pixel driving circuits in multiple sub-pixels, the multiple pixel driving circuits being configured to drive multiple light-emitting elements respectively; Each pixel driving circuit in the plurality of pixel driving circuits includes a plurality of transistors and a storage capacitor. The storage capacitor includes a first capacitor electrode, a second capacitor electrode electrically connected to a corresponding voltage supply line, and an insulating layer between the first capacitor electrode and the second capacitor electrode. The array substrate includes: The semiconductor material layer on the substrate; and The node connection line is located in the same layer as the corresponding voltage supply line. The node connection line is connected to the first capacitor electrode through a first through-hole and to the semiconductor material layer through a second through-hole. Wherein, the orthographic projection of the first anode of the first light-emitting element in the corresponding first sub-pixel onto the substrate overlaps at least partially with the orthographic projection of the node connection line in the corresponding first sub-pixel onto the substrate; The orthographic projection of the second anode of the second light-emitting element in the corresponding second sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the node connection line in the corresponding second sub-pixel onto the substrate. The orthographic projection of the third anode of the third light-emitting element in the corresponding third sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the node connection line in the corresponding third sub-pixel onto the substrate; and The orthographic projection of the fourth anode of the fourth light-emitting element in the corresponding fourth sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the node connecting line in the corresponding fourth sub-pixel onto the substrate.

2. The array substrate according to claim 1, wherein, The ratio of the column distance to the row distance is in the range of 1.1 to 2.

0.

3. The array substrate according to claim 1, wherein, Adjacent first spacers along the column direction are spaced apart by a first column distance from each other; Adjacent second spacers along the column direction are spaced apart by a second column distance from each other; Adjacent first spacers along the row direction are spaced apart by a first row distance; Adjacent second spacers along the row direction are spaced apart by a second row distance; The ratio of the distance in the first column to the distance in the second column is in the range of 0.8 to 0.2; and The ratio of the distance of the first row to the distance of the second row is in the range of 0.8 to 0.

2.

4. The array substrate according to claim 1, wherein, The ratio of the area of ​​the first spacer to the area of ​​the second spacer is in the range of 0.8 to 0.

2.

5. The array substrate according to claim 1, wherein, The ratio of the first dimension to the second dimension of each spacer is in the range of 0.8 to 0.

2. Wherein, the first dimension is the dimension of each spacer along a direction substantially parallel to the edge of the opening adjacent to each spacer; and The second dimension is the dimension of each spacer along a direction substantially perpendicular to the edge of the opening adjacent to each spacer.

6. The array substrate according to claim 1, wherein, Multiple subpixels are arranged in an array of multiple rows along a first direction and multiple columns along a second direction; The first spacers in each row are along the first direction; Each row of second spacers is along the first direction; The first spacers in each column are along the second direction; as well as Each column of second spacers is along the second direction; Two adjacent first spacers in each row are separated by twice the distance between the first anodes, which is the distance along the first direction and between the centers of the two most adjacent third anodes of the two most adjacent third light-emitting elements along the first direction. Two adjacent second spacers in each row are separated by twice the distance between the first anodes; Two adjacent first spacers in each column are separated by a distance three times the distance between second anodes, which is the distance along the second direction and between the centers of the two most adjacent third anodes of the two most adjacent third light-emitting elements along the second direction. as well as Two adjacent second spacers in each column are separated by a distance three times the distance between the second anodes.

7. The array substrate according to claim 6, wherein, The orthographic projection of the third light-emitting layer on the substrate partially overlaps with the orthographic projection of the corresponding first spacer on the substrate. The orthographic projection of the second light-emitting layer on the substrate partially overlaps with the orthographic projection of the corresponding first spacer on the substrate; The first edge of the third light-emitting layer passing through the corresponding first spacer is substantially parallel to the first centerline of the corresponding first spacer; and The second edge of the second light-emitting layer passing through the corresponding first spacer is substantially parallel to the first centerline of the corresponding first spacer.

8. The array substrate according to claim 7, wherein, The first edge is spaced a first distance from the first center line along a direction perpendicular to the first center line; The second edge is spaced a second distance from the first centerline along a direction perpendicular to the first centerline; and The average value of the first distance along the first edge is substantially the same as the average value of the second distance along the second edge.

9. The array substrate according to claim 7, wherein, The orthographic projection of the third light-emitting layer on the substrate partially overlaps with the orthographic projection of the corresponding second spacer on the substrate; The orthogonal projection of the fourth light-emitting layer on the substrate partially overlaps with the orthogonal projection of the corresponding second spacer on the substrate. The third edge of the third light-emitting layer, passing through the corresponding second spacer, is substantially parallel to the second center line of the corresponding second spacer; as well as The fourth edge of the fourth light-emitting layer, passing through the corresponding second spacer, is substantially parallel to the second centerline of the corresponding second spacer.

10. The array substrate according to claim 9, wherein, The third edge is spaced a third distance from the second center line along a direction perpendicular to the second center line; The fourth edge is spaced a fourth distance from the second centerline along a direction perpendicular to the second centerline; and The average value of the third distance along the third edge is substantially the same as the average value of the fourth distance along the fourth edge.

11. The array substrate according to claim 1, wherein, The plurality of transistors includes a driving transistor; The orthogonal projection of the first anode in the corresponding first sub-pixel onto the substrate covers the orthogonal projection of a portion of the node connection line in the corresponding first sub-pixel at the location connected to the first capacitor electrode onto the substrate. The orthogonal projection of the second anode in the corresponding second sub-pixel onto the substrate covers the orthogonal projection of a portion of the node connection line in the corresponding second sub-pixel at the location connected to the first capacitor electrode onto the substrate. The orthogonal projection of the third anode in the corresponding third sub-pixel onto the substrate covers the orthogonal projection of a portion of the node connection line in the corresponding third sub-pixel at the location connected to the first capacitor electrode onto the substrate. as well as The orthographic projection of the fourth anode in the corresponding fourth sub-pixel onto the substrate covers the orthographic projection of a portion of the node connection line in the corresponding fourth sub-pixel at the location connected to the first capacitor electrode onto the substrate.

12. The array substrate according to claim 1, wherein, The orthographic projection of the third anode on the substrate covers the orthographic projection of the source of the third transistor in the corresponding third sub-pixel on the substrate, overlaps with the orthographic projection of the active layer of the third transistor in the corresponding third sub-pixel on the substrate, and overlaps with the orthographic projection of the active layer of the third transistor in the corresponding fourth sub-pixel on the substrate.

13. The array substrate according to claim 12, wherein, The orthographic projection of the first anode on the substrate partially overlaps with the source of the third transistor in the corresponding first sub-pixel on the substrate, and also partially overlaps with the orthographic projection of the active layer of the third transistor in the corresponding first sub-pixel on the substrate.

14. The array substrate according to claim 12, wherein, The orthographic projection of the fourth anode onto the substrate overlaps with the orthographic projection of the source of the third transistor in the corresponding second sub-pixel onto the substrate, and also overlaps with the orthographic projection of the active layer of the third transistor in the corresponding second sub-pixel onto the substrate.

15. The array substrate according to claim 1, further comprising: A gate insulating layer is located on the side of the semiconductor material layer away from the substrate. An insulating layer located on the side of the gate insulating layer away from the substrate; An interlayer dielectric layer is located on the side of the insulating layer away from the gate insulating layer; A relay electrode layer is located on the side of the interlayer dielectric layer away from the insulating layer; A first planarization layer is located on the side of the relay electrode layer away from the interlayer dielectric layer; An anode contact pad layer is located on the side of the first planarization layer away from the interlayer dielectric layer; and A second planarization layer is located on the side of the anode contact pad layer away from the first planarization layer; and The pixel defining layer is located on the side of the second planarization layer away from the substrate. Each anode is located on the side of the second planarization layer away from the first planarization layer; and each light-emitting layer is located on the side of each anode away from the second planarization layer. In each first sub-pixel, the first anode is connected to the first anode contact pad through a first via extending through the second planarization layer, the first anode contact pad is connected to the first relay electrode through a second via extending through the first planarization layer, and the first relay electrode is connected to the drain of the fifth transistor in each first sub-pixel through a third via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer. In each second sub-pixel, the second anode is connected to the second anode contact pad through a fourth via extending through the second planarization layer, the second anode contact pad is connected to the second relay electrode through a fifth via extending through the first planarization layer, and the second relay electrode is connected to the drain of the fifth transistor in each second sub-pixel through a sixth via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer. In each third sub-pixel, the third anode is connected to the third anode contact pad via a seventh via extending through the second planarization layer; the third anode contact pad is connected to the third relay electrode via an eighth via extending through the first planarization layer; and the third relay electrode is connected to the drain of the fifth transistor in each third sub-pixel via a ninth via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer. In each fourth sub-pixel, the fourth anode is connected to the fourth anode contact pad through a tenth via extending through the second planarization layer, the fourth anode contact pad is connected to the fourth relay electrode through an eleventh via extending through the first planarization layer, and the fourth relay electrode is connected to the drain of the fifth transistor in each fourth sub-pixel through a twelfth via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer.

16. The array substrate according to claim 15, wherein, The orthographic projection of a portion of the first anode contact pad in the second via on the substrate does not substantially overlap with the orthographic projection of a portion of the first anode in the first via on the substrate, and also does not substantially overlap with the orthographic projection of a portion of the first relay electrode in the third via on the substrate. The orthographic projection of a portion of the second anode contact pad in the fifth via on the substrate does not substantially overlap with the orthographic projection of a portion of the second anode in the fourth via on the substrate, and also does not substantially overlap with the orthographic projection of a portion of the second relay electrode in the sixth via on the substrate. The orthographic projection of a portion of the third anode contact pad in the eighth via on the substrate does not substantially overlap with the orthographic projection of a portion of the third anode in the seventh via on the substrate, and also does not substantially overlap with the orthographic projection of a portion of the third relay electrode in the ninth via on the substrate; and The orthographic projection of a portion of the fourth anode contact pad in the eleventh via on the substrate does not substantially overlap with the orthographic projection of a portion of the fourth anode in the tenth via on the substrate, and also does not substantially overlap with the orthographic projection of a portion of the fourth relay electrode in the twelfth via on the substrate.

17. The array substrate according to claim 1, wherein, The ratio of the number of subpixels to the number of spacers is in the range of 28:1 to 20:

1.

18. A display device comprising an array substrate according to claim 1 and an integrated circuit connected to the array substrate.

Images