Solid-state imaging element, imaging device, and control method of solid-state imaging element

Abstract

The present invention provides a solid-state imaging element in which all pixels are exposed simultaneously, the solid-state imaging element having improved PLS tolerance. A front-stage transfer transistor transfers charge from a photoelectric conversion element to a front-stage charge retention region and a rear-stage charge retention region having different capacities. A rear-stage transfer transistor transfers charge from the rear-stage charge retention region to a floating diffusion region. An intermediate transfer transistor transfers charge remaining in the front-stage charge retention region after the charge has been transferred from the rear-stage charge retention region to the floating diffusion region via the front-stage charge retention region.

Description

Technical Field

[0001] The present technology relates to a solid-state imaging element, and more particularly to a solid-state imaging element that performs analog-to-digital (AD) conversion for each column, an imaging device, and a control method for the solid-state imaging element. Background Art

[0002] Typically, in solid-state imaging devices, in order to miniaturize pixels, a column analog-to-digital converter (ADC) method is used, in which an ADC is configured for each column outside the pixel array unit to sequentially read out pixel signals row by row. In this column ADC method, when exposure is performed using a rolling shutter method in which exposure is started sequentially row by row, rolling shutter distortion may occur. Therefore, in order to implement a global shutter method in which exposure is started simultaneously for all pixels, a solid-state imaging device has been proposed in which a charge retention unit and a transfer transistor for transferring charge to the charge retention unit are added to the pixel (for example, see Patent Document 1).

[0003] List of citations

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2019-169668 Summary of the Invention

[0006] Technical problem to be solved by the invention

[0007] In the above-mentioned prior art, when the exposure of all pixels is completed, each pixel holds a charge corresponding to the exposure amount in the charge holding unit, and the ADC of each column sequentially reads out a signal corresponding to the charge amount, thereby attempting to implement a global shutter method. However, in the above-mentioned solid-state imaging element, light leaking from the photoelectric conversion element to the charge holding unit may cause undesirable image artifacts. Resistance to this phenomenon is called PLS (parasitic light sensitivity) resistance. In the above-mentioned solid-state imaging element, measures are taken to shield the charge holding unit with a light-shielding layer such as a metal wiring, but the charge of the photoelectric conversion element needs to be transferred to the charge holding unit via a transfer transistor. For this reason, the charge holding unit must be configured adjacent to the photoelectric conversion element, and it is difficult to prevent light from leaking from the photoelectric conversion element to the charge holding unit.

[0008] The present technology has been created in view of such circumstances, and its object is to improve PLS resistance in a solid-state imaging element in which all pixels are exposed simultaneously.

[0009] Solutions to technical problems

[0010] The present technology is proposed to solve the above-mentioned problems. In its first aspect, a solid-state imaging element and a control method thereof are provided. The solid-state imaging element includes: a photoelectric conversion element; a front-stage charge retention region; a rear-stage charge retention region having a different capacity from the front-stage charge retention region; a front-stage transfer transistor that transfers charge from the photoelectric conversion element to the front-stage charge retention region and the rear-stage charge retention region; a rear-stage transfer transistor that transfers charge from the rear-stage charge retention region to a floating diffusion region; an intermediate transfer transistor that transfers charge remaining in the front-stage charge retention region after the charge has been transferred from the rear-stage charge retention region to the floating diffusion region via the front-stage charge retention region; and a light shielding wall that prevents charge from leaking from the photoelectric conversion element to the rear-stage charge retention region. This has the effect of generating pixel signals at high illumination and generating pixel signals at low illumination.

[0011] In addition, in the first aspect, the front-stage charge holding region and the rear-stage charge holding region can be impurity diffusion regions having the same polarity, and a predetermined impurity diffusion region having a polarity different from that of the front-stage charge holding region and the rear-stage charge holding region can be configured between the front-stage charge holding region and the rear-stage charge holding region.

[0012] Furthermore, in the first aspect, the preceding charge holding region and the succeeding charge holding region may be formed in the same impurity diffusion region. This has the effect of reducing the impurity diffusion region.

[0013] Furthermore, in the first aspect, the impurity concentration of the region between the preceding charge holding region and the succeeding charge holding region in the impurity diffusion region is different from the impurity concentration of the surrounding region, which has the effect of increasing the potential barrier.

[0014] Furthermore, in the first aspect, an adjustment transistor may be provided to adjust the height of the potential barrier between the preceding charge retention region and the succeeding charge retention region. This has the effect of adjusting the height of the potential barrier.

[0015] Furthermore, in the first aspect, a vertical scanning circuit may be provided that controls each of the preceding transfer transistor, the succeeding transfer transistor, and the intermediate transfer transistor to be turned on or off. The vertical scanning circuit may turn on the preceding transfer transistor and the intermediate transfer transistor while turning off the succeeding transfer transistor to transfer charge to the preceding charge retention region and the succeeding charge retention region, may turn on the succeeding transfer transistor while turning off the preceding transfer transistor and the intermediate transfer transistor to transfer charge from the succeeding charge retention region to the floating diffusion region, and may turn on the intermediate transfer transistor and the succeeding transfer transistor to transfer charge from the preceding charge retention region to the floating diffusion region. This has the effect of sequentially transferring charge from each of the preceding charge retention region and the succeeding charge retention region.

[0016] Furthermore, in the first aspect, a signal processing circuit may be provided that compares a first pixel signal corresponding to the amount of charge transferred from the subsequent charge holding region and a second pixel signal corresponding to the amount of charge transferred from the preceding and subsequent charge holding regions with a predetermined threshold value, and selects one of the first and second pixel signals based on the comparison result. This has the effect of reducing the PLS of low-illuminance signals.

[0017] Furthermore, in the first aspect, the photoelectric conversion element may be formed on the front surface with wiring, of the two surfaces of the predetermined semiconductor substrate. This has the effect of improving image quality in the surface illumination type solid-state imaging element.

[0018] In the first aspect, the photoelectric conversion element may be formed on the back surface of the semiconductor substrate, which is opposite to the front surface with wiring. This has the effect of improving image quality in the back-illuminated solid-state imaging element.

[0019] In addition, in the first aspect, the photoelectric conversion element may include a first photoelectric conversion element and a second photoelectric conversion element, the front-stage charge holding region may include a first front-stage charge holding region and a second front-stage charge holding region, the rear-stage charge holding region may include a first rear-stage charge holding region and a second rear-stage charge holding region, the front-stage transfer transistor may include a first front-stage transfer transistor and a second front-stage transfer transistor, the intermediate transfer transistor may include a first intermediate transfer transistor and a second intermediate transfer transistor, and the rear-stage transfer transistor may include a first rear-stage transfer transistor and a second rear-stage transfer transistor. This has the effect of improving image quality in a solid-state imaging element in which a plurality of pixels share a floating diffusion region.

[0020] Furthermore, in the first aspect, a charge discharge transistor for discharging charge from the photoelectric conversion element, a reset transistor for initializing the floating diffusion region, an amplifier transistor for amplifying a signal corresponding to the amount of charge transferred to the floating diffusion region, and a select transistor for outputting the amplified signal as a pixel signal in response to a predetermined select signal may be further provided. This has the effect of reading out pixel signals row by row.

[0021] In addition, a second aspect of the present technology is an imaging device including: a photoelectric conversion element; a front-stage charge retention region; a rear-stage charge retention region having a different capacity from the front-stage charge retention region; a front-stage transfer transistor that transfers charge from the photoelectric conversion element to the front-stage charge retention region and the rear-stage charge retention region; a rear-stage transfer transistor that transfers charge from the rear-stage charge retention region to a floating diffusion region; an intermediate transfer transistor that transfers charge remaining in the front-stage charge retention region after the charge has been transferred from the rear-stage charge retention region to the floating diffusion region via the front-stage charge retention region; a light shielding wall that prevents charge from leaking from the photoelectric conversion element to the rear-stage charge retention region; and a signal processing circuit that processes a pixel signal corresponding to the amount of charge transferred to the floating diffusion region. This has the effect of processing both pixel signals at high illumination and pixel signals at low illumination. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a block diagram showing a configuration example of an imaging device according to a first embodiment of the present technology.

[0023] Figure 2 It is a block diagram showing a configuration example of a solid-state imaging element according to a first embodiment of the present technology.

[0024] Figure 3 is a circuit diagram showing a configuration example of a pixel according to the first embodiment of the present technology.

[0025] Figure 4 is an example of a cross-sectional view of a pixel according to the first embodiment of the present technology.

[0026] Figure 5 is an example of a potential diagram of a pixel according to the first embodiment of the present technology.

[0027] Figure 6 It is a plan view showing an example of element layout within a pixel according to the first embodiment of the present technology.

[0028] Figure 7 is an example of a cross-sectional view taken along line AB according to the first embodiment of the present technology.

[0029] Figure 8is an example of a cross-sectional view taken along line CD according to the first embodiment of the present technology.

[0030] Figure 9 is an example of a cross-sectional view taken along line EF according to the first embodiment of the present technology.

[0031] Figure 10 It is a block diagram showing a configuration example of a load MOS circuit block and a column signal processing circuit according to the first embodiment of the present technology.

[0032] Figure 11 is a timing chart illustrating an example of a global shutter operation of the solid-state imaging element according to the first embodiment of the present technology.

[0033] Figure 12 is an example showing a potential diagram until ST reset when the illuminance is low according to the first embodiment of the present technology.

[0034] Figure 13 is an example showing a potential diagram until the charge holding region separates when the illuminance is low according to the first embodiment of the present technology.

[0035] Figure 14 is an example showing a potential diagram until ST reset when the illuminance is high according to the first embodiment of the present technology.

[0036] Figure 15 is an example showing a potential diagram until the charge holding region separates when the illuminance is high according to the first embodiment of the present technology.

[0037] Figure 16 is a timing chart showing an example of an operation of reading out one row when the illuminance is low according to the first embodiment of the present technology.

[0038] Figure 17 is an example of a potential diagram at the time of readout when the illuminance is low according to the first embodiment of the present technology.

[0039] Figure 18 is a timing chart showing an example of an operation of reading out one row when the illuminance is high according to the first embodiment of the present technology.

[0040] Figure 19 is an example of a potential diagram at the time of readout when the illuminance is high according to the first embodiment of the present technology.

[0041] Figure 20 is a flowchart illustrating an example of the operation of the solid-state imaging element according to the first embodiment of the present technology.

[0042] Figure 21 is an example of a cross-sectional view taken along line AB according to the first modification example of the first embodiment of the present technology.

[0043] Figure 22 is an example of a cross-sectional view taken along line CD according to the first modification example of the first embodiment of the present technology.

[0044] Figure 23 is an example of a cross-sectional view taken along line EF according to the first modification example of the first embodiment of the present technology.

[0045] Figure 24 is a circuit diagram illustrating a configuration example of a pixel block according to a second modification example of the first embodiment of the present technology.

[0046] Figure 25 It is a plan view showing an example of element layout within a pixel block according to a second modification example of the first embodiment of the present technology.

[0047] Figure 26 is a circuit diagram showing a configuration example of a pixel according to a second embodiment of the present technology.

[0048] Figure 27 is an example of a cross-sectional view of a pixel according to a second embodiment of the present technology.

[0049] Figure 28 is an example of a potential diagram of a pixel according to the second embodiment of the present technology.

[0050] Figure 29 is a circuit diagram showing a configuration example of a pixel according to a third embodiment of the present technology.

[0051] Figure 30 is an example of a cross-sectional view of a pixel according to a third embodiment of the present technology.

[0052] Figure 31 is an example of a potential diagram of a pixel according to the third embodiment of the present technology.

[0053] Figure 32 is a timing chart illustrating an example of a global shutter operation of the solid-state imaging element according to the third embodiment of the present technology.

[0054] Figure 33 is a timing chart showing an example of an operation of reading out one row when the illuminance is low according to the third embodiment of the present technology.

[0055] Figure 34 is an example of a potential diagram at the time of readout when the illuminance is low according to the third embodiment of the present technology.

[0056] Figure 35 is a timing chart showing an example of an operation of reading out one row when the illuminance is high according to the third embodiment of the present technology.

[0057] Figure 36is an example of a potential diagram at the time of readout when the illuminance is high according to the third embodiment of the present technology.

[0058] Figure 37 This is a block diagram showing a schematic configuration example of a vehicle control system.

[0059] Figure 38 is an explanatory diagram illustrating an example of an installation position of an imaging unit. DETAILED DESCRIPTION

[0060] Hereinafter, a mode for implementing the present technology (hereinafter referred to as an embodiment) will be described. The description will be made in the following order.

[0061] 1. First Embodiment (Example of Transferring Charges to a Pair of Charge Retention Regions)

[0062] 2. Second Embodiment (Example in which a pair of charge retention regions are formed in one n-layer and charges are transferred to the pair of charge retention regions)

[0063] 3. Third Embodiment (Example of Adjusting Barrier Height and Transferring Charges to a Pair of Charge Retention Regions)

[0064] 4. Application examples for mobile objects

[0065] <1. First Implementation Method>

[0066] [Configuration Example of Imaging Device]

[0067] Figure 1 This is a block diagram illustrating an example configuration of an imaging device 100 according to a first embodiment of the present technology. The imaging device 100 is a device for capturing image data and includes an imaging lens 110, a solid-state imaging element 200, a recording unit 120, and an imaging control unit 130. As the imaging device 100, for example, a digital camera or an electronic device with an imaging function (such as a smartphone or a personal computer) is assumed.

[0068] The solid-state imaging element 200 captures image data under the control of the imaging control unit 130. The solid-state imaging element 200 supplies the image data to the recording unit 120 via the signal line 209.

[0069] The imaging lens 110 collects light and guides it to the solid-state imaging element 200. The imaging control unit 130 controls the solid-state imaging element 200 to capture image data. The imaging control unit 130 supplies an image control signal including, for example, a vertical synchronization signal VSYNC to the solid-state imaging element 200 via a signal line 139. The recording unit 120 records the image data.

[0070] Here, the vertical synchronization signal VSYNC is a signal indicating imaging timing, and a periodic signal having a certain frequency (such as 60 Hz) is used as the vertical synchronization signal VSYNC.

[0071] In addition, although the imaging device 100 records image data, the image data may be transmitted to the outside of the imaging device 100. In this case, an external interface for transmitting image data is also provided. Alternatively, the imaging device 100 may further display the image data. In this case, a display unit is also provided.

[0072] [Configuration Example of Solid-State Imaging Element]

[0073] Figure 2 This is a block diagram showing an example configuration of a solid-state imaging element 200 according to a first embodiment of the present technology. The solid-state imaging element 200 includes a vertical scanning circuit 211, a pixel array unit 212, a timing control circuit 213, a digital-to-analog converter (DAC) 214, a load MOS circuit block 250, and a column signal processing circuit 260. A plurality of pixels 220 are arranged in a two-dimensional lattice pattern in the pixel array unit 212.

[0074] Hereinafter, a group of pixels 220 arranged in the horizontal direction is referred to as a “row”, and a group of pixels 220 arranged in a direction perpendicular to the row is referred to as a “column”.

[0075] The timing control circuit 213 controls the operation timing of the vertical scanning circuit 211 , the DAC 214 , and the column signal processing circuit 260 in synchronization with the vertical synchronization signal VSYNC from the imaging control unit 130 .

[0076] The DAC 214 generates an analog reference signal that fluctuates over time through digital-to-analog (DA) conversion. For example, a ramp signal with a sawtooth waveform is used as the reference signal. The DAC 214 supplies the generated reference signal to the column signal processing circuit 260.

[0077] The vertical scanning circuit 211 sequentially selects and drives each row and outputs an analog pixel signal. The pixel 220 performs photoelectric conversion on incident light to generate an analog pixel signal. The pixel 220 supplies the pixel signal to the column signal processing circuit 260 via the load MOS circuit block 250.

[0078] The load MOS circuit block 250 is provided with a MOS transistor for supplying a constant current for each column.

[0079] The column signal processing circuit 260 performs signal processing such as AD conversion and high dynamic range (HDR) synthesis on the pixel signal for each column. The column signal processing circuit 260 supplies image data including the processed signal to the recording unit 120. The column signal processing circuit 260 is an example of a signal processing circuit described in the claims.

[0080] [Pixel Configuration Example]

[0081] Figure 3 This is a circuit diagram showing an example configuration of a pixel 220 according to the first embodiment of the present technology. The pixel 220 includes a charge discharge transistor 221, a photoelectric conversion element 222, transfer transistors 223, 225, and 227, charge holding regions 224 and 226, and a floating diffusion region 228. Furthermore, the pixel 220 includes a reset transistor 231, an amplification transistor 232, and a selection transistor 233.

[0082] The capacities of charge retention regions 224 and 226 are different from each other. For example, the capacity of charge retention region 224 is larger than the capacity of charge retention region 226. Charge retention region 224 is an example of a front-stage charge retention region described in the claims, while charge retention region 226 is an example of a rear-stage charge retention region described in the claims.

[0083] The transfer transistors 223, 225, and 227 are connected in series between the photoelectric conversion element 222 and the floating diffusion region 228. In addition, the charge holding region 224 is inserted between the connection node of the transfer transistors 223 and 225 and the ground node, and the charge holding region 226 is inserted between the connection node of the transfer transistors 225 and 227 and the ground node.

[0084] The charge discharge transistor 221 discharges charges from the photoelectric conversion element 222 in accordance with a control signal OFG from the vertical scanning circuit 211. This operation is hereinafter referred to as "photodiode (PD) reset."

[0085] Here, for all pixels, the vertical scanning circuit 211 turns off the transfer transistor 223 at the start of exposure and turns on the transfer transistors 225 and 227 and the reset transistor 231 at the end of exposure. This initializes the charge retention regions 224 and 226 and the floating diffusion region 228. This operation is hereinafter referred to as "storage (ST) reset." Immediately after the ST reset, the vertical scanning circuit 211 turns off the transfer transistor 227 and the reset transistor 231 and turns on the transfer transistors 223 and 225. This transfers charge from the photoelectric conversion element 222 to the charge retention regions 224 and 226.

[0086] Immediately after charge is transferred from the photoelectric conversion element 222 to the charge holding regions 224 and 226, the vertical scanning circuit 211 turns off the transfer transistors 223 and 225. This separates the charge holding regions 224 and 226 from each other. Following this separation, the vertical scanning circuit 211 turns on the transfer transistor 227. This transfers charge from the charge holding region 226 to the floating diffusion region 228, and an analog pixel signal corresponding to the amount of charge in the charge holding region 226 is A / D converted. The vertical scanning circuit 211 then turns on the transfer transistors 225 and 227. This converts the analog pixel signal corresponding to the amount of charge in the charge holding regions 224 and 226 into A / D.

[0087] The photoelectric conversion element 222 generates electric charges (electrons, etc.) by performing photoelectric conversion on incident light.

[0088] The transfer transistor 223 transfers the charge from the photoelectric conversion element 222 to the charge holding regions 224 and 226 according to the transfer signal TX1 from the vertical scanning circuit 211. The transfer transistor 223 is an example of a previous-stage transfer transistor described in the claims.

[0089] The transfer transistor 225 transfers the charge from the charge holding region 224 to the charge holding region 226 in response to the transfer signal TX2 from the vertical scanning circuit 211. As described above, after transferring the charge from the charge holding region 226 to the floating diffusion region 228, the vertical scanning circuit 211 turns on the transfer transistors 225 and 227. Consequently, the charge remaining in the charge holding region 224 is transferred to the floating diffusion region 228 via the charge holding region 226 and the turned-on transfer transistor 227. The transfer transistor 225 is an example of the intermediate transfer transistor described in the claims.

[0090] The transfer transistor 227 transfers charges from the charge holding region 226 to the floating diffusion region 228 in accordance with a transfer signal TG from the vertical scanning circuit 211. The transfer transistor 227 is an example of a subsequent-stage transfer transistor described in the claims.

[0091] The reset transistor 231 extracts charge from the floating diffusion region 228 to initialize it according to the reset signal RST from the vertical scanning circuit 211. The vertical scanning circuit 211 turns on the reset transistor 231 while turning off the transfer transistors 225 and 227, so that it can initialize only the floating diffusion region 228. This operation is called "floating diffusion (FD) reset."

[0092] The amplifier transistor 232 amplifies an analog signal corresponding to the amount of charge in the floating diffusion region 228. The selection transistor 233 outputs the amplified analog signal to the vertical signal line 239 as a pixel signal in accordance with the selection signal SEL from the vertical scanning circuit 211.

[0093] Figure 4 2 is an example of a cross-sectional view of a pixel 220 according to the first embodiment of the present technology. A p-type semiconductor substrate 320 in which p-type impurities are diffused is stacked on an n-type semiconductor substrate 310. On the front surface of the p-type semiconductor substrate 320, an n-type semiconductor substrate 310 is formed. + Layers 331, 335 and 336 and p + Layers 337, 338, and 339. In addition, n layers 332, 333, and 334 as diffusion regions of n-type impurities are formed on the p + Below layers 337, 338 and 339. These p + Layers 337 , 338 , and 339 serve as pinning layers and are used to fill incomplete junctions between atoms at the silicon interface with holes to improve dark current and fix the interface potential.

[0094] Furthermore, on the front surface of the p-type semiconductor substrate 320, a gate electrode 341 is provided across the n-type semiconductor substrate 320 via an oxide film. + Layer 331 and p + The gate electrode 342 is provided in the region of the layer 337 via an oxide film. + Layer 337 and p + The gate electrode 343 is provided in the region of the layer 338 via an oxide film. + Layer 338 and p + The gate electrode 344 is provided in the region of the layer 339 via an oxide film across the p + Layer 339 and n + The gate electrode 345 is provided in the region of the layer 335 via an oxide film across the n + Layer 335 and n + in the region of layer 336 .

[0095] The control signal OFG, the transfer signal TX1, the transfer signal TX2, the transfer signal TG, and the reset signal RST are input to the gate electrodes 341, 342, 343, 344, and 345, respectively. + Layers 331 and 336 are connected to a node of a power supply voltage VDD.

[0096] n + layer 331, p-type semiconductor substrate 320, p +Layer 337 and gate electrode 341 function as charge discharge transistor 221. Similarly, gate electrodes 342, 343, 344, and 345, along with the semiconductor regions thereunder, function as transfer transistor 223, transfer transistor 225, transfer transistor 227, and reset transistor 231, respectively.

[0097] N-layer 332 functions as photoelectric conversion element 222. N-layers 333 and 334 function as charge holding regions 224 and 226. As shown in the figure, region 321 between n-layer 333 (charge holding region 224) and n-layer 334 (charge holding region 226) is a diffusion region containing p-type impurities of a different polarity (in other words, p-type semiconductor substrate 320).

[0098] The voltage level applied to the gate of each transistor, such as the charge discharge transistor 221, and its control timing can be independently set. When a particular transistor is on, the vertical scanning circuit 211 applies a positive voltage to the gate of that transistor to lower the potential beneath the gate. Furthermore, when the transistor is off, the vertical scanning circuit 211 applies a ground or negative voltage to that transistor. When the voltage applied to the gate is negative, holes are attracted by the electric field beneath the gate and accumulate at the silicon interface, achieving an effect similar to the pinning layer described above.

[0099] Figure 5 : This is an example of a potential diagram of the pixel 220 according to the first embodiment of the present technology. The solid lines in the figure represent the potentials when the charge discharge transistor 221, transfer transistors 223, 225, and 227, and reset transistor 231 are off. Furthermore, the thin dashed lines represent the potentials when each of the charge discharge transistor 221 and transfer transistor 223 is on. The dashed-dotted line represents the potential when the transfer transistor 225 is on. The thick dashed line represents the potential when the transfer transistor 227 is on. Reference symbol ST1 in the figure represents the charge holding region 224, and reference symbol ST2 in the figure represents the charge holding region 226. Reference symbol FD represents the floating diffusion region 228.

[0100] As shown in the figure, when the transfer transistor 223 is turned off, a potential barrier is generated between the photoelectric conversion element 222 and the charge holding region 224. Furthermore, when the transfer transistor 225 is turned off, a potential barrier is generated between the charge holding region 224 and the charge holding region 226, and when the transfer transistor 227 is turned off, a potential barrier is generated between the charge holding region 226 and the floating diffusion region 228. Figure 4 As shown, there is a p-type region 321 between the n-type charge holding region 224 and the n-type charge holding region 226. Therefore, due to this npn structure, as shown in FIG. Figure 5 As shown, a potential barrier is formed between the charge retention region 224 and the charge retention region 226.

[0101] In addition, the potential of the charge holding region 224 (ST1) and the charge holding region 226 (ST2) is designed to satisfy the following two conditions. The first condition is that the potential of ST2 when the charge is transferred from the photoelectric conversion element 222 to ST1 and ST2 is lower than the potential of ST1. The second condition is that there is a potential barrier between ST1 and ST2 during the charge retention period after the charge is transferred from the photoelectric conversion element 222 to ST1 and ST2. These two conditions can be satisfied by adjusting the impurity concentration of the well that forms the potential of ST1 and ST2 during manufacturing. Alternatively, these two conditions can be satisfied by adjusting the voltage level and timing of the gates of the transistors and polysilicon configured on or around ST1 and ST2. Alternatively, these conditions can be satisfied by adjusting the impurity concentration and adjusting the voltage level and timing.

[0102] Furthermore, the amount of charge that can be held by ST2 alone is defined as Qh, which is a value proportional to the product of the height of the potential barrier under the second condition and the capacity of ST2.

[0103] When the illumination is low enough that the amount of charge transferred from the photoelectric conversion element 222 to ST1 and ST2 is less than Qh, due to the first condition, all the transferred charge passes through ST1 and moves to ST2. Consequently, ST1 becomes empty. However, due to the second condition, the charge that enters ST2 is retained by the potential barrier and held in ST2. Furthermore, even if photoelectric conversion occurs during the charge retention period due to light leakage generated in ST1, the charge in ST1 remains in ST1 and does not enter ST2 due to the potential barrier. On the other hand, when the illumination is high enough that the amount of charge transferred from the photoelectric conversion element 222 to ST1 and ST2 becomes greater than Qh, the charge is distributed and held in both ST1 and ST2.

[0104] Figure 6 This is a plan view showing an example of the element layout within pixel 220 according to the first embodiment of the present technology. Hereinafter, the optical axis is defined as the Z-axis, and a predetermined axis perpendicular to the Z-axis is defined as the X-axis. An axis perpendicular to both the X-axis and the Z-axis is defined as the Y-axis. This figure shows the layout as viewed from the optical axis (Z-axis).

[0105] As shown in the figure, a charge discharge transistor 221, transfer transistors 223, 225, and 227, and a transistor arrangement region 230 are arranged around the photoelectric conversion element 222. A reset transistor 231, an amplifier transistor 232, and a selection transistor 233 are arranged in the transistor arrangement region 230.

[0106] Figure 7 According to the first embodiment of the present technology Figure 6. The front surface of the p-type semiconductor substrate 320, on which the wiring layer 414 is formed, is defined as the front surface, and the photoelectric conversion element 222 and the charge holding region 224 (ST1) are formed on the front surface. The solid-state imaging element 200 having the photoelectric conversion element 222 formed on the front surface in this manner is generally referred to as a front-side illumination type solid-state imaging element.

[0107] The upper portion of the photoelectric conversion element 222 is open, and the upper portion of the charge holding region 224 (ST1) is shielded from light by the metal plane of the wiring layer 414. Light-shielding walls 411 and 412 are formed around the pixel 220 by deep trench isolation (DTI). In addition, since a charge transfer channel 413 must be formed between the photoelectric conversion element 222 and ST1, a light-shielding wall cannot be provided, and light such as incident light 415 may leak into ST1. This leaked light may cause undesirable image artifacts. Resistance to this phenomenon is called PLS resistance.

[0108] Figure 8 According to the first embodiment of the present technology Figure 6 An example of a cross-sectional view taken along line CD is shown. The upper portion of charge retention region 226 (ST2) is also shielded from light by metal. Furthermore, unlike charge retention region 224 (ST1), a light-shielding wall 416 is formed between photoelectric conversion element 222 and ST2. This prevents charge from leaking from photoelectric conversion element 222 to ST2, and allows ST2 to have stronger PLS resistance than ST1.

[0109] Figure 9 According to the first embodiment of the present technology Figure 6 An example of a cross-sectional view taken along line EF of FIG. A light shielding wall 417 is formed around the pixel 220 , and the upper portions of the charge holding region 224 ( ST1 ) and the charge holding region 226 ( ST2 ) are light shielded by the metal of the wiring layer 414 .

[0110] exist Figures 7 to 9 In FIG. 2 , for convenience of explanation, the color filter and the on-chip lens above the photoelectric conversion element 222 are omitted.

[0111] [Configuration Example of Column Signal Processing Circuit]

[0112] Figure 10 : is a block diagram showing a configuration example of the load MOS circuit block 250 and the column signal processing circuit 260 according to the first embodiment of the present technology.

[0113] A vertical signal line 239 is wired for each column in the load MOS circuit block 250. When the number of columns is 1 (I is an integer), 1 vertical signal line 239 is wired. In addition, a load MOS transistor 251 that supplies a constant current is connected to each vertical signal line 239.

[0114] A plurality of ADCs 261 and a digital signal processing unit 262 are provided in the column signal processing circuit 260. The ADC 261 is provided for each column. When the number of columns is one, one ADC 261 is provided.

[0115] The ADC 261 converts the analog pixel signal from the corresponding column into a digital signal using a reference signal (ramp signal Rmp, etc.) from the DAC 214 . The ADC 261 supplies the digital signal to the digital signal processing unit 262 .

[0116] The digital signal processing unit 262 performs predetermined signal processing such as correlated double sampling (CDS) processing and HDR synthesis processing on each of the digital signals of each column, and supplies image data including the processed digital signal to the recording unit 120 .

[0117] [Operation Example of Solid-State Imaging Element]

[0118] Figure 11 This is a timing diagram illustrating an example of global shutter operation of the solid-state imaging element 200 according to the first embodiment of the present technology. From time T0 immediately before exposure begins to time T1 when exposure begins, the vertical scanning circuit 211 supplies the control signal OFG to all pixels, turning on the charge discharge transistor 221 and performing a PD reset. Below, the number of rows is set to N (N is an integer), and the control signal for the pixels in the nth row (n is an integer from 1 to N) is set to OFG_[n]. The same applies to the reset signal RST and the transmission signals TX1, TX2, and TG.

[0119] During the exposure period between times T1 and T2, the photoelectric conversion elements 222 of all pixels perform photoelectric conversion. This control of exposing all pixels simultaneously is called a global shutter method. The amount of charge generated varies with the intensity of the incident light. At time T2 when exposure ends, the vertical scanning circuit 211 turns on the reset transistors 231 and transfer transistors 225 and 227 of all pixels based on the reset signal RST, the transfer signal TX2, and the TG signal. As a result, the charge retention regions 224 and 226 and the floating diffusion region 228 of all pixels are reset (ST reset).

[0120] Then, at time T3, the vertical scanning circuit 211 turns off the transfer transistors 225 of all pixels in response to the transfer signal TX2, and at time T4 immediately after T3, turns off the transfer transistors 227 of all pixels in response to the transfer signal TG. At time T5 immediately after T4, the vertical scanning circuit 211 turns off the reset transistors 231 of all pixels in response to the reset signal RST. In this way, the vertical scanning circuit 211 sequentially turns off the transfer transistors 225, 227, and reset transistor 231. This control maintains the state in which the potential decreases from the charge holding region 224 (ST1) toward the floating diffusion region 228, and fully resets ST1 and ST2 of all pixels.

[0121] At time T6, immediately after ST reset, the vertical scanning circuit 211 turns on the transfer transistors 223 and 225 of all pixels based on transfer signals TX1 and TX2, transferring the charge from the photoelectric conversion element 222 to the charge holding regions 224 and 226. At this point, the potential of the photoelectric conversion element 222 is higher than that of the charge holding region 224 (ST1), and the potential of ST1 is higher than that of the charge holding region 226 (ST2). This potential relationship is achieved by adjusting the implant concentration during manufacturing and the on-state voltage level applied to the gates of the transfer transistors 223 and 225.

[0122] Then, at time T7, the vertical scanning circuit 211 turns off the transfer transistors 223 of all pixels according to the transfer signal TX1, and at time T8, just after T7, turns off the transfer transistors 225 of all pixels according to the transfer signal TX2. In this way, by sequentially turning off the transfer transistors 223 and 225, the charge in ST2 at low illumination levels does not flow back to ST1. In low illumination levels, the charge is retained only in ST2. On the other hand, in high illumination levels, the charge is retained in both ST1 and ST2.

[0123] Figure 12 1 shows an example of a potential diagram during low illuminance until ST reset according to the first embodiment of the present technology. (a) in the figure shows an example of a potential diagram during PD reset, and (b) in the figure shows an example of a potential diagram during exposure accumulation. (c) in the figure shows an example of a potential diagram during ST reset.

[0124] As shown in a of the figure, the vertical scanning circuit 211 performs a PD reset while turning on only the charge discharge transistor 221 and turning off the transfer transistors 223, 225, and 227, as well as the reset transistor 231. Then, as shown in b of the figure, the vertical scanning circuit 211 turns off the charge discharge transistor 221, thereby performing exposure accumulation. Subsequently, as shown in c of the figure, the vertical scanning circuit 211 turns on the transfer transistors 225 and 227, as well as the reset transistor 231, to perform an ST reset.

[0125] Figure 13 1 shows an example of a potential diagram when the illuminance is low until the charge retention regions separate according to the first embodiment of the present technology. (a) in the figure shows an example of a potential diagram when charge is transferred to the charge retention regions 224 and 226. (b) in the figure shows an example of a potential diagram when the charge retention regions 224 and 226 separate.

[0126] As shown in a in the figure, the vertical scanning circuit 211 turns on the transfer transistors 223 and 225 while turning off the transfer transistor 227 and the reset transistor 231. Therefore, the charge is transferred from the photoelectric conversion element 222 to the charge holding regions 224 and 226. In the case of low illumination, the charge is held only in ST2.

[0127] Then, as shown in b in the figure, the vertical scanning circuit 211 turns off the transfer transistors 223 and 225 , thereby separating the charge holding region 224 from the charge holding region 226 .

[0128] Figure 14 1 is an example of a potential diagram until ST reset when the illuminance is high according to the first embodiment of the present technology. a in the figure is an example of a potential diagram when PD is reset, and b in the figure is an example of a potential diagram during exposure accumulation. c in the figure is an example of a potential diagram when ST is reset. These potential diagrams are the same except that the amount of charge is different. Figure 12 The potential diagrams shown are similar.

[0129] Figure 15 1 is an example of a potential diagram showing the separation of the charge holding region when the illumination is high according to the first embodiment of the present technology. a in the figure is an example of a potential diagram when the charge is transferred to the charge holding regions 224 and 226. b in the figure is an example of a potential diagram when the charge holding region 224 is separated from the charge holding region 226. These potential diagrams are the same except that the amount of charge is different. Figure 13 The potential diagram shown is similar to that shown in Figure 15 As shown, under high illumination conditions, charge is retained in both ST1 and ST2.

[0130] Figure 16 is a timing chart showing an example of the operation of reading out one row when the illumination is low according to the first embodiment of the present technology. Figure 11 The global shutter shown is then performed sequentially row by row.

[0131] For example, at times T11 and T16, the horizontal synchronization signal XHS is supplied by the timing control circuit 213 to the column signal processing circuit 260. The vertical scanning circuit 211 supplies the selection signal SEL in synchronization with the horizontal synchronization signal XHS. For example, when the first row is selected during the period from time T11 to T16, the selection signal SEL_[1] is supplied.

[0132] At time T11, the vertical scanning circuit 211 supplies a reset signal RST during the pulse period, turning on the reset transistor 231 and resetting the FD. During the period until time T12, the reset level at the time of FD reset is output to the vertical signal line 239 via the amplifier transistor 232 and the select transistor 233, and is then A / D-converted by the column signal processing circuit 260. This reset level is also referred to as the P-phase level. The P-phase level after A / D conversion is defined as Vp.

[0133] Then, at time T12, the vertical scanning circuit 211 supplies a transfer signal TG during the pulse period to turn on the transfer transistor 227, transferring the charge in the charge holding region 226 (ST2) to the floating diffusion region 228. The charge in the charge holding region 224 (ST1) and the charge holding region 226 (ST2) is a signal charge generated by photoelectric conversion, and the signal level corresponding to the amount of signal charge is referred to as the D-phase level. Until time T13, the D-phase level is A / D-converted by the column signal processing circuit 260. The D-phase level after the first A / D conversion is defined as Vd1.

[0134] Subsequently, at time T13, the vertical scanning circuit 211 supplies transfer signals TG and TX2 to turn on the transfer transistors 225 and 227, and transfer the charge in the charge holding region 224 (ST1) to the floating diffusion region 228. Furthermore, at time T14, the vertical scanning circuit 211 turns off the transfer transistor 225, and at time T15 immediately after T14, turns off the transfer transistor 227. By sequentially turning off the transfer transistors 225 and 227, the potential of ST2 can be kept higher than the potential of the floating diffusion region 228, allowing the signal charge of ST1 to be completely transferred to the floating diffusion region 228.

[0135] During the period until time T16, the D-phase level is AD-converted by column signal processing circuit 260. The D-phase level after the second AD conversion is defined as Vd2. In the second conversion, the charge transferred from charge holding region 224 to floating diffusion region 228 is added to the charge transferred from charge holding region 226 in the first conversion. Therefore, the second D-phase level becomes a level corresponding to the value obtained by adding the charge amounts held in each of charge holding regions 224 and 226.

[0136] The column signal processing circuit 260 performs the following calculation in the CDS process: By the CDS process, reset noise of the floating diffusion region 228 and noise offset of the circuit can be eliminated.

[0137] Δ1=Vd1-Vp

[0138] Δ2=Vd2-Vp

[0139] The column signal processing circuit 260 compares the difference Δ1 with a predetermined threshold Δth and determines whether the difference Δ1 is equal to or less than the threshold Δth. Here, the threshold Δth is the amount of charge that ST2 can safely hold alone and is proportional to the product of the capacity of ST2, the potential barrier between ST1 and ST2, and the charge-voltage conversion efficiency of the floating diffusion region 228.

[0140] As shown in the figure, when the difference value Δ1 is equal to or less than the threshold value Δth, the column signal processing circuit 260 determines that the illuminance is relatively low and outputs the difference value Δ1 as the final pixel signal. On the other hand, when the difference value Δ1 is greater than the threshold value Δth, the column signal processing circuit 260 determines that the illuminance is relatively high and outputs the difference value Δ2 as the final pixel signal.

[0141] In this way, pixels with low illumination output a difference value Δ1 and pixels with high illumination output a difference value Δ2, thereby reducing the PLS of the low illumination signal.

[0142] Furthermore, since ST2 can maintain a greater distance from the open photoelectric conversion element 222 than ST1, light leakage is less likely to reach it. Furthermore, since ST2 only needs to receive a portion of the signal charge within the full range, the capacity of ST2 can be kept small. These two effects effectively suppress light leakage from ST2.

[0143] Here, artifacts, which typically occur in low-illuminance signals, are particularly noticeable in image data. This is likely because high-illuminance signals contain a large amount of optical shot noise, and even if artifacts are present, they are buried within the optical shot noise and are therefore less noticeable. In the solid-state imaging element 200, as described above, the charge signal at low illumination levels, where artifacts are noticeable, is retained in ST2, which is less susceptible to light leakage, thereby reducing the effects of light leakage.

[0144] Figure 17 This is an example of a potential diagram during readout under low illumination conditions according to the first embodiment of the present technology. Under low illumination conditions, as shown in the figure, no signal charge remains in ST1 during the first D-phase level readout. The potential diagram during the second D-phase level readout is similar to the potential diagram during the first D-phase level readout.

[0145] Figure 18is a timing chart showing an example of the operation of reading out one row when the illumination is high according to the first embodiment of the present technology. Figure 16 The control shown is similar. As shown in the figure, when the illuminance is high, the difference Δ1 becomes larger than the threshold Δth. In this case, the column signal processing circuit 260 outputs the difference Δ2 as the final pixel signal.

[0146] Figure 19 1 is an example of a potential diagram when reading out the D-phase level for the first time, and b is an example of a potential diagram when reading out the D-phase level for the second time according to the first embodiment of the present technology.

[0147] As shown in a of the figure, under high illumination conditions, when the D-phase level is read out for the first time, the signal level remains in ST1. As shown in b of the figure, the signal charge remaining in ST1 is transferred to the floating diffusion region 228, added to the first charge amount, and read out as the second D-phase level.

[0148] Figure 20 1 is a flowchart showing an example of the operation of the solid-state imaging element 200 according to the first embodiment of the present technology. For example, this operation is started when a predetermined application for generating an HDR image is executed.

[0149] The vertical scanning circuit 211 in the solid-state imaging element 200 performs a PD reset for all pixels (step S901) and performs exposure accumulation (step S902). After the exposure is completed, the vertical scanning circuit 211 performs an ST reset for all pixels (step S903) and transfers the charge to the charge holding regions 224 and 226 (step S904). The vertical scanning circuit 211 separates the charge holding regions 224 and 226 (step S905).

[0150] The vertical scanning circuit 211 selects a row, and the column signal processing circuit 260 calculates the difference values ​​Δ1 and Δ2 for each column through CDS processing (step S906). The column signal processing circuit 260 determines whether the difference value Δ1 is equal to or less than the threshold value for each column (step S907). When the difference value Δ1 is equal to or less than the threshold value (step S907: Yes), the column signal processing circuit 260 selects the difference value Δ1 and outputs it as a pixel signal (step S908). On the other hand, when the difference value Δ1 is greater than the threshold value (step S907: No), the column signal processing circuit 260 selects the difference value Δ2 and outputs it as a pixel signal (step S909). The processing of steps S906 to S909 is performed for each column in the selected row, but in the figure, for convenience of explanation, the processing of all but one column is omitted.

[0151] After step S908 or S909, the solid-state imaging device 200 determines whether the readout of all rows has been completed (step S910). If the readout of all rows has not been completed (step S910: No), the solid-state imaging device 200 repeats step S906 and subsequent steps. If the readout of all rows is completed (step S910: Yes), the solid-state imaging device 200 ends the operation for generating the HDR image.

[0152] Furthermore, in the case of continuously generating a plurality of HDR images, the processes of steps S901 to S910 are repeatedly performed in synchronization with a vertical synchronization signal.

[0153] As described above, in the first embodiment of the present technology, the light shielding wall prevents charge from leaking from the photoelectric conversion element 222 to the subsequent charge holding region 226, thereby improving PLS resistance. Furthermore, the transfer transistor 223 transfers charge to the charge holding regions 224 and 226, and the transfer transistors 225 and 227 sequentially transfer the retained charge to the floating diffusion region 228. Consequently, the column signal processing circuit 260 can output either a low-light signal or a high-light signal for each pixel, reducing the PLS of the low-light signal and improving image quality.

[0154] [First Modification]

[0155] In the first embodiment described above, the front-illuminated solid-state imaging element 200 has been used. However, in the front-illuminated type, it is necessary to guide the incident light to the photoelectric conversion element 222 while avoiding the wiring layer 414, which may result in insufficient sensitivity. The solid-state imaging element 200 of the first modified example of the first embodiment is different from the first embodiment in that it is a back-illuminated type.

[0156] The layout of the solid-state imaging element 200 according to the first modification of the first embodiment as viewed in the Z-axis direction is similar to that of the solid-state imaging element 200 according to the first modification of the first embodiment. Figure 6 The layout of the first embodiment shown is similar.

[0157] Figure 21 This is an example of a cross-sectional view taken along line AB according to the first variant of the first embodiment of the present technology. As shown in the figure, the surface on which the wiring layer 414 is formed, of the two surfaces of the p-type semiconductor substrate 320, serves as the front surface, and the photoelectric conversion element 222 is formed on the back surface of the front surface. On the back surface, the upper portion of the charge holding region 224 (ST1) is shielded from light by the metal 421. In addition, light-shielding walls 411 and 412 are formed around the pixel 220 by DTI. As shown in the figure, the solid-state imaging element 200 with the photoelectric conversion element 222 formed on the back surface is referred to as a back-illuminated solid-state imaging element.

[0158] Figure 22This is an example of a cross-sectional view taken along line CD according to the first modification of the first embodiment of the present technology. On the back surface, the upper portion of the charge holding region 226 (ST2) is shielded from light by metal 421. Furthermore, a light-shielding wall 416 is formed between the photoelectric conversion element 222 and ST2. Light-shielding walls 416 and 412 surrounding ST2 extend from the wiring layer 414 in the Z-axis direction, penetrate the p-type semiconductor substrate 320, and connect to the metal 421. This improves ST2's resistance to light shielding.

[0159] Figure 23 This is an example of a cross-sectional view taken along line EF according to the first modification of the first embodiment of the present technology. A light-shielding wall 417 is formed around the pixel 220, and on the back surface, the upper portions of the charge retention region 224 (ST1) and the charge retention region 226 (ST2) are shielded from light by a metal 421.

[0160] As described above, in a modified example of the first embodiment of the present technology, since the photoelectric conversion element 222 is formed on the back surface opposite to the front surface on which the wiring layer 414 on the substrate is formed, there is no need to guide the incident light to avoid the wiring layer 414, thereby improving the sensitivity compared to the front illumination type.

[0161] [Second Modification]

[0162] In the first embodiment described above, a floating diffusion region 228 is provided for each pixel, but in this configuration, it is difficult to reduce the circuit scale of the pixel array unit 212. The solid-state imaging element 200 of the second modified example of the first embodiment differs from the first embodiment in that a plurality of pixels share the floating diffusion region 228.

[0163] Figure 24 This is a circuit diagram illustrating an example configuration of a pixel block 240 according to a second variation of the first embodiment of the present technology. In the second variation of the first embodiment, a plurality of pixel blocks 240 are arranged in the pixel array unit 212. Each pixel block 240 includes charge discharge transistors 221 and 241, photoelectric conversion elements 222 and 242, and transfer transistors 223, 225, 227, 243, 245, and 247. Furthermore, the pixel block 240 includes charge holding regions 224, 226, 244, and 246, a floating diffusion region 228, a reset transistor 231, an amplification transistor 232, and a selection transistor 233.

[0164] In the second modification, the configuration for connecting the charge discharge transistor 221, the photoelectric conversion element 222, the transfer transistors 223, 225, and 227, the charge holding regions 224 and 226, and the floating diffusion region 228 is similar to that of the first embodiment. The configuration for connecting the charge discharge transistor 241, the photoelectric conversion element 242, the transfer transistors 243, 245, and 247, and the charge holding regions 244 and 246 is similar to that of the first embodiment. The configuration for connecting the reset transistor 231, the amplification transistor 232, and the selection transistor 233 is similar to that of the first embodiment.

[0165] Furthermore, the transfer transistors 243, 245, and 247 of the second modification are connected in series between the connection node between the charge discharge transistor 241 and the photoelectric conversion element 242, and the floating diffusion region 228. According to the configuration illustrated in the figure, the pixel block 240 functions as two pixels, and these pixels share a single floating diffusion region 228. Since multiple pixels share a single floating diffusion region 228 in this manner, the number of elements per pixel is reduced compared to the first embodiment, which does not share a single floating diffusion region, thereby reducing the circuit scale of the pixel array unit 212.

[0166] Photoelectric conversion elements 221 and 241 are examples of the first and second photoelectric conversion elements described in the claims. Transfer transistors 223 and 243 are examples of the first and second preceding transfer transistors described in the claims. Transfer transistors 225 and 245 are examples of the first and second intermediate transfer transistors described in the claims. Transfer transistors 227 and 247 are examples of the first and second following transfer transistors described in the claims. Charge retention regions 224 and 244 are examples of the first and second preceding charge retention regions described in the claims. Charge retention regions 226 and 246 are examples of the first and second following charge retention regions described in the claims.

[0167] Figure 25 This is a plan view showing an example of the element layout of a pixel block 240 according to a second variation of the first embodiment of the present technology. As shown in the figure, the charge discharge transistor 221, the photoelectric conversion element 222, and the transfer transistors 223, 225, and 227 are arranged on the left side in a layout similar to that of the first embodiment. The charge discharge transistor 241, the photoelectric conversion element 242, and the transfer transistors 243, 245, and 247 are arranged on the right side in a layout symmetrical to the left side. The floating diffusion region 228 is arranged between the transfer transistors 227 and 247, and the transistor arrangement region 230 is arranged between the photoelectric conversion elements 222 and 242.

[0168] exist Figure 24 and Figure 25In the embodiment, the number of pixels sharing the floating diffusion region 228 is set to 2, but a plurality of pixels having 3 or more pixels may share the floating diffusion region 228. Furthermore, the first modification of the first embodiment may be applied to the second modification of the first embodiment.

[0169] As described above, in the second modification of the first embodiment of the present technology, since a plurality of pixels share one floating diffusion region 228 , the number of elements per pixel can be reduced compared to the case of no sharing.

[0170] <2. Second Implementation Plan>

[0171] In the first embodiment described above, two independent n-layers are provided as the charge holding regions 224 and 226. However, since two n-layers are required for each pixel, the area of ​​the pixel 220 increases, making it difficult to obtain finer pixels. The solid-state imaging element 200 of the second embodiment differs from the first embodiment in that the charge holding regions 224 and 226 are formed within a single n-layer.

[0172] Figure 26 2 is a circuit diagram showing a configuration example of a pixel 220 according to a second embodiment of the present technology. The pixel 220 of the second embodiment differs from the first embodiment in that transfer transistors 223 and 225 share the same n-layer. Charge holding regions 224 and 226 are formed in this n-layer.

[0173] Figure 27 2 is an example of a cross-sectional view of a pixel 220 according to a second embodiment of the present technology. In the pixel 220 of the second embodiment, the n layer 334 and the p layer 336 are not formed. + layer 339, and gate electrodes 342 and 343 are formed on the n layer 333 and the p + On n-layer 338. In n-layer 333, the left side of region 321 below the gap between gate electrodes 342 and 343 serves as charge retention region 224 (ST1), and the right side serves as charge retention region 226 (ST2). Thus, ST1 and ST2 are formed within the same n-layer 333. Therefore, compared to a case where two separate n-layers are provided for ST1 and ST2, one n-layer is unnecessary, and the area of ​​pixel 220 can be reduced.

[0174] Region 321 has weaker electrolysis from the gate electrode than the region directly under each of gate electrodes 342 and 343. For this reason, when transfer transistors 223 and 225 are turned off, the potential of region 321 becomes higher than the potential of the region directly under the gate electrode, and a potential barrier is generated in region 321 between ST1 and ST2.

[0175] Furthermore, the potential barrier can be adjusted during manufacturing by adjusting the implantation concentration of impurities in the region 321. In this case, for example, the impurity concentration in the region 321 is adjusted to be lower than that in the surrounding region.

[0176] Figure 28 is an example of a potential diagram for pixel 220 according to the second embodiment of the present technology. This diagram shows the potentials when the charge discharge transistor 221, transfer transistors 223, 225, and 227, and reset transistor 231 are off. As shown in the diagram, since ST1 and ST2 are formed in the same n-layer 333, the potential barrier between them when off is lower than that in the first embodiment.

[0177] Note that the first modification example and the second modification example of the first embodiment can be applied to the second embodiment.

[0178] As described above, in the second embodiment of the present technology, since the charge holding region 224 and the charge holding region 226 are formed in the same n-layer 333 , the number of n-layers can be reduced compared to the case where two independent n-layers are provided.

[0179] <3. Third Implementation Plan>

[0180] In the second embodiment described above, the charge holding region 224 and the charge holding region 226 are formed in the same n-layer 333. However, in this configuration, the height of the potential barrier between them may be insufficient. The solid-state imaging element 200 of the third embodiment differs from the second embodiment in that a transistor for adjusting the potential barrier height is provided.

[0181] Figure 29 2 is a circuit diagram showing a configuration example of a pixel 220 according to a third embodiment of the present technology. The pixel 220 of the third embodiment is different from that of the second embodiment in that it further includes an adjustment transistor 229.

[0182] The adjustment transistor 229 adjusts the potential barrier between the charge holding region 224 and the charge holding region 226 according to the control signal TXc from the vertical scanning circuit 211 .

[0183] Figure 30 : is an example of a cross-sectional view of a pixel 220 according to a third embodiment of the present technology. The pixel 220 of the third embodiment is different from the second embodiment in that a gate electrode 346 is further provided.

[0184] Furthermore, as in the second embodiment, the region of the n layer 333 directly below the gate electrode 342 is used for the charge holding region 224 ( ST1 ), and the region directly below the gate electrode 343 is used for the charge holding region 226 ( ST2 ).

[0185] The gate electrode 346 is arranged between the gate electrode 342 and the gate electrode 343 (ie, just above the potential barrier), and a control signal TXc is input thereto. The gate electrode 346 and the semiconductor region thereunder function as the adjustment transistor 229 .

[0186] The vertical scanning circuit 211 applies a positive voltage to the gate of the adjustment transistor 229, thereby lowering the potential below the gate. Furthermore, when off, the vertical scanning circuit 211 applies ground or a negative voltage to the adjustment transistor 229. The vertical scanning circuit 211 can adjust the potential barrier by adjusting the voltage applied to the gate of the adjustment transistor 229. When the voltage applied to the gate of the adjustment transistor 229 is set lower than the voltages of the transfer transistors 223 and 225 on either side of it when off (when charge is retained in ST1, etc.), the potential barrier directly below it becomes higher than the potential barriers surrounding it.

[0187] Figure 31 : This is an example of a potential diagram for pixel 220 according to the third embodiment of the present technology. This diagram shows the potentials when the charge discharge transistor 221, transfer transistors 223, 225, and 227, adjustment transistor 229, and reset transistor 231 are off. As shown in the diagram, the addition of the adjustment transistor 229 increases the potential barrier compared to the second embodiment.

[0188] Figure 32 This is a timing chart illustrating an example of global shutter operation of a solid-state imaging element according to a third embodiment of the present technology. In the third embodiment, PD reset and exposure accumulation control are similar to those in the first and second embodiments. At time T2, the vertical scanning circuit 211 turns on the reset transistor 231, transfer transistors 225 and 227, and trim transistor 229 of all pixels based on the reset signal RST, transfer signal TX2, TG signal, and control signal TXc. This performs an ST reset.

[0189] Furthermore, the vertical scanning circuit 211 turns off the adjustment transistor 229 according to the control signal TXc at time T3 , and turns off the transfer transistor 225 according to the transfer signal TX2 at time T4 .

[0190] Then, at time T5 , the vertical scanning circuit 211 turns off the transfer transistor 227 according to the transfer signal TG, and turns off the reset transistor 231 according to the reset signal RST at time T6 .

[0191] Subsequently, at time T7 just after ST reset, the vertical scanning circuit 211 turns on the transfer transistors 223 and 227 and the adjustment transistor 229 of all pixels to transfer charges according to the transfer signals TX1 and TX2 and the control signal TXc.

[0192] Then, at time T8, the vertical scanning circuit 211 turns off the transfer transistor 223 according to the transfer signal TX1, and at time T9 immediately after T8, turns off the adjustment transistor 229 according to the control signal TXc. At time T10 immediately after T9, the vertical scanning circuit 211 turns off the transfer transistor 225 according to the transfer signal TX2.

[0193] Figure 33 3 is a timing chart showing an example of an operation of reading out one row when the illuminance is low according to the third embodiment of the present technology. The control until just before time T23 is similar to that in the first and second embodiments.

[0194] At time T23, the vertical scanning circuit 211 supplies transfer signals TG and TX2 and a control signal TXc to turn on the transfer transistors 225 and 227 and the adjustment transistor 229, and transfer charge to the floating diffusion region 228. Furthermore, at time T24, the vertical scanning circuit 211 turns off the adjustment transistor 229 based on the control signal TXc, and at time T25 immediately after T24, turns off the transfer transistor 225 based on the transfer signal TX2. At time T26 immediately after T25, the vertical scanning circuit 211 turns off the transfer transistor 227 based on the transfer signal TG.

[0195] Figure 34 This figure shows an example of a potential diagram during readout under low illumination conditions according to the third embodiment of the present technology. When the D-phase level is read out for the first time under low illumination conditions, as shown in the figure, no signal charge remains in ST1. The potential diagram during the second D-phase level readout is similar to that during the first D-phase level readout.

[0196] Figure 35 is a timing chart showing an example of the operation of reading out one row when the illumination is high according to the third embodiment of the present technology. Figure 33 The controls shown are similar.

[0197] Figure 36 1 is an example of a potential diagram when reading out a D-phase level for the first time, and b is an example of a potential diagram when reading out a D-phase level for the second time according to the third embodiment of the present technology.

[0198] In addition, the first modification example and the second modification example of the first embodiment can be applied to the third embodiment.

[0199] As described above, according to the third embodiment of the present technology, since the transistor for adjusting the height of the potential barrier is provided, the deficiency in the height of the potential barrier can be solved.

[0200] <4. Application Examples of Mobile Objects>

[0201] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile object such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, an unmanned aerial vehicle, a ship, a robot, etc.

[0202] Figure 37 This is a block diagram showing a schematic configuration example of a vehicle control system as an example of a vehicle control system to which the technology according to the present disclosure can be applied.

[0203] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Figure 37 In the illustrated example, vehicle control system 12000 includes a drive system control unit 12010, a main body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, as functional components of integrated control unit 12050, a microcomputer 12051, an audio and video output unit 12052, and an in-vehicle network interface (I / F) 12053 are illustrated.

[0204] Drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, drive system control unit 12010 functions as a control device for a drive force generating device such as an internal combustion engine or a drive motor that generates the vehicle's drive force, a drive force transmission mechanism that transmits the drive force to the wheels, a steering mechanism that adjusts the vehicle's steering angle, and a braking device that generates the vehicle's braking force.

[0205] The main system control unit 12020 controls the operation of various devices attached to the vehicle body according to various programs. For example, the main system control unit 12020 functions as a control device for a keyless entry system, a smart key system, power windows, or various lights such as headlights, taillights, brake lights, turn signals, and fog lights. In this case, instead of key presses, radio waves transmitted from a portable device or signals from various switches can be input to the main system control unit 12020. The main system control unit 12020 receives the input of radio waves or signals and controls the vehicle's door locks, power windows, lights, and the like.

[0206] The vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed. For example, the imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the vehicle exterior and receive the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform object detection processing such as a person, a car, an obstacle, a sign, or text on the road, or perform distance detection processing.

[0207] Imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. Imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by imaging unit 12031 can be visible light or invisible light such as infrared light.

[0208] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the driver's state is connected to the in-vehicle information detection unit 12040. For example, the driver state detection unit 12041 includes a camera that images the driver, and based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or concentration, or can determine whether the driver is drowsy.

[0209] The microcomputer 12051 can calculate control target values ​​for the driving force generation device, the steering mechanism, or the braking device based on the information inside and outside the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and can output control instructions to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to implement functions of an advanced driver assistance system (ADAS) including collision avoidance or collision mitigation of vehicles, tracking driving based on the distance between vehicles, vehicle speed maintenance driving, vehicle collision warning, and vehicle lane departure warning.

[0210] In addition, the microcomputer 12051 can coordinate control by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040 to achieve automatic driving in which the vehicle travels autonomously without relying on the driver's operation.

[0211] Furthermore, the microcomputer 12051 can output a control command to the main system control unit 12020 based on the information outside the vehicle obtained by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of the preceding vehicle or oncoming vehicle detected by the vehicle exterior information detection unit 12030 to implement coordinated control such as switching the high beam to the low beam to prevent glare.

[0212] The audio and image output unit 12052 transmits an output signal of at least one of audio and image to an output device capable of visually or auditorily notifying the vehicle occupants or the outside of the vehicle of information. Figure 37 In the example of FIG, as output devices, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are shown. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0213] Figure 38 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0214] exist Figure 38 In the figure, as the imaging unit 12031, imaging units 12101, 12102, 12103, 12104 and 12105 are provided.

[0215] Imaging units 12101, 12102, 12103, 12104, and 12105 are disposed, for example, on the front of the vehicle 12100, the sideview mirrors, the rear bumper, the rear door, and the upper portion of the windshield inside the vehicle. Imaging unit 12101 disposed on the front of the vehicle and imaging unit 12105 disposed on the upper portion of the windshield inside the vehicle primarily obtain images of the front of the vehicle 12100. Imaging units 12102 and 12103 disposed on the sideview mirrors primarily obtain images of the sides of the vehicle 12100. Imaging unit 12104 disposed on the rear bumper or rear door primarily obtains images of the rear of the vehicle 12100. Imaging unit 12105 disposed on the upper portion of the windshield inside the vehicle is primarily used to detect vehicles ahead, pedestrians, obstacles, traffic signals, traffic signs, lanes, and the like.

[0216] also, Figure 38The figure shows examples of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 represents the imaging range of imaging unit 12101, which is located at the front of the vehicle. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103, respectively, which are located at the side mirrors. Imaging range 12114 represents the imaging range of imaging unit 12104, which is located at the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104, a bird's-eye view image of vehicle 12100 can be obtained.

[0217] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or an imaging element having pixels for phase difference detection.

[0218] For example, based on the distance information obtained from imaging units 12101-12104, microcomputer 12051 obtains the distance to each 3D object within imaging ranges 12111-12114 and the temporal change in that distance (relative speed to vehicle 12100). Microcomputer 12051 then identifies the 3D object closest to vehicle 12100 on its travel path, particularly the 3D object traveling in the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher), as the leading vehicle. Furthermore, microcomputer 12051 can set a predetermined inter-vehicle distance to the leading vehicle and perform automatic braking control (including tracking stop control), automatic acceleration control (including tracking start control), and other functions. This allows for coordinated control for autonomous driving, in which the vehicle autonomously travels without relying on driver input.

[0219] For example, based on the distance information obtained from imaging units 12101-12104, microcomputer 12051 can classify 3D object data regarding 3D objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other 3D objects such as utility poles, extract the 3D object data, and use this 3D object data to automatically avoid obstacles. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as those that can be visually identified by the driver of vehicle 12100 and those that are difficult to visually identify. Furthermore, microcomputer 12051 determines a collision risk, indicating the degree of risk of collision with each obstacle. When the collision risk is equal to or higher than a set value and a collision is possible, driving assistance for collision avoidance can be provided by outputting a warning to the driver via audio speaker 12061 and display unit 12062 or by initiating forced deceleration or evasive steering via drive system control unit 12010.

[0220] At least one of the imaging units 12101-12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether the pedestrian is present in the images captured by the imaging units 12101-12104. For example, pedestrian identification may be performed by extracting feature points from the images captured by the imaging units 12101-12104, which are infrared cameras, and performing pattern matching on a series of feature points indicating the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101-12104 and identifies the pedestrian, the audio and video output unit 12052 causes the display unit 12062 to superimpose and display a rectangular outline on the identified pedestrian for emphasis. Furthermore, the audio and video output unit 12052 causes the display unit 12062 to display an icon indicating the pedestrian at a desired location.

[0221] An example of a vehicle control system to which the technology of the present disclosure can be applied has been described above. The technology of the present disclosure can be applied to the imaging unit 12031 in the above-mentioned configuration. Specifically, Figure 1 The imaging device 100 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, PLS tolerance can be improved, and a clearer captured image can be obtained, thereby reducing the fatigue of the driver.

[0222] In addition, the above-mentioned embodiments illustrate examples for implementing the present technology, and the matters in the embodiments and the invention-specific matters in the claims have a corresponding relationship with each other. Similarly, the invention-specific matters in the claims and the matters in the embodiments of the present technology with the same names have a corresponding relationship with each other. However, the present technology is not limited to the embodiments and can be implemented by making various modifications to the embodiments without departing from its main purpose.

[0223] In addition, the effects described in this specification are merely examples and are not limiting. In addition, there may be other effects.

[0224] The present technology can have the following configurations.

[0225] (1) A solid-state imaging element comprising:

[0226] Photoelectric conversion element;

[0227] Front stage charge holding area;

[0228] a rear-stage charge retention region having a different capacity from that of the front-stage charge retention region;

[0229] a front-stage transfer transistor that transfers charge from the photoelectric conversion element to the front-stage charge holding region and the rear-stage charge holding region;

[0230] a subsequent stage transfer transistor that transfers charge from the subsequent stage charge holding region to a floating diffusion region;

[0231] an intermediate transfer transistor that transfers charge remaining in the preceding-stage charge holding region after charge has been transferred from the succeeding-stage charge holding region to the floating diffusion region via the preceding-stage charge holding region to the floating diffusion region; and

[0232] A light shielding wall prevents charge from leaking from the photoelectric conversion element to the subsequent-stage charge holding region.

[0233] (2) The solid-state imaging element according to (1) above, wherein

[0234] The front-stage charge holding region and the rear-stage charge holding region are impurity diffusion regions having the same polarity, and

[0235] A predetermined impurity diffusion region having a polarity different from both the preceding-stage charge holding region and the succeeding-stage charge holding region is arranged between the preceding-stage charge holding region and the succeeding-stage charge holding region.

[0236] (3) The solid-state imaging element according to (1) above, wherein

[0237] The front-stage charge holding region and the rear-stage charge holding region are formed in the same impurity diffusion region.

[0238] (4) The solid-state imaging element according to (3) above, wherein

[0239] The impurity concentration of a region between the preceding-stage charge holding region and the succeeding-stage charge holding region in the impurity diffusion region is different from the impurity concentration of the surroundings of the region.

[0240] (5) The solid-state imaging device according to (3) above, further comprising:

[0241] An adjustment transistor adjusts the height of a potential barrier between the preceding charge retention region and the succeeding charge retention region.

[0242] (6) The solid-state imaging device according to any one of (1) to (5) above, further comprising:

[0243] a vertical scanning circuit that controls each of the front-stage transfer transistor, the rear-stage transfer transistor, and the intermediate transfer transistor to be turned on or off,

[0244] In which, the vertical scanning circuit turns on the front-stage transfer transistor and the intermediate transfer transistor while turning off the rear-stage transfer transistor to transfer charge to the front-stage charge holding area and the rear-stage charge holding area, turns on the rear-stage transfer transistor while turning off the front-stage transfer transistor and the intermediate transfer transistor to transfer charge from the rear-stage charge holding area to the floating diffusion area, and turns on the intermediate transfer transistor and the rear-stage transfer transistor to transfer charge from the front-stage charge holding area to the floating diffusion area.

[0245] (7) The solid-state imaging device according to any one of (1) to (6) above, further comprising:

[0246] A signal processing circuit compares a first pixel signal corresponding to the amount of charge transferred from the subsequent charge holding area and a second pixel signal corresponding to the amount of charge transferred from the preceding charge holding area and the subsequent charge holding area with a predetermined threshold value, and performs processing for selecting one of the first pixel signal and the second pixel signal based on the comparison result.

[0247] (8) The solid-state imaging device according to any one of (1) to (7) above, wherein

[0248] The photoelectric conversion element is formed on the front surface with wiring, of the two surfaces of a predetermined semiconductor substrate.

[0249] (9) The solid-state imaging device according to any one of (1) to (7) above, wherein

[0250] The photoelectric conversion element is formed on a back surface, which is opposite to a front surface with wiring, of two surfaces of a predetermined semiconductor substrate.

[0251] (10) The solid-state imaging device according to any one of (1) to (7) above, wherein

[0252] The photoelectric conversion element includes a first photoelectric conversion element and a second photoelectric conversion element.

[0253] The front-stage charge holding region includes a first front-stage charge holding region and a second front-stage charge holding region.

[0254] The latter stage charge holding region includes a first latter stage charge holding region and a second latter stage charge holding region.

[0255] The front-stage transfer transistor includes a first front-stage transfer transistor and a second front-stage transfer transistor,

[0256] The intermediate transfer transistors include a first intermediate transfer transistor and a second intermediate transfer transistor, and

[0257] The latter-stage transfer transistor includes a first latter-stage transfer transistor and a second latter-stage transfer transistor.

[0258] (11) The solid-state imaging device according to any one of (1) to (10) above, further comprising:

[0259] a charge discharge transistor that discharges charge from the photoelectric conversion element,

[0260] a reset transistor that initializes the floating diffusion region,

[0261] an amplifying transistor that amplifies a signal corresponding to the amount of charge transferred to the floating diffusion region, and

[0262] A selection transistor is configured to output the amplified signal as a pixel signal according to a predetermined selection signal.

[0263] (12) An imaging device comprising:

[0264] Photoelectric conversion element;

[0265] Front stage charge holding area;

[0266] a rear-stage charge retention region having a different capacity from that of the front-stage charge retention region;

[0267] a front-stage transfer transistor that transfers charge from the photoelectric conversion element to the front-stage charge holding region and the rear-stage charge holding region;

[0268] a subsequent stage transfer transistor that transfers charge from the subsequent stage charge holding region to a floating diffusion region;

[0269] an intermediate transfer transistor that transfers charge remaining in the preceding-stage charge holding region after the charge has been transferred from the succeeding-stage charge holding region to the floating diffusion region via the preceding-stage charge holding region to the floating diffusion region;

[0270] a light-shielding wall that prevents charge from leaking from the photoelectric conversion element to the subsequent-stage charge holding region; and

[0271] A signal processing circuit processes a pixel signal corresponding to the amount of charge transferred to the floating diffusion region.

[0272] (13) A method for controlling a solid-state imaging element, comprising:

[0273] A front-stage transfer process of transferring charge from a photoelectric conversion element to a front-stage charge holding region and a rear-stage charge holding region having different capacities;

[0274] a subsequent-stage transfer process of transferring charge from the subsequent-stage charge holding region to a floating diffusion region, wherein charge leakage from the photoelectric conversion element to the subsequent-stage charge holding region is prevented by a light-shielding wall; and

[0275] An intermediate transfer process in which charges remaining in the preceding-stage charge holding region after charges have been transferred from the succeeding-stage charge holding region to the floating diffusion region are transferred via the preceding-stage charge holding region to the floating diffusion region.

[0276] Reference Signs List

[0277] 100 Imaging Device

[0278] 110 Imaging Lens

[0279] 120 recording units

[0280] 130 Imaging Control Unit

[0281] 200 solid-state imaging element

[0282] 211 vertical scanning circuit

[0283] 212 pixel array unit

[0284] 213 Timing Control Circuit

[0285] 214 DAC

[0286] 220 pixels

[0287] 221,241 Charge discharge transistor

[0288] 222,242 Photoelectric conversion elements

[0289] 223, 225, 227, 243, 245, 247 pass transistors

[0290] 224,226,244,246 Charge retention region

[0291] 228 floating diffusion region

[0292] 229 Adjusting the transistor

[0293] 230 transistor configuration area

[0294] 231 Reset transistor

[0295] 232 amplifier transistor

[0296] 233 Select transistor

[0297] 240 pixel blocks

[0298] 250 load MOS circuit block

[0299] 251 Load MOS transistor

[0300] 260 columns of signal processing circuits

[0301] 261 ADC

[0302] 262 Digital Signal Processing Unit

[0303] 310 n-type semiconductor substrate

[0304] 320 p-type semiconductor substrate

[0305] 331,335,336 n + layer

[0306] 332,333,334 n-layer

[0307] 337~339 p + layer

[0308] 341~346 gate electrode

[0309] 411,412,416,417 Light-shielding wall

[0310] 413 Charge Transfer Channel

[0311] 414 wiring layer

[0312] 421 Metal

[0313] 12031 Imaging Unit

Claims

1. A solid-state imaging element, comprising: Photoelectric conversion element; Front stage charge holding area; a rear-stage charge retention region having a different capacity from that of the front-stage charge retention region; a front-stage transfer transistor that transfers charge from the photoelectric conversion element to the front-stage charge holding region and the rear-stage charge holding region; a subsequent stage transfer transistor that transfers charge from the subsequent stage charge holding region to a floating diffusion region; an intermediate transfer transistor that transfers charge remaining in the preceding-stage charge holding region after the charge has been transferred from the succeeding-stage charge holding region to the floating diffusion region via the preceding-stage charge holding region to the floating diffusion region; a light shielding wall that prevents charge from leaking from the photoelectric conversion element to the subsequent-stage charge holding region; as well as A signal processing circuit compares a first pixel signal corresponding to the amount of charge transferred from the subsequent charge holding area and a second pixel signal corresponding to the amount of charge transferred from the preceding charge holding area and the subsequent charge holding area with a predetermined threshold value, and performs processing for selecting one of the first pixel signal and the second pixel signal based on the comparison result.

2. The solid-state imaging element according to claim 1, wherein The front-stage charge holding region and the rear-stage charge holding region are impurity diffusion regions having the same polarity, and A predetermined impurity diffusion region having a polarity different from both the preceding-stage charge holding region and the succeeding-stage charge holding region is arranged between the preceding-stage charge holding region and the succeeding-stage charge holding region.

3. The solid-state imaging element according to claim 1, wherein The front-stage charge holding region and the rear-stage charge holding region are formed in the same impurity diffusion region.

4. The solid-state imaging element according to claim 3, wherein The impurity concentration of a region between the preceding-stage charge holding region and the succeeding-stage charge holding region in the impurity diffusion region is different from the impurity concentration of the surroundings of the region.

5. The solid-state imaging element according to claim 3, further comprising: An adjustment transistor adjusts the height of a potential barrier between the preceding charge retention region and the succeeding charge retention region.

6. The solid-state imaging element according to any one of claims 1 to 5, further comprising: a vertical scanning circuit that controls each of the front-stage transfer transistor, the rear-stage transfer transistor, and the intermediate transfer transistor to be turned on or off, In which, the vertical scanning circuit turns on the front-stage transfer transistor and the intermediate transfer transistor while turning off the rear-stage transfer transistor to transfer charge to the front-stage charge holding area and the rear-stage charge holding area, turns on the rear-stage transfer transistor while turning off the front-stage transfer transistor and the intermediate transfer transistor to transfer charge from the rear-stage charge holding area to the floating diffusion area, and turns on the intermediate transfer transistor and the rear-stage transfer transistor to transfer charge from the front-stage charge holding area to the floating diffusion area.

7. The solid-state imaging element according to any one of claims 1 to 5, wherein The photoelectric conversion element is formed on the front surface with wiring, of the two surfaces of a predetermined semiconductor substrate.

8. The solid-state imaging element according to any one of claims 1 to 5, wherein The photoelectric conversion element is formed on a back surface, which is opposite to a front surface with wiring, of two surfaces of a predetermined semiconductor substrate.

9. The solid-state imaging element according to any one of claims 1 to 5, wherein The photoelectric conversion element includes a first photoelectric conversion element and a second photoelectric conversion element. The front-stage charge holding region includes a first front-stage charge holding region and a second front-stage charge holding region. The latter stage charge holding region includes a first latter stage charge holding region and a second latter stage charge holding region. The front-stage transfer transistor includes a first front-stage transfer transistor and a second front-stage transfer transistor, The intermediate transfer transistors include a first intermediate transfer transistor and a second intermediate transfer transistor, and The latter-stage transfer transistor includes a first latter-stage transfer transistor and a second latter-stage transfer transistor.

10. The solid-state imaging element according to any one of claims 1 to 5, further comprising: a charge discharge transistor that discharges charge from the photoelectric conversion element, a reset transistor that initializes the floating diffusion region, an amplifying transistor that amplifies a signal corresponding to the amount of charge transferred to the floating diffusion region, and A selection transistor is configured to output the amplified signal as a pixel signal according to a predetermined selection signal. 11 . An imaging device comprising the solid-state imaging element according to claim 1 .

12. A method for controlling a solid-state imaging element, comprising: A front-stage transfer process of transferring charge from a photoelectric conversion element to a front-stage charge holding region and a rear-stage charge holding region having different capacities; a subsequent-stage transfer process of transferring charge from the subsequent-stage charge holding region to a floating diffusion region, wherein charge leakage from the photoelectric conversion element to the subsequent-stage charge holding region is prevented by a light-shielding wall; and an intermediate transfer process of transferring the charge remaining in the preceding-stage charge holding region after the charge has been transferred from the succeeding-stage charge holding region to the floating diffusion region via the preceding-stage charge holding region to the floating diffusion region, Among them, among the first pixel signal corresponding to the amount of charge transferred from the latter-stage charge holding area and the second pixel signal corresponding to the amount of charge transferred from the former-stage charge holding area and the latter-stage charge holding area, the signal processing circuit compares the first pixel signal with a predetermined threshold value and performs processing to select one of the first pixel signal and the second pixel signal based on the comparison result.

Images