Effective Storage Allocation for Sequentially-Written Memory Devices

Abstract

This application relates to efficient storage allocation for sequentially written memory devices. An input / output (I / O) write request pointing to a plurality of memory devices having memory cells is received by a processing device. The write request includes a data set. The processing device appends the data set to a composite data object. The composite data object includes one or more sequentially written data objects. The processing device associates the composite data object with one or more memory cell groups of the plurality of memory devices. The processing device causes the composite data object to be written to the one or more memory cell groups of the plurality of memory devices.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to memory subsystems, and more particularly, to efficient storage allocation for sequentially writing to memory devices. Background Art

[0002] A memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at and retrieve data from the memory devices. Summary of the Invention

[0003] One aspect of the present application relates to a system that includes a plurality of memory devices and a processing device coupled to the plurality of memory devices. The processing device performs operations including: receiving an input / output (I / O) write request directed to the plurality of memory devices, where the I / O write request includes a data set; appending the data set to a composite data object, where the composite data object includes one or more sequentially written data objects; associating the composite data object with one or more memory cell groups of the plurality of memory devices; and causing the composite data object to be written to the one or more memory cell groups of the plurality of memory devices.

[0004] Another aspect of the present application relates to a method that includes: receiving, by a processing device executing a file system of an operating system, an input / output (I / O) write request directed to a memory subsystem that includes a memory device, where the memory device includes a plurality of zones and where the I / O write request includes at least a portion of a file; appending the at least a portion of the file to a composite file, where the composite file includes one or more sequentially written files; allocating the composite file to one or more of the plurality of zones; and causing the composite file to be written to the one or more of the plurality of zones.

[0005] Yet another aspect of the present application relates to a non-transitory computer-readable storage medium that includes instructions that, when executed by a processing device, cause the processing device to perform operations including: receiving an input / output (I / O) write request directed to a plurality of memory devices, where the I / O write request includes a data set; appending the data set to a composite data object, where the composite data object includes one or more sequentially written data objects; associating the composite data object with one or more memory cell groups of the plurality of memory devices; and causing the composite data object to be written to the one or more memory cell groups of the plurality of memory devices. Brief Description of the Drawings

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the disclosure. However, the figures should not be regarded as limiting the disclosure to specific embodiments, but are for explanatory and understanding purposes only.

[0007] Figure 1A Illustrate an example computing system that includes a memory subsystem in accordance with some embodiments of the present disclosure.

[0008] Figure 1B For a Figure 1A detailed block diagram of a computing system in accordance with some embodiments.

[0009] Figure 2 A block diagram illustrating an example of a zone mapping data structure in accordance with some embodiments.

[0010] Figure 3 A schematic diagram illustrating a data object attached to a composite data object in accordance with some embodiments.

[0011] Figure 4 A schematic diagram illustrating a data object allocated to a group of memory cells in accordance with some embodiments.

[0012] Figure 5 A flowchart of an example method for efficiently allocating data objects to groups of memory cells of a memory device in accordance with some embodiments of the present disclosure.

[0013] Figure 6 A flowchart of an example method for performing a zone reset in accordance with some embodiments of the present disclosure.

[0014] Figure 7 A flowchart of an example method for efficiently allocating a sequentially written file to zones of a memory device in accordance with some embodiments of the present disclosure.

[0015] Figure 8 A block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0016] Aspects of the present disclosure relate to efficient storage allocation for sequentially writing to a memory device. A memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices and memory modules are described below in connection with Figure 1A Typically, a host system may utilize a memory subsystem that includes one or more components such as a memory device that stores data. The host system may provide data to be stored at the memory subsystem and may request retrieval of data from the memory subsystem.

[0017] A memory subsystem may include high-density non-volatile memory devices where data retention is desired when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND memory device. Other examples of non-volatile memory devices are described in conjunction with Figure 1A A non-volatile memory device is a package of one or more dies. Each die may be composed of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a set of physical blocks. Each block is composed of a set of pages. Each page is composed of a set of memory cells ("cells"). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and have various logical states associated with the number of bits stored. The logical states may be represented as binary values such as "0" and "1", or combinations of such values.

[0018] A memory subsystem may include multiple components such as a memory device that stores data from a host system in a storage medium (e.g., an integrated circuit (IC) die having addressable memory cells that store data individually). Processing in certain memory subsystems today is typically performed by randomly allocating to the IC die and in smaller data increment sizes (e.g., four kilobytes (KB)). These random allocations of pages or data blocks include non-sequential and / or random writes to the IC die. This practice results in high costs in the memory for storing mapped data structures such as dynamic random access memory (DRAM), static random access memory (SRAM), or persistent memory, which track the logical-to-physical (L2P) address mapping between the logical block address (LBA) space and the physical address space of the IC die. For example, the mapping overhead is approximately one gigabyte (GB) per terabyte (TB) of host addressable media, and thus, a 16 TB solid state drive (SSD) requires a significant 16 GB of memory mapping overhead. Additionally, periodic snapshots and recordings are made to persist the mapped data structures in the event of a shutdown and unexpected power failure. This adds additional write overhead and performance loss to the IC die.

[0019] A storage stack that maps physical block devices to a higher-level virtual block device can utilize sequential input / output (I / O) memory device efficiency. The storage stack can be used to direct I / O from user space applications to physical memory devices. For example, the storage stack is included in file system group data by locality (e.g., according to thread, process, lifetime, or application) and writes data sequentially to the storage device. The file system can then write data of different localities to the storage device as parallel sequential streams, each stream having its own locality. References to locality can refer to temporal locality or spatial locality. Data with temporal locality is data that a processor tends to access repeatedly at the same memory location within a short period of time, e.g., data that is written, overwritten, and fine-tuned at approximately the same time. Data with spatial locality has the tendency that when a memory device references a particular storage location at a particular time, the memory device is likely to reference nearby memory locations in the near future. In this case, the processor can attempt to determine the size and shape of the area around the currently referenced area that is worth preparing for faster access for subsequent accesses. A reference to sequential locality is a special case of spatial locality that occurs when data elements are linearly arranged and accessed (e.g., when traversing the elements in a one-dimensional array).

[0020] When writing data with locality sequentially, the data is written to a group of memory cells, also simply referred to as a zone, where each zone can store multiple physical blocks of data. Thus, mapping can be recorded at a higher granularity (megabytes instead of kilobytes) to map a particular group of data to a zone in the LBA space, which significantly reduces the metadata recorded. The mapping space associated with the LBA space at this granularity can be referred to as a zone namespace (ZNS), and the memory device written in this way is referred to as a ZNS memory device. In one example, the group of data consists of multiple data blocks with locality, where each data block corresponds to a physical block (e.g., an erase unit) of an IC die. In one embodiment, the size of a physical block (or erase unit) of the memory device is approximately 16 megabytes (MB). The group of memory cells (or zone) can be at least two to four times (or more) the size of a physical block. Thus, a zone can store at least 64 MB of data (e.g., 64 MB, 128 MB, 256 MB, 512 MB, or more), each of which is significantly larger than four kilobytes (KB).

[0021] In some host operating systems, the file system manages files from the operating system, files from applications running on the operating system, and metadata generated by the file system for the purpose of organizing files and allocating space in the IC die, the space being necessary for writing the files and the metadata when the metadata is generated. The file systems of some host operating systems (e.g., Linux, Unix, etc.) allocate block groups (e.g., contiguous portions of a file, such as a series of LBAs) to a series of physical addresses in the IC die where the block groups are stored. Files can be, for example, data files, metadata containing inodes, directory structures, free space managers, etc., as well as other data structures (or objects) capable of encapsulating data / metadata and being written to the IC. These file systems typically allocate certain types of block groups to a specific series of physical addresses of the memory device based on whether the block groups contain data or metadata, and attempt not to intermix the data and metadata within these specific series of physical addresses. In some host operating systems, for the purpose of organizing data objects and allocating space in the memory device, a device mapper operating at the kernel level manages data objects from the operating system. For example, a host system can include a software framework designed to receive (or intercept) write requests directed to the memory device. A write request can include a payload that contains the data to be written. The payload can have certain characteristics, for example, whether the data to be written represents metadata or data in a file system, or a key or value in a key-value store.

[0022] In some host operating systems, a file system driver and / or a storage driver can be configured to allocate groups (or regions) of memory cells to specific data sets. For example, a host operating system (e.g., the file system of a host operating system) can allocate one or more groups (or regions) of memory cells to each stream. A stream can contain a data set (e.g., a file, a group of files, a data object, a group of data objects, or another similar construct) that shares one or more characteristics (e.g., creation or deletion time, access frequency, etc.).

[0023] Each memory cell group may have a specific size. In some host systems, each data set is assigned to one or more memory cell groups such that no memory cell groups are shared between two or more data sets (streams). However, the size of a data set may not match the size of a memory cell group. When this occurs, the data set does not completely fill the memory cell group, resulting in empty and unavailable memory cells. For example, a data set that is one quarter the size of a memory cell group will be stored in one memory cell group, leaving three quarters of the memory cell group empty. As another example, a data set that is 3.5 times the size of a memory cell group will be stored in 4 memory cell groups, leaving one half of the memory cell groups empty. This empty space can lead to inefficient use of the memory device.

[0024] Aspects of the present disclosure address the above - noted deficiencies and other deficiencies by enhancing the ability of a host system (e.g., the file system of a host operating system and / or a device mapper associated with the host system) to assign one or more data sets to each memory cell group (e.g., to each zone in a ZNS). In some embodiments, aspects of the present disclosure may be implemented by a memory subsystem controller. Instead of assigning each data set to one or more memory cell groups, a host system operating in accordance with aspects of the present disclosure may append one or more data sets to a composite data object, such as a temporary file residing in volatile memory. The composite data object contains two or more sequentially written data sets (data objects). The host system associates the composite data object with one or more memory cell groups of a memory device and causes the composite data object to be written to the one or more memory cell groups. Thus, each memory cell group (e.g., each zone in a ZNS) can be shared among one or more data sets and each memory cell group can be utilized fully.

[0025] Advantages of the present disclosure include, but are not limited to, improving the utilization efficiency of zones using ZNS. Some storage allocation systems for sequential writes to a memory device (e.g., using ZNS) where zones are not shared among data sets may result in partially filled zones that are equivalent to wasted storage capacity. In contrast, aspects of the present disclosure achieve fully filled zones by enabling zones to be shared among multiple data sets, thus avoiding wasted storage capacity. Additionally, aspects of the present disclosure reduce write amplification. Zone reset involves erasing an entire zone. During zone reset in some systems where zones are partially filled, erasing the entire zone will result in unnecessary erasure of empty blocks, thus increasing write amplification, which adversely affects the wear of the memory device. Therefore, an advantage of the present disclosure is reduced write amplification, which results in a longer memory device life. Other advantages discussed below will be apparent to those skilled in the art of memory allocation and mapping to memory devices.

[0026] Figure 1A Describe an example computing system 100 that includes a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such devices.

[0027] The memory subsystem 110 can be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controllers (eMMCs), universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0028] The computing system 100 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, an industrial device, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0029] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple different types of memory subsystems 110. Figure 1A Describe an example of a host system 120 coupled to one memory subsystem 110. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without an intermediate component), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0030] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110 to, for example, write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0031] The host system 120 can be coupled to the memory subsystem 110 through a physical host interface. Examples of the physical host interface include but are not limited to Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnect Express (PCIe) interface, Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), Double Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interface (e.g., DIMM socket interface supporting Double Data Rate (DDR)), etc. The physical host interface can be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a physical host interface (e.g., PCIe bus), the host system 120 can further utilize the Non-Volatile Memory Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface can provide an interface for transmitting control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1A The memory subsystem 110 is described as an example. Generally speaking, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0032] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. The volatile memory device (e.g., the memory device 140) can be but is not limited to random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0033] Some examples of non-volatile memory devices (e.g., the memory device 130) include NAND-type flash memory and write-in-place memory, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory cells can perform bit storage based on the change of bulk resistance in combination with a stackable cross-gridded data access array. In addition, compared with many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, in which non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0034] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), and penta-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to the logical units of the memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0035] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND-type flash memories (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), nor flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0036] The memory subsystem controller 115 (or simply the controller 115 for simplicity) may communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-wired) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., field programmable gate array (FPGA), application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0037] The memory subsystem controller 115 may include a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines to control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0038] In some embodiments, the local memory 119 may include memory registers that store memory pointers, fetched data, and the like. The local memory 119 may also include a read-only memory (ROM) for storing microcode. Although the example memory subsystem 110 in Figure 1A is illustrated as including the memory subsystem controller 115, in another embodiment of the present disclosure, the memory subsystem 110 does not include the memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0039] Generally, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may translate the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block address (LBA), namespace) and physical addresses (e.g., physical block address) associated with the memory device 130. The memory subsystem controller 115 may also include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry may translate commands received from the host system into command instructions to access the memory device 130 and translate responses associated with the memory device 130 into information for the host system 120.

[0040] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that may receive an address from the memory subsystem controller 115 and decode the address to access the memory device 130.

[0041] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory subsystem 110 is a managed memory device that is an original memory device 130 with control logic on the die (e.g., the local media controller 135) and a controller for media management within the same memory device package (e.g., the memory subsystem controller 115). An example of a managed memory device is a managed NAND (MNAND) device.

[0042] The computing system 100 includes a storage drive 133 in the host system 120, the storage drive being configured with the storage allocation and device mapping functions discussed throughout the figures herein. In some embodiments, the storage allocation and device mapping functions may be implemented by a user space drive. In some embodiments, the host system 120 includes at least a portion of the storage allocation and device mapping functions. In other embodiments, the memory subsystem controller 115 includes at least a portion of the storage allocation and device mapping functions. For example, the memory subsystem controller 115 and the processing device (processor) of the host system 120 may be configured to execute instructions stored in memory for performing operations of the mapping and storage allocation functions described herein.

[0043] Figure 1B is in accordance with some embodiments Figure 1ADetailed block diagram of computing system 100. In various embodiments, host system 120 includes processing device 122, cache 123, file system driver 124, one or more applications 126A through 126B, and storage driver 133. In an embodiment, processing device 122 can execute instructions to execute storage driver 133 and / or file system driver 124, for example, by executing the kernel of the operating system of host system 120. Host system 120 can execute one or more applications 126A through 126B. In an illustrative example, application 126A can communicate with file system driver 124. File system driver 124 can run in the kernel space of host system 120 and can be used to process I / O requests (e.g., as read, write, and erase operations) initiated by one or more applications 126 (including application 126A) running in the user space of host system 120. In an embodiment, file system driver 124 can translate read, write, erase, and other requests issued by application 126A to storage driver 133. Storage driver 133 can communicate with memory subsystem controller 115. Storage driver 133 can run in the kernel space of host system 120 and can process requests received from file system driver 124 and / or from application 126B. Storage driver 133 can process the requests into commands to be processed by memory subsystem controller 115. In some embodiments, the storage allocation and device mapping functions described in detail can be implemented by a user space driver. That is, the functions described with respect to storage driver 133 can be implemented by a user space driver (not shown).

[0044] In various embodiments, computing system 100 includes a memory device 130 associated with a sequential namespace (e.g., ZNS). In one embodiment, memory device 130 is a partitioned namespace (ZNS) solid state device that implements the partitioned namespace command set defined by the Non-Volatile Memory Express TM (NVMe TM ) organization. A zone in ZNS can be a block group of sequentially numbered LBAs that map to sequentially ordered physical addresses within a physical address space. Memory device 130 can be the storage device previously mentioned that includes multiple IC dies. Writing sequentially to zones (e.g., zone 0, zone 1,... zone N-1), also referred to as memory cell groups, is generally performed sequentially from the top (or lowest address) to the bottom (or highest address) of the IC die, as illustrated by the patterned data blocks that have been written to the zones described. Memory device 130 can also include composite data object 160 and zone mapping data structure 158. In conjunction with Figure 2Describe an example zone mapping data structure. In an embodiment, the zone mapping data structure 158 and / or the composite data object 160 may be stored in a volatile memory device. In an embodiment, the zone mapping data structure 158 may be a data structure for providing memory device layout information for each zone in a namespace. In an embodiment, the zone mapping data structure 158 may include a logical-to-physical (L2P) mapping data structure to map logical block numbers (or addresses) in the LBA space to memory blocks assigned to a zone or a memory group. In these embodiments, the storage driver 133 may track the logical block numbers (or addresses) in the LBA space to the ZNS of the memory device 130 through a sequential relationship, such as through sequential physical addresses programmed to access zones (or groups of memory cells) within multiple IC dies of the memory device 130. A write pointer (WP) to a zone of the memory device 130 may be stored in the cache 123.

[0045] In an embodiment, the storage driver 133 of the host system 120 may receive write requests from the application 126A and / or from the file system driver 124. The write requests may be directed to multiple IC dies of the memory device 130. The write requests may include at least a portion of a stream to be stored at the memory device 130. The stream may contain data sets (such as files, file groups, data objects, data object groups, or other similar constructs) that share one or more characteristics (such as creation or deletion time, access frequency, etc.). The storage driver 133 may identify the data sets from the write requests and append the data sets to the composite data object 160. The composite data object 160 contains sequentially written data objects. The composite data object 160 may be stored as a temporary file residing on a volatile memory device of the memory subsystem. Additionally or alternatively, the composite data object 160 may be stored in the non-volatile memory device 130. Examples of data sets appended to the composite data object 160 are described below Figure 3 as follows. The storage driver 133 may associate the composite data object with a group of memory cells of the memory device 130 and write to the group of memory cells by updating the zone mapping data structure 158. For example, the storage driver 133 may associate each data set in the composite data object 160 with one or more zones. The storage driver 133 may update the zone mapping data structure 158 to include which data sets are assigned to each zone and increment the data set counter. The zone mapping data structure 158 is further described in conjunction with Figure 2 the following.

[0046] In an embodiment, the storage driver 133 may maintain a data set counter for each group of memory cells (the group of memory cells is Figure 1B(described as a region in the Examples). In an embodiment, the counter can be stored in the cache 123 and / or stored in the region mapping data structure 158. Each data set counter represents the number of streams (or data sets) allocated to the region. When the storage drive 133 associates the composite data object 160 with a region in the memory device 130, the storage drive 133 can increment the counter associated with each region based on the number of data sets associated with each corresponding region. For example, region 0 can be shared among three data sets, and thus the storage drive 133 can increment (e.g., increment by one) the counter associated with region 0 three times. As another example, region 1 can be shared among two data sets, and thus the storage drive 133 can increment the counter associated with region 1 twice.

[0047] In an embodiment, the storage drive 133 of the host system 120 can receive an erase or delete request directed to multiple IC dies of the memory device 130. The erase request can specify which stream (or data set) is to be deleted. Using the region mapping data structure 158, the storage drive 133 can identify the group of memory cells (e.g., region) storing the data set. In an embodiment, the erase request can include the LBA where the data set to be erased is located. The storage drive 133 can use the region mapping data structure 158 to translate the LBA to the physical address of the block in the memory device 130 storing the data set to be erased. The storage drive 133 can mark the block storing the data set to be erased for erasure. In addition, the storage drive 133 can decrement the counter associated with the group of memory cells storing the data set marked for erasure. For example, if the storage drive 133 receives an erase request for a data set associated with region 0, the storage drive 133 can mark the block storing the data set for erasure and can decrement (e.g., decrement by 1) the counter associated with region 0. As another example, if the storage drive 133 receives an erase request for a data set associated with both region 0 and region 1, the storage drive 133 can mark the block storing the data set for erasure and can decrement the counters associated with region 0 and region 1. In an embodiment, marking the data set for erasure can include updating the L2P mapping data structure to indicate that the block storing the data set contains invalid data.

[0048] To implement zone reset, the storage drive 133 may use a dataset counter to identify empty zones. In an embodiment, the zone mapping data structure 158 may maintain a pool of free zones, and the storage drive 133 may use the pool of free zones to allocate newly written datasets. Once a zone is empty (e.g., the dataset stored in the zone has been marked for erasure), the zone may be reset and returned to the pool of free zones. The storage drive 133 may identify zones that meet the zone reset condition by identifying zones with a counter that meets a threshold condition. In an embodiment, the threshold condition may be a threshold value, such as a value of zero. Thus, the storage drive 133 may identify zones with a counter value of zero that meet the zone reset condition. The storage drive 133 may perform zone reset for zones with a dataset counter value that meets the threshold condition, which may involve marking multiple memory devices associated with the zone to be erased and returning the zone to the free pool. In an embodiment, the memory cells associated with the zone are not erased until just before they are rewritten to avoid threshold voltage shift.

[0049] Figure 2 FIG. is a block diagram illustrating an example of a zone mapping data structure 158 according to various embodiments. The controller 115 may store the zone mapping data structure 158 in Figure 1B the non-volatile memory device 130. Alternatively or additionally, the controller 115 may store the zone mapping data structure 158 in a volatile memory device (e.g., Figure 1A the memory device 140). Alternatively or additionally, the host system 120 may store at least a portion of the zone mapping data structure 158 in local memory. The controller 115 may use the zone mapping data structure 158 itself or in combination with other data structures not depicted to configure or implement a media layout (e.g., a layout of where data groups of zones will be located within the physical address space).

[0050] In Figure 2 it, the zone mapping data structure 158 is configured to provide memory device layout information for zones in a namespace (e.g., an LBA space for ZNS operations). The zone mapping data structure 158 may have multiple entries. Each zone mapping entry in the zone mapping data structure 158 identifies information about a zone, e.g., the starting LBA 260 of the zone, the block set identifier 262 of the zone, the zone cursor value 264, the status 266 of the zone, the dataset identifier 268, the counter 270 of the zone, etc.

[0051] The host system 120 can associate the composite data object 160 with one or more extents starting at the starting LBA 260 of the first free extent. The host system 120 can sequentially write the composite data object 160 into the extents in the LBA space. After a certain amount of data has been written into an extent, the current starting LBA address for writing subsequent data is identified by the extent cursor value 264. The status 266 can have values indicating that the extent is empty, full, implicitly open, explicitly open, closed, etc., to track the process of writing to the extent.

[0052] The composite data object 160 includes one or more data sets. In an embodiment, the extent mapping data structure 158 can include a data set identifier 268. The data set identifier 268 can store a reference to the data set stored in the extent. For example, the data set identifier 268 can include a specific data set ID for each data set stored in the extent. In addition, for each data set stored in the extent, a counter 270 can increment a predetermined value (e.g., increment by one). For each data set marked for erasure in the extent, the counter 270 can decrement a predetermined value (e.g., decrement by one). Thus, the counter 270 represents the number of data sets associated with each extent. Thus, the counter 270 can be used to identify empty extents. For example, for a counter 270 starting with a zero value, the host system 120 and / or the controller 115 can determine that an extent with a counter 270 value of zero is empty. An empty extent is an extent in which all data stored in the extent has been marked for erasure. The controller 115 can assign the empty extent to the free extent pool.

[0053] Figure 3 Describe data objects attached to the composite data object 300 implemented in accordance with some embodiments of the present disclosure. In some embodiments, the composite data object 300 can be Figure 1B the same as the composite data object 160. This example illustrates attaching a data set to a composite data object. However, as described throughout the present disclosure, embodiments of the present disclosure can be applied to data objects, groups of data objects, files, groups of files, or other similar constructs. In an embodiment, the composite data object 300 can be stored in Figure 1B the extent mapping data structure 158, or can be locally stored on Figure 1B the host system 120.

[0054] In an embodiment, the processing logic of the host system (e.g., the device mapping logic of the kernel) receives a write request directed to a plurality of memory devices. In Figure 3In the example described, the write requests include data sets (DS) A - D 310A to 310D. For example, the first write request includes data set A 310A, the second write request includes DS B 310B, the third write request includes DS C 310C, and the fourth write request includes DS D 310D. In a conventional host operating system, the processing logic of the host system would associate each data set with an integer number of groups of memory cells (e.g., extents). For example, if data set A 310A is 3.5 times the extent size, the conventional host operating system would allocate 4 extents to data set A 310A, leaving half of the extent empty. As another example, if DS C 310C is one - tenth of the extent size, the conventional host operating system would allocate 1 extent to DS C 310C, leaving nine - tenths of the extent empty.

[0055] As Figure 3 illustrated, data sets A - D 310A to 310D are sequentially appended to the composite data object 300. In an embodiment, the kernel may store entries into a logical - to - physical (L2P) mapping data structure that maps the data sets to the composite data object 300. Additionally, the kernel may store additional entries that map the composite data object to a particular group of memory cells, as described Figure 4 below.

[0056] Figure 4 illustrates data sets from Figure 3 that are allocated to groups of memory cells (illustrated as extents) in the memory device 130. As Figure 4 illustrated, data set A 310A completely fills extents 0, 1, 2, and 3, and a portion of extent 4. Extent 4 is shared between data set A 310A and data set B 310B. Data set B 310B further completely fills extents 5 through 7, and a portion of extent 8. Data set C 310C is allocated to a portion of extent 8. The remainder of extent 8 is allocated to data set D 310D. Data set D 310D further fills extents 9 through 12, and a portion of extent 13. As Figure 4 illustrated, each extent may be allocated to more than one data set.

[0057] In response to allocating an extent (or a portion of an extent) to a data set, the storage drive increments a counter associated with the extent (e.g., increments by 1). For example, each data set counter may start at 0 and be incremented by 1 whenever the data set is written to the extent. Thus, in Figure 4In the example, the counter associated with zone 0 will be 1 because only data set A 310A is associated with zone 0. The counter associated with zone 4 will be incremented twice because zone 4 is associated with data set A 310A and data set B 310B. The counter associated with zone 8 will be incremented three times because zone 8 is associated with data set B 310B, data set C 310C, and data set D 310D.

[0058] According to this illustrative example, the DS identifier 268 entry for zone 0 in the zone mapping data structure 158 references data set A, and the counter 270 entry for zone 0 in the zone mapping data structure 158 is incremented by a predetermined value (e.g., incremented by 1). The DS identifier 268 entry for zone 4 in the zone mapping data structure 158 references data sets A and B, and the counter 270 entry for zone 4 in the zone mapping data structure 158 is incremented twice by the predetermined value. The DS identifier 268 entry for zone 8 in the zone mapping data structure 158 references data sets A, B, and C, and the counter 270 entry for zone 8 in the zone mapping data structure 158 is incremented three times by the predetermined value. Finally, the DS identifier 268 entries for zone 13 in the zone mapping data structure 158 all reference data set D, the counter 270 entry for zone 13 in the zone mapping data structure 158 is incremented by the predetermined value, and the status 266 entry for zone 13 in the zone mapping data structure 158 may indicate that the zone is not full and that the next composite data object written by the host system will start from this zone.

[0059] In an embodiment, the kernel receives a delete or erase request. The storage drive identifies which data set is included in the delete request and marks the data set for erasure. Specifically, the storage drive may identify the zone to which the data set in the delete request is assigned and may mark the blocks associated with the data set for erasure. The storage drive also decrements the counter associated with the zone to which the data set is associated. As an illustrative example, if the kernel receives a delete request for data set C 310C, the storage drive may identify the blocks in zone 8 to which data set C 310C is assigned and mark those blocks for erasure. In addition, the storage drive may decrement the counter associated with zone 8 (e.g., decrement by one). The storage drive may use the counter associated with each zone to identify empty zones. If the data set counter associated with a particular zone meets a threshold, the storage drive may determine that the particular zone is empty and may perform a zone reset, as further described below with respect to Figure 6 is further described.

[0060] Figure 5is a flow diagram of an example method 500 for efficiently allocating data objects from a write request to a group of memory cells of a memory device in accordance with some embodiments of the present disclosure. Method 500 may be executed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 500 is executed by Figure 1A and 1B host system 120 (e.g., via storage driver 133 executed by processing device 122). Although shown in a particular order or sequence, the order of the process may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood only as examples, and the illustrated process may be executed in a different order, and some processes may be executed in parallel. Additionally, one or more processes may be omitted in various embodiments. Accordingly, not all processes are required in every embodiment. Other process flows are possible.

[0061] At operation 510, the processing logic receives an input / output (I / O) write request directed to a plurality of memory devices, such as Figure 1A memory device 130. The write request may be a request to write a data set to memory device 130. The data set may include one or more data objects sharing one or more characteristics (e.g., creation or deletion time, access frequency, etc.). In an embodiment, the write request is received from a file system executing on the host system.

[0062] At operation 520, the processing logic appends the data set to a composite data object. The composite data object may be a data object that includes one or more sequentially written data objects. Thus, at operation 520, the processing logic sequentially adds one or more data objects included in the data set to the end of the composite data object. In an embodiment, the processing logic stores an entry into a zone mapping data structure that maps the data set to the composite data object.

[0063] At operation 530, the processing logic associates the composite data object with one or more groups of memory cells of multiple memory devices. In an embodiment, the processing logic may allocate one or more sequentially written data objects from the composite data object to one or more groups of memory cells of the multiple memory devices. The groups of memory cells may be sequentially numbered LBAs that map to physically sequential addresses within the physical address space of the die. The processing logic may increment a data set counter associated with each of the one or more groups of memory cells of the multiple memory devices. The data set counter represents the number of data sets allocated to each memory cell group, and thus the processing logic increments each data set counter according to the number of data sets allocated to the corresponding memory cell group.

[0064] At operation 540, the processing logic causes the composite data object to be written to one or more groups of memory cells of the multiple memory devices. For example, the processing logic sends a write command to the memory device. The write command may include the composite data object and may be directed to one or more groups of memory cells. In an embodiment, the storage driver may access the physical addresses of the groups of memory cells of the multiple memory devices. Additionally, the storage driver performs a sequential write operation for the physical addresses.

[0065] At operation 550, the processing logic stores one or more entries into a logical-to-physical (L2P) mapping data structure, the one or more entries mapping one or more data objects from a logical block address (LBA) to memory blocks in non-volatile memory allocated to one or more groups of memory cells.

[0066] Figure 6 is a flowchart of an example method 600 for implementing area reset according to some embodiments of the present disclosure. Method 600 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 600 is performed by Figure 1A and 1B host system 120 (e.g., via storage driver 133 executed by processing device 122). Although shown in a particular order or sequence, the order of the process may be modified unless otherwise specified. Accordingly, the illustrated embodiments should only be construed as examples, and the illustrated processes may be performed in a different order and some processes may be performed in parallel. Additionally, one or more processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0067] At operation 610, processing logic receives an input / output (I / O) erase request directed to multiple memory devices. The I / O erase request includes a data set to be erased.

[0068] At operation 620, processing logic identifies a memory cell group of the multiple memory devices associated with the data set. A logical-to-physical (L2P) mapping data structure includes entries that map the data set from a logical block address (LBA) to a memory block in non-volatile memory allocated to one or more memory cell groups. Processing logic may use the L2P mapping data structure to identify the memory cell group associated with the data set in the erase request.

[0069] At operation 630, processing logic marks the data set for erasure. Processing logic may use the L2P mapping data structure to identify the physical block storing the data set and mark the physical block for erasure. In an implementation, marking a physical block for erasure may include marking the block as invalid in the L2P mapping data structure.

[0070] At operation 640, processing logic decrements a counter associated with a memory cell group of the multiple memory devices. The counter represents the number of data sets associated with each memory cell group.

[0071] At operation 650, processing logic identifies an empty memory cell group, where the data set counter associated with the empty memory cell group meets a threshold condition. The threshold condition may be meeting a threshold, such as a value of zero. Thus, processing logic identifies a memory cell group having a data set counter of zero as empty.

[0072] At operation 660, processing logic marks the empty memory cell group for erasure. Processing logic may perform a reset on the memory cell group marked for erasure and return the memory cell group to an idle pool. Memory cell groups allocated to the idle pool may be erased and allocated to newly received write requests.

[0073] Figure 7 is a flowchart of an example method 700 for efficiently allocating sequentially written files to regions of a memory device according to some embodiments of the present disclosure. Method 700 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 700 is performed by Figure 1A and 1Bis executed by the host system 120 (e.g., via execution of a file system driver 124 and / or a storage driver 133 by the processing device 122). Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Accordingly, the illustrated embodiments should only be construed as examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. Additionally, one or more of the processes may be omitted in various embodiments. Accordingly, all processes are not required in every embodiment. Other process flows are possible.

[0074] At operation 710, processing logic receives an input / output (I / O) write request directed to a memory subsystem that includes a memory device, where the memory device includes a plurality of zones, and where the I / O write request includes at least a portion of a file. In an embodiment, the memory subsystem includes a solid state drive (SSD), and the plurality of zones includes a partition namespace.

[0075] At operation 720, processing logic appends at least a portion of the file to a composite file, where the composite file includes one or more sequentially written files. In an embodiment, the composite file may be a temporary file resident on a volatile memory device.

[0076] At operation 730, processing logic allocates the composite file to one or more of the plurality of zones. Processing logic stores an entry into a logical-to-physical (L2P) mapping data structure that maps the sequentially written file from a logical block address to a memory block in non-volatile memory allocated to the zone.

[0077] At operation 740, processing logic causes the composite file to be sequentially written to one or more of the plurality of zones. Processing logic may increment a file counter associated with each of the one or more zones. Each file counter may represent the number of files associated with a corresponding zone.

[0078] In an embodiment, processing logic may receive an erase request directed to a memory subsystem. The erase request may specify a file to be erased. The processing logic may use an L2P mapping data structure to identify the extents allocated to the file to be erased and decrement the file counter associated with the identified extents. Using the file counter, the processing logic may identify empty extents that meet an extent reset condition. Extent reset may include erasing the data stored at the extent and allocating the extent to a free extent pool. The processing logic may identify empty extents that meet the extent reset condition by identifying extents having a file counter that meets a threshold condition. In an implementation, the threshold condition may be a threshold of, for example, zero. Thus, the processing logic identifies extents having a file counter equal to zero as extents that meet the extent reset condition. The processing logic may mark the identified empty extents for erase, for example, by updating the LPT mapping data structure to mark the data stored in the empty extents as invalid. The processing logic may further associate the identified empty extents with the free extent pool.

[0079] Figure 8 An example machine of a computer system 800 is illustrated within which a set of instructions may be executed to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, the computer system 800 may correspond to a host system (e.g., Figure 1A and 1B host system 120) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1A memory subsystem 110). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0080] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a network device, a server, a network router, a switch, or a bridge, or any machine capable of executing a set of (sequentially or otherwise) instructions that specify actions to be taken by the machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein.

[0081] The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 818, which communicate with each other via a bus 830.

[0082] The processing device 802 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device 802 can also be one or more dedicated processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 802 is configured to execute instructions 826 for performing the operations and steps discussed herein. The computer system 800 may also include a network interface device 808 to communicate on a network 820.

[0083] The data storage system 818 may include a machine-readable storage medium 824 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 826 or software embodying any one or more of the methods or functions described herein. The instructions 826 may also reside, completely or at least partially, within the main memory 804 and / or within the processing device 802 during execution by the computer system 800, and the main memory 804 and the processing device 802 also constitute machine-readable storage media. The machine-readable storage medium 824, the data storage system 818, and / or the main memory 804 may correspond to Figure 1A the memory subsystem 110.

[0084] In one embodiment, the instructions 826 include instructions implementing the functionality corresponding to Figure 1A and 1B the storage driver 133. Although the machine-readable storage medium 824 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing a set or multiple sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding a set of instructions for execution by a machine and that causes the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid state memories, optical media, and magnetic media.

[0085] Some parts of what has been previously described in detail have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are ways for those skilled in the data processing art to most effectively convey the substance of their work to other technicians in the field. An algorithm is here, and generally, a self-consistent sequence of operations that produces the desired result. The operations are those that require physical manipulation of physical quantities. These quantities are often, but not necessarily, in the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Sometimes, for primarily general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and the like.

[0086] However, it should be borne in mind that all such and similar terms are to be associated with appropriate physical quantities and are merely convenient labels applied to these quantities. This disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the memory or registers of the computer system or other such information storage systems.

[0087] This disclosure also relates to apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such computer programs may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to the computer system bus.

[0088] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the method. The structure of many of these systems will be presented as will be set forth in the description below. Additionally, the present disclosure has not been described with reference to any particular programming language. It should be understood that various programming languages may be used to implement the teachings of the present disclosure described herein.

[0089] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable form (e.g., for a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium such as a read-only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory components, and the like.

[0090] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A system for storage allocation, wherein include: a plurality of memory devices; as well as a processing device coupled to the plurality of memory devices, the processing device performing operations comprising: receiving an input / output (I / O) write request directed to the plurality of memory devices, wherein the I / O write request comprises a first data object, wherein the plurality of memory devices comprises a plurality of memory cell groups corresponding to sequential logical addresses, and wherein each memory cell group of the plurality of memory cell groups is associated with an available capacity status, the available capacity status indicating at least one of: a full status or a not full status; appending the first data object to a composite data object, wherein the composite data object comprises one or more sequentially written data objects; identifying a first memory cell group of the plurality of memory cell groups based on an order corresponding to the sequential logical addresses, wherein the first memory cell group is in a not full state; associating a first portion of the composite data object with the first group of memory cells; responsive to determining that the first portion of the composite data object is associated with the first group of memory cells resulting in the full state of the first group of memory cells, identifying one or more sequential groups of memory cells in the not-full state in the order corresponding to the sequential logical addresses; associating a second portion of the composite data object with the one or more sequential groups of memory cells; as well as The composite data object is caused to be written to the first memory cell group and the one or more sequential groups of memory cells, resulting in the full state of the first memory cell group and at least one of the one or more sequential groups of memory cells.

2. The system of claim 1 , wherein the composite data object is associated with the first group of memory cells and the one or more sequential groups of memory cells. include: Allocating the one or more sequentially written data objects to the first memory cell group and the one or more sequential memory cell groups; as well as A data set counter associated with the first memory cell group and each of the one or more sequential groups of memory cells is incremented, wherein the data set counter represents a number of data sets associated with the one or more sequential groups of memory cells and each of the first memory cell group.

3. The system of claim 1, wherein the operations performed are performed by a storage driver on which an operating system of a host file system is executing.

4. The system of claim 3, wherein the storage driver can access physical addresses of cell groups of the plurality of memory devices, and wherein the storage driver is to perform sequential write operations for the physical addresses.

5. The system according to claim 1, wherein the operation further include: receiving an input / output (I / O) erase request directed to the plurality of memory devices, wherein the I / O erase request includes a second data set; identifying a second group of memory cells in the plurality of memory devices associated with the second data set; Mark the second data set for erasure; and decrement a data set counter associated with the second memory cell group of the plurality of memory devices, wherein the data set counter represents the number of data sets associated with each of the second memory cell groups.

6. The system according to claim 1, the operation further comprises: identifying an empty memory cell group, wherein a data set counter associated with the empty memory cell group meets a threshold condition; and marking the empty memory cell group for erasure.

7. The system according to claim 1, the operation further comprises: storing one or more entries into a logical-to-physical L2P mapping data structure, the one or more entries mapping the one or more sequentially written data objects from a logical block address LBA to memory blocks in a non-volatile memory allocated to the first memory cell group and the one or more memory cell sequential groups.

8. A method for storage allocation, which comprises: receiving, by a processing device executing a file system of an operating system, an input / output I / O write request directed to a memory subsystem including a memory device, wherein the memory device includes a plurality of zones corresponding to sequential logical addresses, wherein each of the plurality of zones is associated with an available capacity state, the available capacity state indicating at least one of: a full state or a non-full state, and wherein the I / O write request includes at least a portion of a file; appending the at least portion of the file to a composite file, wherein the composite file includes one or more sequentially written files; identifying a first zone among the plurality of zones based on an order corresponding to the sequential logical address, wherein the first zone is in a non-full state; allocating a first portion of the composite file to the first zone; in response to determining that allocating the first portion of the composite file to the first zone causes the full state of the first zone, identifying one or more sequential zones in the non-full state in the order corresponding to the sequential logical address; allocating a second portion of the composite file to the one or more sequential zones; and causing the composite file to be written to the first zone and the one or more sequential zones, resulting in the full state of the first zone and at least one of the one or more sequential zones.

9. The method according to claim 8, which further comprises: incrementing a file counter associated with each of the plurality of zones allocated to the one or more sequentially written files, wherein the file counter represents the number of files associated with each of the plurality of zones.

10. The method according to claim 8, wherein the memory subsystem includes a solid state drive SSD, and the plurality of zones includes a zoned namespace ZNS.

11. The method according to claim 8, which further comprises: receiving an input / output IO erase request directed to the memory subsystem, wherein the erase request includes a second file; identifying a second zone associated with the second file; marking the second file for erasure; and Decrement a file counter associated with the second region, where the file counter represents the number of files associated with the second region.

12. The method according to claim 8, further comprising: Identifying an empty region, where a file counter associated with the empty region meets a threshold condition; and Marking the empty region for erasure.

13. The method according to claim 8, further comprising: Storing one or more entries into a logical-to-physical L2P mapping data structure, the one or more entries mapping the one or more sequentially written files from a logical block address LBA to memory blocks in a non-volatile memory allocated to the first region and the one or more sequential regions.

14. A non-transitory computer-readable storage medium including instructions that, when executed by a processing device, cause the processing device to perform operations including the following: Receiving an input / output I / O write request directed to a plurality of memory devices, where the I / O write request includes a first data object, where the plurality of memory devices includes a plurality of groups of memory cells corresponding to sequential logical addresses, and where each group of memory cells of the plurality of groups of memory cells is associated with an available capacity state that indicates at least one of the following: a full state or a non-full state; Appending the first data object to a composite data object, where the composite data object includes one or more sequentially written data objects; Based on the order corresponding to the sequential logical address, identifying a first group of memory cells among the plurality of groups of memory cells, where the first group of memory cells is in a non-full state; Associating a first portion of the composite data object with the first group of memory cells; In response to determining that associating the first portion of the composite data object with the first group of memory cells causes the full state of the first group of memory cells, identifying, in the order corresponding to the sequential logical address, one or more sequential groups of memory cells in the non-full state; Associating a second portion of the composite data object with the one or more sequential groups of memory cells; and Causing the composite data object to be written to the first group of memory cells and the one or more sequential groups of memory cells, causing the full state of the first group of memory cells and at least one of the one or more sequential groups of memory cells.

15. The non-transitory computer-readable storage medium according to claim 14, where associating the composite data object with the first group of memory cells and the one or more sequential groups of memory cells comprises: Allocating the one or more sequentially written data objects to the first group of memory cells and the one or more sequential groups of memory cells; and Incrementing a data set counter associated with each of the first group of memory cells and the one or more sequential groups of memory cells, where the data set counter represents the number of data sets associated with each of the one or more sequential groups of memory cells and the first group of memory cells.

16. The non-transitory computer-readable storage medium according to claim 14, wherein the operations performed are performed by a storage drive of an operating system that is currently executing a host file system.

17. The non-transitory computer-readable storage medium according to claim 16, wherein the storage drive can access the physical addresses of a group of cells of the plurality of memory devices, and wherein the storage drive performs sequential write operations for the physical addresses.

18. The non-transitory computer-readable storage medium according to claim 14, wherein the processing device is configured to perform operations further comprising: Receiving an input / output (I / O) erase request directed to the plurality of memory devices, wherein the I / O erase request includes a second data set; Identifying a second group of memory cells in the plurality of memory devices associated with the second data set; Marking the second data set for erasure; And Decrementing a data set counter associated with the second group of memory cells of the plurality of memory devices, wherein the data set counter represents the number of data sets associated with the second group of memory cells.

19. The non-transitory computer-readable storage medium according to claim 14, wherein the processing device is configured to perform operations further comprising: Identifying an empty group of memory cells, wherein a data set counter associated with the empty group of memory cells meets a threshold condition; and Marking the empty group of memory cells for erasure.

20. The non-transitory computer-readable storage medium according to claim 14, wherein the processing device is configured to perform operations further comprising: Storing one or more entries into a logical-to-physical (L2P) mapping data structure, the one or more entries mapping the one or more sequentially written data objects from a logical block address (LBA) to memory blocks in non-volatile memory allocated to the first group of memory cells and the one or more groups of memory cells in sequence.

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