Device and method for configuring cooperative thread warps in vector computing system

Abstract

The present invention relates to a device and method for configuring cooperative thread bundles in a vector operation system, wherein the device comprises: a general register; an arithmetic logic unit; a thread bundle instruction scheduler and a plurality of thread bundle resource registers. The thread bundle instruction scheduler allows each of a plurality of thread bundles to include a portion of relatively independent instructions in the program core according to the thread bundle allocation instruction in the program core, and allows each of the plurality of thread bundles to access all or a specified part of the data in the general register through the arithmetic logic unit according to the configuration of the software during execution, and completes the operation of each of the above-mentioned thread bundles through the arithmetic logic unit. The present invention can be more widely adapted to different applications, such as big data, artificial intelligence operations, etc., by enabling the software to dynamically adjust and configure general registers to different thread bundles as described above.

Description

[0001] This application is a divisional application of a Chinese invention patent application filed on October 21, 2020, with application number 202011131448.9, and invention name “Device and method for configuring collaborative thread warps in a vector computing system”. Technical Field

[0002] The present invention relates to a vector operation device, and in particular to a device and method for configuring cooperative thread warps in a vector operation system. Background Art

[0003] A vector computer is a computer equipped with special vector instructions for increasing the speed of vector processing. A vector computer can process data calculations of multiple warps at the same time. Therefore, a vector computer is much faster than a scalar computer in processing warp data. However, multiple warps may conflict when accessing a general-purpose register file (GPR File). Therefore, the present invention proposes a method for configuring a device for cooperating warps in a vector computing system. Summary of the invention

[0004] In view of this, how to alleviate or eliminate the above-mentioned defects in related fields is indeed a problem to be solved.

[0005] An embodiment of the present invention relates to a device for configuring cooperative thread warps in a vector computing system, comprising: a general register; an arithmetic logic unit; a thread warp instruction scheduler and a plurality of thread warp resource registers. The thread warp instruction scheduler allows each of the plurality of thread warps to include a portion of relatively independent instructions in the program core according to the thread warp allocation instruction in the program core, allows each of the plurality of thread warps to access all or a specified part of the data in the general register through the arithmetic logic unit according to the configuration of the software during execution, and completes the operation of each of the above thread warps through the arithmetic logic unit. Each of the thread warp resource registers is associated with one of the thread warps and stores a base address corresponding to the associated thread warp. Wherein, before sending an instruction associated with one of the thread warps to the arithmetic logic unit, the thread warp instruction scheduler modifies the source address and destination address in the instruction according to the content of the corresponding thread warp resource register, so that the instruction can only access the specified part of the general register when executed by the arithmetic logic unit.

[0006] An embodiment of the present invention also relates to a method for configuring cooperative thread bundles in a vector computing system, comprising: according to the thread bundle allocation instructions in the program core, allowing each of the multiple thread bundles to include a portion of relatively independent instructions in the program core; according to the configuration of the software during execution, allowing each of the multiple thread bundles to access all or a specified part of the data in the general register through the arithmetic logic unit; and completing the operation of each of the above thread bundles through the arithmetic logic unit. The method also includes: providing a base address corresponding to each of the thread bundles; and before sending an instruction associated with one of the thread bundles to the arithmetic logic unit, modifying the source address and destination address in the instruction according to the corresponding base address, so that the instruction can only access the specified part of the general register when executed by the arithmetic logic unit.

[0007] One of the advantages of the above embodiment is that by enabling software to dynamically adjust and configure general registers to components and operations of different thread warps, it can be more widely adapted to different applications, such as big data, artificial intelligence computing, etc.

[0008] One of the advantages of the above embodiment is that by dynamically allocating multiple relatively independent instructions in the program core to different thread warps, mutual interference between thread warps can be avoided to improve the utilization rate of the pipeline.

[0009] Other advantages of the present invention will be explained in more detail with reference to the following description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application.

[0011] Figure 1 is a block diagram of a vector operation system according to an embodiment of the present invention.

[0012] Figure 2 is a block diagram of a streaming multiprocessor according to an embodiment of the present invention.

[0013] Figure 3 A schematic diagram of the partitioning of general registers in some implementation modes.

[0014] Figure 4 FIG. 1 is a schematic diagram of a dynamic partitioning of general registers with resource registers of each warp according to an embodiment of the present invention.

[0015] Figure 5 1 is a flow chart of an embodiment of the present invention, which is applied to cooperative warps for executing tasks in parallel.

[0016] Figure 6FIG. 4 is a schematic diagram of cooperative warps of producers and consumers according to an embodiment of the present invention.

[0017] Figure 7 1 is a flow chart of an embodiment of the present invention, which is applied to cooperative warps for executing producer-consumer tasks.

[0018] Among them, the simple description of the symbols in the accompanying drawings is as follows:

[0019] 10: electronic device; 100: streaming multiprocessor; 210: arithmetic logic unit; 220: thread bundle instruction scheduler; 230: general register; 240: instruction cache; 250: barrier register; 260, 260#0~260#7: resource registers of each thread bundle; 300#0~300#7: storage block of general registers; Base#0~Base#7: base position; S510~S540: method steps; 610: consumer thread bundle; 621, 663: barrier instruction; 623, 661: a series of instructions; 650: producer thread bundle; S710~S770: method steps. DETAILED DESCRIPTION

[0020] The embodiments of the present invention will be described below with reference to the accompanying drawings. In these drawings, the same reference numerals represent the same or similar components or method flows.

[0021] It must be understood that the words "comprise", "include" and the like used in this specification are used to indicate the existence of specific technical features, values, method steps, job processing, components and / or assemblies, but do not exclude the addition of more technical features, values, method steps, job processing, components, assemblies, or any combination of the above.

[0022] The words "first", "second", "third", etc. used in the present invention are used to modify the components in the claims, and are not used to indicate a priority order, a prior relationship, or that one component precedes another, or a time sequence when executing method steps. They are only used to distinguish components with the same name.

[0023] It should be understood that when a component is described as being "connected" or "coupled" to another component, it can be directly connected or coupled to the other component, and there may be intervening components. Conversely, when a component is described as being "directly connected" or "directly coupled" to another component, there are no intervening components. Other words used to describe the relationship between components can also be interpreted in a similar manner, such as "between" versus "directly between", or "adjacent" versus "directly adjacent", etc.

[0024] refer to Figure 1. The electronic device 10 can be implemented in electronic products such as mainframes, workstations, personal computers, laptop computers (Laptop PCs), tablet computers, mobile phones, digital cameras, digital video cameras, etc. The electronic device 10 can set a streaming multiprocessor cluster (Streaming Multiprocessor Cluster, SMC) in a vector computing system, including multiple streaming multiprocessors (Streaming Multiprocessor, SM) 100, and the instruction execution between different streaming multiprocessors 100 can be synchronized with each other using signals. After being programmed, the streaming multiprocessor 100 can execute various application tasks, including but not limited to: linear and nonlinear data conversion, database operations, big data operations, artificial intelligence calculations, audio, video data encoding, decoding, modeling operations, image rendering operations, etc. Each streaming multiprocessor 100 can execute multiple warps (Warps) at the same time, and each warp is composed of a group of threads (Group of Threads), and a thread is a minimum unit that runs using hardware and has its own life cycle. The thread warp may be associated with a single instruction multiple data (SIMD) instruction, a single instruction multiple thread (SIMT) technology, etc. The execution of different thread warps may be independent or sequential. A thread may represent a task associated with one or more instructions. For example, each stream multiprocessor 100 may execute 8 thread warps simultaneously, and each thread warp contains 32 threads. Although Figure 1 Four streaming multiprocessors 100 are described. Those skilled in the art may configure more or fewer streaming multiprocessors in a vector computing system according to different needs, and the present invention is not limited thereto.

[0025] refer to Figure 2. Each stream multiprocessor 100 includes an instruction cache (Instruction Cache) 240, which is used to store multiple instructions of the program kernel (Kernel). Each stream multiprocessor 100 also includes a warp instruction scheduler (WarpInstruction Scheduler) 220, which is used to extract a series of instructions for each warp and store them in the instruction cache 240, and obtain the instructions to be executed from the instruction cache 240 for each warp according to the program counter. Each warp has an independent program counter (Program Counter, PC) register, which is used to record the location of the instruction currently being executed (that is, the instruction address). Whenever an instruction is extracted from the instruction cache for a warp, the corresponding program counter is increased by one. The warp instruction scheduler 220 sends the instructions to the arithmetic logic unit (Arithmetic Logical Unit, ALU) 210 for execution at the appropriate time point. These instructions are defined in the instruction set architecture (Instruction Set Architecture, ISA) of the specific computing system. The arithmetic logic unit 210 can perform a variety of operations, such as integer and floating-point addition and multiplication calculations, comparison operations, Boolean operations, bit shifts, algebraic functions (such as plane interpolation, trigonometric functions, exponential functions, logarithmic functions), etc. During the execution process, the arithmetic logic unit 210 can read data from a specified location (also called a source address) of a general-purpose register (General-Purpose Registers, GPRs) 230, and write back the execution result to a specified location (also called a destination address) of the general-purpose register 230. Each streaming multiprocessor 100 also includes a barrier register 250, which can be used to allow the software to synchronize the execution between different thread warps, and a resource register 230 for each thread warp, which can be used to allow the software to dynamically configure the spatial range of the general-purpose register 230 that can be used by each thread warp during execution. Although Figure 2 Only components 210 to 260 are listed, but this is only used to briefly illustrate the technical features of the present invention. Those skilled in the art understand that each stream multiprocessor 100 also includes more components.

[0026] In some embodiments, the general register 230 can be physically or logically fixedly divided into multiple blocks, and the storage space of each block is only allocated to one thread warp for access. The storage space between different blocks does not overlap, so as to avoid access conflicts between different thread warps. Figure 3For example, when a stream multiprocessor 100 can process data of eight thread warps and the general register 230 includes 256 kilobytes (KB) of storage space, the storage space of the general register 230 can be divided into eight blocks 300#0 to 300#7, ​​each of which includes non-overlapping 32KB storage space and is provided to the specified thread warp for use. However, because vector operation systems are often used in big data and artificial intelligence computing, the amount of data processed is huge, so the fixed divided space may be insufficient for one thread warp and cannot meet the computing needs of a large amount of data. In order to be applied to big data and artificial intelligence computing, these embodiments can be modified to allow each stream multiprocessor 100 to only process the data of one thread warp, so that the storage space of the entire general register 230 is only used by this thread warp. However, when two consecutive instructions have data association, that is, the input data of the second instruction is the output result after the execution of the first instruction, the operation of the arithmetic logic unit 210 will be inefficient. Specifically, the second instruction must wait for the execution result of the first instruction to be ready in the general register 230 before it can start executing. For example, assume that each instruction in the pipeline needs 8 clock cycles from initialization to outputting the result to the general register 230: when the second instruction needs to wait for the execution result of the first instruction, the second instruction needs to start executing from the 9th clock cycle. At this time, the instruction execution latency is 8 clock cycles, resulting in a very low utilization rate of the pipeline. In addition, because the stream multiprocessor 100 only processes one thread bundle, instructions that could have been executed in parallel need to be arranged for sequential execution, which is inefficient.

[0027] In order to solve the above problems, from one aspect, the thread warp instruction scheduler 220 allows each of the multiple thread warps to access all or a specified part of the data in the general register 230 through the arithmetic logic unit 210 according to the configuration of the software during execution, and completes the operation of each thread warp through the arithmetic logic unit 210. By allowing the software to dynamically adjust and configure the general registers for different thread warps as described above, different applications can be more widely adapted, such as big data, artificial intelligence operations, etc.

[0028] From another aspect, the embodiments of the present invention provide an environment that enables software to determine the instruction segments contained in each thread warp. In some embodiments, a program core can divide instructions into multiple segments, each of which is independent of each other and is executed as a thread warp. Table 1 is an example of the virtual code of the program core:

[0029] Table 1

[0030]

[0031] Assume that each stream multiprocessor 100 runs at most eight thread warps, and each thread warp has a unique identifier: when the thread warp instruction scheduler 220 extracts the instructions of the program core shown in Table 1, it can check the thread warp identifier for a specific thread warp, jump to the instruction segment associated with this thread warp, and store it in the instruction cache 240, and then obtain instructions from the instruction cache 240 according to the value of the corresponding program counter and send it to the arithmetic logic unit 210 to complete a specific calculation. In this case, each thread warp can execute tasks independently, and all thread warps can run at the same time, so that the pipeline in the arithmetic logic unit 210 is as busy as possible to avoid bubbles. The instructions of each segment in the same program core can be called relatively independent instructions. Although the example in Table 1 adds conditional judgment instructions to the program core to achieve instruction segmentation, those skilled in the art can use other different instructions that can achieve the same or similar effects to complete instruction segmentation in the program core. In the program core, these instructions used to segment instructions for multiple thread warps can also be called thread warp allocation instructions. In general, the warp instruction scheduler 240 can allocate instructions according to the warp in the program core so that each of the plurality of warps includes a portion of relatively independent instructions in the program core, so as to allow the ALU 210 to execute the plurality of warps independently and in parallel.

[0032] The barrier register 250 can store information for synchronizing the execution of different warps, including the number of warps that need to wait for other warps to complete execution and the number of warps that are currently waiting to continue execution. In order to coordinate the execution process of different warps, the software can set the content of the barrier register 250 to record the number of warps that need to wait for execution to complete. Each instruction segment in the program core can add a barrier instruction (BarrierInstruction) at an appropriate place according to system requirements. When the warp instruction scheduler 220 extracts a barrier instruction for a warp, the number of warps that are waiting to continue execution recorded in the barrier register 250 is increased by 1, and the warp enters a waiting state. Then, the warp instruction scheduler 220 checks the content of the barrier register 250 to determine whether the number of warps that are currently waiting to continue execution is equal to or greater than the number of warps that need to wait for other warps to complete execution. If so, the warp instruction scheduler 220 wakes up all waiting warps so that these warps can continue execution. Otherwise, the warp instruction scheduler 220 extracts the instructions of the next warp from the instruction cache.

[0033] also, Figure 3The partitioning of the embodiment is a pre-configuration of the streaming multiprocessor 100 and cannot be modified by software. However, the storage space required by different warps may be inconsistent. For some warps, the pre-partitioned storage space may exceed the requirement, while for other warps, it may be insufficient.

[0034] On the other hand, although a stream multiprocessor 100 can execute multiple thread warps and all thread warps execute the same program core, the embodiment of the present invention does not pre-split the general registers 230 for different thread warps. Specifically, in order to more widely adapt to different applications, the stream multiprocessor 100 does not divide the general registers 230 into multiple blocks of storage space for multiple thread warps, but provides an environment that allows software to dynamically adjust and configure the general registers 230 for different thread warps, so that the software can allow each thread warp to use all or part of the general registers 230 according to application needs.

[0035] In some other embodiments, each stream multiprocessor 100 may include a warp resource register 260 for storing information about the base position of each warp, each base position pointing to a specific address of the general register 230. In order to allow different warps to access non-overlapping storage space in the general register 230, software may dynamically change the content of each warp resource register 260 to set the base position of each warp. For example, referring to Figure 4 , the software can divide the general register 230 into eight blocks for eight thread warps, the 0th block is associated with the 0th thread warp, and its address range includes Base#0 to Base#1-1; the 1st block is associated with the 1st thread warp, and its address range includes Base#1 to Base#2-1; and so on. The software can set the content of each thread warp resource register 260#0 to 260#7 before or at the beginning of the execution of the program core to point to the base address associated with each thread warp in the general register 230. After the thread warp instruction scheduler 220 extracts the instruction from the instruction cache 240 for the i-th thread warp, it can adjust the source address and destination address of the instruction according to the content of the thread warp resource register 260#i for mapping to the storage space dynamically allocated to the i-th thread warp in the general register 230. For example, the original instruction is:

[0036] Dest_addr=Instr_i(Src_addr0,Src_addr1)

[0037] Instr_i represents the operation code (OpCode) of the instruction assigned to the i-th thread warp, Src_addr0 represents the 0th source address, Src_addr0 represents the 1st source address, and Dest_addr represents the destination address.

[0038] The thread warp instruction scheduler 220 modifies the above-mentioned instruction to become:

[0039] Base#i+Dest_addr=Instr_i(Base#i+Src_addr0,Base#i+Src_addr1)

[0040] Base#i represents the base position recorded in the warp resource register 260#i. That is, the warp instruction scheduler 220 adjusts the source address and destination address of the instruction according to the content of each warp resource register 260 so that the designated parts of the general register mapped between different warps do not overlap.

[0041] In some other embodiments, not only can a program core divide instructions into multiple independent segments and execute each segment of instructions as a thread warp, but the software can also set the contents of each thread warp resource register 260#0 to 260#7 before or at the beginning of the execution of the program core to point to the base address associated with each thread warp in the general register 230.

[0042] The present invention can be applied to cooperative warps that execute tasks in parallel, see Figure 5 An example flowchart is shown.

[0043] Step S510 : the warp instruction scheduler 220 starts to extract instructions of each warp and stores them into the instruction cache 240 .

[0044] Steps S520 to S540 form a loop, and the warp instruction scheduler 220 may use a scheduling method (e.g., a polling scheduling algorithm) to obtain the specified instructions from the instruction cache 240 one by one according to the corresponding program counters of the warps, and send them to the arithmetic logic unit 210 for execution. The warp instruction scheduler 220 may sequentially obtain the instruction indicated by the program counter of the 0th warp, the instruction indicated by the program counter of the 1st warp, the instruction indicated by the program counter of the 2nd warp, and so on from the instruction cache 240.

[0045] Step S520 : the warp instruction scheduler 220 obtains the instruction of the 0th or next warp from the instruction cache 240 .

[0046] Step S530 : the warp instruction scheduler 220 sends the acquired instruction to the ALU 210 .

[0047] Step S540 : The ALU 210 performs the specified operation according to the input instruction. In the pipeline of executing the instruction, the ALU 210 obtains data from the source address of the general register 230 , performs the specified operation on the obtained data, and stores the result of the operation to the destination address in the general register 230 .

[0048] In order to prevent conflicts between different thread warps when accessing the general register 230, in some embodiments of step S510, the thread warp instruction scheduler 220 may allocate instructions to the thread warps in the program core (such as the example shown in Table 1) so that each thread warp is responsible for processing multiple instructions (also called relatively independent instructions) of a specified segment in the same program core. These instruction segments are independent of each other under arrangement and can be executed in parallel.

[0049] In other embodiments, the thread warp instruction scheduler 220 may adjust the source address and destination address in the instruction according to the content of each corresponding thread warp resource register 260 before the instruction is sent to the arithmetic logic unit 210 (before step S530) for mapping to the storage space dynamically allocated to this thread warp in the general register 230.

[0050] In some other embodiments, in addition to allowing each thread warp to process multiple instructions of a specified segment in the same program core according to relevant instructions in the program core (such as the example shown in Table 1) in step S510, the thread warp instruction scheduler 220 can also adjust the source address and destination address in the instruction according to the content of each corresponding thread warp resource register 260 before the instruction is sent to the arithmetic logic unit 210 (before step S530).

[0051] The present invention can be applied to cooperative warps that perform producer-consumer tasks. Figure 6 , assuming that warp 610 is a consumer of data and warp 650 is a producer of data. In other words, the execution of a portion of instructions in warp 610 requires reference to the execution results of a portion of instructions in warp 650. In some embodiments, software may configure the contents of each warp resource register corresponding to warps 610 and 650 during execution, so that the instructions of warps 610 and 650 can access an overlapping block of general registers 230 through the arithmetic logic unit 210.

[0052] For details about producer-consumer task execution, refer to Figure 7 An example flowchart is shown.

[0053] Step S710: The thread warp instruction scheduler 220 starts to extract instructions of each thread warp and stores them in the instruction cache 240. The thread warp instruction scheduler 220 can let each thread warp be responsible for processing multiple instructions of a specified segment in the same program core according to the relevant instructions in the program core (such as the example shown in Table 1), and these instruction segments form a producer-consumer relationship under the arrangement.

[0054] Step S720 : The warp instruction scheduler 220 obtains the barrier instruction 621 of the consumer warp 610 from the instruction cache 240 , and accordingly makes the consumer warp 610 enter a waiting state.

[0055] Step S730 : the warp instruction scheduler 220 obtains a series of instructions 661 of the producer warp 650 from the instruction cache 240 and sends the obtained instructions to the ALU 210 in sequence.

[0056] Step S740: the ALU 210 performs the specified operation according to the input instruction 661. In the pipeline of executing the instruction, the ALU 210 obtains data from the source address of the general register 230, performs the specified operation on the obtained data, and stores the result of the operation to the destination address in the general register 230.

[0057] Step S750: The warp instruction scheduler 220 obtains the barrier instruction 663 of the producer warp 650 from the instruction cache 240, and wakes up the consumer warp 610 accordingly. In some embodiments, the warp instruction scheduler 220 may also put the producer warp 650 into a waiting state.

[0058] Step S760 : The warp instruction scheduler 220 obtains a series of instructions 623 of the consumer warp 610 from the instruction cache 240 and sends the obtained instructions to the ALU 210 in sequence.

[0059] Step S770: The ALU 210 performs the specified operation according to the input instruction 623. In the pipeline of executing the instruction, the ALU 210 obtains data (including data previously generated by the producer warp 650) from the source address of the general register 230, performs the specified operation on the obtained data, and stores the result of the operation to the destination address in the general register 230.

[0060] What needs to be known here is that the contents of steps S730, S740, S760 and S770 are only brief descriptions for ease of understanding. During the execution of steps S730, S740, S760 and S770, the thread warp instruction scheduler 220 may also obtain instructions of other thread warps (that is, neither thread warp 610 nor any thread warp of thread warp 610) from the instruction cache 240 and drive the arithmetic logic unit 210 to perform operations.

[0061] Although Figure 1 , Figure 2 The above-described components are included, but it does not exclude the use of more additional components to achieve better technical effects without violating the spirit of the invention. Figure 5 , Figure 7 The flowchart is executed in a specified order, but without violating the spirit of the invention, a person skilled in the art can modify the order of these steps while achieving the same effect, so the present invention is not limited to using only the order described above. In addition, a person skilled in the art can also integrate several steps into one step, or execute more steps sequentially or in parallel in addition to these steps, and the present invention should not be limited thereto.

[0062] The above description is only a preferred embodiment of the present invention, but it is not intended to limit the scope of the present invention. Any person familiar with this technology can make further improvements and changes on this basis without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the claims of this application.

Claims

1. A device for configuring cooperative thread warps in a vector computing system, characterized in that: Include: General registers; an arithmetic logic unit, coupled to the general register; a thread warp instruction scheduler coupled to the arithmetic logic unit, wherein the thread warp instruction scheduler allows each of the plurality of thread warps to include a portion of relatively independent instructions in the program core according to the thread warp allocation instructions in the program core, allows each of the plurality of thread warps to access the designated local data in the general register through the arithmetic logic unit according to the configuration of the software during execution, and independently and in parallel executes the operation of each of the thread warps through the arithmetic logic unit; as well as a plurality of warp resource registers, wherein each of the warp resource registers is associated with one of the warps and stores a base address corresponding to the associated warp, Before sending an instruction associated with a thread bundle to the arithmetic logic unit, the thread bundle instruction scheduler modifies the source address and destination address in the instruction according to the contents of the corresponding thread bundle resource registers, so that the instruction can only access a specified part of the general register when executed by the arithmetic logic unit.

2. The apparatus for configuring cooperative warps in a vector computing system according to claim 1, wherein: The apparatus does not pre-configure a designated portion of the general register associated with each of the warps.

3. The apparatus for configuring cooperative warps in a vector computing system according to claim 1, wherein: The content of each warp resource register is set by software.

4. The apparatus for configuring cooperative warps in a vector computing system according to claim 1, wherein: The thread warp includes a first thread warp and a second thread warp, and when the thread warp instruction scheduler obtains a barrier instruction of the first thread warp from an instruction cache, the first thread warp is put into a waiting state, and when the thread warp instruction scheduler obtains a barrier instruction of the second thread warp from the instruction cache, the first thread warp is awakened, wherein the first thread warp and the second thread warp are configured to be associated with an overlapping block of the general register.

5. The apparatus for configuring cooperative warps in a vector computing system according to claim 4, characterized in that: The first warp is a consumer warp, and the second warp is a producer warp.

6. The apparatus for configuring cooperative warps in a vector computing system according to claim 1, wherein: The thread warps are independent of each other, and each of the thread warps is configured to be associated with a non-overlapping block of the general register.

7. The apparatus for configuring cooperative warps in a vector computing system according to claim 1, wherein: The thread warp instruction scheduler maintains an independent program counter for each of the thread warps.

8. A method for configuring cooperative thread warps in a vector computing system, executed in a streaming multiprocessor, characterized in that: Include: Allocating instructions according to the thread warps in the program core so that each of the plurality of thread warps contains a portion of relatively independent instructions in the program core; Allowing each of the plurality of thread warps to access designated local data in a general register through an arithmetic logic unit according to a configuration of the software during execution; as well as The arithmetic logic unit performs the operations of each of the above thread warps independently and in parallel, The method further comprises: providing a base address corresponding to each of the warps; as well as Before sending an instruction associated with one of the thread warps to the ALU, a source address and a destination address in the instruction are modified according to the corresponding base address so that the instruction can only access a specified portion of the general register when executed by the ALU.

9. The method for configuring cooperative warps in a vector computing system according to claim 8, characterized in that: The streaming multiprocessor does not pre-configure a designated portion of the general register associated with each of the warps.

10. The method for configuring cooperative warps in a vector computing system according to claim 8, characterized in that: The thread warps include a first thread warp and a second thread warp, the first thread warp and the second thread warp are configured to be associated with an overlapping block of the general register, and the method includes: When obtaining the barrier instruction of the first thread warp from the instruction cache, placing the first thread warp into a waiting state; and When the barrier instruction of the first warp is obtained from the instruction cache, the second warp is awakened.

11. The method for configuring cooperative warps in a vector computing system according to claim 10, characterized in that: The first warp is a consumer warp, and the second warp is a producer warp.

12. The method for configuring cooperative warps in a vector computing system according to claim 8, characterized in that: Include: An independent program counter is maintained for each of the warps.

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