Apparatus and method for using error correction code in memory system

Abstract

The present invention relates to an error correction code apparatus comprising a data input node configured to receive data to be encoded, and an encoder in communication with the data input node and configured to generate a first result by multiplying data bits by a first matrix, divide parity check bits into a first parity check group and a second parity check group based on a plurality of polynomials determined according to a second matrix, the first parity check group being obtained by multiplying the first result by the second matrix, the second parity check group being obtained by an exclusive OR operation on the first result and the first parity check group, multiply the first result by the second matrix to generate one or more first parity check bits in the first parity check group, perform an exclusive OR operation on the first result and the first parity check group to generate one or more second parity check bits in the second parity check group, and generate a codeword having the data bits and the parity check bits.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority and benefit to Korean Patent Application No. 10-2021-0024565, filed on February 24, 2021, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Embodiments of the disclosed technology relate to apparatus and methods for using error correction codes in memory systems. Background Technology

[0004] Recently, the computing environment paradigm has shifted towards ubiquitous computing, enabling computing to occur anytime, anywhere. The increased use of ubiquitous computing has led to a rise in the use of portable electronic devices (e.g., mobile phones, digital cameras, laptops, etc.). Such portable electronic devices can use or include memory systems having at least one memory device (as its data storage medium). The memory system can be a data storage device, which can be used as the primary or secondary storage device of the portable electronic device.

[0005] Because semiconductor memory devices have no mechanical moving parts (e.g., a robotic arm), these semiconductor-based data storage devices offer advantages over traditional hard disk drives, providing superior stability and durability, high data access speeds, and low power consumption. Examples of semiconductor-based data storage devices include, but are not limited to, Universal Serial Bus (USB) memory devices, memory cards with various interfaces, and solid-state drives (SSDs). Summary of the Invention

[0006] Embodiments of the disclosed technology relate to error correction code encoding and decoding schemes that can reduce the complexity of encoder and decoder design.

[0007] In some embodiments of the disclosed technology, an error correction code device includes: a data input node configured to receive data to be encoded; and an encoder communicating with the data input node and configured to (a) generate a first result by multiplying a first number of data bits by a first matrix, (b) generate a first parity check group including one or more first parity bits, the first parity check group being obtained by multiplying the first result by a second matrix, (c) generate a second parity check group including one or more second parity bits by performing an XOR operation on the first result and the first parity check group, (d) determine a plurality of parity bits for generating a codeword for LDPC encoding based on the first parity check group and the second parity check group, and (e) generate a codeword having a first number of data bits and the plurality of parity bits determined in operation (d).

[0008] In some embodiments of the disclosed technology, a memory system includes a memory device including a plurality of non-volatile memory cells, and a controller in communication with the memory device and configured to store or read codewords in or from the plurality of non-volatile memory cells, wherein the controller is configured to: (a) multiply one or more data bits by a first matrix to generate a first result, (b) generate a first parity group including one or more first parity bits by multiplying the first result by a second matrix, (c) generate a second parity group including one or more second parity bits by performing an exclusive OR operation on the first result and the first parity group based on one or more calculations including multiplication of the first result and the second matrix, (d) perform calculations for obtaining the first parity group and the second parity group, and (e) combine the one or more data bits with the first and second parity bits to generate the codeword.

[0009] In some embodiments of the disclosed technology, a method for operating a memory system includes checking one or more data bits and a program command provided by an external device, multiplying the one or more data bits by a first matrix to generate a first result, generating a first parity group including one or more first parity bits by multiplying the first result by a second matrix and generating a second parity group including one or more second parity bits by performing an exclusive OR operation on the first result and the first parity group based on one or more calculations including multiplication of the first result and the second matrix, performing calculations for obtaining the first parity group and the second parity group, and combining the one or more data bits with the first and second parity bits to generate a codeword to be written to the memory system.

[0010] In some embodiments of the disclosed technology, an error correction code device includes an encoder configured to generate M-bit parity corresponding to K-bit data to output a codeword having a size of N bits (N = K + M), wherein the encoder multiplies the K-bit data by a first matrix to generate a first result, divides the M-bit parity into a first parity group and a second parity group based on a plurality of polynomials generated by multiplying the first result by a second matrix, and performs calculations for obtaining the first parity group and the second parity group, the first parity group being obtained by multiplying the first result by the second matrix, the second parity group being obtained by an exclusive OR operation on the first result and the first parity group, and a decoder configured to detect and correct errors in the codeword generated by the encoder.

[0011] In some embodiments of the disclosed technology, a memory system includes: a memory device including a plurality of non-volatile memory cells; and a controller configured to store codewords in or read codewords from the plurality of non-volatile memory cells, wherein the controller is configured to: multiply data by a first matrix to generate a first result; divide parity checks into a first parity check group obtained by multiplying the first result by a second matrix and a second parity check group obtained by XORing the first result and the first parity check group; perform calculations to obtain the first parity check group and the second parity check group; and combine data and parity checks to generate codewords to be written to the memory device.

[0012] In some embodiments of the disclosed technology, a method for operating a memory system includes: examining data and programming commands input from an external device; multiplying the data by a first matrix to generate a first result; dividing parity checks into a first parity check group and a second parity check group based on a plurality of polynomials generated by multiplying the first result by a second matrix, the first parity check group being obtained by multiplying the first result by the second matrix, and the second parity check group being obtained by XORing the first result and the first parity check group; performing calculations to obtain the first parity check group and the second parity check group; and combining the data and parity checks to generate a codeword for programming the codeword in the memory device. Attached Figure Description

[0013] Figure 1 Examples of memory systems based on some embodiments of the disclosed technology are shown.

[0014] Figure 2 Examples of data processing systems based on some embodiments of the disclosed technology are shown.

[0015] Figure 3 Examples of memory systems based on some embodiments of the disclosed technology are shown.

[0016] Figure 4 It shows Figures 1 to 3 The example configuration of the controller is shown.

[0017] Figure 5 An example of an encoding device for generating low-density parity-check (LDPC) codes is shown.

[0018] Figure 6 It shows Figure 5 Examples of the first and second matrices used.

[0019] Figure 7 Examples of encoding devices and methods based on some embodiments of the disclosed technology are shown.

[0020] Figure 8 A flowchart of an encoding method based on some embodiments of the disclosed technology is shown.

[0021] Figure 9 The computation of low-density parity-check (LDPC) codes based on some embodiments of the disclosed technology is shown.

[0022] Figure 10 It shows how to obtain Figure 9 The matrix multiplication and logical operations performed by the LDPC codes described in the document.

[0023] Figure 11 The effects of an encoding device in a memory system based on some embodiments of the disclosed technology are shown. Detailed Implementation

[0024] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments that may be variations of any of the disclosed embodiments.

[0025] In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in terms such as “one embodiment,” “example embodiment,” “embodiment,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “optional embodiments,” etc., are intended to include any such feature in one or more embodiments of this disclosure, but they may or may not be combined in the same embodiment.

[0026] In this disclosure, the terms “comprising,” “including,” “containing,” and “comprising” are open-ended. As used in the appended claims, these terms specify the presence of the stated element and do not exclude the presence or addition of one or more other elements. The terms in the claims do not exclude the device from including additional components (e.g., interface units, circuitry, etc.).

[0027] In the present disclosure, various units, circuits, or other components can be described or claimed as "configured to" perform a task or tasks. In such contexts, "configured to" is used to connote structure by indicating that a block / circuit / component includes structure (e.g., circuitry) that performs the task or tasks during operation. As such, the task or tasks can be performed by the block / circuit / component, even if the specific block / circuit / component is not currently operational (e.g., is not on). Similarly, a block / circuit / component can be described or claimed as being "configured to" perform one or more tasks if, in a special situation or configuration, the block / circuit / component includes structure (e.g., circuitry) that performs the task or tasks during operation. The block / circuit / component can be specifically configured to perform the task or tasks in a particular situation or context. In another context, a block / circuit / component can be described or claimed as being "configured to" perform one or more tasks if, in a special situation or configuration, the block / circuit / component includes structure (e.g., circuitry) that performs the task or tasks during operation. The block / circuit / component may

[0028] As used in the present disclosure, the terms "circuit" or "logic" refer to all of the following: (a) hardware-only circuit implementations (such as implementations in only analog and / or digital circuitry) and (b) combinations of circuits and software (and / or firmware), such as (as applicable): (i) to a combination of processor(s) or (ii) to portions of processor(s) / software (including digital signal processors), software, and memory(ies) that work together to cause an apparatus, such as a mobile phone or server, to perform various functions) and (c) to circuits, such as a microprocessor or a portion of a microprocessor, that require software or firmware for operation, even if the software or firmware is not physically present. This definition of "circuit" or "logic" applies to all uses of this term in this application, including in any claims. As a further example, as used in this application, the terms "circuit" or "logic" also encompass an implementation of merely a processor (or multiple processors) or portion of a processor and its (or their) incidental software and / or firmware. For example, this term encompasses an integrated circuit that stores software and / or firmware that implement the integrated circuit's functionality, if applicable to the particular claim element.

[0029] As used herein, the terms "first," "second," "third," etc. are used as labels for nouns that they precede, and do not necessarily describe the order, frequency, or importance of those entities. The terms "first" and "second" are used merely as identifiers, and do not necessarily indicate that the corresponding elements must be written in the first or second order. Further, although these terms can be used herein to identify various elements, the elements are not limited by these terms. The terms are used to distinguish one element from another. For example, a first circuit can be distinguished from a second circuit.

[0030] Further, the term "based on" is used to describe one or more factors to which determination is based. It should be understood that determination can be based on additional factors not listed. That is, a determination can be based on those factors alone, or based on those factors at least in part. Consider the phrase "determine A based on B." While it is possible that B is a factor that affects the determination of A, this phrase does not exclude determinations of A based on C. In other instances, A can be determined based on B alone.

[0031] Herein, a term of data, data item, data entry, or entry of data can be an order of bits. For example, a data item can include content of a file, a portion of a file, a page in a memory, an object in an object-oriented program, a digital message, a digitally scanned image, a portion of a video or audio signal, metadata, or any other entity that can be represented by an order of bits. According to an embodiment, a data item can include a discrete object. According to another embodiment, a data item can include a unit of information within a transmission packet between two different components.

[0032] The disclosed technology can be implemented in some embodiments to provide a data processing system and a method for operating the data processing system. In some implementations, the data processing system includes components and resources configured to store data, and data paths to be used for data communication between the components and resources can be dynamically allocated based on usage of the components and resources.

[0033] In addition, the disclosed technology can be implemented in some embodiments to provide an apparatus and a method for improving performance of a memory system by reducing an amount of operations performed based on a low-density parity-check (LDPC) code, which is an error correction code used to detect and correct errors in data read out from a memory system or a nonvolatile memory unit.

[0034] In some embodiments of the disclosed technology, a memory system can generate parity bits to perform encoding based on an LDPC code by dividing the parity bits into two groups: (1) a first group obtained by multiplying a first matrix by a second matrix; and (2) a second group obtained by a simple logical operation (e.g., an exclusive-OR (XOR) operation). The memory system can change the order of computation to reduce the number of matrix multiplications, thereby reducing the amount of computation required to generate the parity bits.

[0035] The disclosed technology can also be implemented based on some embodiments to reduce the amount of operations required to perform encoding based on regular or irregular LDPC codes corresponding to a size of data in a read operation or a write operation performed within a memory system, thereby reducing the complexity of encoder and decoder designs and resource consumption in the memory system.

[0036] In some embodiments, an encoder can: generate a first result by multiplying a first number of data bits by a first matrix; divide a second number of parity bits into a first parity group and a second parity group based on a plurality of polynomials determined from a second matrix, the first parity group obtained by multiplying the first result by the second matrix, the second parity group obtained by an exclusive-OR operation of the first result and the first parity group; generate one or more first parity bits included in the first parity group, the first parity group obtained by multiplying the first result by the second matrix; generate one or more second parity bits in the second parity group, the second parity group obtained by the exclusive-OR operation of the first result and the first parity group; and generate a codeword having the first number of data bits and the second number of parity bits.

[0037] In an embodiment, an error correction code device can include: a data input node configured to receive data to be encoded; and an encoder in communication with the data input node and configured to: generate a first result by multiplying data bits by a first matrix; divide parity bits into a first parity group and a second parity group based on a plurality of polynomials determined from a second matrix, the first parity group obtained by multiplying the first result by the second matrix, the second parity group obtained by an exclusive-OR operation of the first result and the first parity group; multiply the first result by the second matrix to generate one or more first parity bits in the first parity group; perform the exclusive-OR operation of the first result and the first parity group to generate one or more second parity bits in the second parity group; and generate a codeword having the data bits and the parity bits.

[0038] The encoder can be configured to change an order of computation for generating the one or more first parity bits and the one or more second parity bits to reduce a number of the first parity bits included in the first parity group.

[0039] The encoder can be configured to use one or more first or second parity bits that have been calculated in the first or second parity group to perform a subsequent XOR operation for generating another second parity bit based on a calculation order.

[0040] The encoder can include a first calculator configured to multiply the data bits by a first matrix to output a first result, a first selector configured to divide the parity bits into a first parity group and a second parity group, a second calculator configured to multiply the first result by a second matrix to determine one or more first parity bits included in the first parity group, a second selector configured to selectively transfer an output of the second calculator for an XOR operation, a determination circuit configured to sequentially group the plurality of parity bits and feed back at least one parity bit for the XOR operation, and a third calculator configured to perform an XOR operation on the first result and the first and second parity bits output from the second selector and the determination circuit to obtain one or more second parity bits included in the second parity group.

[0041] The first matrix can include a plurality of rows representing a number of data bits and a plurality of columns representing a number of parity bits, and the second matrix includes a plurality of rows representing a number of parity bits and a plurality of columns representing a number of parity bits.

[0042] Each of the plurality of polynomials determined by multiplying the first result by the second matrix can include a mathematical relationship between the first result and at least a portion of the parity bits.

[0043] In another embodiment, a memory system can include a memory device including a plurality of non-volatile memory cells, and a controller in communication with the memory device and configured to store or read a codeword in or from the plurality of non-volatile memory cells. The controller is configured to multiply one or more data bits by a first matrix to generate a first result, divide parity bits into a first parity group and a second parity group based on a plurality of polynomials determined from a second matrix, the first parity group being obtained by multiplying the first result by the second matrix, the second parity group being obtained by an XOR operation on the first result and the first parity group, perform a calculation to obtain the first parity group and the second parity group, and combine the one or more data bits with the first parity bits and the second parity bits to generate the codeword.

[0044] A length of the codeword can be determined based on a length of one or more bits programmed or read in each programming or read operation.

[0045] The controller can be configured to change a computation order for generating one or more first parity bits in the first parity group and one or more second parity bits in the second parity group to reduce a number of first parity bits included in the first parity group.

[0046] The controller can be configured to use one or more first or second parity bits that have been computed in the first or second parity group to perform a subsequent XOR operation for generating another second parity bit based on the computation order.

[0047] The controller can include a first calculator configured to multiply one or more data bits by a first matrix to output a first result, a first selector configured to divide parity bits into a first parity group and a second parity group, a second calculator configured to multiply the first result by a second matrix to determine one or more first parity bits included in the first parity group, a second selector configured to selectively transfer an output of the second calculator for an XOR operation, a determination circuit configured to sequentially group first and second parity bits included in the first and second parity groups and feed back at least one parity bit for the XOR operation, and a third calculator configured to perform an XOR operation on the first result and the first and second parity bits output from the second selector and the determination circuit to obtain one or more second parity bits included in the second parity group.

[0048] The one or more data bits can include a first number of data bits, and the parity bits include a second number of parity bits, and wherein the first matrix includes a plurality of columns representing the number of parity bits and a plurality of rows representing the number of data bits, and the second matrix includes a plurality of rows representing the number of parity bits and a plurality of columns representing the number of parity bits.

[0049] Each of a plurality of polynomials determined by multiplication of the first result and the second matrix can include a mathematical relationship between the first result and at least some of the parity bits.

[0050] The controller can be configured to detect and correct errors in the codeword as the codeword is received from the memory device.

[0051] In another embodiment, a method for operating a memory system can include checking one or more data bits and a program command input from an external device; multiplying the one or more data bits by a first matrix to generate a first result; dividing parity bits into a first parity group and a second parity group based on a plurality of polynomials determined from a second matrix, the first parity group obtained by multiplying the first result by the second matrix, the second parity group obtained by an exclusive OR operation on the first result and the first parity group; performing a calculation to obtain the first parity group and the second parity group; and combining the one or more data bits with the first parity bits and the second parity bits to generate a codeword to be written to the memory system.

[0052] A length of the codeword can be determined based on a length of one or more bits programmed or read once in each program operation or read operation.

[0053] The method can further include changing a calculation order for generating one or more first parity bits in the first parity group and one or more second parity bits in the second parity group to reduce a number of the first parity bits included in the first parity group.

[0054] One or more first or second parity bits already calculated in the first parity group or the second parity group can be used to perform a subsequent exclusive OR operation according to a calculation order of the plurality of polynomials to generate another second parity bit.

[0055] The one or more data bits can include a first number of data bits, and the parity bits include a second number of parity bits. The first matrix can include a plurality of columns representing the number of parity bits and a plurality of rows representing the number of data bits, and the second matrix includes a plurality of rows representing the number of parity bits and a plurality of columns representing the number of parity bits.

[0056] The plurality of polynomials determined by the multiplication of the first result and the second matrix can include a mathematical relationship between the first result and at least some of the parity bits.

[0057] Figure 1 An example of a memory system 110 based on some embodiments of the disclosed technology is shown.

[0058] Reference is made to Figure 1The memory system 110 can include a memory device 150 and a controller 130. The memory device 150 and the controller 130 can be physically separated from each other in the memory system 110. The memory device 150 and the controller 130 can be connected via at least one data path. For example, the data path can include a channel and / or a lane. In some embodiments of the disclosed technology, the memory device 150 and the controller 130 can be divided by function. Further, in some embodiments of the disclosed technology, the memory device 150 and the controller 130 can be implemented with a single chip or multiple chips.

[0059] The memory device 150 can include a plurality of memory planes 162 or a plurality of memory dies 172. In some embodiments of the disclosed technology, a memory plane 162 can include a logical partition or a physical partition that includes at least one memory block 152, a drive circuit capable of controlling an array including a plurality of non-volatile memory cells, and a buffer that can temporarily store data to be input to or output from the non-volatile memory cells.

[0060] The memory device 150 can include a plurality of memory planes 162 or a plurality of memory dies 172. In some embodiments of the disclosed technology, a memory plane 162 can include a logical partition or a physical partition that includes at least one memory block 152, a drive circuit capable of controlling an array including a plurality of non-volatile memory cells, and a buffer that can temporarily store data to be input to or output from the non-volatile memory cells.

[0061] In addition, in some embodiments of the disclosed technology, a memory die 172 can include at least one memory plane 162. The memory die 172 can include a set of components implemented on a substrate. Each memory die 172 can be connected to the controller 130 through a data path. Each memory die 172 can include an interface that exchanges data and signals with the controller 130.

[0062] In some embodiments of the disclosed technology, the memory device 150 can include at least one memory block 152, at least one memory plane 162, or at least one memory die 172. Figure 1 The internal configuration of the memory device 150 shown can be modified to meet performance requirements of the memory system 110.

[0063] The controller 130 can perform a data input / output operation in response to a request from an external device. For example, when the controller 130 performs a read operation in response to a read request from an external device, data stored in a plurality of non-volatile memory cells included in the memory device 150 is transferred to the controller 130.

[0064] The controller 130 can use the memory 144 for data input / output operations. For example, the controller 130 can temporarily store data transferred from the memory device 150 in the memory 144 as shown. Figure 2 and Figure 3 The controller 130 can output the data stored in the memory 144 to an external device in response to a read request.

[0065] When a manufacturer reduces a physical size of the memory system 110 while increasing a data storage capacity within a limited memory bandwidth for data input / output operations, an error rate in data read out from the memory system 110 can increase. To improve performance of the memory system 110, data requested by an external device should be stored in the memory device 150 and read out to the external device without error. Errors in read out data can occur inside the memory device 150 or during data communication between the controller 130 and the memory device 150. To improve performance of the memory system 110, an error correction code is used to correct errors in read out data. In some embodiments, the controller 130 can encode data provided by an external device based on an error correction code and write (program) the encoded data in the memory device 150. During a read operation, the controller 130 can detect and correct errors in encoded data read from the memory device 150 by decoding the encoded data based on the error correction code.

[0066] In one example, errors can occur in the data read out from the memory device 150 as described below. Each of the plurality of non-volatile memory cells in the memory device 150 can include a minimum physical component for storing data. The non-volatile memory cells can be classified according to how many bits of data can be stored in a single memory cell: single-level cell (SLC), configured to store 1 bit of data per cell; multi-level cell (MLC), configured to store 2 bits of data per cell; triple-level cell (TLC), configured to store 3 bits of data per cell. In some embodiments, the non-volatile memory cells are located at each intersection of a bit line (BL), through which current flows to indicate the data stored in the memory cell. In other embodiments, the non-volatile memory cells are connected in series to the bit line (BL). A word line (WL) is also disposed across the memory cell array of non-volatile memory cells to select / activate a particular memory cell. In some embodiments, each of the non-volatile memory cells can include a floating gate FG to store an electrical charge corresponding to a bit of data. In one example, the floating gate FG can include a conductor material. In another example, the floating gate FG can include an insulator material such as an oxide film. When a high-level voltage (e.g., a positive high voltage) is applied from a control gate, electrons pass through an oxide layer disposed on the floating gate FG and into the floating gate FG. By allowing the electrons to pass through the oxide layer and remain in the floating gate FG, data can be written (programmed) to the non-volatile memory cell. Conversely, to erase the programmed data from the non-volatile memory cell, the trapped electrons in the floating gate FG are removed from the floating gate FG by applying a high voltage (e.g., a positive high-level voltage) to the semiconductor substrate. As the electrons move into and out of the non-volatile memory cell during the programming and erasing operations, the oxide layer can become damaged, resulting in readout data errors. As the number of bits of data that can be stored in the non-volatile memory cell increases (e.g., MLC, TLC, etc.), the data integrity of the non-volatile memory cell can decrease.

[0067] The controller 130 can include error correction and bad block control circuitry 182. The error correction and bad block control circuitry 182 can include error correction circuitry configured to encode data using error correction codes to detect and correct errors in data read out from the memory device 150 and bad block control circuitry to determine whether to discard or continue to use a non-volatile memory cell in which an error occurred. When a storage block is marked as a bad block, the controller 130 does not write data to the “bad” storage block.

[0068] Further, the controller 130 can include a randomizer 184. When data to be programmed in the memory device 150 has a regular pattern that includes repetition of a particular data, the reliability of reading out the data can be degraded due to interference, such as Back Pattern Dependency (BPD) or coupling between adjacent non-volatile memory cells. Back Pattern Dependency (BPD) can occur when the threshold voltage of a non-volatile memory cell programmed first increases due to an increase in resistance of the string, while an adjacent non-volatile memory cell is programmed during a random programming operation or a min-max programming operation. For example, BPD can change the threshold voltage of a particular non-volatile memory cell depending on the state pattern of adjacent non-volatile memory cells coupled to the particular non-volatile memory cell via the same word line or bit line when a programming or reading operation is performed in the memory device 150.

[0069] In addition, the coupling occurs when the threshold voltage of a particular non-volatile memory cell increases proportionally to the change in the threshold voltage of surrounding non-volatile memory cells adjacent to the particular memory cell. The randomizer 184 can be used to avoid distortion of voltage values corresponding to data that can occur due to interference or coupling between different memory cells. When the state (e.g., programmed, erased, etc.) of non-volatile memory cells in which data is stored in the memory device 150 is equalized by the randomizer 184, distortion of the threshold voltage of the non-volatile memory cells can be avoided based on a particular pattern of the data, thereby improving the reliability of the data. The randomizer 184 can not eliminate all bad patterns that can occur in the memory device 150. However, the randomizer 184 can remove typical bad patterns that can occur in the data. For example, if all memory cells in a particular page are programmed to 0 (logical low) and all memory cells in an immediately adjacent page are programmed to 1 (logical high), the data pattern can be characterized as a bad pattern. In some embodiments, the randomizer 184 can randomize the data to reduce the gap between good and bad patterns. Thus, the randomizer 184 can be used to randomize data to be written to the memory device 150.

[0070] In some embodiments of the disclosed technology, the controller 130 can include circuitry configured to perform additional operations to enhance the performance of the error correction and bad block control circuitry 182 and improve operational reliability. As manufacturing processes improve, the size of non-volatile memory cells can decrease. When the size of non-volatile memory cells is small, the number of electrons stored (or trapped) in the non-volatile memory cells decreases, such that the probability of error can increase. Increasing data density or information density can reduce the noise margin and make non-volatile memory cells susceptible to errors. As a countermeasure to this problem, when the number of data bits per non-volatile memory cell increases, a more powerful error correction code (ECC) function can be used. In addition, the controller 130 can include additional circuitry for detecting and correcting errors that can occur in data communication between the controller 130 and the memory device 150 when the memory system 110 performs data input / output operations at high speed.

[0071] In data communication between the controller 130 and the memory device 150, data can be transmitted and received according to a preset communication protocol. Data can be encapsulated in a data packet based on the corresponding protocol. For example, the controller 130 can support at least one protocol such as Fibre Channel (FC), Universal Serial Bus (USB) 3.0, Serial Attached SCSI (SAS), and Peripheral Component Interconnect Express (PCIe). The controller 130 can include link cyclic redundancy code (LCRC) circuitry 186 for detecting errors that can occur in data communication between the memory device 150 and the controller 130. Here, link cyclic redundancy code (LCRC) is a standard PCIe feature that protects the contents of Transaction Layer Packets (TLPs) across a single PCIe link.

[0072] In some embodiments, the controller 130 and the memory device 150 support Peripheral Component Interconnect Express (PCIe). PCIe can support split transactions in which requests and responses are separated in time domain to allow the link to deliver different traffic while the target device collects data included in the response. The PCIe-enabled controller 130 and memory device 150 can have a point-to-point connection and can be implemented in a double simplex method using two differential amplifiers in one direction. In addition, as the number of data transmission lines (or lanes) in a bidirectional direction increases, the bandwidth of data communication between the controller 130 and the memory device 150 can be configured to be scalable.

[0073] Data packets can be generated by the transaction layer and the data link layer. Depending on which layer is associated, the data packets can be referred to as transaction layer packets (TLPs) or data link layer packets (DLLPs). Additionally, physical layer packets (PLPs) can be generated for link control of the physical layer. Further, the data packets of each layer can be exchanged between the same layer of each part of the link connection. For example, a lower protocol layer adds information before and after the data packet, and the data packet can be transmitted through a data transmission line. After the information added by each protocol layer is removed, the data packet received by the memory device 150 can be transmitted to an upper protocol layer. Specifically, a transaction layer packet (TLP) for end-to-end communication can include a TLP header generated in the transaction layer, a data payload, and an end-to-end CRC (ECRC) (or cyclic redundancy check). When transmitted in the data link layer, a sequence number and a link cyclic redundancy check (LCRC) can be added to a data link layer packet (DLLP). When received by the memory device 150, the sequence number and the link cyclic redundancy check (LCRC) can be removed after being checked. The data link layer packet DLLP can be used to exchange information such as an acknowledgement response (ACK) and a negative acknowledgement response (NAK) of the transaction layer packet (TLP) between both sides of the link.

[0074] The complexity of the error correction and bad block control circuit 182 can increase as its error correction capability or performance increases. As the error rate of the non-volatile memory cells increases, the ECC portion (e.g., parity bits) of the data (e.g., payload data) can increase in order to detect and correct more erroneous data bits. Additionally, the time and resources required to complete the ECC operation can increase. In a page of the memory device 150, there is a spare area in addition to a data area for storing data, and the spare area can be used to store the ECC portion (e.g., parity bits) generated by the ECC operation. In some embodiments, the memory system 110 can use binary Bose-Chaudhuri-Hocquenghem (BCH) codes, non-binary BCH codes, or other codes. Further, when the error rate of the non-volatile memory cells increases, a low-density parity-check (LDPC) code with strong error detection and correction capability can also be used.

[0075] In some embodiments of the disclosed technology, the controller 130 can include an error correction circuit 188 using a low-density parity-check (LDPC) code. The error correction circuit 188 can include an encoder and / or a decoder to perform an error correction operation based on a low-density parity-check (LDPC) code. LDPC codes can be generally classified into random LDPC codes, block-based structured LDPC codes, and semi-random LDPC codes. Unlike random LDPC codes, structured LDPC codes can be generated by an algebraic or geometric method. Block-based structured LDPC codes can include a parity-check matrix (H matrix) whose sub-matrices or zero matrices have column weights and row weights of 1. For example, structured LDPC codes can be classified into regular LDPC codes and irregular LDPC codes according to the weights of columns and rows.

[0076] Since the parity-check matrix (H matrix) of a random LDPC code is randomly generated, the transmission / reception circuit of the controller 130 and the memory device 150 in the memory system 110 stores all parity-check matrices (H matrices) in order to satisfy different frame sizes and code rates. On the other hand, in a structured LDPC code, the parity-check matrix (H matrix) can be generated based on a preset rule, so that the transmission / reception circuit of the controller 130 and the memory device 150 does not have to store all parity-check matrices (H matrices). Further, the parity-check matrix (H matrix) can be easily created based on frame sizes and code rates. However, due to the limitation of generating the parity-check matrix (H matrix) of a structured LDPC code, it can be difficult to generate the parity-check matrix (H matrix) satisfying all frame sizes and code rates. A semi-random LDPC code can randomly generate a part of the parity-check matrix (H matrix), and another part can be generated based on a preset rule, so that a large storage space can not be required because the transmission / reception circuit of the controller 130 and the memory device 150 does not have to store the entire parity-check matrix (H matrix). An example encoding operation using a low-density parity-check (LDPC) code will be described below with reference to FIG. 2. Figures 5 to 10 An example encoding operation using a low-density parity-check (LDPC) code will be described below with reference to FIG. 2.

[0077] In embodiments of the disclosed technology, a device and method can be provided to reduce the amount of computation associated with error correction circuitry 188 that uses a low-density parity-check (LDPC) code. A parity-check matrix (H matrix) can include a plurality of matrices. The error correction circuitry 188 can multiply input data by a first matrix to generate a first result obtained by multiplying the data by the first matrix, and divide the parity-check into a first parity-check group obtained by multiplying the first result by a second matrix and a second parity-check group obtained by an exclusive-OR operation of the first result and the first parity-check group based on a plurality of polynomials generated by multiplying the first result by the second matrix. The error correction circuitry 188 can perform matrix multiplication to obtain the first parity-check group, but perform a logical operation (e.g., an exclusive-OR operation) to obtain the second parity-check group. After performing the calculations to obtain the first and second parity-check groups, the error correction circuitry 188 can combine the parity-check including the first and second parity-check groups with the data to generate a codeword. The error correction circuitry 188 can transmit the codeword to the memory device 150.

[0078] In some embodiments of the disclosed technology, data input to the error correction circuitry 188 can include data transmitted from an external device, and can also include data or data packets processed by the randomizer 184 and the link cyclic redundancy code (LCRC) circuitry 186. In some implementations, the error correction circuitry 188 using a low-density parity-check (LDPC) code can calculate K-bit input data based on a parity-check matrix (H matrix) to generate M-bit parity-checks, and then add the K-bit data and the M-bit parity-checks to output an N-bit codeword (N = K + M).

[0079] Hereinafter, reference will be made to Figures 3 to 4 The flash translation layer (FTL) 240 in the controller 130 will be described in more detail.

[0080] Figure 2 and Figure 3 An example configuration that can be used to implement the disclosed technology by the memory system 110 based on some embodiments of the disclosed technology is shown.

[0081] Referring to Figure 2 The data processing system 100 can include a host 102 coupled with a memory system, such as the memory system 110. For example, the host 102 and the memory system 110 can be coupled with each other to perform data communication via a data bus, a host cable, or other means.

[0082] The memory system 110 can include a memory device 150 and a controller 130. The memory device 150 and the controller 130 in the memory system 110 can include components or elements that are physically separate from each other. The memory device 150 and the controller 130 can be connected via at least one data path. For example, the data path can include a channel and / or a lane.

[0083] In some embodiments of the disclosed technology, the memory device 150 and the controller 130 can be components or elements that are divided by function. Further, in some embodiments of the disclosed technology, the memory device 150 and the controller 130 can be implemented with a single chip or multiple chips. The controller 130 can perform data input / output operations in response to requests from an external device. For example, when the controller 130 performs a read operation in response to a read request from an external device, data stored in a plurality of non-volatile memory cells included in the memory device 150 is transferred to the controller 130.

[0084] As shown in FIG. 1, the memory device 150 can include a plurality of memory planes 160, 162, 164, 166, 168, 170. The memory planes 160, 162, 164, 166, 168, 170 can include a plurality of memory dies 172, 174, 176, 178, 180, 182. The memory planes 160, 162, 164, 166, 168, 170 can include a plurality of memory blocks 152, 154, 156. The memory blocks 152, 154, 156 can include a group of non-volatile memory cells that have data removed together by a single erase operation. Although not shown, the memory blocks 152, 154, 156 can include a plurality of pages that have data stored together during a single program operation or output together during a single read operation. For example, one memory block can include a plurality of pages. Figure 2

[0085] For example, the memory device 150 can include a plurality of memory planes or a plurality of memory dies. In some embodiments of the disclosed technology, a memory plane can include a logical partition or a physical partition that includes at least one memory block, a drive circuit to control an array including a plurality of non-volatile memory cells, and a buffer that can temporarily store data input to or output from the non-volatile memory cells.

[0086] Additionally, in some embodiments of the disclosed technology, a memory die can include at least one memory plane. A memory die can include a group of components implemented on a physically distinguishable substrate. Each memory die can be connected to the controller 130 through a data path (e.g., a channel). Each memory die can include an interface to exchange data and other signals with the controller 130.

[0087] ​In some embodiments of the disclosed technology, the memory device 150 can include at least one memory bank 152, 154, 156, at least one memory plane, or at least one memory die. For example, each plane can include a plurality of memory banks, and each plane can be coupled to a channel via each of the accesses. Depending on the performance of the memory system 110, Figure 1 The internal configuration of the memory device 150 shown in FIG. 1 can vary.

[0088] Referring to Figure 2 The memory device 150 can include a voltage supply circuit 170 for supplying at least some voltages to the memory banks 152, 154, 156. The voltage supply circuit can supply a read voltage Vrd, a program voltage Vprog, a pass voltage Vpass, or an erase voltage Vers to the non-volatile memory cells included in the memory banks. For example, during a read operation for reading data stored in the non-volatile memory cells included in the memory banks 152, 154, 156, the voltage supply circuit can apply the read voltage Vrd to the selected non-volatile memory cells. During a program operation for storing data in the non-volatile memory cells included in the memory banks 152, 154, 156, the voltage supply circuit can apply the program voltage Vprog to the selected non-volatile memory cells. Also, during the read operation or the program operation performed on the selected non-volatile memory cells, the voltage supply circuit can apply the pass voltage Vpass to the unselected non-volatile memory cells. During an erase operation for erasing data stored in the non-volatile memory cells included in the memory banks 152, 154, 156, the voltage supply circuit can apply the erase voltage Vers to the memory banks.

[0089] According to the operation, the memory device 150 can store information about various voltages applied to the memory banks 152, 154, 156. For example, when the non-volatile memory cells in the memory banks 152, 154, 156 can store multi-bit data, a plurality of levels of the read voltage Vrd for identifying or reading the multi-bit data can be required. The memory device 150 can include a mapping table including different voltage levels as the read voltage Vrd. For example, the table can include voltage values corresponding to the read voltage Vrd to be applied to read out a specific data bit of the multi-bit data, and such voltage values can be stored in a register. The number of voltage values for the read voltage Vrd of the read operation can be limited within a preset range. Also, the voltage values can be quantized.

[0090] The host 102 can include a portable electronic device (e.g., a mobile phone, an MP3 player, a laptop computer, etc.) or a non-portable electronic device (e.g., a desktop computer, a game console, a television, a projector, etc.).

[0091] The host 102 can further include at least one operating system (OS) to control functions and operations performed in the host 102. The OS can provide interoperability between the host 102 and a user intending to store data in the memory system 110 operatively engaged with the memory system 110. The OS can support functions and operations corresponding to a request of the user. As an example and not by way of limitation, the OS can be classified as a general-purpose operating system and a mobile operating system according to mobility of the host 102. The general-purpose operating system can be classified as a personal operating system and an enterprise operating system according to system requirements or user environments. The enterprise operating system can be specialized to secure and support high-performance computing compared to the personal operating system.

[0092] The mobile operating system can be used to support services or functions for mobility (e.g., power saving functions). The host 102 can include a plurality of operating systems. The host 102 can run a plurality of operating systems interlocked with the memory system 110 corresponding to a request of the user. The host 102 can transmit a plurality of commands corresponding to a request of the user to the memory system 110, thereby performing operations corresponding to the plurality of commands within the memory system 110.

[0093] The controller 130 in the memory system 110 can control the memory device 150 in response to a request or a command input from the host 102. For example, the controller 130 can perform a read operation to provide data read from the memory device 150 to the host 102, and can perform a write operation (or a program operation) to store data input from the host 102 in the memory device 150. To perform data input / output (I / O) operations, the controller 130 can control and manage internal operations of reading data, programming data, erasing data, and the like.

[0094] In some embodiments of the disclosed technology, the controller 130 can include a host interface 132, a processor 134, an error correction circuit 138, a power management unit (PMU) 140, a memory interface 142, and a memory 144. As shown in FIG. 1, the controller 130 can include a plurality of components. The plurality of components included in the controller 130 can be different according to the structure, functions, operational performance, and the like of the memory system 110. Figure 2 The components included in the controller 130 as shown in FIG. 1 can be different according to the structure, functions, operational performance, and the like of the memory system 110.

[0095] For example, depending on the protocol of the host interface, the memory system 110 can be implemented with any of various types of storage devices electrically coupled with the host 102. Examples of suitable storage devices include solid state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), reduced size MMCs (RS-MMCs), micro-type MMCs, secure digital (SD) cards, mini-SDs, micro-SDs, universal serial bus (USB) storage devices, universal flash storage (UFS) devices, compact flash (CF) cards, smart media (SM) cards, memory sticks, and the like. Depending on the implementation of the memory system 110, components can be added to or omitted from the controller 130.

[0096] The host 102 and the memory system 110 can each include a controller or interface for transmitting and receiving signals, data, and the like according to one or more predetermined protocols. For example, the host interface 132 in the memory system 110 can include a device capable of transmitting and receiving signals, data, and the like to and from the host 102.

[0097] The host interface 132 included in the controller 130 can receive signals, commands (or requests), and / or data input from the host 102. For example, the host 102 and the memory system 110 can use a predetermined protocol to transmit and receive data between them. Examples of protocols or interfaces supported by the host 102 and the memory system 110 for transmitting and receiving data include universal serial bus (USB), multimedia card (MMC), parallel advanced technology attachment (PATA), small computer system interface (SCSI), enhanced small disk interface (ESDI), electronic integrated drive (IDE), peripheral component interconnect express (PCIE), serial SCSI (SAS), serial advanced technology attachment (SATA), mobile industry processor interface (MIPI), and the like. In some embodiments of the disclosed technology, the host interface 132 is a layer for exchanging data with the host 102, and is implemented or driven by firmware referred to as a host interface layer (HIL).

[0098] An electronic integrated drive (IDE) or an advanced technology attachment (ATA) can be used as one of the interfaces for transmitting and receiving data, for example, a cable including 40 parallel connections of wires can be used to support data transmission and reception between the host 102 and the memory system 110. When a plurality of memory systems 110 are connected to a single host 102, the plurality of memory systems 110 can be divided into a master and a slave by using a location or a dip switch to which the plurality of memory systems 110 are connected. The memory system 110 set as the master can be used as a master memory device. The IDE (ATA) can include, for example, Fast-ATA, ATAPI, or enhanced IDE (EIDE).

[0099] A serial advanced technology attachment (SATA) interface is a serial data communication interface compatible with various ATA standards used in an electronic integrated drive (IDE) device. The 40 wires in the IDE interface can be reduced to six wires in the SATA interface. For example, 40 parallel signals for the IDE can be converted into 6 serial signals for the SATA interface. The SATA interface has been widely used because of its faster data transmission and reception rate and less resource consumption for data transmission and reception in the host 102. The SATA interface can connect up to 30 external devices to a single transceiver included in the host 102. In addition, the SATA interface can support hot plugging, which allows an external device to be attached to or detached from the host 102 even when data communication is being performed between the host 102 and another device. Accordingly, the memory system 110 can be connected or disconnected as an additional device as a device supported by a universal serial bus (USB) even when the host 102 is powered on. For example, in a host 102 having an eSATA port, the memory system 110 can be freely attached to or detached from the host 102 as an external hard disk.

[0100] A small computer system interface (SCSI) is a serial data communication interface for connecting a computer or a server with other peripheral devices. The SCSI can provide a higher transmission speed compared to other interfaces such as IDE and SATA. In the SCSI, the host 102 and at least one peripheral device (for example, the memory system 110) are connected in series, but data transmission and reception between the host 102 and each peripheral device can be performed through parallel data communication. In the SCSI, it is easy to connect or disconnect a device such as the memory system 110 to or from the host 102. The SCSI can support 15 other devices to be connected to a single transceiver included in the host 102.

[0101] Serial Attached SCSI (SAS) can include a serial data communication version of SCSI. In SAS, the host 102 is connected in series with multiple peripheral devices, and data transmission and reception between the host 102 and each peripheral device can be performed in a serial data communication scheme. SAS can support connection between the host 102 and the peripheral devices through a serial cable rather than a parallel cable to easily manage equipment using SAS and enhance or improve operational reliability and communication performance. SAS can support eight external devices connected to a single transceiver included in the host 102.

[0102] Non-Volatile Memory Express (NVMe) is an interface based at least on Peripheral Component Interconnect Express (PCIe) designed to improve performance and design flexibility of a host 102, server, computing device, etc. equipped with a memory system 110. PCIe can use a slot or a specific cable to connect a computing device (e.g., host 102) and a peripheral device (e.g., memory system 110). For example, PCIe can use a plurality of pins (e.g., 18 pins, 32 pins, 49 pins, or 82 pins) and at least one wire (e.g., xl, x4, x8, or x16) to achieve high-speed data communication of more than hundreds of MB per second (e.g., 250 MB / s, 500 MB / s, 984.6250 MB / s, or 1969 MB / s, etc.). In some embodiments of the disclosed technology, a PCIe scheme can achieve a bandwidth of tens to hundreds of megabits per second. NVMe can support an operating speed of a non-volatile memory system 110 (such as an SSD) faster than a hard disk.

[0103] In some embodiments of the disclosed technology, the host 102 and the memory system 110 can be connected through a Universal Serial Bus (USB). Universal Serial Bus (USB) is an extensible, hot-pluggable, plug-and-play serial interface that can provide a cost-effective standard connection between the host 102 and peripheral devices such as a keyboard, a mouse, a joystick, a printer, a scanner, a storage device, a modem, a video camera, etc. A plurality of peripheral devices such as the memory system 110 can be coupled to a single transceiver included in the host 102.

[0104] Referring to Figure 2The error correction circuit 138 can correct error bits of data read from the memory device 150 and can include an error correction code (ECC) encoder and an ECC decoder. The ECC encoder can perform error correction encoding on data to be programmed into the memory device 150 to generate encoded data by adding one or more parity bits to the data and store the encoded data in the memory device 150. When the controller 130 reads data stored in the memory device 150, the ECC decoder can detect and correct error bits contained in the data read from the memory device 150. For example, after performing error correction decoding on data read from the memory device 150, the error correction circuit 138 determines whether the error correction decoding has been successful and outputs an instruction signal (e.g., a correction success signal or a correction failure signal) based on the result of the error correction decoding. The error correction circuit 138 can correct error bits of read data using one or more parity bits generated during the ECC encoding process for data stored in the memory device 150. When the number of error bits exceeds a maximum number of correctable error bits, the error correction circuit 138 can not correct the error bits but can output a correction failure signal indicating a failure to correct the error bits.

[0105] In some embodiments of the disclosed technology, the error correction circuit 138 can perform error correction operations based on encoding modulation such as a low-density parity-check (LDPC) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a turbo code, a Reed-Solomon (RS) code, a convolutional code, a recursive systematic code (RSC), a trellis coded modulation (TCM), a block coded modulation (BCM), etc. The error correction circuit 138 can include all circuits, modules, systems, and / or devices that perform error correction operations based on at least one of the above-mentioned codes. Figure 2 The error correction circuit 138 shown in FIG. 1A can include at least some components included in the controller 130 shown in FIG. 1A. Figure 1 The error correction circuit 138 shown in FIG. 1A can include at least some components included in the controller 130 shown in FIG. 1A.

[0106] For example, the ECC decoder can perform hard decision decoding or soft decision decoding on data transmitted from the memory device 150. Hard decision decoding can include one of two methods widely classified for correcting errors. Hard decision decoding can include an operation of correcting error bits by reading digital data of “0” or “1” from a non-volatile memory cell in the memory device 150. Because hard decision decoding deals with binary logic signals, the circuit / algorithm of the ECC encoder / decoder can have a simpler design or configuration, and the processing speed can be faster than soft decision decoding.

[0107] Soft decision decoding can quantize threshold voltages of non-volatile memory cells in memory device 150 into two or more quantized values (e.g., multi-bit data, approximations, analog values, etc.) in order to correct error bits based on the two or more quantized values. Controller 130 can receive two or more alphabets or quantized values from a plurality of non-volatile memory cells in memory device 150 and then perform decoding based on information generated by characterizing the quantized values as a combination of information such as conditional probabilities or likelihood ratios.

[0108] In some embodiments of the disclosed technology, the ECC decoder can use a low-density parity-check and generator matrix (LDPC-GM) code, which can be designed to perform soft decision decoding. A low-density parity-check (LDPC) code uses an algorithm that can read data values of several bits from memory device 150 according to reliability, rather than simple data of 1 or 0 as in hard decision decoding, and iterates repeatedly through message passing to improve the reliability of the values. The values are then ultimately determined as data of 1 or 0. For example, a decoding algorithm using an LDPC code can include probabilistic decoding. In hard decision decoding, values output from non-volatile memory cells are encoded as 0 or 1. In contrast to hard decision decoding, soft decision decoding can determine values stored in non-volatile memory cells based on stochastic information. With respect to bit-flipping, which can include errors that can occur in memory device 150, soft decision decoding can provide an improved probability of correcting errors and recovering data, and provide reliability and stability in correcting data. An LDPC-GM code can have a scheme in which an inner LDGM code can be concatenated with a high-speed LDPC code.

[0109] In some embodiments of the disclosed technology, the ECC decoder can use soft decision decoding using, for example, a low-density parity-check convolutional code (LDPC-CC). An LDPC-CC can have a scheme that uses linear-time encoding and pipelined decoding based on variable block length and shift registers.

[0110] In some embodiments of the disclosed technology, the ECC decoder can use soft decision decoding using, for example, a log-likelihood ratio turbo code (LLR-TC). A log-likelihood ratio (LLR) can be calculated as a non-linear function of the distance between a sampled value and an ideal value. In addition, a turbo code (TC) can include a simple code in two or three dimensions (e.g., a Hamming code), and decoding is repeated in a row direction and a column direction to improve the reliability of the values.

[0111] A power management unit (PMU) 140 can control power provided to the controller 130. The PMU 140 can monitor power supplied to the memory system 110 (e.g., a voltage supplied to the controller 130) and provide power to components included in the controller 130. The PMU 140 can not only detect power on or power off, but can generate a trigger signal to enable the memory system 110 to urgently back up a current state when power supplied to the memory system 110 is unstable. In some embodiments of the disclosed technology, the PMU 140 can include a device or component capable of accumulating power that can be used in an emergency.

[0112] The memory interface 142 can serve as an interface for handling commands and data transmitted between the controller 130 and the memory device 150 in order to allow the controller 130 to control the memory device 150 in response to a command or request from the host 102. The memory interface 142 can generate a control signal for the memory device 150, and in the case of the memory device 150 being a flash memory, can process data input to or output from the memory device 150 under the control of the processor 134.

[0113] For example, when the memory device 150 includes a NAND flash memory, the memory interface 142 includes a NAND flash controller (NFC). The memory interface 142 can provide an interface for handling commands and data between the controller 130 and the memory device 150. According to an embodiment, the memory interface 142 can be implemented or driven by firmware called a flash interface layer (FIL) to exchange data with the memory device 150.

[0114] In some embodiments of the disclosed technology, the memory interface 142 can support an open NAND flash interface (ONFi), a toggle mode, etc., for data input / output between the controller 130 and the memory device 150. For example, the ONFi can use a data path (e.g., a channel, a lane, etc.) including at least one signal line supporting bidirectional transmission and reception in units of 8-bit data or 16-bit data. Data communication between the controller 130 and the memory device 150 can be implemented through at least one interface with respect to an asynchronous single data rate (SDR), a synchronous double data rate (DDR), a toggle double data rate (DDR), etc.

[0115] The memory 144 can be used as a working memory of the memory system 110 or the controller 130 while temporarily storing transaction data of operations performed in the memory system 110 and the controller 130. For example, the memory 144 can temporarily store read data output from the memory device 150 in response to a read request from the host 102 before the read data is output to the host 102. Also, the controller 130 can temporarily store write data input from the host 102 in the memory 144 before the write data is programmed into the memory device 150. When the controller 130 controls operations of the memory device 150 such as data read operations, data write or program operations, data erase operations, data transmitted between the controller 130 of the memory system 110 and the memory device 150 can be temporarily stored in the memory 144.

[0116] In addition to read data or write data, the memory 144 can store information (e.g., mapping data, read requests, program requests, etc.) for inputting or outputting data between the host 102 and the memory device 150. In some embodiments of the disclosed technology, the memory 144 can include one or more command queues, program memories, data memories, write buffers / caches, read buffers / caches, data buffers / caches, mapping buffers / caches, etc. The controller 130 can allocate some storage spaces in the memory 144 for components established to perform data input / output operations. For example, a write buffer established in the memory 144 can be used to temporarily store target data for a program operation.

[0117] In embodiments, the memory 144 can be implemented with volatile memory. For example, the memory 144 can be implemented with static random access memory (SRAM), dynamic random access memory (DRAM), or both. Although Figure 2 Although the memory 144 is shown to be disposed inside the controller 130, the memory 144 can be disposed outside the controller 130. For example, the memory 144 can be implemented by an external volatile memory having a memory interface that transfers data and / or signals between the memory 144 and the controller 130.

[0118] The processor 134 can control overall operations of the memory system 110. For example, the processor 134 can control a program operation or a read operation of the memory device 150 in response to a write request or a read request input from the host 102. In some embodiments of the disclosed technology, the processor 134 can run firmware to control a program operation or a read operation in the memory system 110. Herein, the firmware can be referred to as a flash translation layer (FTL). Reference will be made to FIG. 2 to describe the firmware. Figure 3 and Figure 4Detailed description of an example of FTL. In some embodiments of the disclosed technology, the processor 134 can be implemented with a microprocessor, a central processing unit (CPU), or the like.

[0119] In some embodiments of the disclosed technology, the memory system 110 can be implemented with at least one multi-core processor. A multi-core processor is a circuit or chip in which two or more cores, which are considered as different processing regions, are integrated. For example, when the multiple cores in the multi-core processor independently drive or run multiple flash translation layers (FTLs), the data input / output speed (or performance) of the memory system 110 can be improved. Based on some embodiments of the disclosed technology, data input / output (I / O) operations in the memory system 110 can be independently performed by different cores in the multi-core processor.

[0120] The processor 134 in the controller 130 can perform operations corresponding to requests or commands input from the host 102. Further, the memory system 110 can perform operations independent of the commands or requests from the host 102. In one case, the operations performed by the controller 130 in response to the requests or commands input from the host 102 can include foreground operations, and the operations performed by the controller 130 independent of the requests or commands input from the host 102 can include background operations. The controller 130 can perform foreground operations or background operations for reading, writing, or erasing data in the memory device 150. In addition, parameter setting operations corresponding to setting parameter commands or setting feature commands transmitted from the host 102 as setting commands can include foreground operations. As background operations performed without commands transmitted from the host 102, the controller 130 can perform garbage collection (GC), wear leveling (WL), bad block management for identifying and processing bad blocks, and the like.

[0121] In some embodiments, substantially similar operations can be performed as both foreground operations and background operations. For example, when the memory system 110 performs garbage collection in response to a request or a command input from the host 102 (e.g., manual GC), the garbage collection can include a foreground operation. When the memory system 110 performs garbage collection independent of the host 102 (e.g., automatic GC), the garbage collection can include a background operation.

[0122] When the memory device 150 includes multiple semiconductor chip dies, each including multiple non-volatile memory cells, the controller 130 can perform parallel processing of multiple requests or commands input from the host 102 in order to improve the performance of the memory system 110. For example, the transmitted requests or commands can be divided into multiple groups that include at least some of the multiple planes, multiple dies, or multiple chips included in the memory device 150, and the multiple groups of requests or commands are processed individually or in parallel in each plane, each die, or each chip.

[0123] The memory interface 142 in the controller 130 can connect to multiple dies or chips in the memory device 150 through at least one channel and at least one lane. When the controller 130 distributes and stores data in multiple dies through each channel or each lane in response to a request or command associated with multiple pages including non-volatile memory cells, multiple operations corresponding to the request or command can be performed simultaneously or in parallel with respect to the multiple dies or planes. Such a processing method or scheme can include an interleaving method. Because the data input / output speed of the memory system 110 is improved by operating in the interleaving method, the data I / O performance of the memory system 110 can be improved.

[0124] By way of example and not limitation, the controller 130 can identify the status of multiple channels (or lanes) associated with multiple dies included in the memory device 150. The controller 130 can determine the status of each channel or each lane as one of a busy state, a ready state, an active state, an idle state, a normal state, and an abnormal state. The controller determines through which channel or lane to deliver the instruction (and / or data) can be associated with a physical block address. The controller 130 can include a descriptor delivered from the memory device 150. The descriptor can include a block parameter or a page parameter describing information about the memory device 150. The descriptor can have a predetermined format or structure. For example, the descriptor can include a device descriptor, a configuration descriptor, a cell descriptor, etc. The controller 130 can use the descriptor to determine which channel(s) to exchange the instruction or data using.

[0125] Referring to Figure 2 The memory device 150 in the memory system 110 can include multiple memory blocks 152, 154, 156. Each of the multiple memory blocks 152, 154, 156 includes multiple non-volatile memory cells. Based on some embodiments of the disclosed technology, the memory blocks 152, 154, 156 can be a group of non-volatile memory cells that are erased together. The memory blocks 152, 154, 156 can include multiple pages, each of which includes a group of non-volatile memory cells that are read or programmed together.

[0126] In one embodiment, each memory block 152, 154, or 156 can have a three- dimensional stacked structure. Further, memory device 150 can include multiple dies, each die including multiple planes, each plane including multiple memory blocks 152, 154, 156. The configuration of memory device 150 can vary depending on the performance required of memory system 110.

[0127] Figure 2 Memory device 150 is shown to include multiple memory blocks 152, 154, and 156. Depending on the number of bits that can be stored in one memory cell, multiple memory blocks 152, 154, 156 can be any of a single-level cell (SLC) memory block, a multi-level cell (MLC) memory block, and the like. An SLC memory block includes multiple pages implemented by memory cells that store one bit of data per memory cell. An SLC memory block can have higher data I / O operation performance and higher endurance than an MLC memory block. An MLC memory block includes multiple pages implemented by memory cells that store multiple bits of data (e.g., two or more bits of data) per memory cell. An MLC memory block can have greater storage capacity than an SLC memory block for the same space. From a storage capacity perspective, an MLC memory block can be highly integrated.

[0128] In an embodiment, memory device 150 can be implemented with MLC memory blocks such as double-level cell (DLC) memory blocks, triple-level cell (TLC) memory blocks, quad-level cell (QLC) memory blocks, and combinations thereof. A DLC memory block can include multiple pages implemented by memory cells that are capable of storing 2 bits of data per memory cell. A TLC memory block can include multiple pages implemented by memory cells that are capable of storing 3 bits of data per memory cell. A QLC memory block can include multiple pages implemented by memory cells that are capable of storing 4 bits of data per memory cell. In another embodiment, memory device 150 can be implemented with blocks including multiple pages implemented by memory cells that are capable of storing 5 bits or more of data per memory cell.

[0129] In some embodiments of the disclosed technology, the controller 130 can use a MLC storage block included in the memory device 150 as an SLC storage block that stores one bit of data per memory cell. The data input / output speed of a multi-level cell (MLC) storage block can be slower than that of an SLC storage block. That is, when a MLC storage block is used as an SLC storage block, the margin of a read operation or a program operation can be reduced. For example, when a MLC storage block is used as an SLC storage block, the controller 130 can perform a data input / output operation at a higher speed. Accordingly, the controller 130 can use a MLC storage block as an SLC buffer to temporarily store data, as the buffer can require a higher data input / output speed.

[0130] Further, in some embodiments of the disclosed technology, the controller 130 can program data into a MLC multiple times without performing an erase operation on a particular MLC storage block included in the memory device 150. Generally, a non-volatile memory cell does not support data rewriting. However, the controller 130 can use the feature of a MLC that is capable of storing multiple bits of data to program 1 bit of data in a MLC multiple times. For a MLC rewriting operation, when 1 bit of data is programmed into a MLC, the controller 130 can store the number of iterations of the program operation as separate operation information. In some embodiments of the disclosed technology, the threshold voltage of the MLC can be uniformly distributed before other 1 bit of data can be programmed into the same MLC.

[0131] In an embodiment, the memory device 150 includes a non-volatile memory such as a flash memory, e.g., a NAND flash memory or a NOR flash memory. In another embodiment, the memory device 150 can include at least one of a phase change random access memory (PCRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), a spin transfer torque magnetic random access memory (STT-MRAM), etc.

[0132] Referring to Figure 3 The controller 130 in the memory system operates with the host 102 and the memory device 150. As shown, the controller 130 includes a host interface 132, a flash translation layer (FTL) 240, a memory interface 142, and a memory 144.

[0133] In some embodiments of the disclosed technology, Figure 2 The error correction circuit 138 shown in FIG. 1 can be included in the flash translation layer (FTL) 240. In another embodiment, the error correction circuit 138 can include a separate module, circuit, firmware, etc., included in or associated with the controller 130.

[0134] The host interface 132 can handle commands, data, and other signals transferred from the host 102. By way of example and not limitation, the host interface 132 can include the command queue 56, the buffer manager 52, and the event queue 54. The command queue 56 can sequentially store commands, data, and the like received from the host 102, and output them to the buffer manager 52, for example, in the order they are stored in the command queue 56. The buffer manager 52 can sort, manage, or adjust the commands, data, and the like received from the command queue 56. The event queue 54 can sequentially transfer events for processing the commands, data, and the like received from the buffer manager 52.

[0135] Multiple commands or data of the same characteristics can be transferred from the host 102, or multiple commands and data of different characteristics can be mixed or scrambled by the host 102 and then transferred to the memory system 110. For example, multiple commands for reading data (i.e., read commands) can be delivered, or commands for reading data (i.e., read commands) and commands for programming / writing data (i.e., write commands) can be alternately transferred to the memory system 110. The host interface 132 can sequentially store the commands, data, and other signals transferred from the host 102 in the command queue 56. Hereinafter, the host interface 132 can estimate or predict which type of internal operation the controller 130 will perform according to the characteristics of the commands, data, and the like that have been transferred from the host 102. The host interface 132 can determine the processing order and priority of the commands, data, and other signals based on their characteristics.

[0136] Based on the characteristics of the commands and data transferred from the host 102, the buffer manager 52 in the host interface 132 is configured to determine whether the buffer manager 52 should store the commands and data in the memory 144, or whether the buffer manager 52 should deliver the commands and data to the flash translation layer (FTL) 240. The event queue 54 receives events transferred from the buffer manager 52, and delivers the events to the flash translation layer (FTL) 240 in the order of the events input to the event queue 54, which will be internally run and processed by the memory system 110 or the controller 130 in response to the commands, data, and the like.

[0137] In an embodiment, Figure 3 The illustrated flash translation layer (FTL) 240 can implement a multi-threading scheme to perform data input / output (I / O) operations. The multi-threading FTL can be implemented using multi-threading included in the controller 130 by a multi-core processor.

[0138] In embodiments, the flash translation layer (FTL) 240 can include a host request manager (HRM) 46, a mapping manager (MM) 44, a state manager (GC / WL) 42, and a block manager (BM / BBM) 48. The host request manager (HRM) 46 can manage events transferred from the event queue 54. The mapping manager (MM) 44 can handle or control mapping data. The state manager 42 can perform garbage collection (GC) or wear leveling (WL). The block manager 48 can run commands or instructions on blocks in the memory device 150.

[0139] By way of example and not limitation, the host request manager (HRM) 46 can handle or process requests for events according to read commands and program commands passed from the host interface 132 and events using the mapping manager (MM) 44 and the block manager 48. The host request manager (HRM) 46 can send a query request to the mapping manager (MM) 44 to determine a physical address corresponding to a logical address input with the event. The host request manager (HRM) 46 can send a read request to the memory interface 142 with the physical address to process the read request, i.e., handle the event. In one embodiment, the host request manager (HRM) 46 can send a program request (or write request) to the block manager 48 to program data into a particular blank page in the memory device 150 that does not store data, and can then transfer a mapping update request corresponding to the program request to the mapping manager (MM) 44 to update an item related to the programmed data in information mapping logical and physical addresses to each other.

[0140] The block manager 48 can convert program requests passed from the host request manager (HRM) 46, the mapping data manager (MM) 44, and / or the state manager 42 into flash program requests for the memory device 150 to manage flash blocks in the memory device 150. To maximize or enhance program performance or write performance of the memory system 110, the block manager 48 can collect program requests and send flash program requests for multi-plane and single-trigger program operations to the memory interface 142. In embodiments, the block manager 48 can send several flash program requests to the memory interface 142 to enhance or maximize parallel processing of multi-channel and multi-direction flash controllers.

[0141] In an embodiment, the block manager 48 can manage the blocks in the memory device 150 according to the number of valid pages, select and erase a block having no valid page when a free block is needed, and select a block including the least number of valid pages when it is determined that garbage collection is to be performed. The state manager 42 can perform garbage collection to move valid data stored in the selected block to a free block and erase the remaining data stored in the selected block, so that the memory device 150 can have enough free blocks (i.e., blocks having no data). When the block manager 48 provides information about the block to be erased to the state manager 42, the state manager 42 can check all flash pages of the block to be erased to determine whether each page of the block is valid.

[0142] For example, to determine the validity of each page, the state manager 42 can identify a logical address recorded in an out-of-band (OOB) area of each page. To determine whether each page is valid, the state manager 42 can compare the physical address of the page with a physical address mapped to the logical address obtained from the query request. For each valid page, the state manager 42 sends a program request to the block manager 48. When the program operation is completed, the mapping table can be updated by the mapping manager 44.

[0143] The mapping manager 44 can manage mapping data, such as a logical-physical mapping table. The mapping manager 44 can process various requests, such as a query, an update, etc., generated by the host request manager (HRM) 46 or the state manager 42. The mapping manager 44 can store the entire mapping table in the memory device 150 (e.g., flash / non-volatile memory) and cache mapping entries according to the storage capacity of the memory 144. When a mapping cache miss occurs while processing a query request or an update request, the mapping manager 44 can send a read request to the memory interface 142 to load the relevant mapping table stored in the memory device 150. When the number of dirty cache blocks in the mapping manager 44 exceeds a certain threshold, a program request can be sent to the block manager 48, thereby forming clean cache blocks, and the dirty mapping table can be stored in the memory device 150.

[0144] When garbage collection is performed, the state manager 42 copies the valid page into the free block, and the host request manager (HRM) 46 can program the latest version of data for the same logical address of the page and currently make an update request. When the state manager 42 requests a mapping update in a state in which the copying of the valid page is not normally completed, the mapping manager 44 can not perform a mapping table update. This is because, when the state manager 42 requests a mapping update and then the valid page copying is completed, a mapping request with old physical information is made. The mapping manager 44 can perform a mapping update operation to ensure accuracy only when the latest mapping table still points to the old physical address.

[0145] Figure 4 An example configuration of the controller shown in Figures 1 to 3 FIG. 1 is a block diagram of an example configuration of a controller shown in

[0146] Referring to Figure 4 The flash translation layer (FTL) 240 in the controller 130 can be divided into three layers: an address translation layer ATL; a virtual flash layer VFL; and a flash interface layer FIL.

[0147] For example, the address translation layer ATL can convert a logical address LA transferred from a file system into a logical page address. The address translation layer ATL can perform an address translation process with respect to a logical address space. That is, the address translation layer ATL can perform an address translation process based on mapping information that maps a logical page address LPA to a logical address LA transferred from a host. Such logical-to-logical address mapping information (hereinafter referred to as L2L mapping) can be stored in an area in which metadata is stored in the memory device 150.

[0148] The virtual flash layer VFL can convert a logical page address LPA mapped by the address translation layer ATL into a virtual page address VPA. Here, the virtual page address VPA can correspond to a physical address of a virtual memory device. That is, the virtual page address VPA can correspond to a storage block 152 in the memory device 150. If there is a bad block among the storage blocks 152 in the memory device 150, the virtual flash layer VFL can exclude the bad block. In addition, the virtual flash layer VFL can include a recovery algorithm for scanning a scan area to recover logical-to-virtual address mapping information (L2V mapping) stored in the memory device 150 and mapping information in a data area for storing user data. The recovery algorithm is capable of recovering the logical-to-virtual address mapping information (L2V mapping). Based on the logical-to-virtual address mapping information (L2V mapping) recovered through such a recovery algorithm, the virtual flash layer VFL can perform an address translation process with respect to a virtual address space.

[0149] The flash interface layer FIL can convert a virtual page address of the virtual flash layer VFL into a physical page address of the memory device 150. The flash interface layer FIL performs low-level operations for interfacing the memory device 150. For example, the flash interface layer FIL can include low-level drivers for controlling hardware of the memory device 150, an error correction code (ECC) for checking and correcting errors in data transmitted from the memory device 150, and a module for performing operations such as bad block management (BBM).

[0150] Figure 5 An example of an encoding apparatus that generates a low-density parity-check (LDPC) code is illustrated.

[0151] Referring to Figure 5 , the encoding apparatus can encode K-bit data (u) into an N-bit codeword (C) based on a low-density parity-check (LDPC) code. In this case, it is assumed that the codeword (C) has N bits, the input data (u) has K bits, and the generated parity check has M bits. This is shown in Equation 1 described below.

[0152] C = u GM (Equation 1)

[0153] Hereinafter, GM is a generator matrix having a size of M x N. A parity check matrix (H matrix) is a binary matrix having a size of K x N. GM can satisfy Equation 2 below.

[0154] GM H t = 0 (Equation 2)

[0155] Columns of the parity check matrix (H matrix) can be associated with bits of the codeword, and each row can correspond to a parity check. A "1" included in each row indicates that the corresponding bit contributes to the parity check. The LDPC code can be divided into a regular code and an irregular code according to a characteristic of the parity check matrix (H matrix). The LDPC code can be regular when all rows have the same number of "1"s and all columns have the same number of "1"s. Otherwise, the LDPC code can be irregular. Specifically, the LDPC code can be represented as a Tanner graph, which is an equivalent bipartite graph. The Tanner graph is a graph that uses the parity check matrix (H matrix) as an incidence matrix. Each column of the parity check matrix (H matrix) is a variable node, and each row is a check node. Each "1" of the parity check matrix (H matrix) can indicate an edge connecting one variable node and one check node. The number of edges connected to a node is called the degree of the node. When the degrees of all variable nodes are the same and the degrees of all check nodes are the same, the LDPC code is called a regular LDPC code. Otherwise, the LDPC code can be called an irregular LDPC code.

[0156] The parity check matrix (H matrix) can include two matrices: a first partial matrix H1 corresponding to parity bits and a second partial matrix H2 corresponding to a data size, as shown in Equation 3 below.

[0157] H = [H1 H2] (Equation 3)

[0158] That is, the parity check matrix (H matrix) can include an (M x K) partial matrix H1 and a (K x K) partial matrix H2. Herein, the (M x K) partial matrix H1 is a sparse matrix having a lower density, but the (K x K) partial matrix H2 can not be a sparse matrix. Based on some embodiments of the disclosed technology, the (K x K) partial matrix H2 can have (M-1) orders in two columns and a final order in one column. With reference to Equations 1 to 3, a generator matrix GM can be defined as Equation 4 below.

[0159] GM = [u H1 t H2 -t ] (Equation 4)

[0160] The codeword (C) output from the encoding apparatus described in Figure 5 is a sum of the input data (u) and the parity (p).

[0161] C = u + p (Equation 5)

[0162] In the encoding operation using the LDPC code, in order to reduce the amount of calculation and lower the complexity, the encoding calculation with respect to the input data (u) in the codeword (C) can not be performed, but the encoding calculation for determining the parity (p) will be performed. Thus, with reference to Equations 1 to 4, the operation with respect to each parity (p) can be defined as Equations 6 to 8 below.

[0163] [u p]*[H1 H2] = u H1 t +p H2 t = 0 (Equation 6)

[0164] u H1 t = p H2 t (Equation 7)

[0165] p = [u H1 t H2 -t ] (Equation 8)

[0166] With reference to Figure 5The encoding device can perform calculations to determine parity (p) based on low-density parity-check codes (LDPC codes). Specifically, the encoding device generates a first result (x) by multiplying the input data (u: information) by a first matrix (H1′) (operation 532), and then multiplies the first result (x) by a second matrix (G) to determine parity (p) (operation 534). The encoding device may include: a first calculator 512 configured to multiply the input data (u: information) by the first matrix H1′; and a second calculator 514 configured to multiply the first result (x) by the second matrix (G). Therefore, Figure 5 The second matrix G described in the text can be H2 -t .

[0167] Figure 5 The first matrix H1′ described is a sparse matrix with low density, while the second matrix G can be denser than the first matrix H1′, so that a large amount of resources in the memory system 110 used for performing matrix multiplication can be consumed. Based on some embodiments of the disclosed technology, the number of computations in matrix multiplication using the second matrix G can have a property proportional to the square of the parity length.

[0168] Figure 6 It shows Figure 5 Examples of the first and second matrices used.

[0169] Reference Figure 6 The first matrix (H1′) can have a size of (M×K). Here, K is the number of bits in the input data (u), and M is the number of bits for parity checking. The second matrix (G matrix) can have a size of (K×K). The codeword C, which is the sum of the data and parity check, can have a length of N bits. When the non-volatile memory cells included in the memory device 150 are TLCs capable of storing 3 bits of data, the second matrix (G matrix) can have a size of (TLC_B#×TLC_B#). When the non-volatile memory cells included in the memory device 150 are QLCs capable of storing 4 bits of data, the second matrix (G matrix) can have a size of (QLC_B#×QLC_B#). When the non-volatile memory cells in the memory device 150 are TLCs or QLCs, the parity check can be equally set to a length of 128 bits.

[0170] The encoding device using the LDPC code included in the memory system 110 can include a first matrix (H1') and a second matrix (G matrix) having different sizes according to the size of data transmitted from the controller 130 to the memory device 150. An example of the data transmitted from the controller 130 to the memory device 150 is program data (data to be written to the memory device) transmitted during a program operation.

[0171] The memory system 110 can set various program operations. Basically, when a page is set as a minimum unit of a program operation, the controller 130 can transmit data having a size corresponding to the page size to the memory device 150. Also, the size of data transmitted from the controller 130 to the memory device 150 can vary according to whether the memory device 150 includes a decoding device corresponding to the encoding device included in the controller 130.

[0172] For example, it is assumed that the number of nonvolatile memory cells connected to a single word line in the memory device 150 is 200. 150 nonvolatile memory cells among the 200 nonvolatile memory cells can be allocated as a data region for storing data, and 50 nonvolatile memory cells can be left as a spare region. Based on some embodiments of the disclosed technology, according to the number of nonvolatile memory cells allocated as a data region and the number of data bits that can be stored in each nonvolatile memory cell, the size of data that can be transferred by a single program operation can be determined. The controller 130 can transmit the amount of data that can be transmitted for a program operation to the memory system 150 in a single data transmission.

[0173] In addition, when 3-bit, 4-bit, or more data can be stored in a nonvolatile memory cell, the controller 150 can transfer data items stored in each memory cell on a bit basis. For example, the controller 130 can sequentially transmit a first data item corresponding to the most significant bit (MSB) of the 150 nonvolatile memory cells to the memory device 150, a second data item corresponding to the center significant bit (CSB) of the 150 nonvolatile memory cells to the memory device 150, and then a third data item corresponding to the least significant bit (LSB) of the 150 nonvolatile memory cells to the memory device 150.

[0174] A codeword output from an encoding apparatus using a low-density parity-check (LDPC) code can include data (u) and parity (p). Based on some embodiments of the disclosed technology, both the data (u) and the parity (p) can be stored in a data region of each page in the memory device 150, or the data (u) and the parity (p) can be stored in a data region and a spare region of each page in the memory device 150, respectively.

[0175] As described above, the length of a codeword output from an encoding apparatus using an LDPC code can be set differently depending on how the controller 130 performs a programming operation and how the memory device 150 stores data and parity. Further, the size of a first matrix (H1') and a second matrix (G matrix) used by the encoding apparatus can differ depending on the size of data input to the encoding apparatus or the number of bits of parity or a codeword output from the encoding apparatus.

[0176] Figure 7 An example of an encoding apparatus and method based on some embodiments of the disclosed technology is shown.

[0177] Referring to Figure 7 , an encoding operation for determining parity associated with input data (u) can be performed in two different methods. One of the two methods is to perform matrix multiplication, and the other is to perform an exclusive OR (XOR) operation, which is a kind of logical operation. Specifically, in the encoding operation, a first result (x) can be obtained by multiplying the input data (u: information) by a first matrix (H1') (operation 632). Parity (p) can be generated based on a plurality of polynomials obtained by multiplying the first result (x) by a second matrix (G L ) is divided into a first parity group P L and a second parity group P R , the first parity group P L is obtained by multiplying the first result (x) by the second matrix (G L ), and the second parity group P R is obtained by performing an exclusive OR operation on the first result (x) and the first parity group P L . The encoding operation can include matrix multiplication performed on the first parity group P L (operation 634), and logical operation performed on the second parity group P R (operation 636) using the first parity group P L . The encoding apparatus in the controller 130 can obtain the first parity group P L and the second parity group P RBoth perform calculations and then add the data (u) and the parity (p) to generate a codeword (C) to determine the parity (p) of the input data (u). The codeword (C) can be output to the memory device 150.

[0178] The encoding apparatus in the controller 130 can perform the calculations on each bit of the parity (p) in any order. In an embodiment, the encoding apparatus can change the order of the calculations to generate each bit of the parity (p) corresponding to each of the plurality of polynomials in order to reduce the number of parity bits included in the first parity group P L The change in the order of the calculations will be described in detail below with reference to Figure 9 and Figure 10

[0179] In addition, the encoding apparatus in the controller 130 can use some of the parity bits that have been determined in the first parity group P L or the second parity group P R to perform an exclusive OR (XOR) operation on the following operations according to the order of the calculations corresponding to the plurality of polynomials. The operations for determining each parity bit included in the first parity group P L or the second parity group P R will be described in detail below with reference to Figure 9 and Figure 10

[0180] Specifically, the encoding apparatus in the controller 130 can include a first calculator 612 configured to multiply the input data (u) by a first matrix (H1') to output a first result (x), a first selector configured to divide the parity (p) into a first parity group P L and a second parity group P R , a second calculator 614 configured to multiply the first result (x) by a second matrix (G L ) to determine the parity bits included in the first parity group P L , a second selector configured to selectively transmit the output of the second calculator 614 for an exclusive OR (NOR) operation, a determination circuit 618 configured to sequentially group the parity bits included in the first parity group P L and the second parity group P R and feed back at least one parity bit for the exclusive OR (NOR) operation, and a third calculator 616 configured to perform the exclusive OR (NOR) operation on the first result (x) and the parity bits output from the second selector and the determination circuit 618 to obtain the parity bits included in the second parity group P R .

[0181] Figure 8 ​​A flowchart illustrating an encoding method based on some embodiments of the disclosed technology is shown.

[0182] Referring to Figure 8 , the encoding method includes initializing a transmission parity list (P T list) transmitted from the controller 130 to the memory device 150, a first parity group list (P L list), and a second parity group list (P R list) (operation 712). The transmission parity list (P T list) can include M parity bits (0 to m-1, i.e., P0 to P m-1 ) determined through an operation or calculation.

[0183] The controller 130 selects a row H s having the lowest degree from the second matrix H2. The controller 130 generates a first parity list (P S list) associated with the row H s . In addition, the controller 130 can add parity bits duplicated in the first parity list (P S list) and the transmission parity list (P T list) to a second parity list (P C list). The controller 130 can set the number of parity bits included in the second parity list (P C list) to "N". Here, "N" can mean the number of parity bits that have not yet been determined among parity bits used to determine an operation of another specific parity bit.

[0184] The controller 130 can check whether "N" is greater than 0 (operation 716). If "N" is 0 (No in operation 716), the controller 130 can delete the selected row H s from the second matrix H2 (operation 726). The controller 130 can check whether the transmission parity list (P T list) is empty (operation 732). If the transmission parity list (P T list) is empty (Yes in operation 732), the controller 130 can complete the encoding operation (operation 734). If the transmission parity list (P T list) is not empty (No in operation 732), the controller 130 can select another row H s having the lowest degree from the remaining second matrix H2 (operation 714). In some embodiments of the disclosed technology, the plurality of rows H s of the second matrix H2 can correspond to Figure 9and Figure 10 the plurality of polynomials described in the middle.

[0185] If "N" is not 0 (Yes in operation 716), the controller 130 can check whether "N" is greater than "1" (operation 718). If "N" is greater than "1" (Yes in operation 718), the controller 130 should perform matrix multiplication. The controller 130 excludes one from the second parity check list (P C list) and includes the remaining parity bits in the first parity check group list (P L list), and the excluded parity bits can be included in the second parity check group list (P R list) (operation 722). The controller 130 can not perform matrix multiplication on N parity bits, and can perform an exclusive OR (XOR) operation on one parity bit.

[0186] If "N" is 1 (No in operation 718), the controller 130 does not need to perform matrix multiplication. The controller 130 can add the parity bits included in the second parity check list (P C list) to the second parity check group list (P R list).

[0187] As described above, after the controller 130 divides the parity bits into the first parity check group list (P L list) and the second parity check group list (P R list), the controller 130 can delete the parity bits of the second parity check list (P T list) from the transmission parity check list (P C list) (operation 728). Since the parity bits are divided into the first parity check group list (P L list) and the second parity check group list (P R list), at least some of the corresponding parity bits can be deleted from the transmission parity check list (P T list) to reduce the number of calculations or the amount of operations for additionally determining the parity bits (operation 728).

[0188] Hereinafter, the controller 130 can check whether the transmission parity check list (P T list) is empty (operation 732). If the transmission parity check list (P T list) is empty (Yes in operation 732), the controller 130 can terminate the encoding operation (operation 734). If the transmission parity check list (P Tis not empty (NO in operation 732), the controller 130 can select another row H s from the remaining second matrix H2 with the lowest order (operation 714).

[0189] Referring to Figure 7 and Figure 8 , in the process of calculating and determining the parity check transmitted to the memory device 150 by the controller 130, the above encoding operation can provide the following example: dividing the parity check bits into a first parity check group P L and a second parity check group P R , the parity check bits in the first parity check group P L are obtained by multiplying the first result (x) by the second matrix (GL), and the parity check bits in the second parity check group P R are obtained by performing an exclusive OR (XOR) operation on the first result (x) and the first parity check group P L In some embodiments of the disclosed technology, this operation can be performed by a first selector in the encoding apparatus, which is capable of dividing the parity check bits into a first parity check group P L and a second parity check group P R In another embodiment, another device or module can perform the operation to classify the above parity check bits into a first parity check group P L and a second parity check group P R Then Figure 7 the encoding apparatus described in L and R can control the operation to sequentially calculate the parity check bits included in the first parity check group P M-1 and the second parity check group P M-1 .

[0190] Figure 9 The calculation of a low-density parity-check (LDPC) code based on some embodiments of the disclosed technology is shown. Figure 9 How to determine the parity check through the encoding operation described in Figure 7 is shown.

[0191] Referring to Figure 9 , it is assumed that the input data (u) has M bits (M = 10), and Equation 6 is applied to the input data (u). In addition, referring to Figure 7 and Figure 9 , the first result (x0, x1,..., x M-1 ) can be obtained by the operation 632 of multiplying the first matrix H1' by the input data (u). The 10 parity check bits or parity check bits (p0, p1,..., p M-1 ) can be obtained by the matrix multiplication (operation 634) and the exclusive OR (XOR) operation (operation 636).Figure 9 An example of the second matrix H2 is shown in the middle.

[0192] First, when multiplication is performed on the second matrix H2, ten polynomials of ten first results (x0, x1, …, x M-1 ) can be calculated. When a regular LDPC code is used, each of the 10 polynomials can include the same number of variables (for example, 4 variables). When the first results (x0, x1, …, x M-1 ) are calculated, and then 10 parity check bits (p0, p1, …, p M-1 ) are determined through matrix multiplication, the amount of operation can increase. In this document, the 10 polynomials can be sequentially calculated.

[0193] In the first polynomial, three parity check bits (p2, p3, p6) other than the first result (x0) are not determined. The controller 130 can perform matrix multiplication on two of the three parity check bits p2, p3, p6 using the second matrix H2, and can perform an exclusive OR (XOR) operation on the other one of the three parity check bits p2, p3, p6 (see operation 722 in Figure 8 ).

[0194] When the operation on the first polynomial ends, the controller 130 can perform an operation on the second polynomial. In the second polynomial, the first result (x1) and one parity check bit (p3) are determined, but two parity check bits (p0, p7) are not determined. The controller 130 can perform matrix multiplication on one of the two parity check bits (p0, p7) using the second matrix H2, and can perform an exclusive OR (XOR) operation on the other one of the two parity check bits (p0, p7) (see operation 722 in Figure 8 ).

[0195] When the operation on the second polynomial is completed, the controller 130 can perform an operation on the third polynomial. In the third polynomial, the first result (x2) and two parity check bits (p0, p6) are determined, but one parity check bit p8 is not determined. The controller 130 can perform an exclusive OR operation on the one parity check bit p8 so that the controller 130 can not perform matrix multiplication using the second matrix H2 for determining the one parity check bit p8 (see operation 724 in Figure 8 ).

[0196] As described above, when the calculation is sequentially performed on the plurality of polynomials, matrix multiplication using the second matrix H2 is performed only on some of the 10 parity check bits, and the other parity check bits can be determined through an exclusive OR (XOR) operation.

[0197] Figure 10 An example of obtaining Figure 9matrix multiplication and logical operations performed by the LDPC codes described in the background art.

[0198] When the 10 polynomials described in the background art are sequentially calculated, Figure 9 The controller 130 can perform matrix multiplication in many cases when the 10 polynomials are calculated. After all 10 parity check bits are determined, the controller 130 can sequentially arrange the 10 parity check bits and transfer the 10 parity check bits to the memory device 150. In some embodiments of the disclosed technology, to reduce the case of performing matrix multiplication (G multiplication) using the second matrix H2, the controller 130 can adjust or change the calculation order of the 10 polynomials.

[0199] Referring to Figure 9 and Figure 10 , the calculation order of the two polynomials associated with the two first results x5, x6 is changed. When the polynomial of the first result x5 is calculated earlier than the polynomial of the first result x6, matrix multiplication (G multiplication) should be performed to determine at least one of the two parity check bits p1, p9. However, when the polynomial of the first result x6 is calculated first after the calculation order is changed, both parity check bits p1, p9 can be sequentially determined by exclusive OR (XOR) operations.

[0200] Referring to Figure 10 , all 10 parity check bits can be determined by the calculation of 7 polynomials among the 10 polynomials. In addition, matrix multiplication (G multiplication) is performed only for 3 parity check bits p2, p3, p0 among the 10 parity check bits, and the remaining 7 parity check bits p1, p4, p5, p6, p7, p8, p9 can be determined by exclusive OR (XOR) operations. Accordingly, the performance ratio (g_mult_ratio) of matrix multiplication (G multiplication) can be 3 / 10 (i.e., 0.3).

[0201] Referring to Figure 6 and Figures 9 to 10 , the first case in which matrix multiplication is performed for all parity check bits can be compared with the second case in which matrix multiplication is reduced and exclusive OR operations are used instead of matrix multiplication. First, it is assumed that the average density of the second matrix H2 is 0.5.

[0202] In the case of performing matrix multiplication for all parity check bits, when the data length is M bits, the number of calculations can be determined as follows.

[0203] Number of calculations (# of Calculations) = M x M x 0.5 (average density) (Equation 9)

[0204] Referring to Figure 6, assuming that M is 30, corresponding to the nonvolatile memory cells in the memory device 150, the number of calculations is 450 (= 30 x 30 x 0.5).

[0205] On the other hand, in the case of reducing the number of matrix multiplications and replacing the matrix multiplications with XOR operations, when the data length is M bits, the number of calculations can be determined as follows.

[0206] Number of calculations = M x (M x g_mult_ratio) x 0.5 + M x (1 - g_mult_ratio) x V_deg (Equation 10)

[0207] Here, "V_deg" denotes the degree of the variable nodes of the parity check matrix (H matrix). Referring to Figure 6 , assuming that M is 30, corresponding to the nonvolatile memory cells in the memory device 150, the number of calculations is 250 (= 30 x 30 x (1 / 3) x 0.5 + 30 x (1 - 1 / 3) x 5). In some embodiments of the disclosed technology, when some of the matrix multiplications are replaced with XOR operations, the amount of operations or the number of calculations can be reduced by 50% to 70%.

[0208] In Figure 9 and Figure 10 , a regular low-density parity-check code (regular LDPC code) is shown as an example, but an irregular low-density parity-check code (irregular LDPC code) can also be applied. In the case of a regular low-density parity-check code (regular LDPC code), the number of variables in a plurality of polynomials can be the same. For example, in Figure 10 , there are four variables in each polynomial. On the other hand, in the case of an irregular low-density parity-check code (irregular LDPC code), the number of variables included in each polynomial can be different. In this case, in order to reduce the number of matrix multiplication operations (G multiplication) while increasing the number of XOR operations, the controller 130 can first perform calculations on polynomials having a smaller number of variables and delay operations on polynomials having a larger number of variables, so that the order of calculations can be modified.

[0209] Figure 11 The effect of the encoding apparatus in the memory system based on some embodiments of the disclosed technology is shown. Figure 11 The amount of operations of the encoding apparatus, which can be determined based on the number of bits of the data stored in the nonvolatile memory cells TLC, QLC in the memory device 150 by Equation 9 and Equation 10, is shown. Here, the number of gates can correspond to the amount of operations of the encoding apparatus.

[0210] To configure the encoding device, when matrix multiplication is performed on all parity check bits of data length (2KB, 4KB) (conventional example), the number of gates required is a in the case of TLC and 2KB data length, and 1.33 to 1.39a in the case of TLC, QLC, and 4KB data length. On the other hand, in the case of reducing matrix multiplication and using XOR operation instead of matrix multiplication (embodiment), the number of gates required is 0.85 to 0.92a in the case of TLC, QLC, and 4KB data length. In some embodiments of the disclosed technology, the amount of G matrix multiplication operation based on the use of regular LDPC codes can be reduced by about 60% to 70% compared to the two cases of TLC and 4KB data length. Accordingly, the number of gates of the encoding device can be reduced by about 30-35%. Therefore, the resource utilization of the memory system 110 can be improved.

[0211] The memory system based on some embodiments of the disclosed technology can improve the performance of detecting and correcting errors occurring in the memory system by using a low-density parity-check (LDPC) code.

[0212] In addition, the memory system based on some embodiments of the disclosed technology has the advantage of reducing resource consumption in the memory system by reducing the amount of operation for generating parity check bits using a low-density parity-check code (LDPC code).

[0213] While various embodiments have been described for illustrative purposes, modifications or improvements can be made to the disclosed embodiments and other embodiments based on the disclosure in this patent document.

Claims

1. An error correction code device comprising: a data input node to receive data to be encoded; and an encoder in communication with the data input node and to: generate a first result by multiplying data bits by a first matrix; divide parity bits into a first parity group and a second parity group based on a plurality of polynomials determined from a second matrix, the first parity group obtained by multiplying the first result by the second matrix, the second parity group obtained by an exclusive OR operation on the first result and the first parity group; multiply the first result by the second matrix to generate one or more first parity bits in the first parity group; perform an exclusive OR operation on the first result and the first parity group to generate one or more second parity bits in the second parity group; and generate a codeword having the data bits and the first parity bits and the second parity bits.

2. The error correction code device of claim 1, wherein the encoder changes a calculation order of generating the one or more first parity bits and the one or more second parity bits to reduce a number of first parity bits included in the first parity group.

3. The error correction code device of claim 1, wherein the encoder uses one or more first parity bits or second parity bits already calculated in the first parity group or the second parity group to generate another second parity bit based on a calculation order to perform a subsequent exclusive OR operation.

4. The error correction code device of claim 1, wherein the encoder comprises: a first calculator to multiply the data bits by the first matrix to output the first result; a first selector to divide the parity bits into the first parity group and the second parity group; a second calculator to multiply the first result by the second matrix to determine the one or more first parity bits included in the first parity group; a second selector to transfer an output of the second calculator for the exclusive OR operation; a determination circuit to sequentially group a number of the parity bits and to feed back at least one parity bit for the exclusive OR operation; and a third calculator to perform the exclusive OR operation on the first result and the first parity bits and the second parity bits output from the second selector and the determination circuit to obtain the one or more second parity bits included in the second parity group. a plurality of rows representing a number of data bits; 5. The error correcting code device of claim 1, wherein the first matrix comprises: and a plurality of columns representing a number of parity bits, and the second matrix comprises: a plurality of rows representing a number of parity bits; and a plurality of columns representing a number of parity bits.

6. The error correction code device of claim 1, wherein each of the plurality of polynomials determined by multiplying the first result by the second matrix comprises a mathematical relationship between the first result and at least a portion of the parity bits.

7. A memory system comprising: A memory device including a plurality of non-volatile memory cells; and a controller in communication with the memory device and storing or reading codewords in or from the plurality of non-volatile memory cells, and wherein the controller: multiplies one or more data bits by a first matrix to generate a first result; divides parity bits into a first parity group and a second parity group based on a plurality of polynomials determined from a second matrix, the first parity group obtained by multiplying the first result by the second matrix, the second parity group obtained by an exclusive-OR operation on the first result and the first parity group; multiplies the first result by the second matrix to generate one or more first parity bits in the first parity group; performs an exclusive-OR operation on the first result and the first parity group to generate one or more second parity bits in the second parity group; and combines the one or more data bits with the first parity bits and the second parity bits to generate the codeword.

8. The memory system of claim 7, wherein a length of the codeword is determined based on a length of one or more bits programmed or read in each programming or read operation.

9. The memory system of claim 7, wherein the controller changes a calculation order of generating the one or more first parity bits in the first parity group and the one or more second parity bits in the second parity group to reduce a number of first parity bits included in the first parity group.

10. The memory system of claim 7, wherein the controller uses one or more first or second parity bits already calculated in the first or second parity group to generate another second parity bit based on a calculation order to perform a subsequent exclusive-OR operation.

11. The memory system of claim 7, wherein the controller includes: a first calculator that multiplies the one or more data bits by the first matrix to output the first result; a first selector that divides the parity bits into the first parity group and the second parity group; a second calculator that multiplies the first result by the second matrix to determine one or more first parity bits included in the first parity group; a second selector that transfers an output of the second calculator for the exclusive-OR operation; a determination circuit that sequentially groups the first parity bits included in the first parity group and the second parity bits included in the second parity group and feeds back at least one parity bit for the exclusive-OR operation; and a third calculator that performs the exclusive-OR operation on the first result and the first and second parity bits output from the second selector and the determination circuit to obtain one or more second parity bits included in the second parity group. a plurality of columns representing a number of parity bits; 12. The memory system of claim 7, wherein the one or more data bits comprise a first number of data bits and the parity bits comprise a second number of parity bits, and wherein the first matrix comprises: ​ and a plurality of rows representing a number of data bits, and the second matrix includes: a plurality of rows representing a number of parity bits; and a plurality of columns representing a number of parity bits.

13. The memory system of claim 7, wherein each of the plurality of polynomials determined by multiplying the first result by the second matrix includes a mathematical relationship between the first result and at least some of the parity bits.

14. The memory system of claim 7, wherein the controller detects and corrects errors in the codeword upon receiving the codeword from the memory device.

15. A method of operating a memory system, comprising: checking one or more data bits and a program command input from an external device; multiplying the one or more data bits by a first matrix to generate a first result; dividing parity bits into a first parity group and a second parity group based on a plurality of polynomials determined from a second matrix, the first parity group obtained by multiplying the first result by the second matrix, the second parity group obtained by an exclusive-OR operation on the first result and the first parity group; multiplying the first result by the second matrix to generate one or more first parity bits in the first parity group; performing an exclusive-OR operation on the first result and the first parity group to generate one or more second parity bits in the second parity group; and combining the one or more data bits with the first parity bits and the second parity bits to generate a codeword to be input to the memory system.

16. The method of claim 15, wherein a length of the codeword is determined based on a length of one or more bits programmed or read at a time in each program operation or read operation.

17. The method of claim 15, further comprising: changing a calculation order of generating the one or more first parity bits in the first parity group and the one or more second parity bits in the second parity group to reduce a number of first parity bits included in the first parity group.

18. The method of claim 15, wherein one or more first parity bits or second parity bits already calculated in the first parity group or the second parity group are used to generate another second parity bit according to a calculation order of the plurality of polynomials by performing a subsequent exclusive-OR operation.

19. The method of claim 15, wherein the one or more data bits comprise a first number of data bits and the parity bits comprise a second number of parity bits, and wherein the first matrix comprises: a plurality of columns representing a number of parity bits; and a plurality of rows representing a number of data bits, and the second matrix includes: a plurality of rows representing a number of parity bits; and a plurality of columns representing a number of parity bits.

20. The method of claim 15, wherein each of the plurality of polynomials determined by multiplying the first result by the second matrix includes a mathematical relationship between the first result and at least some of the parity bits.

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