Bus relationship detection device, slave device, system and chip

Abstract

A bus relationship detection device, a slave device, a system and a chip. The device includes a pre-detection circuit for obtaining two input signals through a first input port and a second input port. The two input signals are a bus clock signal and a bus data signal respectively, and only the input signal that meets the preset frequency requirement is output as an intermediate clock signal; a detection circuit connected to the pre-detection circuit for performing address matching according to the two input signals and the intermediate clock signal to determine the bus relationship, and outputting the matched bus data signal and the bus clock signal. The bus relationship detection device, slave device, system and chip of the present application prevent abnormal detection and judgment situations. The judgment result of the bus connection relationship is accurate and reliable, and the accuracy of host differentiation is improved when differentiating devices.

Description

Technical Field

[0001] The present application relates to the field of electronic technologies, and particularly to a bus relationship detection device, a slave device, a system, and a chip. Background Art

[0002] With the continuous development of communication technologies, people's demand for radio frequency front-end devices (such as power amplifiers, low-noise amplifiers, antenna tuners, filters, switches, etc.) is also increasing continuously. Equipment manufacturers in the radio frequency field are facing the challenge of complex control of many devices. In this regard, the MIPI (Mobile Industry Processor Interface) Alliance has proposed an RFFE (RF Front_End) bus interface for connecting one or more RFICs (RF Integrated Circuits) in a mobile terminal to its related FEM (front-end module) for control and monitoring.

[0003] Slave devices mounted on the RFFE bus can all be recognized by the host through signals such as their unique USID (Unique Slave ID), PID (Product_ID), and MID (MANUFACTURER_ID). In a communication, the USID is included in the command frame and is used to identify whether the slave is a device for correct communication with the host. Only after the USID matches successfully can the slave continue to receive other command frames, address frames, or data frames from the host.

[0004] However, in current application scenarios with more and more multi-chip synchronization, and more and more application scenarios where multiple chips of the same type are commonly mounted on the same radio frequency front-end system, if two devices with the same USID, PID, and MID are required in a radio frequency front-end system, the accuracy of the RFFE host in making distinctions is relatively low. Summary of the Invention

[0005] In view of this, the present application provides a bus relationship detection device, a slave device, a system, and a chip to solve the problem that in an existing radio frequency front-end system, when two devices with the same USID, PID, and MID are used, the accuracy of the host in making distinctions is relatively low.

[0006] A bus relationship detection device provided by the present application includes: a pre-detection circuit for obtaining two input signals through a first input port and a second input port, where the two input signals are a bus clock signal and a bus data signal respectively, and only outputting the input signal that meets the preset frequency requirement as an intermediate clock signal; a detection circuit connected to the pre-detection circuit for performing address matching according to the two input signals and the intermediate clock signal to determine the bus relationship, and outputting the matched bus data signal and the bus clock signal.

[0007] Optionally, the pre-detection circuit includes a pre-detection unit and a gating logic unit; the pre-detection unit is configured to obtain the input signal through the first input port and the second input port, and determine whether the preset frequency requirement is met according to at least one of the number of level changes, the number of rising edges, or the number of falling edges of the input signal, and output a corresponding clock control signal when the preset frequency requirement is met; the gating logic unit is connected to the pre-detection unit for selecting a corresponding input signal as the intermediate clock signal according to the clock control signal and outputting it, and at the same time closing the other input signal from being output as the intermediate clock signal.

[0008] Determining the signal frequency relationship by the number of level changes can prevent interference caused by signal glitches. It is convenient to design the signal frequency circuit by judging the number of rising edges or falling edges through a register.

[0009] Optionally, the pre-detection circuit further includes a sequence detection unit; the sequence detection unit is configured to obtain the input signal through the first input port and the second input port, and output a reset signal after detecting a flag bit in the input signal; the pre-detection unit is connected to the sequence detection unit for performing a reset according to the reset signal, and determining whether the preset frequency requirement is met according to at least one of the number of level changes, the number of rising edges, or the number of falling edges of the input signal after the reset.

[0010] Through the sequence detection unit, after detecting the flag bit in the input signal, a reset signal is output to control the pre-detection unit to perform a reset. The reset method includes synchronous reset and asynchronous reset, preferably asynchronous reset. It is possible to determine whether the two input signals meet the preset frequency requirement after determining that the two input signals are valid bus data signals SDA, further eliminating the influence of invalid signals and improving the accuracy of the frequency judgment result.

[0011] Optionally, the pre-detection unit includes a first pre-detection sub-unit and a second pre-detection sub-unit with the same circuit structure; one of the two input signals is used as the first input signal, and the other is used as the second input signal; the first pre-detection sub-unit, connected to the sequence detection unit, is used to perform asynchronous reset according to the reset signal, and determine whether the preset frequency requirement is met according to at least one of the number of level changes, the number of falling edges, or the number of rising edges of the first input signal, and output a first clock control signal when it is determined that the preset frequency requirement is met; the second pre-detection sub-unit, connected to the sequence detection unit, is used to perform asynchronous reset according to the reset signal, and determine whether the preset frequency requirement is met according to at least one of the number of level changes, the number of falling edges, or the number of rising edges of the second input signal, and output a second clock control signal when it is determined that the preset frequency requirement is met; the gating logic unit, connected to the first pre-detection sub-unit and the second pre-detection sub-unit, is used to select the corresponding input signal as the intermediate clock signal output according to the first clock control signal and the second clock control signal, and at the same time turn off the other input signal as the intermediate clock signal output.

[0012] The same judgment on the two input signals can be realized by the first pre-detection sub-unit and the second pre-detection sub-unit with the same circuit structure to determine the bus clock signal SCL among them, improving the consistency of detection and facilitating the circuit design.

[0013] Optionally, the first pre-detection sub-unit includes at least two registers and a first AND gate device. Among them, the input end of the first register is connected to a high level, the clock end is connected to the first input signal, the reset end is connected to the reset signal, and the output end is connected to the first input end of the first AND gate device. The second input end of the first AND gate device is connected to the inverted second clock control signal after being inverted; the output end of the first AND gate device is connected to the input end of the second register. The clock end of the second register is connected to the first input signal, the reset end is connected to the reset signal, and the output end is used to output the first clock control signal; the second pre-detection sub-unit includes at least two registers and a second AND gate device. Among them, the input end of the third register is connected to a high level, the clock end is connected to the second input signal, the reset end is connected to the reset signal, and the output end is connected to the first input end of the second AND gate device. The second input end of the second AND gate device is connected to the inverted first clock control signal after being inverted; the output end of the second AND gate device is connected to the input end of the fourth register. The clock end of the fourth register is connected to the second input signal, the reset end is connected to the reset signal, and the output end is used to output the second clock control signal.

[0014] Optionally, the flag bit is a sequence start condition flag bit; the sequence detection unit includes a first sequence detection subunit, a second sequence detection subunit, and a first OR gate device; the first sequence detection subunit is configured to output a first intermediate reset signal to a first input end of the first OR gate device after detecting the sequence start condition flag bit in the second input signal; the second sequence detection subunit is configured to output a second intermediate reset signal to a second input end of the first OR gate device after detecting the sequence start condition flag bit in the first input signal; the first OR gate device is configured to output the reset signal according to the first intermediate reset signal and the second intermediate reset signal.

[0015] Optionally, the gating logic unit includes a third AND gate device and a fourth AND gate device; a first input end of the third AND gate device is connected to an output end of the second register after being inverted, and a second input end is connected to the second input signal; the third AND gate device is configured to control the second input signal to be output as a second intermediate clock signal according to the first clock control signal; a first input end of the fourth AND gate device is connected to an output end of the fourth register after being inverted, and a second input end is connected to the first input signal; the fourth AND gate device is configured to control the first input signal to be output as a first intermediate clock signal according to the second clock control signal.

[0016] Optionally, the detection circuit includes a first detection unit and a second detection unit; a first input end of the first detection unit is configured to obtain the first input signal, a second input end is configured to obtain the first intermediate clock signal, and a reset end is configured to obtain the reset signal, and the first detection unit is configured to perform address matching according to the first input signal and the first intermediate clock signal and output a first address matching signal; a first input end of the second detection unit is configured to obtain the second input signal, a second input end is configured to obtain the second intermediate clock signal, a reset end is configured to obtain the reset signal, and is configured to perform address matching according to the second input signal and the second intermediate clock signal and output a second address matching signal.

[0017] The first detection unit and the second detection unit support asynchronous reset of signals. Therefore, the detection result of the detection circuit is not locked. When the host sends a new instruction, the bus relationship of the input port of the slave needs to be re-detected, which can achieve real-time detection and improve the accuracy of detection.

[0018] Optionally, the detection circuit further includes a signal selection unit; the signal selection unit is connected to the first detection unit and the second detection unit, and is configured to select and output a matching bus clock signal and bus data signal according to the first address matching signal and the second address matching signal.

[0019] Optionally, the reset signal includes a first reset signal and a second reset signal. The first reset signal is used to control the reset of the first pre-detection sub-unit, and the second reset signal is used to control the reset of the second pre-detection sub-unit. The sequence detection unit further includes a second OR gate device and a third OR gate device. The first input terminal of the second OR gate device is used to obtain the first address matching signal, the second input terminal is connected to the output terminal of the first OR gate device, and the output terminal is used to output the first reset signal. The first input terminal of the third OR gate device is used to obtain the second address matching signal, the second input terminal is connected to the output terminal of the first OR gate device, and the output terminal is used to output the second reset signal.

[0020] Optionally, the detection circuit includes a counter. The counter is used to count according to the two input signals and the intermediate clock signal, perform address matching when the count value reaches a preset value to determine the bus relationship, and output the matched signals as the bus data signal and the bus clock signal.

[0021] This application also provides a slave device, including: the bus relationship detection device and the data processing unit. The bus relationship detection device is used to select the matching bus data signal and bus clock signal according to the frequency relationship of the input signals and send them to the data processing unit. The data processing unit is connected to the bus relationship detection device and is used to process the received bus data signal and bus clock signal.

[0022] Optionally, the data processing unit includes a data frame processing unit, a state machine, and a register module. The data frame processing unit and the state machine are connected to the bus relationship detection device and are used to receive the command in the bus data signal and process the command. The register has its first input terminal connected to the output terminal of the data frame processing unit and state machine, and its second input terminal connected to the detection circuit, and is used to receive the slave device address in the bus data signal and process the slave device address.

[0023] This application also provides a communication system, including: a master device, at least two of the above-mentioned slave devices. The first slave device and the second slave device are two devices of the same type manufactured by the same manufacturer. Among them, the clock terminal of the master device is respectively connected to the first input port of the first slave device and the second input port of the second slave device, and the data terminal of the master device is respectively connected to the second input port of the first slave device and the first input port of the second slave device.

[0024] This application also provides a radio frequency chip, including a circuit interface composed of the above-mentioned bus relationship detection device.

[0025] The bus relationship detection device, slave device, system and chip of the present application, a pre-detection circuit, is used to obtain two input signals through a first input port and a second input port, the two input signals are a bus clock signal and a bus data signal respectively, and only outputs the input signal that meets the preset frequency requirement as an intermediate clock signal; a detection circuit, connected to the pre-detection circuit, is used to perform address matching according to the two input signals and the intermediate clock signal to determine the bus relationship, and outputs the matched bus data signal and the bus clock signal, preventing the situation of abnormal detection and judgment, and the judgment result of the connection relationship of the bus is accurate and reliable, improving the accuracy of host differentiation when differentiating devices. Description of the Drawings

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for description in the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained according to these drawings.

[0027] Figure 1a Schematic diagram of the RFFE device interface defined by the MIPI RFFE standard;

[0028] Figure 1b Schematic diagram of the MIPI RFFE command sequence;

[0029] Figure 2 Schematic diagram of the structure of the bus relationship detection device in an embodiment;

[0030] Figure 3 Schematic diagram of the structure of the bus relationship detection device in an embodiment;

[0031] Figure 4 Schematic diagram of the structure of the bus relationship detection device in an embodiment;

[0032] Figure 5 Timing diagram when the SCL bus is connected to the first input port and the SDA bus is connected to the second input port;

[0033] Figure 6 Timing diagram when the SDA bus is connected to the first input port and the SCL bus is connected to the second input port;

[0034] Figure 7 Schematic diagram of the structure of the slave device in an embodiment;

[0035] Figure 8 Communication system in an embodiment. Detailed Embodiments

[0036] In the process of implementing the present invention, the inventor invented that the MIPI RFFE standard defines an interface between RFFE devices, as Figure 1a shown. Up to 1 master device and 15 slave devices can be mounted on a single RFFE bus ( Figure 1a only slave device 1 and slave device 2 are shown in

[0037] ). The bus consists of a clock signal line SCLK and SDATA, where SCLK is controlled by the host, and SDATA is a bidirectional data line that can be controlled by both the host and the slave. The slave devices mounted on the RFFE bus can be recognized by the host through signals such as their unique USID, product ID, and manufacturer ID. Figure 1b As

[0038] shown, the MIPI RFFE command sequence mainly consists of the following three parts, in sequence:

[0039] 1. Transmission of the sequence start condition

[0040] 2. Transmission of frames (including one command frame, 0, 1, or multiple address / data frames, depending on the type of command frame)

[0041] 3. Bus release (Bus Park Cycle) Figure 1b Taking the register write instruction as an example, a typical MIPI communication includes the following process, as

[0042] (1) The host sends a start signal "SSC (Sequence Start Condition)", and at this time, no clock signal is transmitted on SCLK. After the SSC signal, the start of a communication begins;

[0043] (2) The host then sends a command frame (RegisterWrite Command Frame). This command frame consists of a 4-bit slave device address USID, namely SA3, SA2, SA1, and SA0, a 3-bit register write identification code, namely 010, a 5-bit register address, namely A4, A3, A2, A1, and A0, and a 1-bit parity bit P. The composition of the command frame for different read / write instruction sequences will be different;

[0044] (3) The host then sends a data frame (Data Frame). This data frame consists of 8-bit data D7, D6, D5, D4, D3, D2, D1, and D0 and a 1-bit parity bit P;

[0045] (4) The host sends a bus release (Bus Park) 0 to end this communication and release the bus.

[0046] In a communication, the USID is included in the command frame to identify whether the slave device is a device for correct communication with the master device. Only after the USID matches successfully can the slave device continue to receive other command frames, address frames, or data frames from the master device.

[0047] To solve the problem of low accuracy in distinguishing when there are multiple slave devices with the same USID / PID / MID in a radio frequency front-end system, the prior art provides a solution.

[0048] Prior art 1: When two MIPI RFFE slave devices (slave device 1 and slave device 2) are exactly the same, connect the SCLK of slave device 1 to the SCLK of the master device and the SDATA to the SDATA of the master device; connect the SCLK of slave device 2 to the SDATA of the master device and the SDATA to the SCLK of the master device. Each slave device determines the current bus connection relationship by detecting the SSC signal in the received signal. Since the USIDs corresponding to different bus connection methods are different, two exactly the same MIPI RFFE slave devices can be distinguished in the MIPI RFFE system.

[0049] Prior art 2: Detect the data characteristics of the first 13-bit command frame of the instruction sent by the master device through two sets of signal detection circuits (signal detection circuit 1 and signal detection circuit 2) with symmetric structures and cross-connected buses, and then judge the current bus connection method, so as to distinguish two exactly the same MIPI RFFE slave devices in the MIPI RFFE system.

[0050] The inventor found that the prior art has the following disadvantages:

[0051] Disadvantages of prior art 1: This technology judges the current connection relationship of the SCL and SDA buses through SSC detection. If there are glitches in the bus before a communication judgment, it is very likely to cause misdetection of the SSC signal, resulting in abnormal judgment of the current bus relationship. Therefore, this technology lacks consideration for abnormal situations and has poor detection and judgment accuracy.

[0052] Disadvantages of the prior art 2: This technology uses two signal detection circuits (signal detection circuit 1 and signal detection circuit 2) with symmetric structures and cross-connected buses to detect the data characteristics (whether the command sequence is the sequence specified by the protocol and whether the parity check bit is correct) of the first 13-bit command frame of the instructions sent by the master device. If the data sent by the host is abnormal or the data is distorted due to interference during transmission, the command frame of the instruction will not meet the data characteristics, and the operation of the bus relationship anomaly detection system cannot be blocked in time. When sufficient pulses are provided, it will lead to an abnormal judgment of the bus relationship. Therefore, this technology has insufficient consideration for abnormal situations and poor accuracy of detection and judgment.

[0053] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of the present application. Without conflict, the following various embodiments and their technical features can be combined with each other.

[0054] Please refer to Figure 2 , a schematic structural diagram of a bus relationship detection device according to an embodiment of the present application.

[0055] The bus relationship detection device of the present application includes: a pre-detection circuit 1 and a detection circuit 2.

[0056] The pre-detection circuit 1 is used to obtain two input signals data_in1 and data_in2 through a first input port and a second input port. The two input signals are a bus clock signal and a bus data signal respectively, and only the input signal data_in1 or the input signal data_in2 that meets the preset frequency requirement is output as an intermediate clock signal gata_clk1 or gata_clk2.

[0057] The detection circuit 2 is connected to the pre-detection circuit 1 and is used to perform address matching according to the input signal data_in1, the input signal data_in2, and the intermediate clock signal gata_clk1 or gata_clk2 to determine the bus relationship, and output the matched bus data signal data_in_ctrl and the bus clock signal clk_ctrl.

[0058] The bus relationship detection device of this embodiment, a pre-detection circuit 1, is configured to obtain two input signals data_in1 and data_in2 through a first input port and a second input port. The two input signals are a bus clock signal and a bus data signal respectively, and only the input signal data_in1 or the input signal data_in2 that meets the preset frequency requirement is output as an intermediate clock signal gata_clk1 or gata_clk2; a detection circuit 2, connected to the pre-detection circuit 1, is configured to perform address matching according to the input signal data_in1, the input signal data_in2, and the intermediate clock signal gata_clk1 or gata_clk2 to determine the bus relationship, and output the matched bus data signal data_in_ctrl and bus clock signal clk_ctrl, preventing the situation of abnormal detection and judgment. The judgment result of the bus connection relationship is accurate and reliable, improving the accuracy of host differentiation when differentiating devices.

[0059] In an alternative embodiment, one of gata_clk1 and gata_clk2 serves as an intermediate clock signal, which is consistent with the bus clock signal in the input signals, and the other remains at a constant level.

[0060] A bus relationship detection device of this embodiment is composed of a pre-detection circuit 1 and a detection circuit 2. The working process of the bus relationship detection device: When the MIPI host sends a complete instruction to the slave, (1) the pre-detection circuit 1 of the bus relationship detection device pre-judges the bus relationship by detecting the signal frequency relationship of two input ports (the first input port and the second input port), outputs the signal that meets the preset frequency requirement to the detection circuit in the form of an intermediate clock signal, and turns off the signal that does not meet the preset frequency requirement; (2) the detection circuit 2 determines the final bus relationship by judging the matching situation between the intermediate clock signal output from the output end of the pre-detection circuit 1 and the address id (identity identification number) of the two input signals, and selects and outputs the correct data end and clock end for subsequent data processing units to use.

[0061] In the bus relationship detection device of this embodiment, the pre-detection circuit 1 pre-judges the bus relationship based on the frequency relationship between two input signals, determines which of the two input signals is the bus clock signal, i.e., the bus clock signal SCL, and which is the bus data signal, i.e., the bus data signal SDA. Since the frequency of the bus clock signal SCL is several times that of the bus data signal SDA, such as 2 times, 3 times or other multiples, by judging whether the two input signals meet the preset frequency requirements, it can be determined which of the two input signals is the bus clock signal SCL and which is the bus data signal SDA, and only the bus clock signal SCL that meets the preset frequency requirements is output to the detection circuit. Since the level of the bus data signal SDA does not change, that is, the clock transmission pre-judged as the bus data signal SDA is turned off, thereby controlling the number of pulses of the corresponding detection unit in the detection circuit 2 with the bus data signal SDA as the clock, resulting in the corresponding detection unit in the detection circuit 2 being unable to continue the detection work. The advantage of this design is that even if the instruction sent by the current host does not meet the detection conditions of the detection unit with the bus clock signal SCL as the clock, since the pre-detection unit controls the number of clock pulses of the bus data signal SDA, the detection unit with the bus data signal SDA as the clock cannot perform the detection work due to the limitation of the number of pulses, preventing the situation of abnormal detection and judgment. The detection circuit 2 determines the final bus relationship by judging the address matching situation between the intermediate clock signal output from the output end of the pre-detection circuit 1 and the two input signals, and selects and outputs the data end and clock end with the correct relationship for subsequent units to use, realizing address expansion through bus switching. The judgment result of the bus connection relationship is accurate, reliable, and the implementation circuit is simple.

[0062] The bus relationship detection device of this application judges the bus relationship through the frequency relationship. Compared with the judgment of the bus relationship through the data characteristic relationship, it avoids the situation that when the data sent by the host is abnormal or the data is distorted due to interference during the transmission process, the command frame of the instruction does not meet the data characteristics, and the abnormal detection system of the bus relationship cannot be shielded in time. When enough pulses are provided, it will lead to the abnormal judgment of the bus relationship. Therefore, the bus relationship detection device of this application considers sufficient abnormal situations and has high detection and judgment accuracy.

[0063] Please refer to Figure 3 , the structural schematic diagram of the bus relationship detection device of an embodiment of this application.

[0064] In this embodiment, the pre-detection circuit includes a pre-detection unit 11 and a gating logic unit 12; the pre-detection unit 11 is configured to obtain the input signal through a first input port and a second input port, and determine whether the preset frequency requirement is met according to at least one of the number of level changes, the number of rising edges, or the number of falling edges of the input signal, and output a corresponding clock control signal when the preset frequency requirement is met.

[0065] For example, the pre-detection unit 11 determines the signal frequencies of the first input signal and the second input signal by judging the number of level changes of the first input signal and the second input signal through a level comparator and a counter, and then compares the signal frequencies with the preset frequency requirement to determine whether it is an intermediate clock signal, i.e., the bus clock signal SCL, or a data signal, i.e., the bus data signal SDA. Determining the signal frequency relationship by the number of level changes can prevent interference caused by signal glitches.

[0066] Alternatively, the number of rising edges or the number of falling edges of the two input signals is judged through a register to determine the signal frequencies of the two input signals, and then the signal frequencies are compared with the preset frequency requirement to determine whether it is an intermediate clock signal, the bus clock signal SCL, or a data signal, i.e., the bus data signal SDA. Judging the number of rising edges or the number of falling edges through a register to determine the signal frequency is convenient for circuit design.

[0067] The gating logic unit 12 is connected to the pre-detection unit 11 and is configured to select a corresponding input signal as the intermediate clock signal output according to the clock control signal, and at the same time turn off the other input signal as the intermediate clock signal output. By turning off the output of the bus data signal SDA, even if the current instruction cannot generate a final judgment on the detection circuit, since the number of clocks of the detection unit with the SDA bus input terminal as the clock is limited, no false detection operation will occur, ensuring the reliability of the bus relationship detection device.

[0068] In an optional embodiment, the pre-detection circuit further includes a sequence detection unit 13; the sequence detection unit 13 is configured to obtain the input signal through a first input port and a second input port, and output a reset signal after detecting a flag bit in the input signal; the pre-detection unit 11 is connected to the sequence detection unit 13 and is configured to be reset according to the reset signal, and determine whether the preset frequency requirement is met according to at least one of the number of level changes, the number of rising edges, or the number of falling edges of the input signal after the reset.

[0069] Through the sequence detection unit 13, after detecting the flag bit in the input signal, a reset signal is output to control the pre-detection unit 11 to be reset. The reset methods include synchronous reset and asynchronous reset, and preferably asynchronous reset. It is possible to determine whether the two input signals meet the preset frequency requirements after determining that the two input signals are valid bus data signals SDA, further eliminating the influence of invalid signals and improving the accuracy of the frequency judgment result.

[0070] In another alternative embodiment, the pre-detection unit 11 includes a first pre-detection sub-unit 111 and a second pre-detection sub-unit 112 with the same circuit structure; one of the two input signals serves as the first input signal, and the other serves as the second input signal; the first pre-detection sub-unit 111 is connected to the sequence detection unit 13 and is used to perform asynchronous reset according to the reset signal, and determine whether the preset frequency requirement is met according to at least one of the number of level changes, the number of falling edges, or the number of rising edges of the first input signal, and output a first clock control signal when it is determined that the preset frequency requirement is met; the second pre-detection sub-unit 112 is connected to the sequence detection unit 13 and is used to perform asynchronous reset according to the reset signal, and determine whether the preset frequency requirement is met according to at least one of the number of level changes, the number of falling edges, or the number of rising edges of the second input signal, and output a second clock control signal when it is determined that the preset frequency requirement is met; the gating logic unit 12 is connected to the first pre-detection sub-unit 111 and the second pre-detection sub-unit 112, and is used to select the corresponding input signal as the intermediate clock signal output according to the first clock control signal and the second clock control signal, and at the same time turn off the other input signal as the intermediate clock signal output.

[0071] By using the first pre-detection sub-unit and the second pre-detection sub-unit with the same circuit structure, the same judgment can be made on the two input signals to determine the bus clock signal SCL therein, improving the consistency of detection and facilitating circuit design.

[0072] Please refer to Figure 4 , the structural schematic diagram of the bus relationship detection device according to an embodiment of the present application.

[0073] The pre-detection circuit 1 of this embodiment is composed of two pre-detection units (the first pre-detection sub-unit 111 and the second pre-detection sub-unit 112) and a sequence detection unit (the first sequence detection sub-unit SSC1 and the second sequence detection sub-unit SSC2), and the first pre-detection sub-unit 111 and the second pre-detection sub-unit 112 have the same structure.

[0074] The first pre-detection sub-unit 111 includes at least two registers and a first AND gate device. Among them, the input end of the first register Q1 is connected to a high level, the clock end is connected to the first input signal, the reset end is connected to the reset signal, and the output end is connected to the first input end of the first AND gate device A1. The second input end of the first AND gate device A1 is connected to the second clock control signal gc2 after being inverted; the output end of the first AND gate device A1 is connected to the input end of the second register Q2. The clock end of the second register Q2 is connected to the first input signal, the reset end is connected to the reset signal, and the output end is used to output the first clock control signal gc1.

[0075] The first pre-detection sub-unit 111 of this embodiment is composed of two-stage registers and the high1&!gc2 logic therebetween. Moreover, the D end of the first-stage register is connected to a high level, and the gc1 signal generated by the second-stage register is inverted and ANDed with the second input port. The clock ends of the two-stage registers are controlled by the falling edge of the first input port signal and support the asynchronous reset of the SSC1 signal, the SSC2 signal, and the flag signal of the second pre-detection sub-unit 112.

[0076] The specific working principle of the first pre-detection sub-unit 111 is as follows: After the first register Q1 and the second register Q2 receive the asynchronous reset of the reset signal, the output end of the first register Q1 outputs a high level high1 under the action of the first falling edge of the first input signal. When the second clock control signal gc2 is 0, it is inverted and input to the first AND gate device A1. The input end of the second register Q2 is at a high level. Under the action of the second falling edge of the first input signal, the first clock control signal gc1 is output. Therefore, the first pre-detection sub-unit 111 can output the first clock control signal gc1 as 1 after two clock falling edges, indicating that the current first input signal is the bus clock signal SCL. If the clock falling edge signal is not detected, the first clock control signal gc1 is 0.

[0077] In other alternative embodiments, the number of registers can be 3, 4, or more to achieve the detection of multiple clock falling edges.

[0078] The second pre-detection sub-unit 112 includes at least two registers and a second AND gate device. Among them, the input end of the third register Q3 is connected to a high level, the clock end is connected to the second input signal, the reset end is connected to the reset signal, and the output end is connected to the first input end of the second AND gate device A2. The second input end of the second AND gate device A2 is connected to the first clock control signal gc1 after being inverted; the output end of the second AND gate device A2 is connected to the input end of the fourth register Q4. The clock end of the fourth register Q4 is connected to the second input signal, the reset end is connected to the reset signal, and the output end is used to output the second clock control signal gc2.

[0079] The second pre-detection sub-unit 112 of this embodiment is composed of the high2&!gc1 logic between two levels of registers. The D terminal of the first-level register is connected to a high level. The gc2 signal generated by the second-level register is inverted and ANDed with the first input port. The clock terminals of the two levels of registers are controlled by the falling edge of the second input port signal and support the asynchronous reset of the SSC1 signal, the SSC2 signal, and the flag signal of the first pre-detection sub-unit 111.

[0080] The specific working principle of the second pre-detection sub-unit 112 is as follows: After the third register Q3 and the fourth register Q4 receive the reset signal and are asynchronously reset, the third register Q3 outputs a high level high2 at the output terminal under the action of the first falling edge of the first input signal. When the first clock control signal gc1 is 0, it is inverted and then input to the second AND gate device A2. The input terminal of the fourth register Q4 is at a high level. Under the action of the second falling edge of the second input signal, the second clock control signal gc2 is output. Therefore, the second pre-detection sub-unit 112 can output the second clock control signal gc2 as 1 after two clock falling edges, indicating that the current second input signal is the bus clock signal SCL. If the clock falling edge signal is not detected, the second clock control signal gc2 is 0.

[0081] In other alternative embodiments, the number of registers can be 3, 4, or more to achieve the detection of multiple clock falling edges.

[0082] The flag bit is the sequence start condition flag bit SSC; the sequence detection unit includes a first sequence detection sub-unit SSC1, a second sequence detection sub-unit SSC2, and a first OR gate device O1; the first sequence detection sub-unit SSC1 is used to output a first intermediate reset signal to the first input terminal of the first OR gate device O1 after detecting the sequence start condition flag bit SSC in the second input signal; the second sequence detection sub-unit SSC2 is used to output a second intermediate reset signal to the second input terminal of the first OR gate device O1 after detecting the sequence start condition flag bit SSC in the first input signal; the first OR gate device O1 is used to output the reset signal according to the first intermediate reset signal and the second intermediate reset signal.

[0083] The pre-detection circuit 1 utilizes the feature that the frequency of the bus clock signal SCL is at least twice the frequency of the bus data signal SDA. By using the first sequence detection subunit SSC1 and the second sequence detection subunit SSC2, it pre-judges the SSC signal and then outputs a reset signal to control the asynchronous reset of the first pre-detection subunit 111 and the second pre-detection subunit 112. After the reset, the input terminals of the first pre-detection subunit 111 and the second pre-detection subunit 112 that first reach two falling-edge input signals are the bus clock signal SCL, that is, this input terminal is the input terminal of the SCL bus, and the other input terminal is the input terminal of the SDA bus. At this time, the units in the first pre-detection subunit 111 and the second pre-detection subunit 112 that use the input terminal of the SCL bus as the clock will first generate a clock control signal, the first clock control signal gc1 or the second clock control signal gc2. This clock control signal can shield the generation of the clock control signal of the pre-detection unit using the input terminal of the SDA bus as the clock, and close the clock generation of the detection unit using the input terminal of the SDA bus as the clock through gating logic, while keeping the clock of the detection unit using the input terminal of the SCL bus as the clock enabled.

[0084] The gating logic unit includes a third AND gate device A3 and a fourth AND gate device A4. The first input terminal of the third AND gate device A3 is connected to the output terminal of the second register Q2 after inversion, and the second input terminal is connected to the second input signal. The third AND gate device A3 is used to control the output of the second input signal as the second intermediate clock signal gata_clk2 according to the first clock control signal gc1. The first input terminal of the fourth AND gate device A4 is connected to the output terminal of the fourth register Q4 after inversion, and the second input terminal is connected to the first input signal. The fourth AND gate device A4 is used to control the output of the first input signal as the first intermediate clock signal gata_clk1 according to the second clock control signal.

[0085] As can be seen from the above description, after the first pre-detection subunit 111 and the second pre-detection subunit 112 detect two clock falling edges in the first input signal or the second input signal, they will output a corresponding clock control signal of 1, and the units that do not detect the clock falling edge will output a clock control signal of 0. Through the third AND gate device A3 and the fourth AND gate device A4, the input signal with a clock control signal of 0 is closed, that is, the signal of the SDA bus is closed from being output as an intermediate clock signal to the detection circuit.

[0086] The detection circuit 2 includes a first detection unit 21 and a second detection unit 22 with the same circuit structure.

[0087] The first input terminal of the first detection unit 21 is used to obtain the first input signal data_in1, the second input terminal is used to obtain the first intermediate clock signal gata_clk1, and the reset terminal is used to obtain the reset signal. The first detection unit 21 is configured to perform address matching based on the first input signal data_in1 and the first intermediate clock signal gata_clk1 and output a first address matching signal id_match1. The first input terminal of the second detection unit 22 is used to obtain the second input signal data_in2, the second input terminal is used to obtain the second intermediate clock signal gata_clk2, the reset terminal is used to obtain the reset signal, and is configured to perform address matching based on the second input signal data_in2 and the second intermediate clock signal gata_clk1 and output a second address matching signal id_match2.

[0088] After successful detection, the first detection unit 21 generates a first address matching signal id_match1, which is used to mask the detection work of the second pre-detection subunit 112 and the second detection unit 22 under the current instruction, and selects the correct data input (data_in1) and the clock input terminal (gate_clk1) for subsequent use by the data frame processing unit. After successful detection, the second detection unit 22 generates a second address matching signal id_match2, which is used to mask the detection work of the first pre-detection subunit 111 and the first detection unit 21 under the current instruction, and selects the correct data input (data_in2) and the clock input terminal (gate_clk2) for subsequent use by the signal selection unit 23.

[0089] The reset signal includes a first reset signal and a second reset signal. The first reset signal is used to control the reset of the first pre-detection subunit 111, and the second reset signal is used to control the reset of the second pre-detection subunit 112.

[0090] The sequence detection unit further includes a second OR gate device O2 and a third OR gate device O3; the first input terminal of the second OR gate device O2 is used to obtain the first address matching signal id_match1, the second input terminal is connected to the output terminal of the first OR gate device O1, and the output terminal is used to output the first reset signal; the first input terminal of the third OR gate device O3 is used to obtain the second address matching signal id_match2, the second input terminal is connected to the output terminal of the first OR gate device O1, and the output terminal is used to output the second reset signal.

[0091] The detection circuit 2 further includes a signal selection unit 23; the signal selection unit 23 is connected to the first detection unit 21 and the second detection unit 22, and is configured to select a matching bus clock signal and a bus data signal for output according to the first address matching signal id_match1 and the second address matching signal id_match2.

[0092] The detection circuit of this embodiment is composed of two detection units (the first detection unit and the second detection unit) and a signal selection unit. The clock terminal gate_clk1 of the first detection unit is controlled by the first input port, and the data terminal data_in1 is controlled by the second input port, supporting asynchronous reset of the SSC1 signal and the flag signal of the second detection unit; the clock terminal gate_clk2 of the second detection unit is controlled by the second input port, and the data terminal data_in2 is controlled by the first input port, supporting asynchronous reset of the SSC2 signal and the flag signal of the first detection unit.

[0093] The feature of the detection circuit is that it finally determines the bus relationship of the input port by verifying whether the slave device address of the command frame sent by the current host matches. The slave device addresses include BSID (broadcast address), GSID (group address), and USID (user-defined address), and different USIDs are reserved for the two detection circuits; the first detection unit supports asynchronous reset of the SSC1 signal, and the second detection unit supports asynchronous reset of the SSC2 signal. Therefore, the detection result of the detection circuit is not locked. When the host sends a new instruction, the bus relationship of the input port of the slave device needs to be re-detected, which can achieve real-time detection and improve the accuracy of detection.

[0094] In another alternative embodiment, the detection circuit 2 includes a counter; the counter is configured to count according to the two input signals and the intermediate clock signal, and perform address matching when the count value reaches a preset value to determine the bus relationship, and output the matched signals as the bus data signal and the bus clock signal. For example, the pre-detection circuit requires two clock edges to generate a clock control signal and mask the clock output of another detection unit, but the detection circuit requires 4 intermediate clock signals to generate an address matching signal. Therefore, the preset value can be set to 4. When the counter counts to 4, address matching is performed to determine the correct data signal and intermediate clock signal of the bus relationship and output them. In other alternative embodiments, the preset value can be set to other values according to specific situations.

[0095] The detection circuit further includes a fourth OR gate device O4 and a fifth OR gate device O5. The first input terminal of the fourth OR gate device O4 is connected to the output terminal of the first sequence detection subunit SSC1, and the second input terminal is connected to the first address matching signal id_match1. The fourth OR gate device O4 is configured to control the reset of the first detection unit 21 according to the first reset signal or the first address matching signal. The first input terminal of the fifth OR gate device O5 is connected to the output terminal of the second sequence detection subunit SSC2, and the second input terminal is connected to the second address matching signal id_match2. The fifth OR gate device O5 is configured to control the reset of the second detection unit 22 according to the second reset signal or the second address matching signal.

[0096] In this embodiment, the pre-detection circuit supports the asynchronous reset of the SSC1 signal and the SSC2 signal. The first detection unit supports the SSC1 signal reset, and the second detection unit supports the SSC2 signal reset, so that the bus detection device will re-detect the bus relationship when receiving a new instruction. The advantage of this design is that even if the previous instruction has a bus relationship anomaly check, the new instruction will be re-judged to prevent the slave from being unable to work properly due to mislocking.

[0097] The working process of the above bus relationship detection device will be specifically introduced by way of examples as follows:

[0098] Please refer to Figure 5 , the timing diagram when the SCL bus is connected to the first input port and the SDA bus is connected to the second input port.

[0099] When the SCL bus is connected to the first input port and the SDA bus is connected to the second input port, the host sends a command sequence to the slave. First, the first sequence detection unit SSC1 will detect the start signal SSC of the command sequence and output the reset signal SSC1 as 1, resetting the first pre-detection subunit and the second pre-detection subunit to the state to be detected. Then, the clock terminal of the first pre-detection subunit will first come two falling-edge pulses to make the first input terminal high1 of the first AND gate be 1, and the first clock control signal gc1 is first valid. (When the SSC2 signal is invalid), the valid first clock control signal gc1 will make the D terminal of the second-stage register of the second pre-detection subunit remain 0, thereby making the second clock control signal gc2 invalid, be 0, to achieve a shielding effect. And the inverted valid first clock control signal gc1 is ANDed with the second output port (the port connected to the SDA bus), causing the gate_clk2 (the intermediate clock signal with the SDA bus as the source) signal to be converted to 0 and turn it off. Since the second clock control signal gc2 remains 0 at this time, the gate_clk1 intermediate clock signal (the intermediate clock signal with the SCL bus as the source) is always conducting, enabling the subsequent first detection unit to work normally, while the clock of the second detection unit is turned off, causing the circuit operation to stop.

[0100] Please refer to Figure 6 the timing diagram when the SDA bus is connected to the first input port and the SCL bus is connected to the second input port.

[0101] When the SDA bus is connected to the first input port and the SCL bus is connected to the second input port, the host sends a command sequence to the slave. First, the second sequence detection unit SSC2 will detect the start signal SSC of the command sequence and output a valid reset signal SSC2, resetting the first pre-detection unit and the second pre-detection unit to the state to be detected. Then, the clock terminal of the second pre-detection unit will first come two falling-edge pulses to make high2 and the second clock control signal gc2 valid first (when the SSC1 signal is invalid). The valid second clock control signal gc2 will keep the D terminal of the second-stage register of the first pre-detection unit at 0, thus making the first clock control signal gc1 invalid to play a shielding role. And the inverted valid second clock control signal gc2 is ANDed with the first output port (the port connected to the SDA bus), causing the gate_clk1 (the intermediate clock signal formed by the SDA bus) signal to be converted to 0 and turn it off. Since the gc1 signal remains 0 at this time, the gate_clk2 intermediate clock signal (the intermediate clock signal formed by the SCL bus) is always on, enabling the subsequent second detection unit to work normally, while the clock of the first detection unit is turned off, resulting in the circuit operation stopping.

[0102] It can be seen that the pre-detection circuit of this application is designed according to the frequency characteristics between the SCL bus and the SDA bus. It will pre-identify the relationship of the bus input end and close the clock generation of the detection unit with the SDA bus input end as the clock in the form of gating. Even if the current instruction cannot make a final judgment on the detection circuit, due to the limitation of the number of clocks of the detection unit with the SDA bus input end as the clock for the first two clock edges, it will not generate misdetection operations, ensuring the reliability of the bus relationship detection device.

[0103] The bus relationship detection device of this application uses a combination of a pre-detection circuit and a detection circuit to identify the bus and can realize the function of 2-address expansion. The implementation principle is simple, and the judgment result is accurate and reliable.

[0104] Please refer to Figure 7 the structural schematic diagram of the slave device in an embodiment of this application.

[0105] The slave device of the present application includes the above-mentioned bus relationship detection device 7-1 and the data processing unit 7-2; the first input port is connected to the first input end in the bus relationship detection device 7-1; the second input port is connected to the second input end; the data processing unit 7-2 is connected to the detection circuit 2 in the bus relationship detection device 7-1; the first input port is used to receive a bus clock signal or a bus data signal; the second input port is used to receive a bus data signal or a bus clock signal.

[0106] The bus relationship detection device 7-1 is used to select a matching bus data signal and bus clock signal according to the frequency relationship of the input signals and send them to the data processing unit 7-2; the data processing unit 7-2 is used to process the received bus data signal and bus clock signal.

[0107] Optionally, the slave device includes a MIPI RFFR slave device and other communication slave devices.

[0108] Optionally, the first input port is generally the SCLK terminal in the MIPI RFFE slave device, and the second input port is generally the SDA terminal in the MIPI RFFE slave device.

[0109] The slave device of this embodiment can pre-judge the bus relationship according to the frequency relationship of the bus signals through the above-mentioned bus relationship detection device, and perform address matching judgment according to the detection circuit to determine the final bus relationship, realizing address expansion, with a simple circuit, accurate and reliable judgment result of the bus connection relationship.

[0110] In an optional implementation manner, the data processing unit 7-2 includes a data frame processing unit and a state machine 31 and a register 42; the data frame processing unit and the state machine 41 are connected to the bus relationship detection device 7-1 and are used to receive the commands in the bus data signals and process the commands. Optionally, the commands are RFFE commands or commands specified by other communication protocols.

[0111] The register 42 has its first input end connected to the output end of the data frame processing unit and the state machine 41, and its second input end connected to the detection circuit, and is used to receive the slave device address in the bus data signals and process the slave device address.

[0112] The slave device of this embodiment can determine the bus connection relationship according to the frequency relationship of the input signals, and the judgment result of the bus connection relationship is accurate and reliable.

[0113] Please refer to Figure 8 , the present application also provides a communication system.

[0114] An embodiment of the present application further provides a communication system, including: a master device 8-1, and at least two of the above-mentioned slave devices. In this embodiment, taking the inclusion of a first slave device and a second slave device as an example; the first slave device 8-2 and the second slave device 8-3 are two devices of the same type manufactured by the same manufacturer; wherein, the clock terminal SCLK of the master device 8-1 is respectively connected to the first input port of the first slave device 8-2 and the second input port of the second slave device 8-3, and the data terminal SDA of the master device is respectively connected to the second input port of the first slave device and the first input port of the second slave device. The first input ports of the first slave device 8-2 and the second slave device 8-3 are both clock terminals SCLK, and the second input ports are both data terminals SDA.

[0115] The communication system of this embodiment realizes the address expansion of the slave device by switching the SCL and SDA buses, enabling the master device to distinguish two slave devices with the same USID, PID, and MfrlID, and can accurately and reliably solve the bus conflict problem of two completely identical slave devices in the system. The implemented circuit is simple, and the judgment result of the bus connection relationship is accurate and reliable.

[0116] Optionally, the communication system is a MIPI RFFE system, the master device is a MIPI RFFE master device, and the slave device is a MIPI RFFE slave device. The first MIPI RFFE slave device and the second MIPI RFFE slave device in the MIPI RFFE system are two devices of the same type manufactured by the same manufacturer, that is, the USID, PID, and MID of the two devices are the same; wherein, the clock terminal of the MIPI RFFE master device is respectively connected to the first input port of the first MIPI RFFE slave device and the second input port of the second MIPI RFFE slave device, and the data terminal of the MIPI RFFE master device is respectively connected to the second input port of the first MIPI RFFE slave device and the first input port of the second MIPI RFFE slave device.

[0117] Wherein, the clock terminal (SCLK) of the MIPI RFFE master device is respectively connected to the first input port (SCLK) of the first MIPI RFFE slave device and the second input port (SDA) of the second MIPI RFFE slave device, and the data terminal (SDA) of the MIPI RFFE master device is respectively connected to the second input port (SDA) of the first MIPI RFFE slave device and the first input port (SCLK) of the second MIPI RFFE slave device.

[0118] In the MIPI RFFE system of this embodiment, the address expansion of the slave device is realized by switching the SCL and SDA buses, enabling the MIPI RFFE master device to distinguish between two slave devices with the same USID, PID, and MfrlID. It can accurately and reliably solve the bus conflict problem of two completely identical MIPI RFFE slave devices in the MIPI RFFE system. The implemented circuit is simple, and the judgment result of the bus connection relationship is accurate and reliable.

[0119] This application also provides a radio frequency chip, including a circuit interface constituted by the above-mentioned bus relationship detection device. Through the circuit interface constituted by the above-mentioned bus relationship detection device, the radio frequency chip can realize communication between two devices with the same address, and the communication accuracy is high.

[0120] The above are only the embodiments of this application, and do not limit the patent scope of this application accordingly. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of this application, such as the mutual combination of technical features between various embodiments, or direct or indirect application in other related technical fields, shall be included in the patent protection scope of this application by the same token.

Claims

1. A bus relationship detection device, characterized in that, Comprising: A pre-detection circuit, configured to obtain two input signals through a first input port and a second input port, where the two input signals are a bus clock signal and a bus data signal respectively, and output only the input signal that meets a preset frequency requirement as an intermediate clock signal; A detection circuit, connected to the pre-detection circuit, configured to perform address matching based on the two input signals and the intermediate clock signal to determine a bus relationship, and output the matched bus data signal and bus clock signal; The pre-detection circuit includes a pre-detection unit and a sequence detection unit; the pre-detection unit includes a first pre-detection sub-unit and a second pre-detection sub-unit with the same circuit structure; One of the two input signals is used as a first input signal, and the other is used as a second input signal; The first pre-detection sub-unit, connected to the sequence detection unit, is configured to perform asynchronous reset according to a reset signal, and determine whether the preset frequency requirement is met based on at least one of the number of level changes, the number of falling edges, or the number of rising edges of the first input signal, and output a first clock control signal when it is determined that the preset frequency requirement is met; The second pre-detection sub-unit, connected to the sequence detection unit, is configured to perform asynchronous reset according to the reset signal, and determine whether the preset frequency requirement is met based on at least one of the number of level changes, the number of falling edges, or the number of rising edges of the second input signal, and output a second clock control signal when it is determined that the preset frequency requirement is met.

2. The bus relationship detection device according to claim 1, wherein The pre-detection circuit further includes a gating logic unit; The gating logic unit, connected to the first pre-detection sub-unit and the second pre-detection sub-unit, is configured to select a corresponding input signal as the intermediate clock signal for output according to the first clock control signal and the second clock control signal, and simultaneously turn off the other input signal from being output as the intermediate clock signal.

3. The bus relationship detection device according to claim 2, wherein The sequence detection unit is configured to obtain the input signal through the first input port and the second input port, and output a reset signal after detecting a flag bit in the input signal.

4. The bus relationship detection device according to claim 2, wherein The first pre-detection sub-unit includes at least two registers and a first AND gate device, where at least two registers of the first pre-detection sub-unit include a first register and a second register. The input end of the first register is connected to a high level, the clock end is connected to the first input signal, the reset end is connected to the reset signal, and the output end is connected to the first input end of the first AND gate device. The second input end of the first AND gate device is connected to the inverted second clock control signal after being inverted; The output end of the first AND gate device is connected to the input end of the second register. The clock end of the second register is connected to the first input signal, the reset end is connected to the reset signal, and the output end is used to output the first clock control signal; The second pre-detection subunit includes at least two registers and a second AND gate device. At least two registers of the second pre-detection subunit include a third register and a fourth register. The input end of the third register is connected to a high level, the clock end is connected to the second input signal, the reset end is connected to the reset signal, and the output end is connected to the first input end of the second AND gate device. The second input end of the second AND gate device is connected to the first clock control signal after being inverted. The output end of the second AND gate device is connected to the input end of the fourth register. The clock end of the fourth register is connected to the second input signal, the reset end is connected to the reset signal, and the output end is used to output the second clock control signal.

5. The bus relationship detection device according to claim 4, characterized in that, The flag bit is a sequence start condition flag bit. The sequence detection unit includes a first sequence detection subunit, a second sequence detection subunit, and a first OR gate device. The first sequence detection subunit is configured to output a first intermediate reset signal to the first input end of the first OR gate device after detecting the sequence start condition flag bit in the second input signal. The second sequence detection subunit is configured to output a second intermediate reset signal to the second input end of the first OR gate device after detecting the sequence start condition flag bit in the first input signal. The first OR gate device is configured to output the reset signal according to the first intermediate reset signal and the second intermediate reset signal.

6. The bus relationship detection device according to claim 5, wherein, The gating logic unit includes a third AND gate device and a fourth AND gate device. The first input end of the third AND gate device is connected to the output end of the second register after being inverted, and the second input end is connected to the second input signal. The third AND gate device is configured to control the second input signal to be output as a second intermediate clock signal according to the first clock control signal. The first input end of the fourth AND gate device is connected to the output end of the fourth register after being inverted, and the second input end is connected to the first input signal. The fourth AND gate device is configured to control the first input signal to be output as a first intermediate clock signal according to the second clock control signal.

7. The bus relationship detection device according to claim 6, wherein, The detection circuit includes a first detection unit and a second detection unit. The first input end of the first detection unit is used to obtain the first input signal, the second input end is used to obtain the first intermediate clock signal, and the reset end is used to obtain the reset signal. The first detection unit is configured to perform address matching according to the first input signal and the first intermediate clock signal and output a first address matching signal. The first input end of the second detection unit is used to obtain the second input signal, the second input end is used to obtain the second intermediate clock signal, the reset end is used to obtain the reset signal, and is configured to perform address matching according to the second input signal and the second intermediate clock signal and output a second address matching signal.

8. The bus relationship detection device according to claim 7, characterized in that, The detection circuit further includes a signal selection unit. The signal selection unit is connected to the first detection unit and the second detection unit, and is configured to select and output a matching bus clock signal and bus data signal according to the first address matching signal and the second address matching signal.

9. The bus relationship detection device according to claim 7, characterized in that The reset signal includes a first reset signal and a second reset signal. The first reset signal is used to control the reset of the first pre-detection sub-unit, and the second reset signal is used to control the reset of the second pre-detection sub-unit; The sequence detection unit further includes a second OR gate device and a third OR gate device; The first input end of the second OR gate device is used to obtain the first address matching signal, the second input end is connected to the output end of the first OR gate device, and the output end is used to output the first reset signal; The first input end of the third OR gate device is used to obtain the second address matching signal, the second input end is connected to the output end of the first OR gate device, and the output end is used to output the second reset signal.

10. The bus relationship detection device according to claim 1, characterized in that, The detection circuit includes a counter; The counter is used to count according to the two input signals and the intermediate clock signal, perform address matching when the count value reaches a preset value to determine the bus relationship, and output the matched signals as the bus data signal and the bus clock signal.

11. An accessory device, characterized in that, Comprising: The bus relationship detection device and the data processing unit according to any one of claims 1-10; The bus relationship detection device is used to select the matching bus data signal and bus clock signal according to the frequency relationship of the input signals and send them to the data processing unit; The data processing unit is connected to the bus relationship detection device and is used to process the received bus data signal and bus clock signal.

12. The slave device according to claim 11, wherein The data processing unit includes a data frame processing unit, a state machine and a register module; The data frame processing unit and the state machine are connected to the bus relationship detection device and are used to receive the commands in the bus data signal and process the commands; The register, the first input end is connected to the output end of the data frame processing unit and the state machine, and the second input end is connected to the detection circuit. It is used to receive the slave device address in the bus data signal and process the slave device address.

13. A communication system, characterized in that, Comprising: A master device and at least two slave devices according to claim 11 or 12; The first slave device and the second slave device are two devices of the same type manufactured by the same manufacturer; Wherein, the clock terminal of the master device is respectively connected to the first input port of the first slave device and the second input port of the second slave device, and the data terminal of the master device is respectively connected to the second input port of the first slave device and the first input port of the second slave device.

14. A radio frequency chip, characterized in that, Comprising a circuit interface composed of the bus relationship detection device according to any one of claims 1-10.

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