A Hardware Implementation Method for Reservoir Computing Networks

Abstract

The present invention discloses a hardware implementation method for a reservoir computing network. This method realizes the mask layer, reservoir layer, and readout layer of the reservoir computing network only through ferroelectric transistors. The mask layer, reservoir layer, and readout layer are all composed of multiple ferroelectric transistors. The gates of the ferroelectric transistors in the mask layer are connected to triangular pulses, the sources of the ferroelectric transistors in the mask layer are connected to the input voltage, the mask layer is fully connected to the reservoir layer, the gates of the ferroelectric transistors in the reservoir layer and the readout layer are both connected to the preset voltage, the reservoir layer is connected to the readout layer one by one, and the drains of all the ferroelectric transistors in the readout layer are connected in series. The current output by the connected drains is the output of the reservoir computing network. The mask layer utilizes the non-volatile storage characteristics and randomness of the ferroelectric transistors to realize the function of the mask layer. Based on the regulation of the channel current by the gates of the ferroelectric transistors, the collection of node states and the adjustment of weights are realized.

Description

Technical Field

[0001] The present invention relates to a method for implementing a reservoir computing network, belonging to the field of hardware implementation of neural networks. Background Art

[0002] An artificial neural network is a non-linear and adaptive information processing system composed of a large number of interconnected processing units. By logically processing and non-linearly transmitting information, it mimics the operation process of the human brain neural network, thus promising to completely solve the efficiency bottleneck encountered by the traditional von Neumann computing architecture. Among numerous artificial neural networks, the reservoir computing network is an artificial neural network suitable for processing time series signals. By adding virtual nodes to the time series signals, the demand for the number of devices in hardware implementation is significantly reduced, and it has great advantages in terms of computing speed, operating power consumption, etc. Traditional reservoir computing consists of an input layer, a reservoir layer, and an output layer. The input time series signal enters the reservoir from the input layer and undergoes high-dimensional and non-linear changes in the reservoir layer. The training process is only reflected in the weight iteration from the reservoir layer to the output layer, thereby realizing basic tasks of artificial intelligence such as classification and prediction of target signals.

[0003] In the hardware implementation of the reservoir computing network, in order to improve the energy efficiency ratio of the artificial network, on the one hand, the number of devices can be increased to enhance non-linear physical nodes, and on the other hand, according to the non-linear characteristics of physical nodes, virtual nodes can be formed on the delay feedback loop of the time series signal to improve the performance of the reservoir computing network. The hardware implementation of this reservoir computing network usually includes three parts: mask preprocessing, collecting node states in the reservoir, and readout postprocessing. The two processes of mask preprocessing and readout postprocessing are usually implemented through software simulation or based on different non-volatile memories respectively, which brings inconvenience to the hardware integration of the reservoir computing network. Therefore, a hardware implementation method based on the same device and covering all functions of the reservoir computing network is very necessary.

[0004] Figure 1 The schematic diagrams of the traditional reservoir computing network architecture and the hardware implementation of the reservoir computing network are given. For unit devices, they can be two-terminal devices such as memristors, or three-terminal / four-terminal devices such as transistors. However, the mask layer and the output layer are usually implemented in a computer or through different devices respectively. This brings difficulties to the hardware integration of reservoir computing. Summary of the Invention

[0005] Aiming at the problems in the hardware implementation process of the reservoir computing network, such as usually requiring different types of devices and a large number of devices, the present invention provides a hardware implementation method for the reservoir computing network, which uses a single ferroelectric transistor to implement the reservoir computing network, being simple, efficient, and easy to integrate.

[0006] To solve the above-mentioned technical problem, the technical solution adopted by the present invention is as follows: A hardware implementation method for a reservoir computing network. This method realizes the mask layer, reservoir layer, and readout layer of the reservoir computing network only through ferroelectric transistors. The mask layer, reservoir layer, and readout layer are all composed of multiple ferroelectric transistors, and the number of ferroelectric transistors in the reservoir layer is equal to the number of ferroelectric transistors in the readout layer. The gates of the ferroelectric transistors in the mask layer are connected to triangular pulses, the sources of the ferroelectric transistors in the mask layer are connected to the input voltage, and the mask layer is fully connected to the reservoir layer, that is, the drains of each ferroelectric transistor in the mask layer are connected to the sources of all the transistors in the reservoir layer. The gates of the ferroelectric transistors in the reservoir layer and the readout layer are both connected to a preset voltage. The reservoir layer is connected to the readout layer one by one, that is, the drain of each ferroelectric transistor in the reservoir layer is only connected to the source of a single and non-repeating ferroelectric transistor in the readout layer. The drains of all the ferroelectric transistors in the readout layer are connected in series, and the current output from the connected drains is the output of the reservoir computing network. The mask layer utilizes the non-volatile storage characteristics and randomness of ferroelectric transistors to realize the function of the mask layer. Based on the regulation of the channel current by the gate of the ferroelectric transistor, the collection of node states and the adjustment of weights are realized.

[0007] Further, voltages are applied to the gates and sources of the ferroelectric transistors in the mask layer simultaneously, causing the domain structure of the hafnium zirconium oxide layer of the ferroelectric transistors in the mask layer to undergo polarization reversal. Different domain parts of the hafnium zirconium oxide layer of the ferroelectric transistors are reversed, enabling different ferroelectric transistors to output different currents, thereby realizing a multi-valued mask result.

[0008] Further, the timing response characteristic of the reservoir layer is that during consecutive multiple read pulses, the response current gradually decreases.

[0009] Further, the duration of the voltage applied to the reservoir layer determines the number of virtual nodes. The longer the voltage duration, the more virtual nodes there are. The sampling interval uses a fixed time, with an order of magnitude in the range of 10 ns to 100 μs.

[0010] Further, within one voltage cycle, as the gate voltage of the readout layer changes, the change in the drain current exceeds two orders of magnitude.

[0011] Further, within one voltage cycle, the change in the gate voltage of the readout layer is from 0 V to 3 V, the change range of the drain current is from 1*10 -8 mA to 1*10 -4 mA, and the change range of the switching ratio is from 1 to 400.

[0012] Further, the training process of the reservoir computing network is as follows: The gate of the readout layer is adjusted to the required storage state in advance, and a threshold voltage is applied during the recognition process to ensure the readout effect of the weights.

[0013] Further, when this method is used for classification, the mask layer requires more than 4 ferroelectric transistors, the reservoir layer and the readout layer require more than 7 ferroelectric transistors, and the operation time is between 70 ns and 1 ms.

[0014] Advantages of the present invention: The present invention realizes the reservoir computing network only through ferroelectric transistors, greatly reducing the problem of a large number of devices in the hardware implementation process of the reservoir. Through various usage methods of ferroelectric transistors, the integration difficulty of the hardware is reduced. Description of the Drawings

[0015] Figure 1 Schematic diagram of a traditional hardware implementation of a reservoir computing network;

[0016] Figure 2 Schematic diagram of the hardware array circuit of the reservoir computing network in Embodiment 1;

[0017] Figure 3 Schematic diagram of the current fluctuation between different devices when the ferroelectric transistor is used as the mask layer;

[0018] Figure 4 Schematic diagram of the current response characteristics required for the ferroelectric transistor as the reservoir layer;

[0019] Figure 5 Schematic diagram of the change range of different weights when the ferroelectric transistor is used as the readout layer;

[0020] Figure 6 Flowchart of the reservoir computing network for image recognition;

[0021] Figure 7 Schematic diagram of the recognition accuracy of ten digital images by the reservoir computing network based on ferroelectric transistors at different reservoir device numbers and different operation times;

[0022] Figure 8 Schematic diagram of the classification results of pictures of five human activity behaviors through 10 reservoir devices and an operation time of 100 ns. Detailed Embodiments

[0023] The present invention will be further described below in conjunction with the drawings and specific embodiments.

[0024] Embodiment 1

[0025] This embodiment discloses a hardware implementation of a reservoir computing network. This method realizes the mask layer, reservoir layer and readout layer of the reservoir computing network only through ferroelectric transistors, as Figure 2As shown, the mask layer, the reservoir layer, and the readout layer are all composed of multiple ferroelectric transistors, and the number of ferroelectric transistors in the reservoir layer is equal to the number of ferroelectric transistors in the readout layer; the gates of the ferroelectric transistors in the mask layer are connected to triangular pulses, the sources of the ferroelectric transistors in the mask layer are connected to the input voltage, and the mask layer is fully connected to the reservoir layer, that is, the drain of each ferroelectric transistor in the mask layer is connected to the sources of all the transistors in the reservoir layer. The gates of the ferroelectric transistors in the reservoir layer and the readout layer are both connected to the preset voltage. The reservoir layer is connected to the readout layer one by one, that is, the drain of each ferroelectric transistor in the reservoir layer is only connected to the source of a single and non-repeating ferroelectric transistor in the readout layer. The drains of all the ferroelectric transistors in the readout layer are connected in series, and the current output from the connected drains is the output of the reservoir computing network; the mask layer utilizes the non-volatile storage characteristics and randomness of the ferroelectric transistors to realize the function of the mask layer. Based on the regulation of the channel current by the gate of the ferroelectric transistor, the collection of node states and the adjustment of weights are realized.

[0026] Figures 3 - 5 The electrical characteristics of the ferroelectric transistor are given, corresponding to the functions of each layer in the computing network in the reservoir respectively. Figure 3 It is a schematic diagram of the current fluctuation between different devices when the ferroelectric transistor is used as the mask layer. It can be seen from Figure 3 that the output current of the ferroelectric transistor as the mask layer varies greatly between different devices, and this variation can suppress the influence brought by noise to a certain extent. This characteristic is caused by the randomness of the ferroelectric transistor. The randomness comes from the characteristics of the domain structure of the hafnium zirconium oxide layer of the ferroelectric transistor, that is, when voltages are applied to the gate and source of the ferroelectric transistor in the mask layer at the same time, the domain structure of the hafnium zirconium oxide layer of the ferroelectric transistor in the mask layer undergoes polarization reversal, and different domain parts of the hafnium zirconium oxide layer of the ferroelectric transistor are reversed, causing different ferroelectric transistors to output different currents, thereby realizing a multi-valued mask result.

[0027] Figure 4 It shows that the required timing response characteristic of the ferroelectric transistor as the reservoir layer is that during multiple consecutive read pulses, the response current gradually decreases. This represents the change effect of short-term memory and meets the requirements of the reservoir computing network.

[0028] At the same time Figure 4 it also shows that the duration of the voltage applied to the reservoir layer determines the number of virtual nodes. The longer the voltage duration, the more virtual nodes. The sampling interval uses a fixed time, with an order of magnitude in the range of 10 ns to 100 μs.

[0029] Figure 5 It represents the weight change range of the ferroelectric transistor as the output layer. It can be seen from Figure 5 that within one voltage cycle, as the gate voltage of the readout layer changes, the change in the drain current exceeds two orders of magnitude, which can comprehensively represent the weight changes during the training process.

[0030] Specifically, within one voltage cycle, the change in the gate voltage of the readout layer ranges from 0V to 3V, and the change in the drain current ranges from 1*10 -8 mA to 1*10 -4 mA, and the change in the switching ratio ranges from 1 to 400.

[0031] Figure 6 The flowchart shows the pattern recognition process using a reservoir computing circuit built with ferroelectric transistors. First, the input timing signal is classified. If it is during the training process, it will be processed through the mask layer and the reservoir layer and then compared with the reference value to adjust the weights of the readout layer. If it is not the training process, it is necessary to determine whether it is the recognition process. If not, then it will end directly. If it is the recognition process, the data will pass through the mask layer and the reservoir layer, and then be processed by the readout weights obtained from the training process, and finally the recognition result can be obtained.

[0032] Figure 7 The recognition accuracy of ten digital images based on the reservoir computing network built with ferroelectric transistors is given under different numbers of reservoir devices and different operation times. Among them, when the number of reservoir devices and the operation time are 10 and 80ns, and 9 and 90ns or more respectively, the accuracy can reach over 95%. When the operation time increases or the number of devices in the reservoir layer increases, the accuracy can be further improved, or the ability to handle complex problems can be enhanced.

[0033] Figure 8 It shows the classification results of five types of human activity behavior pictures through 10 reservoir devices and an operation time of 100ns. Through the t-distributed stochastic neighbor embedding method, the five types of human activity behaviors are intuitively distinguished, achieving good classification results.

[0034] This embodiment utilizes the randomness of ferroelectric domains during the polarization reversal process of the hafnium zirconium oxide layer to achieve the function of the mask layer, and there are significant fluctuations in different devices, improving the masking effect. Based on the regulation of the channel current by the ferroelectric transistor gate, the collection of node states and the adjustment of weights are achieved. The mask layer realizes a certain degree of randomness through the flipping of ferroelectric domains in the hafnium zirconium oxide layer. The reservoir layer uses random initial states to achieve different fixed values in the reservoir. The readout layer achieves the effect of weight change through gate regulation. The mask layer is fully connected to the reservoir layer, greatly reducing the number of devices required in the hardware implementation process. The reservoir layer is connected to the readout layer one-to-one to represent the weights obtained during the training process.

[0035] During the training process, the required weights are written in advance through the gates, and a preset voltage is applied during the recognition process to ensure the reading effect of the weights. The drains of the ferroelectric transistors in the readout layer are connected in series, and the sum of the currents is the recognition result of the final result.

[0036] The reservoir computing network implemented by this method can be used for image recognition and image classification. For a simple classification process, the required devices are: more than 4 ferroelectric transistors in the mask layer and more than 7 ferroelectric transistors in the reservoir layer, and its operation time is in the range of 70 ns to 1 ms. It can be seen that the number of required devices is small and the implementation is relatively simple.

[0037] The above description is only the basic principle and preferred embodiments of the present invention. The improvements and replacements made by those skilled in the art based on the present invention belong to the protection scope of the present invention.

Claims

1. A hardware implementation method for a reservoir computing network, characterized in that: This method only uses ferroelectric transistors to implement the mask layer, reservoir layer and readout layer of the reservoir computing network. The mask layer, reservoir layer and readout layer are all composed of multiple ferroelectric transistors, and the number of ferroelectric transistors in the reservoir layer is equal to the number of ferroelectric transistors in the readout layer; the gates of the ferroelectric transistors in the mask layer are connected to triangular pulses, the sources of the ferroelectric transistors in the mask layer are connected to the input voltage, and the mask layer is fully connected to the reservoir layer, that is, the drain of each ferroelectric transistor in the mask layer is connected to the sources of all the transistors in the reservoir layer. The gates of the ferroelectric transistors in the reservoir layer and the readout layer are both connected to the preset voltage. The reservoir layer is connected to the readout layer one by one, that is, the drain of each ferroelectric transistor in the reservoir layer is only connected to the source of a single and non-repeating ferroelectric transistor in the readout layer. The drains of all the ferroelectric transistors in the readout layer are connected in series, and the current output from the connected drains is the output of the reservoir computing network; the mask layer uses the non-volatile storage characteristics and randomness of ferroelectric transistors to realize the function of the mask layer. Based on the regulation of the channel current by the gate of the ferroelectric transistor, the collection of node states and the adjustment of weights are realized; By applying voltages to the gates and sources of the ferroelectric transistors in the mask layer simultaneously, the domain structure of the hafnium zirconium oxide layer of the ferroelectric transistors in the mask layer is polarized and reversed. Different domain parts of the hafnium zirconium oxide layer of the ferroelectric transistors are reversed, so that different ferroelectric transistors output different currents, thereby realizing a multi-valued mask result.

2. The hardware implementation method for a reservoir computing network according to claim 1, characterized in that: The timing response characteristic of the reservoir layer is that during consecutive multiple read pulses, the response current gradually decreases.

3. The hardware implementation method for a reservoir computing network according to claim 1, characterized in that: The duration of the voltage applied to the reservoir layer determines the number of virtual nodes. The longer the voltage duration, the more virtual nodes. The sampling interval uses a fixed time, with an order of magnitude between 10 ns and 100 μs.

4. The hardware implementation method for a reservoir computing network according to claim 1, characterized in that: Within one voltage cycle, as the gate voltage of the readout layer changes, the change in the drain current exceeds two orders of magnitude.

5. The hardware implementation method for a reservoir computing network according to claim 4, characterized in that: Within one voltage cycle, the change in the gate voltage of the readout layer is from 0 V to 3 V, the change range of the drain current is from 1×10⁻⁸ mA to 1×10⁻⁴ mA, and the change range of the switching ratio is from 1 to 400.

6. The hardware implementation method for a reservoir computing network according to claim 1, characterized in that: The training process of the reservoir computing network is: the gate of the readout layer is adjusted in advance to the required storage state, and a threshold voltage is applied during the recognition process to ensure the reading effect of the weights.

7. The hardware implementation method for a reservoir computing network according to claim 1, characterized in that: When this method is used for classification, the mask layer requires more than 4 ferroelectric transistors, the reservoir layer and the readout layer require more than 7 ferroelectric transistors, and the operation time is between 70 ns and 1 ms.

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