Display driving module, display driving method and display device

Abstract

The present invention provides a display driving module, a display driving method and a display device. The display driving module includes a clock signal line, a clock signal generating circuit and a gate driving circuit, wherein the gate driving circuit includes a multi-stage gate driving unit; the clock signal generating circuit is electrically connected to the clock signal line, and is used to generate at least two clock signals, and provide different clock signals to the clock signal line in a time-sharing manner; the gate driving unit is electrically connected to the clock signal line, and is used to generate a gate driving signal according to the clock signal on the clock signal line; when the potential of the clock signal is an effective voltage, the potentials of different clock signals are different. The present invention solves the problem in the prior art that the charging rates of different rows of pixel circuits on the display panel are uneven, which leads to insufficient charging of the remote pixel circuits of the display panel, and the occurrence of bad horizontal stripes.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display driving module, a display driving method and a display device. Background Art

[0002] In the related art, display panels are getting bigger and bigger, and the resolution is getting higher and higher. As the screen size of the display panel increases and the resolution increases, the load in the display panel also increases. Under heavy load conditions, the gate drive signal will be significantly attenuated at the far end, seriously affecting the far-end charging rate and the charging uniformity in the display panel. Low far-end charging rate will lead to insufficient charging of the far-end pixel circuit, resulting in dark far-end pixels included in the display panel and uneven display of the display panel.

[0003] At the same time, due to the parasitic capacitance of the pixel circuit in the effective display area of ​​the display panel, when the display panel is displaying normally, the data voltage on the data line will keep jumping, and the gate drive signal on the gate line will also jump between high and low voltages. These voltage jumps will produce parasitic capacitance coupling and cause horizontal stripes. Summary of the invention

[0004] The main purpose of the present invention is to provide a display driving module, a display driving method and a display device to solve the problem in the prior art that the charging rates of different rows of pixel circuits on the display panel are uneven, resulting in insufficient charging of the far-end pixel circuits of the display panel and the occurrence of horizontal stripes.

[0005] In order to achieve the above object, the present invention provides a display driving module, including a clock signal line, a clock signal generating circuit and a gate driving circuit, wherein the gate driving circuit includes a multi-stage gate driving unit;

[0006] The clock signal generating circuit is electrically connected to the clock signal line, and is used to generate at least two clock signals, and provide different clock signals to the clock signal line in a time-sharing manner;

[0007] The gate driving unit is electrically connected to the clock signal line, and is used to generate a gate driving signal according to the clock signal on the clock signal line;

[0008] When the potential of the clock signal is an effective voltage, different clock signals have different potentials.

[0009] Optionally, the gate driving unit is used to transmit the gate driving signal to a pixel circuit included in the display panel;

[0010] The transistor whose control electrode in the pixel circuit is connected to the gate drive signal is an n-type transistor, and the effective voltage is a high voltage; or

[0011] The transistor whose control electrode in the pixel circuit is connected to the gate driving signal is a p-type transistor, and the effective voltage is a low voltage.

[0012] Optionally, the clock signal generating circuit includes a timing controller, a voltage generating subcircuit, a control subcircuit and a clock signal generating subcircuit, wherein:

[0013] The voltage generating subcircuit is used to generate an invalid voltage signal and at least two valid voltage signals, and provide the invalid voltage signal to the clock signal generating subcircuit;

[0014] The timing controller is used to provide a control signal to the control subcircuit through a control signal terminal, and to provide an input clock signal to the clock signal generation subcircuit through an input clock signal terminal;

[0015] The control subcircuit is electrically connected to the control signal terminal and the voltage generating subcircuit respectively, and is used for controlling, under the control of the control signal, to provide a corresponding valid voltage signal of the at least two valid voltage signals to the clock signal generating subcircuit;

[0016] The clock signal generating subcircuit is electrically connected to the timing controller, the control subcircuit and the clock signal line respectively, and is used to generate a corresponding clock signal according to the input clock signal, the invalid voltage signal and the corresponding valid voltage signal, and provide the clock signal to the clock signal line.

[0017] Optionally, the voltage generating subcircuit is used to generate a first effective voltage signal and a second effective voltage signal, and output the first effective voltage signal through a first output terminal, and output the second effective voltage signal through a second output terminal;

[0018] The control subcircuit includes a first control transistor and a second control transistor;

[0019] The control electrode of the first control transistor is electrically connected to the control signal terminal, the first electrode of the first control transistor is electrically connected to the first output terminal, and the second electrode of the first control transistor is electrically connected to the clock signal generating circuit;

[0020] The control electrode of the second control transistor is electrically connected to the control signal terminal, the first electrode of the second control transistor is electrically connected to the second output terminal, and the second electrode of the second control transistor is electrically connected to the clock signal generating circuit.

[0021] Optionally, the voltage generation subcircuit includes a power management integrated circuit;

[0022] The power management integrated circuit includes at least three voltage conversion circuits;

[0023] One of the at least three voltage conversion circuits is used to convert the first predetermined voltage signal into the invalid voltage signal;

[0024] At least two voltage conversion circuits among the at least three voltage conversion circuits are used to convert the second predetermined voltage signal into corresponding effective voltage signals respectively.

[0025] Optionally, the voltage generation subcircuit includes a power management integrated circuit and a voltage generation integrated circuit;

[0026] The power management integrated circuit is used to generate the invalid voltage signal and the first valid voltage signal;

[0027] The voltage generating integrated circuit is used to convert the third predetermined voltage signal into the corresponding at least one effective voltage signal.

[0028] An embodiment of the present invention further provides a display driving method, which is applied to the above-mentioned display driving module, and the display driving method includes:

[0029] The clock signal generating circuit generates at least two clock signals and provides different clock signals to the clock signal line in a time-sharing manner;

[0030] The gate driving unit generates a gate driving signal according to the clock signal on the clock signal line;

[0031] When the potential of the clock signal is an effective voltage, different clock signals have different potentials.

[0032] Optionally, the gate driving circuit is used to transmit the gate driving signal to the pixel circuit included in the display panel through the gate line included in the display panel, the clock signal generating circuit is arranged on the first side of the display panel, the second side is the side opposite to the first side, the clock signal line extends from the first side to the second side, and the extension direction of the gate line intersects with the extension direction of the clock signal line; the effective display area of ​​the display panel is divided into B display areas in sequence along the extension direction of the clock signal line; B is an integer greater than 1; the display driving method comprises:

[0033] When the gate driving circuit provides a gate driving signal to the gate line in the bth display area, the clock signal generating circuit provides a bth clock signal to the clock signal line; b is a positive integer less than or equal to B;

[0034] When the potential of the ath clock signal and the potential of the a+1th clock signal are effective voltages, the absolute value of the potential of the a+1th clock signal is greater than the absolute value of the potential of the ath clock signal; a is a positive integer less than B.

[0035] Optionally, the gate driving circuit is used to transmit the gate driving signal to the pixel circuit included in the display panel through the gate line included in the display panel, and the pixel circuits in the same row included in the display panel are electrically connected to the corresponding row of gate lines; the display driving method also includes:

[0036] When horizontal stripes appear on the display screen of the display panel,

[0037] When the gate driving circuit provides a gate driving signal for the gate line in the display area corresponding to the brighter horizontal stripes, the clock signal generating circuit provides a first clock signal to the clock signal line; when the gate driving circuit provides a gate driving signal for the gate line in the display area corresponding to the darker horizontal stripes, the clock signal generating circuit provides a second clock signal to the clock signal line;

[0038] When the potential of the first clock signal and the potential of the second clock signal are effective voltages, the absolute value of the potential of the first clock signal is smaller than the absolute value of the potential of the second clock signal.

[0039] An embodiment of the present invention further provides a display device, comprising the above-mentioned display driving module.

[0040] The display driving module, display driving method and display device described in the embodiments of the present invention can improve the charging rate of the remote pixel circuit by providing a clock signal with a higher absolute value of the effective voltage to the remote gate driving unit, effectively improve the phenomenon of insufficient charging of the remote pixel circuit in the display panel, and improve the phenomenon of bad horizontal stripes. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a structural diagram of a display driving module according to at least one embodiment of the present invention;

[0042] Figure 2 is a schematic diagram of the positional relationship among the display panel 20, the driving integrated circuit 21 and the gate driving circuit 12;

[0043] Figure 3 is a circuit diagram of at least one embodiment of the gate driving unit;

[0044] Figure 4 is a circuit diagram of at least one embodiment of a clock signal generating circuit in a display driving module according to an embodiment of the present invention;

[0045] Figure 5 It is the waveform diagram of CLK0 and the waveform diagram of CLK;

[0046] Figure 6 is a circuit diagram of at least one embodiment of the clock signal generating circuit;

[0047] Figure 7 Yes Figure 6 An operating timing diagram of at least one embodiment of the clock signal generating circuit shown. DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] The transistors used in all embodiments of the present invention may be triodes, thin film transistors, field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, in order to distinguish the two electrodes of the transistor except the control electrode, one of the electrodes is called the first electrode and the other is called the second electrode.

[0050] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0051] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.

[0052] like Figure 1 As shown, the display driving module according to the embodiment of the present invention includes a clock signal line K1, a clock signal generating circuit 11 and a gate driving circuit 12, wherein the gate driving circuit 12 includes a multi-stage gate driving unit;

[0053] The clock signal generating circuit 11 is electrically connected to the clock signal line K1, and is used to generate at least two clock signals, and provide different clock signals to the clock signal line K1 in a time-sharing manner;

[0054] The gate driving unit in the gate driving circuit 12 is electrically connected to the clock signal line K1, and is used to generate a gate driving signal according to the clock signal on the clock signal line K1;

[0055] When the potential of the clock signal is an effective voltage, different clock signals have different potentials.

[0056] When the display driving module described in the embodiment of the present invention is working, different clock signals can be provided to the clock signal line K1 in time-sharing manner through the clock signal generating circuit 11, and the gate driving unit in the gate driving circuit 12 can generate different gate driving signals according to different clock signals.

[0057] In the embodiment of the present invention, when the potential of the clock signal is an effective voltage, different clock signals have different potentials, so that when the potential of the gate drive signal generated by the gate drive circuit 12 is an effective voltage, the potential of the gate drive signal is different.

[0058] For example, when the effective voltage is a high voltage and the clock signal generating circuit 11 generates a first clock signal and a second clock signal, the high voltage value of the first clock signal is not equal to the high voltage value of the second clock signal.

[0059] In at least one embodiment of the present invention, when the effective voltage is a high voltage,

[0060] When the potential of the first clock signal and the potential of the second clock signal are high voltages, the potential of the first clock signal (that is, the high voltage value of the first clock signal) may be 27V, and the potential of the second clock signal (that is, the high voltage value of the second clock signal) may be 34V; the first clock signal may be provided to a proximal gate driving unit, and the second clock signal may be provided to a distal gate driving unit;

[0061] When the potential of the first clock signal and the potential of the second clock signal are low voltages, the potential of the first clock signal and the potential of the second clock signal may both be -7V.

[0062] In related technologies, such as Figure 2 As shown, a driving integrated circuit 21 may be provided on the lower side of the display panel 20; the driving integrated circuit 21 may include a data driving circuit and a clock signal generating circuit, wherein the clock signal generating circuit may include a timing controller, a power management integrated circuit and a clock signal generating sub-circuit; the data driving circuit is used to drive the data lines ( Figure 2 (not shown) provides a data voltage, and the clock signal generating circuit is used to provide a clock signal for the clock signal line K1;

[0063] The clock signal line K1 and the gate drive circuit can be arranged on the left side and / or the right side of the display panel. Figure 2 In at least one embodiment shown, the clock signal line K1 and the gate driving circuit 12 are arranged on the right side of the display panel as an example;

[0064] exist Figure 2Among them, the area labeled A0 is the effective display area of ​​the display panel;

[0065] The display panel 20 includes a plurality of rows of gate lines arranged horizontally and a plurality of columns of data lines arranged vertically, and the clock signal line K1 is also arranged vertically;

[0066] The gate driving circuit includes a plurality of gate driving units which are arranged in sequence along the longitudinal direction;

[0067] exist Figure 2 In the figure, the first-stage gate driving unit included in the gate driving circuit 12 is labeled S1, the second-stage gate driving unit included in the gate driving circuit 12 is labeled S2, the third-stage gate driving unit included in the gate driving circuit 12 is labeled S3, the N-th stage gate driving unit included in the gate driving circuit 12 is labeled SN, the N+1-th stage gate driving unit included in the gate driving circuit 12 is labeled SN+2, the N+2-th stage gate driving unit included in the gate driving circuit is labeled SN+1, the N+2-th stage gate driving unit included in the gate driving circuit is labeled SM-1, and the M-1-th stage gate driving unit is labeled SM; wherein N is an integer greater than 3, and M is an integer greater than 7;

[0068] Each level of gate driving unit is electrically connected to the clock signal line K1, and each level of gate driving unit generates a corresponding gate driving signal according to the clock signal on the clock signal line K1;

[0069] The lower end of the clock signal line K1 is electrically connected to the clock signal generating circuit in the driving integrated circuit 21, and due to the load in the display panel, the absolute value of the voltage value of the effective voltage corresponding to the gate driving signal output by the remote gate driving unit will be reduced, resulting in a low charging rate of the remote pixel circuit. The display driving module described in the embodiment of the present invention can provide a clock signal with a higher absolute value of the voltage value of the effective voltage to the remote gate driving unit to improve the charging rate of the remote pixel circuit, which can solve the problem of uneven charging at the far and near ends, and effectively improve the phenomenon of insufficient charging of the remote pixel circuit included in the large-size display panel.

[0070] In at least one embodiment of the present invention, the voltage value of the effective voltage corresponding to the gate driving signal refers to: when the potential of the gate driving signal is the effective voltage, the potential of the gate driving signal.

[0071] For example, when the effective voltage is a high voltage, assuming that when the gate driving signal is an effective voltage signal, when the potential of the gate driving signal is 34V, the voltage value of the effective voltage corresponding to the gate driving signal is 34V.

[0072] In at least one embodiment of the present invention, the clock signal having an effective voltage with a relatively high absolute value means that when the potential of the clock signal is the effective voltage, the potential of the clock signal is relatively high.

[0073] In at least one embodiment of the present invention, a remote pixel circuit refers to a pixel circuit that is far away from the driver integrated circuit 21, and a remote gate driving unit refers to a gate driving unit that provides a gate driving signal to the remote pixel circuit; a proximal pixel circuit refers to a pixel circuit that is close to the driver integrated circuit 21, and a proximal gate driving unit refers to a gate driving unit that provides a gate driving signal to the proximal pixel circuit.

[0074] exist Figure 2 In the illustrated embodiment, S1, S2 and S3 may be remote gate drive units, and SM-1 and SM may be near-end gate drive units.

[0075] In the relevant display device, due to the presence of parasitic capacitance in the pixel circuit in the effective display area of ​​the display panel, when the display panel is in normal display, the data voltage on the data line will keep jumping, and the gate drive signal on the gate line will also jump between high and low voltages. These voltage jumps will produce parasitic capacitance coupling. At the same time, there is inevitably an ITO (indium tin oxide) Shift phenomenon in the screen, which may cause horizontal stripes. The horizontal stripes may refer to: light and dark horizontal stripes appear in at least part of the display area in the effective display area; the extension direction of the horizontal stripes is roughly the same as the extension direction of the gate line.

[0076] At least one embodiment of the present invention can improve the horizontal stripe defect by increasing the absolute value of the voltage value of the effective voltage corresponding to the gate drive signal on the gate line in the display area corresponding to the brighter horizontal stripe, and reducing the absolute value of the voltage value of the effective voltage corresponding to the gate drive signal on the gate line in the display area corresponding to the brighter horizontal stripe, thereby adjusting the brightness difference between pixel circuits in different rows.

[0077] The display driver module described in the embodiments of the present invention can effectively prevent defects such as horizontal stripes, can debug display panels of different sizes and resolutions, increase the remote charging rate, and adjust the brightness difference between pixel circuits in different rows; the display driver module described in at least one embodiment of the present invention can be applied to a liquid crystal display device or an OLED (organic light emitting diode) display device.

[0078] In a specific implementation, the gate driving unit is used to transmit the gate driving signal to the pixel circuit included in the display panel;

[0079] The transistor whose control electrode in the pixel circuit is connected to the gate drive signal is an n-type transistor, the effective voltage is a high voltage, and the invalid voltage is a low voltage; or,

[0080] The transistor whose control electrode in the pixel circuit is connected to the gate driving signal is a p-type transistor, the effective voltage is a low voltage, and the invalid voltage is a high voltage.

[0081] In at least one embodiment of the present invention, the circuit structure of the gate driving unit can be as follows: Figure 3 As shown;

[0082] like Figure 3 As shown, at least one embodiment of the gate driving unit may include a first node control circuit 31, a second node control circuit 32, an output circuit 33, an output reset circuit 34 and an output terminal Gout;

[0083] The first node control circuit 31 is electrically connected to the first node P1, and the first node control circuit 31 is used to control the potential of the first node P1;

[0084] The second node control circuit 32 is electrically connected to the second node P2, and the second node control circuit 32 is used to control the potential of the second node P2;

[0085] The output circuit 33 is electrically connected to the first node P1, the clock signal line K1 and the output terminal Gout respectively, and is used to control the connection between the output terminal Gout and the clock signal line K1 under the control of the potential of the first node P1;

[0086] The output reset circuit 34 is electrically connected to the second node P2, the low voltage end and the output end Gout respectively, and is used to control the connection between the output end Gout and the low voltage end under the control of the potential of the second node P2; the low voltage end is used to provide a low voltage signal VSS.

[0087] like Figure 3 When at least one embodiment of the gate driving unit shown is working, the effective voltage may be a high voltage, and the ineffective voltage may be a low voltage;

[0088] In the charging stage, K1 can provide an invalid voltage signal, and the output circuit 33 controls the connection between the output terminal Gout and the clock signal line K1 under the control of the potential of the first node P1, so that Gout provides an invalid voltage signal;

[0089] In the output stage, K1 can provide a valid voltage signal, and the output circuit 33 controls the connection between the output terminal Gout and the clock signal line K1 under the control of the potential of the first node P1, so that Gout provides a valid voltage signal;

[0090] In the reset stage, the output reset circuit 34 controls the output terminal Gout to be connected to the low voltage terminal under the control of the potential of the second node P2.

[0091] Optional, such as Figure 4 As shown, the clock signal generating circuit includes a timing controller 41, a voltage generating subcircuit 42, a control subcircuit 43 and a clock signal generating subcircuit 44, wherein:

[0092] The voltage generating subcircuit 42 is used to generate an invalid voltage signal and at least two valid voltage signals, and provide the invalid voltage signal to the clock signal generating subcircuit 44;

[0093] The timing controller 41 is used to provide a control signal S0 to the control sub-circuit 43 through a control signal terminal, and to provide an input clock signal CLK0 to the clock signal generation sub-circuit through an input clock signal terminal;

[0094] The control subcircuit 43 is electrically connected to the control signal terminal and the voltage generating subcircuit 42 respectively, and is used to control the corresponding effective voltage signal of the at least two effective voltage signals to be provided to the clock signal generating subcircuit 44 under the control of the control signal S0;

[0095] The clock signal generating subcircuit 44 is electrically connected to the timing controller 41, the control subcircuit 43 and the clock signal line K1 respectively, and is used to generate a corresponding clock signal CLK according to the input clock signal CLK0, the invalid voltage signal and the corresponding valid voltage signal, and provide the clock signal CLK to the clock signal line K1.

[0096] In at least one embodiment of the present invention, the timing controller 41 may provide at least one control signal to the control subcircuit 43 .

[0097] The present invention Figure 4When at least one embodiment of the clock signal generating circuit shown is in operation, the voltage generating subcircuit 42 generates an invalid voltage signal and at least two valid voltage signals; the timing controller 41 provides a control signal S0 to the control subcircuit 43 through a control signal terminal, and provides an input clock signal CLK0 to the clock signal generating subcircuit through an input clock signal terminal; under the control of the control signal S0, the control subcircuit 43 controls the corresponding valid voltage signal among the at least two valid voltage signals to be provided to the clock signal generating subcircuit 44; the clock signal generating subcircuit 44 generates a corresponding clock signal CLK according to the input clock signal CLK0, the invalid voltage signal and the corresponding valid voltage signal, and provides the clock signal CLK to the clock signal line K1.

[0098] In a specific implementation, the clock signal generating subcircuit 44 generates the corresponding clock signal CLK according to the input clock signal CLK0, the invalid voltage signal and the corresponding valid voltage signal, which means:

[0099] The duty cycle of CLK0 is controlled to be the same as the duty cycle of CLK, and the rising edge of CLK0 is controlled to be aligned with the rising edge of CLK (that is, CLK0 and CLK rise at the same time), the falling edge of CLK0 is controlled to be aligned with the falling edge of CLK (that is, CLK0 and CLK fall at the same time), the voltage value of the invalid voltage of CLK is set to the voltage value of the invalid voltage signal, and the voltage value of the valid voltage of CLK is set to the voltage value of the corresponding valid voltage signal.

[0100] In at least one embodiment of the present invention, the voltage value of the effective voltage of CLK refers to: the potential of CLK when the potential of CLK is the effective voltage; the voltage value of the invalid voltage of CLK refers to: the potential of CLK when the potential of CLK is the invalid voltage.

[0101] For example, when the invalid voltage signal is a low voltage signal, the voltage value of the invalid voltage signal is -7V, and the valid voltage signal is a high voltage signal, the voltage value of the valid voltage signal is 34V, the waveform diagram of CLK0 and the waveform diagram of CLK can be Figure 5 shown.

[0102] In at least one embodiment of the present invention, the voltage generating subcircuit is used to generate a first effective voltage signal and a second effective voltage signal, and output the first effective voltage signal through a first output terminal and output the second effective voltage signal through a second output terminal;

[0103] The control subcircuit includes a first control transistor and a second control transistor;

[0104] The control electrode of the first control transistor is electrically connected to the control signal terminal, the first electrode of the first control transistor is electrically connected to the first output terminal, and the second electrode of the first control transistor is electrically connected to the clock signal generating circuit;

[0105] The control electrode of the second control transistor is electrically connected to the control signal terminal, the first electrode of the second control transistor is electrically connected to the second output terminal, and the second electrode of the second control transistor is electrically connected to the clock signal generating circuit.

[0106] In a specific implementation, the type of the first control transistor needs to be opposite to the type of the second control transistor; for example, when the first control transistor is an n-type transistor, the second control transistor is a p-type transistor; when the first control transistor is a p-type transistor, the second control transistor is an n-type transistor.

[0107] like Figure 6 As shown, in Figure 4 Based on at least one embodiment of the clock signal generating circuit shown,

[0108] The voltage generating sub-circuit 42 is used to generate a first high voltage signal VGH1 and a second high voltage signal VGH2, and output the first high voltage signal VGH1 through a first output terminal, and output the second high voltage signal VGH2 through a second output terminal;

[0109] The voltage generating sub-circuit is further used to generate a low voltage signal VGL to the clock signal generating sub-circuit 44;

[0110] The control subcircuit 43 includes a first control transistor M1 and a second control transistor M2;

[0111] The gate of the first control transistor M1 is connected to the control signal S0, the drain of the first control transistor M1 is connected to the first high voltage signal VGH1, and the source of the first control transistor M1 is electrically connected to the clock signal generating sub-circuit 44;

[0112] The gate of the second control transistor M2 is connected to the control signal S0 , the source of the second control transistor M2 is connected to the second high voltage signal VGH2 , and the drain of the second control transistor M2 is electrically connected to the clock signal generating sub-circuit 44 .

[0113] exist Figure 6 In at least one embodiment of the clock signal generating circuit shown, the voltage value of VGH2 can be greater than the voltage value of VGH1; M1 is an NMOS tube (N-type metal-oxide-semiconductor transistor), and M2 is a PMOS tube (P-type metal-oxide-semiconductor transistor).

[0114] exist Figure 6 In the illustrated embodiment, the clock signal generating subcircuit 44 generates two clock signals and provides the different clock signals to the clock signal line K1 in a time-sharing manner.

[0115] like Figure 6 When at least one embodiment of the clock signal generating circuit shown is in operation, when the control signal S0 provided by the timing controller 41 is a high voltage signal, M1 is turned on, M2 is turned off, and VGH1 is provided to the clock signal generating sub-circuit 44;

[0116] When the control signal S0 provided by the timing controller is a low voltage signal, M1 is turned off and M2 is turned on, and VGH2 is provided to the clock signal generating sub-circuit 44 .

[0117] like Figure 7 As shown, Figure 6 At least one embodiment of the clock signal generating circuit shown in FIG.

[0118] When the potential of S0 is a high voltage, the voltage signal V0 provided to the clock signal generating sub-circuit 44 is VGH1;

[0119] When the potential of S0 is a low voltage, the voltage signal V0 provided to the clock signal generating sub-circuit 44 is VGH2.

[0120] In a specific implementation, the voltage generating sub-circuit 42 can provide at least three high voltage signals. For example, when the voltage generating sub-circuit 42 provides four high voltage signals, the number of control signals S0 provided by the timing controller 41 can be two, and the number of control transistors included in the control sub-circuit 43 can be four.

[0121] According to a specific embodiment, the voltage generation subcircuit includes a power management integrated circuit;

[0122] The power management integrated circuit includes at least three voltage conversion circuits;

[0123] One of the at least three voltage conversion circuits is used to convert the first predetermined voltage signal into the invalid voltage signal;

[0124] At least two voltage conversion circuits among the at least three voltage conversion circuits are used to convert the second predetermined voltage signal into corresponding effective voltage signals respectively.

[0125] In at least one embodiment of the present invention, a power management integrated circuit can be used to generate an invalid voltage signal and at least two valid voltage signals. In this case, the PMIC (power management integrated circuit) needs to be re-customized, and at least three voltage conversion circuits are required inside the PMIC to generate an invalid voltage signal and at least two valid voltage signals.

[0126] Optionally, the voltage conversion circuit may be a charge pump or a boost circuit, but is not limited thereto.

[0127] Optionally, the first predetermined voltage signal and the second predetermined voltage signal may be DC voltage signals; for example, when the invalid voltage signal is a low voltage signal and the valid voltage signal is a high voltage signal, the first predetermined voltage signal may be a -5V voltage signal and the second predetermined voltage signal may be a +12V voltage signal.

[0128] According to another specific embodiment, the voltage generation subcircuit includes a power management integrated circuit and a voltage generation integrated circuit;

[0129] The power management integrated circuit is used to generate the invalid voltage signal and the first valid voltage signal;

[0130] The voltage generating integrated circuit is used to convert the third predetermined voltage signal into the corresponding at least one effective voltage signal.

[0131] In at least one embodiment of the present invention, the voltage generating sub-circuit may include a power management integrated circuit and a voltage generating integrated circuit. The power management integrated circuit may be used to generate an invalid voltage signal and a valid voltage signal. In this case, there is no need to re-customize the PMIC (power management integrated circuit). There are two voltage conversion circuits inside the PMIC to generate an invalid voltage signal and a valid voltage signal. At least one voltage conversion circuit may be provided in the voltage generating integrated circuit to generate at least one valid voltage signal. Thus, the generation of multiple voltage signals can be achieved without re-customizing the PMIC.

[0132] The display driving method according to the embodiment of the present invention is applied to the above-mentioned display driving module, and the display driving method includes:

[0133] The clock signal generating circuit generates at least two clock signals and provides different clock signals to the clock signal line in a time-sharing manner;

[0134] The gate driving unit generates a gate driving signal according to the clock signal on the clock signal line;

[0135] When the potential of the clock signal is an effective voltage, different clock signals have different potentials.

[0136] The display driving method described in the embodiment of the present invention can improve the charging rate of the remote pixel circuit by providing a clock signal with a higher absolute value of the effective voltage to the remote gate driving unit, and can effectively improve the phenomenon of insufficient charging of the remote pixel circuit included in the large-size display panel. In addition, the display driving method described in the embodiment of the present invention can improve the horizontal stripe defect phenomenon.

[0137] Optionally, the gate driving circuit is used to transmit the gate driving signal to the pixel circuit included in the display panel through the gate line included in the display panel, the clock signal generating circuit is arranged on the first side of the display panel, the second side is the side opposite to the first side, the clock signal line extends from the first side to the second side, and the extension direction of the gate line intersects with the extension direction of the clock signal line; the effective display area of ​​the display panel is divided into B display areas in sequence along the extension direction of the clock signal line; B is an integer greater than 1; the display driving method comprises:

[0138] When the gate driving circuit provides a gate driving signal to the gate line in the bth display area, the clock signal generating circuit provides a bth clock signal to the clock signal line; b is a positive integer less than or equal to B;

[0139] When the potential of the ath clock signal and the potential of the a+1th clock signal are effective voltages, the absolute value of the potential of the a+1th clock signal is greater than the absolute value of the potential of the ath clock signal; a is a positive integer less than B.

[0140] In a specific implementation, the effective display area of ​​the display panel can be divided into multiple display areas in sequence along the extension direction of the clock signal line, the extension direction of the clock signal line is from the first side to the second side, a driving integrated circuit is arranged on the first side, the driving integrated circuit includes a clock signal generating circuit, the second side is the side opposite to the first side, and the absolute value of the voltage value of the effective voltage of the clock signal provided to the gate driving unit corresponding to the display area far away from the driving integrated circuit is set to be larger, so as to solve the problem of uneven charging at the far and near ends, and effectively improve the phenomenon of insufficient charging at the far end of the display panel.

[0141] Optionally, the gate driving circuit is used to transmit the gate driving signal to the pixel circuit included in the display panel through the gate line included in the display panel, and the pixel circuits in the same row included in the display panel are electrically connected to the corresponding row of gate lines; the display driving method also includes:

[0142] When horizontal stripes appear on the display screen of the display panel,

[0143] When the gate driving circuit provides a gate driving signal for the gate line in the display area corresponding to the brighter horizontal stripes, the clock signal generating circuit provides a first clock signal to the clock signal line; when the gate driving circuit provides a gate driving signal for the gate line in the display area corresponding to the darker horizontal stripes, the clock signal generating circuit provides a second clock signal to the clock signal line;

[0144] When the potential of the first clock signal and the potential of the second clock signal are effective voltages, the absolute value of the potential of the first clock signal is smaller than the absolute value of the potential of the second clock signal.

[0145] In a specific implementation, when there is a difference in charging rate between different rows of pixel circuits included in the display panel, which leads to poor display of horizontal stripes, that is, when there are changes in brightness between different rows of pixel circuits, at least one embodiment of the present invention can control the gate driving unit in the display area corresponding to the brighter horizontal stripes to provide a first clock signal with a smaller absolute value of the voltage value of the effective voltage, and provide the gate driving unit in the display area corresponding to the darker horizontal stripes with a second clock signal with a larger absolute value of the voltage value of the effective voltage, so as to compensate for the difference in charging rate between different rows of pixel circuits and improve the poor display of horizontal stripes.

[0146] For example, when there is a defective horizontal stripe phenomenon of two bright rows and two dark rows on the display panel, that is, when the 4n-3th row of pixel circuits and the 4n-2th row of pixel circuits on the display panel are brighter (n is a positive integer), and the 4n-1th row of pixel circuits and the 4nth row of pixel circuits on the display panel are darker, when the gate drive circuit provides a gate drive signal to the 4n-3th row of gate lines and the 4n-2th row of gate lines, the clock signal generating circuit provides a first clock signal to the clock signal line; when the gate drive circuit provides a gate drive signal to the 4n-1th row of gate lines and the 4nth row of gate lines, the clock signal generating circuit provides a second clock signal to the clock signal line to improve the defective horizontal stripes.

[0147] The display device described in the embodiment of the present invention includes the above-mentioned display driving module.

[0148] The display device provided in the embodiment of the present invention can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0149] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A display driving module, comprising a clock signal line, a clock signal generating circuit and a gate driving circuit, wherein the gate driving circuit comprises a multi-stage gate driving unit; The clock signal generating circuit is electrically connected to the clock signal line, and is used to generate at least two clock signals, and provide different clock signals to the clock signal line in a time-sharing manner; The gate driving unit is electrically connected to the clock signal line, and is used to generate a gate driving signal according to the clock signal on the clock signal line; When the potential of the clock signal is an effective voltage, different clock signals have different potentials; The clock signal generating circuit comprises a timing controller, a voltage generating subcircuit, a control subcircuit and a clock signal generating subcircuit, wherein: The voltage generating subcircuit is used to generate an invalid voltage signal and at least two valid voltage signals, and provide the invalid voltage signal to the clock signal generating subcircuit; The timing controller is used to provide a control signal to the control subcircuit through a control signal terminal, and to provide an input clock signal to the clock signal generation subcircuit through an input clock signal terminal; The control subcircuit is electrically connected to the control signal terminal and the voltage generating subcircuit respectively, and is used for controlling, under the control of the control signal, to provide a corresponding valid voltage signal of the at least two valid voltage signals to the clock signal generating subcircuit; The clock signal generating subcircuit is electrically connected to the timing controller, the control subcircuit and the clock signal line respectively, and is used to generate a corresponding clock signal according to the input clock signal, the invalid voltage signal and the corresponding valid voltage signal, and provide the clock signal to the clock signal line; The voltage generating subcircuit is used to generate a first effective voltage signal and a second effective voltage signal, and output the first effective voltage signal through the first output terminal and output the second effective voltage signal through the second output terminal; The control subcircuit includes a first control transistor and a second control transistor; The control electrode of the first control transistor is electrically connected to the control signal terminal, the first electrode of the first control transistor is electrically connected to the first output terminal, and the second electrode of the first control transistor is electrically connected to the clock signal generating circuit; The control electrode of the second control transistor is electrically connected to the control signal terminal, the first electrode of the second control transistor is electrically connected to the second output terminal, and the second electrode of the second control transistor is electrically connected to the clock signal generating circuit.

2. The display driving module according to claim 1, wherein: The gate driving unit is used to transmit the gate driving signal to the pixel circuit included in the display panel; The transistor whose control electrode in the pixel circuit is connected to the gate drive signal is an n-type transistor, and the effective voltage is a high voltage; or The transistor whose control electrode in the pixel circuit is connected to the gate driving signal is a p-type transistor, and the effective voltage is a low voltage.

3. The display driving module according to claim 1, wherein: The voltage generation subcircuit includes a power management integrated circuit; The power management integrated circuit includes at least three voltage conversion circuits; One of the at least three voltage conversion circuits is used to convert the first predetermined voltage signal into the invalid voltage signal; At least two voltage conversion circuits among the at least three voltage conversion circuits are used to convert the second predetermined voltage signal into corresponding effective voltage signals respectively.

4. The display driving module according to claim 1, wherein: The voltage generation subcircuit includes a power management integrated circuit and a voltage generation integrated circuit; The power management integrated circuit is used to generate the invalid voltage signal and the first valid voltage signal; The voltage generating integrated circuit is used to convert the third predetermined voltage signal into the corresponding at least one effective voltage signal.

5. A display driving method, characterized in that: Applied to the display driving module according to any one of claims 1 to 4, the display driving method comprises: The clock signal generating circuit generates at least two clock signals and provides different clock signals to the clock signal line in a time-sharing manner; The gate driving unit generates a gate driving signal according to the clock signal on the clock signal line; When the potential of the clock signal is an effective voltage, different clock signals have different potentials.

6. The display driving method according to claim 5, characterized in that: The gate driving circuit is used to transmit the gate driving signal to the pixel circuit included in the display panel through the gate line included in the display panel, the clock signal generating circuit is arranged on a first side of the display panel, the second side is a side opposite to the first side, the clock signal line extends from the first side to the second side, and the extension direction of the gate line intersects with the extension direction of the clock signal line; The effective display area of ​​the display panel is divided into B display areas in sequence along the extension direction of the clock signal line; B is an integer greater than 1; the display driving method comprises: When the gate driving circuit provides a gate driving signal to the gate line in the bth display area, the clock signal generating circuit provides a bth clock signal to the clock signal line; b is a positive integer less than or equal to B; When the potential of the ath clock signal and the potential of the a+1th clock signal are effective voltages, the absolute value of the potential of the a+1th clock signal is greater than the absolute value of the potential of the ath clock signal; a is a positive integer less than B.

7. The display driving method according to claim 5, characterized in that: The gate driving circuit is used to transmit the gate driving signal to the pixel circuit included in the display panel through the gate line included in the display panel, and the pixel circuits in the same row included in the display panel are electrically connected to the corresponding row of gate lines; the display driving method also includes: When horizontal stripes appear on the display screen of the display panel, When the gate driving circuit provides a gate driving signal for the gate line in the display area corresponding to the brighter horizontal stripes, the clock signal generating circuit provides a first clock signal to the clock signal line; when the gate driving circuit provides a gate driving signal for the gate line in the display area corresponding to the darker horizontal stripes, the clock signal generating circuit provides a second clock signal to the clock signal line; When the potential of the first clock signal and the potential of the second clock signal are effective voltages, the absolute value of the potential of the first clock signal is smaller than the absolute value of the potential of the second clock signal.

8. A display device, characterized in that: The device comprises a display driving module as claimed in any one of claims 1 to 4.

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