Nonvolatile memory device, memory controller, and storage device reading method

Abstract

A nonvolatile memory device includes: a memory block including a memory area; an on-chip valley search (OVS) circuit that performs an OVS read operation on the memory block; and a buffer memory that stores at least one change table including change information of a threshold voltage of a memory cell obtained from the OVS read operation. In response to a read command applied by a memory controller, a read operation including an OVS read operation and a main read operation is performed on the memory area, the OVS read operation is performed at an OVS read level, and the main read operation is performed at a main read level reflecting the change information. In the nonvolatile memory device, the correction accuracy of the degradation of the word line threshold voltage can be improved, and the burden of the memory controller can be reduced.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2021-0026074 filed on February 26, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety for all purposes by reference. Technical Field

[0003] Embodiments of the present disclosure relate to a nonvolatile memory device, a memory controller, and a reading method of a memory device including the same. Background Art

[0004] Generally, in a programming operation, a storage device generates an error correction code (ECC) using an error correction circuit, and in a read operation, the storage device corrects data errors by referring to the error correction code. However, there are cases where the degradation of a memory cell of a storage device is so severe that correction by the error correction circuit is impossible. In this case, a read retry operation using a readout technique is performed, which is different from a normal read operation. Summary of the invention

[0005] Example embodiments provide a nonvolatile memory device and a storage device including the same, wherein accuracy of compensation for degradation can be improved using the nonvolatile memory device including a variation table including variation information according to degradation of a word line threshold voltage.

[0006] According to an aspect of example embodiments, there is provided a nonvolatile memory device, including: a memory block including a first memory region connected to a first word line; and control logic, wherein the control logic includes: an on-chip valley search (OVS) circuit configured to perform an OVS read operation on the memory block; and a first buffer memory configured to store at least one variation table including variation information of threshold voltages of memory cells connected to the first word line obtained from the OVS read operation, wherein the control logic is configured to: perform a first read operation on the first memory region in response to a first read command applied by a memory controller, the first read operation including a first OVS read operation in response to the first read command and a first main read operation, the first OVS read operation being performed at a first OVS read level, and the first main read operation being performed at the first main read level reflecting the variation information.

[0007] According to an aspect of an example embodiment, there is provided a memory controller comprising: a processor; a control pin configured to provide a control signal to at least one nonvolatile memory device including a first memory area connected to a first word line; an error correction circuit configured to correct data read from the at least one nonvolatile memory device based on the control signal; and a buffer memory configured to store a plurality of tables for compensating a read level of a read operation of the at least one nonvolatile memory device, wherein the processor is configured to input a first read command for performing a first read operation on the first memory area using at least one variation table stored in the at least one nonvolatile memory device.

[0008] According to an aspect of an example embodiment, a reading method of a memory device is provided, comprising: in at least one nonvolatile memory device, in response to a first read command received from a memory controller, performing a first on-chip valley search (OVS) read operation on a selected memory cell; extracting variation information of a threshold voltage of the selected memory cell and degradation information of a memory block including the selected memory cell; performing a first main read operation with a modified read level based on the variation information and the degradation information; and outputting a result of the first OVS read operation and data of the first main read operation to the memory controller, wherein the first OVS read operation and the first main read operation are defined as a first read operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description of example embodiments in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a schematic block diagram of a storage device according to an example embodiment;

[0011] Figure 2 is a schematic block diagram illustrating a nonvolatile memory device according to an example embodiment;

[0012] Figure 3 is a circuit diagram of a memory block included in a nonvolatile memory device according to example embodiments;

[0013] Figure 4 is a schematic block diagram illustrating a memory controller according to an example embodiment;

[0014] Figure 5 is a flow chart showing a process of performing a read operation using OVS in a general storage device;

[0015] Figure 6is a diagram illustrating a process of extracting a read level according to an OVS operation in a memory device according to example embodiments;

[0016] Figure 7 and Figure 8 is a diagram showing different read levels and corresponding development times of a distribution valley in an OVS operation of a general memory device;

[0017] Fig. 9 is a diagram illustrating a process of correcting a read level using an OVS table in a memory controller according to example embodiments;

[0018] FIG. 10A to FIG. 10C is a diagram illustrating an OVS operation according to a degree of degradation of a word line threshold voltage in a nonvolatile memory device according to example embodiments;

[0019] Fig.11 and Fig.12 is a diagram illustrating an OVS operation using a change table stored in a nonvolatile memory device according to an example embodiment;

[0020] Fig.13 is a flowchart illustrating a reading method of a storage device according to an example embodiment;

[0021] Fig.14 is a flowchart illustrating a reading method of a storage device according to an example embodiment;

[0022] FIG. 15A to FIG. 15C is a diagram illustrating a reading method of a storage device according to an example embodiment;

[0023] FIG. 16A to FIG. 16C is a diagram illustrating a reading method of a storage device according to an example embodiment;

[0024] FIG. 17A to FIG. 17C is a diagram illustrating a reading method of a storage device according to an example embodiment;

[0025] Fig.18 is a flowchart illustrating a reading method of a storage device according to an example embodiment;

[0026] Fig.19 is a ladder diagram illustrating a reading method of a storage device according to an example embodiment;

[0027] Fig. 20 is a ladder diagram illustrating a reading method of a storage device according to an example embodiment;

[0028] Fig.21 is a schematic block diagram illustrating a storage device according to an example embodiment;

[0029] Fig. 22is a block diagram illustrating a memory system including a memory device according to example embodiments; and

[0030] Fig.23 is a diagram illustrating an electronic device including a storage device according to example embodiments. DETAILED DESCRIPTION

[0031] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings.

[0032] The distribution of programmed threshold voltages may be modified by at least one reason such as retention, interference, temperature, noise, etc. Such changes in the threshold voltage distribution may cause errors in read operations (e.g., error correction is not possible). Defense code may refer to a method of recovering errors in data read in a read operation. Typically, defense code may include a process for finding a distribution valley of the threshold voltage. An on-chip Valley Search (OVS) operation may be beneficial for finding such a distribution valley. The specific details of the OVS operation may be described in U.S. Patent Application Publications Nos. 2020 / 0286545 and 2020 / 0098436, and U.S. Patents Nos. 10,090,046, 10,607,708, and 10,629,259, which are incorporated herein by reference.

[0033] Figure 1 is a schematic block diagram of a storage device according to an example embodiment. Figure 1 , the memory device 10 may include at least one nonvolatile memory device (NVM) 100 and a memory controller (CNTL) 200 .

[0034] At least one nonvolatile memory device 100 may be implemented to store data. Examples of the nonvolatile memory device 100 may include NAND flash memory, vertical NAND flash memory (VNAND), NOR flash memory, resistance random access memory (RRAM) phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM), etc. In addition, the nonvolatile memory device 100 may be implemented as a three-dimensional array structure. The embodiment can be applied not only to a flash memory device in which a charge storage layer is formed by a conductive floating gate, but also to a charge trap flash (CTF) memory in which a charge storage layer is formed by an insulating layer. In the following, for ease of description, a case where the nonvolatile memory device 100 is a vertical NAND flash memory device is provided as an example.

[0035] The nonvolatile memory device 100 according to example embodiments may be implemented to include a plurality of memory blocks BLK1 to BLKz and a control logic 150 , where z is an integer greater than or equal to 2.

[0036] Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of pages Page 1 to Page m, where m is an integer greater than or equal to 2. Each of the plurality of pages Page 1 to Page m may include a plurality of memory cells. Each of the plurality of memory cells may store at least one bit.

[0037] The control logic 150 may be implemented to receive a command and an address from the memory controller 200 and perform an operation corresponding to the received command on a memory cell corresponding to the address. For example, the operation may be any one of a program operation, a read operation, an erase operation, etc.

[0038] The control logic 150 may include an OVS circuit 155. The OVS circuit 155 may be implemented to perform an on-chip valley search (OVS) operation. Generally, the OVS operation may include an operation of obtaining a cell count according to a plurality of development times, an operation of determining an OVS detection condition based on the obtained cell count, an operation of changing an actual development time according to the determined OVS detection condition, and an operation of reading by applying the changed development time.

[0039] In the nonvolatile memory device 100 according to the example embodiment of the present disclosure, the OVS operation may be represented as an OVS read operation and a main read operation, respectively. For example, the nonvolatile memory device 100 according to the example embodiment obtains an X / Y cell count according to a plurality of development times through the OVS read operation, and may determine the OVS detection situation based on the obtained X / Y cell count. On the other hand, the nonvolatile memory device 100 may change the actual development time through the main read operation according to the determined OVS detection situation. For example, the main read operation may be a read operation.

[0040] The OVS circuit 155 may be implemented to store detection information OVSDI (detection situation information) corresponding to the result of the OVS read operation. As an example, the detection information OVSDI may include information such as development time information indicating an optimal distribution valley corresponding to a state.

[0041] In general, the optimal read level for a read operation may change according to the degradation of the nonvolatile memory device 100. For example, word lines included in a plurality of memory blocks BLK1 to BLKz that have experienced different degradations may have different optimal read levels. Therefore, when a read operation is performed, if the same read level is applied to each memory block, the read operation may fail in a specific word line.

[0042] In the nonvolatile memory device 100 according to example embodiments, the same read level is not applied to all word lines included in the plurality of corresponding memory blocks BLK1 to BLKz, but an optimal read level applied to another word line may be set based on a read level set in a specific word line. Therefore, a read operation on all word lines may be stably performed without error.

[0043] In the nonvolatile memory device 100 according to example embodiments, the control logic 150 may further include a first buffer memory including at least one variation table (VT) 180. For example, the nonvolatile memory device 100 may perform a read operation by taking into account variation information about threshold voltages of word lines included in a plurality of corresponding memory blocks BLK1 to BLKz using at least one variation table 180. For example, the variation table 180 may include variation information of threshold voltages of word lines set by an OVS read operation. Threshold voltage variation information of word lines included in each of the plurality of memory blocks BLK1 to BLKz may be generated based on variations in read voltages of the first and second memory regions according to degradation of the nonvolatile memory device 100. For example, the first memory region and the second memory region may correspond to different pages in a plurality of pages Page 1 to Page m, respectively, and the first memory region and the second memory region may be connected to the first word line and the second word line, respectively.

[0044] On the other hand, the nonvolatile memory device 100 according to the example embodiment may further include a selection logic 190 for selecting at least one of the at least one variation table 180 based on the result of the OVS read operation. The selection logic 190 may select the variation table 180 for changing the read level applied to the word line according to the degree of degradation of the nonvolatile memory device 100. However, this is merely an example, and the configuration is not limited thereto. For example, when the nonvolatile memory device 100 includes a first buffer memory having one variation table 180, the selection logic 190 may operate differently. Alternatively, in this case, the nonvolatile memory device 100 may not include the selection logic 190.

[0045] The memory controller 200 may be connected to at least one nonvolatile memory device 100 through a plurality of control pins that transmit control signals (e.g., CLE, ALE, (one or more) CE, WE, RE, etc.). In addition, the memory controller 200 may be implemented to control the nonvolatile memory device 100 using the control signals. For example, the nonvolatile memory device 100 may perform a program operation, a read operation, and / or an erase operation by latching a command CMD or an address ADD at an edge of a write enable signal (WE) according to a command latch enable signal (CLE) or an address latch enable signal (ALE).

[0046] Furthermore, the memory controller 200 may include at least one processor (central processing unit (CPU(s))) 210 , a second buffer memory 220 , and an error correction circuit 230 .

[0047] The processor 210 may be implemented to control the overall operation of the storage device 10. The processor 210 may perform various management operations, such as cache / buffer management, firmware management, garbage collection management, wear leveling management, data deduplication management, read refresh / reclaim management, bad block management, multi-stream management, management of mapping of host data and non-volatile memory, quality of service (QoS) management, system resource allocation management, non-volatile memory queue management, read level management, erase / program management, hot / cold data management, power loss protection management, dynamic thermal management, initialization management, redundant array of independent disks (RAID) management, etc.

[0048] In detail, the processor 210 may drive a read level (RL) compensation unit 211 that manages a read level. The read level compensation unit 211 may reflect detection information corresponding to a result of performing an OVS read operation to a historical read level in real time. For example, the read level compensation unit 211 may accumulate an offset corresponding to the detection information set in the OVS table (OVST) in a historical read level table (HRT). As an example, the read level compensation unit 211 may be implemented in firmware / software. On the other hand, Figure 1 The read level compensation unit 211 shown in FIG. 2 is shown to operate inside the memory controller 200 , but the configuration is not limited thereto. For example, the read level compensation unit may operate inside the nonvolatile memory device 100 .

[0049] The second buffer memory 220 may be implemented as a volatile memory (e.g., static random access memory (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), etc.) or a non-volatile memory (e.g., flash memory, phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc.). The second buffer memory 220 may include at least one predefined table (PDT), OVST, and HRT.

[0050] The PDT may include first read level offset information. For example, the PDT may include first read level offset information corresponding to the programming elapsed time. For example, the first read level offset information may be an offset predetermined based on environmental information. For example, in addition to the programming elapsed time, the PDT may also include first read level offset information corresponding to various degradation information, temperature, program / erase cycle, read cycle, open word line case, etc.

[0051] OVST may include second read level offset information corresponding to the detection information OVSDI. In this case, the detection information OVSDI may be development time information corresponding to the optimal distribution valley. For example, the second read level offset information may include read level offset information corresponding to development time information, where the OVS read operation has been performed at the development time. Therefore, OVST may be a table obtained by converting the detection information OVSDI into read level offset information.

[0052] The HRT may include third read level offset information related to the historical read operation. In an example embodiment, the third read level offset information may include information obtained by accumulating the second read level offset information. In another embodiment, the third read level offset information may be determined using the first read level offset information and the second read level offset information. In this case, the third read level offset information may include a read level at which the historical read operation was performed.

[0053] However, in the memory device 10 according to the example embodiment, the read level included in the third read level shift information may not be an optimal read level because degradation of the word line threshold voltage is corrected inside the nonvolatile memory device 100. Detailed descriptions of historical read operations are found in U.S. Patent Nos. 10,120,589 and 10,373,693, which are incorporated herein as background literature.

[0054] The error correction circuit 230 may be implemented to generate an error correction code (ECC) during a programming operation and to recover data using the error correction code during a read operation. For example, the error correction circuit 230 may generate an error correction code ECC for correcting a failed bit or an error bit of data received from the nonvolatile memory device 100. The error correction circuit 230 may form data with a parity bit added by performing error correction coding on the data provided to the nonvolatile memory device 100. For example, the parity bit may be stored in the nonvolatile memory device 100. In addition, the error correction circuit 230 may perform error correction decoding on the data output from the nonvolatile memory device 100. The error correction circuit 230 may use the parity bit to correct errors. The error correction circuit 230 may use various coded modulations (e.g., low density parity check (LDPC) codes, BCH codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), trellis coded modulation (TCM), block coded modulation (BCM), etc.) to correct errors.

[0055] On the other hand, when error correction is not possible in the error correction circuit 230, a read retry operation may be performed. As an example, the read retry operation may include an OVS read operation. As an example, the OVS read operation may reflect the PDT. However, the embodiment is not limited thereto.

[0056] The memory controller 200 according to example embodiments may further include a command (CMD) selector 225. For example, the command selector 225 may select a command input to the nonvolatile memory device 100. For example, the command selector 225 may select and output a command so that degradation correction of a word line threshold voltage performed in the nonvolatile memory device 100 after an OVS read operation is considered during a next word line read operation.

[0057] The storage device 10 according to the example embodiment can perform degradation correction of the word line threshold voltage using at least one variation table included in the nonvolatile memory device 100. In this case, the degradation correction of the word line threshold voltage can be performed based on the X / Y cell count obtained by the OVS read operation. Therefore, the correction accuracy for the difference in the degree of degradation between the word lines can be improved, and the difference increases as the number of levels of the word lines increases. In addition, the reduction in the read window that occurs when the degradation continues can be significantly reduced. In addition, the nonvolatile memory device 100 according to the example embodiment can reduce the memory usage of the memory controller 200 by storing at least one variation table using the peripheral circuit area, and in addition, the nonvolatile memory device 100 can also be applied to SSDs or mobile products that do not include DRAM.

[0058] Figure 2 is a schematic block diagram illustrating a nonvolatile memory device according to example embodiments.

[0059] Reference Figure 2 , the nonvolatile memory device 100 includes a memory cell array 110, a row decoder 120, a page buffer circuit 130, an input / output (I / 0) buffer circuit 140, a control logic 150, a voltage generator 160, and a cell counter 170.

[0060] The memory cell array 110 may be connected to the row decoder 120 via a word line WL or a selection line. The memory cell array 110 may be connected to the page buffer circuit 130 via a bit line BL. The memory cell array 110 may include a plurality of cell strings. The channel of each cell string may be formed in a vertical direction or in a horizontal direction. Each cell string may include a plurality of memory cells. In this case, a programming operation, an erase operation, or a read operation may be performed on a plurality of memory cells by a voltage applied to a bit line BL or a word line WL. Typically, a programming operation may be performed in units of pages, and an erase operation may be performed in units of blocks. A detailed description of a memory cell may be found in U.S. Patents Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and 9,536,970. For example, the memory cell array 110 may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged in row and column directions.

[0061] The row decoder 120 may be implemented to select any one of the memory blocks BLK1 to BLKz of the memory cell array 110 in response to the address ADD. For example, the row decoder 120 may select any one of the word lines of the selected memory block in response to the address ADD. The row decoder 120 may transfer the word line threshold voltage VWL corresponding to the operation mode to the word line of the selected memory block. During a programming operation, the row decoder 120 may apply a program voltage and a verification voltage to the selected word line, and may apply a pass voltage to an unselected word line. During a read operation, the row decoder 120 may apply a read voltage to the selected word line, and may apply a read pass voltage to an unselected word line.

[0062] The page buffer circuit 130 may be implemented to operate as a write driver or a sense amplifier. During a programming operation, the page buffer circuit 130 may apply a bit line voltage corresponding to the data to be programmed to the bit line of the memory cell array 110. During a read operation or a verification read operation, the page buffer circuit 130 may detect the data stored in the selected memory cell through the bit line BL. Each of the plurality of page buffers PB1 to PBn (n is an integer greater than or equal to 2) included in the page buffer circuit 130 may be connected to at least one bit line.

[0063] Each of the plurality of page buffers PB1 to PBn may be implemented to perform readout and latching for performing an OVS operation. For example, each of the plurality of page buffers PB1 to PBn may perform a plurality of readout operations under the control of the control logic 150 to identify any one state stored in the selected memory cell. In addition, each of the plurality of page buffers PB1 to PBn may store data read out by a plurality of readout operations under the control of the control logic 150, and any one data may be selected. For example, each of the plurality of page buffers PB1 to PBn may perform readout multiple times to identify any one state. In addition, each of the plurality of page buffers PB1 to PBn may select and / or output the best data from a plurality of readout data according to the control of the control logic 150.

[0064] The input / output buffer circuit 140 may input an external signal to the nonvolatile memory device 100 or output a signal of the nonvolatile memory device 100 to the outside. For example, the input / output buffer circuit 140 may provide externally provided data to the page buffer circuit 130. For example, the input / output buffer circuit 140 may provide an externally provided command CMD to the control logic 150. For example, the input / output buffer circuit 140 may provide an externally provided address ADD to the control logic 150 or the row decoder 120. For example, the input / output buffer circuit 140 may output data read out and latched by the page buffer circuit 130 to the outside.

[0065] The control logic 150 may be implemented to control the row decoder 120 and the page buffer circuit 130 in response to a command CMD transmitted from an external source. In addition, the control logic 150 may include an OVS circuit 155 to perform an OVS read operation.

[0066] The OVS circuit 155 can control the page buffer circuit 130 and the voltage generator 160 for the OVS read operation. The OVS circuit 155 can control the page buffer circuit 130 to perform multiple read operations to identify the specific state of the selected memory cell. In addition, the OVS circuit 155 can control the multiple page buffers PB1 to PBn to store the read data corresponding to each of the multiple read results in the multiple latch groups set in the multiple page buffers PB1 to PBn. In addition, the OVS circuit 155 can perform a process of selecting the best data from the multiple read data. In order to select the best data, the OVS circuit 155 can refer to the count result nC provided from the cell counter 170. For example, the OVS circuit 155 can control the page buffer circuit 130 to select and output the read result closest to the distribution valley from the multiple read results.

[0067] In addition, the OVS circuit 155 may store the detection information OVSDI based on the count result nC corresponding to the OVS read operation. The OVS circuit 155 may output the stored detection information OVSDI to the memory controller 200. For example, the detection information OVSDI may be output using a Universal Internal Bus (UIB) output, or in response to a specific command (e.g., a Get Feature command, a Status Read command, etc.).

[0068] On the other hand, Figure 1 As described in, the control logic 150 of the nonvolatile memory device 100 according to the example embodiment may also include a first buffer memory, which includes one or more variation tables 180-1, ... and 180-n. For example, each of the one or more variation tables 180-1, ... and 180-n may include information about the degradation of the threshold voltage of the word line WL. For example, the threshold voltage degradation information of the word line WL may have a predetermined relationship with the arrangement of the word line. However, this is merely an example embodiment, and the configuration is not limited thereto. For example, the first buffer memory may be included in the nonvolatile memory device 100 as a separate configuration instead of inside the control logic 150.

[0069] The voltage generator 160 may be implemented to generate various types of word line threshold voltages VWL to be applied to the corresponding word lines WL and a well voltage to be supplied to a block (e.g., a well region) in which a memory cell is formed under the control of the control logic 150. The word line threshold voltage VWL applied to the corresponding word line WL may include a program voltage, a pass voltage, a read voltage, a read pass voltage, etc.

[0070] The cell counter 170 may be implemented to count memory cells corresponding to a specific threshold voltage range according to data read out by the page buffer circuit 130. For example, the cell counter 170 may count the number of memory cells having a threshold voltage in a specific threshold voltage range by processing data read out in each of the plurality of page buffers PB1 to PBn. Therefore, in an OVS read operation using the cell counter 170, the precise position of the distribution valley may be read out.

[0071] The nonvolatile memory device 100 according to example embodiments may further include a selection logic 190 for selecting the variation tables 180-1, ..., 180-n. The selection logic 190 may select a variation table for setting an optimal read voltage from one or more variation tables 180-1, ..., and 180-n under the control of the control logic 150.

[0072] In the nonvolatile memory device 100 according to example embodiments, in the process of setting the optimal read voltage according to the OVS read operation, at least one variation table 180-1, ..., 180-n can be used, thereby ensuring the reliability of the correction of the word line threshold voltage degradation. In addition, the nonvolatile memory device 100 according to example embodiments selectively uses at least one variation table 180-1, ..., 180-n, and therefore, over-compensation in a case where the degradation is not serious can be prevented, and by significantly reducing the memory usage of the memory controller, the correction of the word line threshold voltage degradation can be applied even to mobile products or SSDs that do not include DRAM.

[0073] Figure 3 is a circuit diagram of a memory block included in a nonvolatile memory device according to example embodiments.

[0074] Figure 3 yes Figure 2 2 is a circuit diagram of any one memory block BLKi among a plurality of memory blocks BLK1 to BLKz included in the nonvolatile memory device 100. For example, a plurality of memory NAND strings included in the memory block BLKi may be formed in a direction perpendicular to a substrate.

[0075] Reference Figure 3 , the memory block BLKi may include a plurality of memory NAND strings NS11 to NS33 connected between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the plurality of memory NAND strings NS11 to NS33 may include a string selection transistor SST, a plurality of memory cells MC1, MC2, ..., MC8, and a ground selection transistor GST. Although Figure 3It is shown in FIG. 4 that each of the plurality of memory NAND strings NS11 to NS33 includes eight memory cells MC1, MC2, . . . , MC8, but the embodiment is not limited thereto.

[0076] The string selection transistor SST may be connected to the corresponding string selection lines SSL1, SSL2, and SSL3. A plurality of memory cells MC1, MC2, ..., and MC8 may be connected to the corresponding gate lines GTL1, GTL2, ..., and GTL8, respectively. The gate lines GTL1, GTL2, ..., and GTL8 may correspond to word lines, and a portion of the gate lines GTL1, GTL2, ..., and GTL8 may correspond to pseudo word lines. The ground selection transistor GST may be connected to the corresponding ground selection lines GSL1, GSL2, and GSL3. The string selection transistor SST may be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground selection transistor GST may be connected to the common source line CSL.

[0077] Word lines having the same height, for example, GTL1 (which may also be referred to herein as WL1 ), may be commonly connected, and ground selection lines GSL1 , GSL2 , and GSL3 and string selection lines SSL1 , SSL2 , and SSL3 may be separated from each other. Figure 3 It is shown that the memory block BLKi may be connected to eight gate lines GTL1 , GTL2 , . . . , and GTL8 and three bit lines BL1 , BL2 , and BL3 , but the configuration is not limited thereto.

[0078] Figure 4 is a schematic block diagram illustrating a memory controller according to example embodiments.

[0079] Reference Figure 4 , the memory controller 200 may include a host interface (I / F) 201, a memory interface 202, at least one CPU 210, a buffer memory 220, an error correction circuit 230, a flash translation layer manager 240, a data packet manager 250, and an encryption device 260. For example, Figure 4 The CPU 210, the buffer memory 220 and the error correction circuit 230 shown in FIG. 2 may correspond to Figure 1 The configuration shown in .

[0080] The host interface 201 may be implemented to send and receive data packets to and from the host. The data packets sent from the host to the host interface 201 may include commands or data to be written to the nonvolatile memory device 100. The data packets sent from the host interface 201 to the host may include responses to commands or data read from the nonvolatile memory device 100. The memory interface 202 may send data to be written to the nonvolatile memory device 100 to the nonvolatile memory device 100, or receive data read from the nonvolatile memory device 100. The memory interface 202 may be implemented to comply with a standard protocol such as JDEC Toggle or ONFI.

[0081] The flash translation layer manager 240 may perform various functions such as address mapping, wear leveling, and garbage collection. The address mapping operation may be an operation of changing a logical address received from a host into a physical address for actually storing data in the nonvolatile memory device 100. Wear leveling is a technique for preventing excessive degradation of a specific block by ensuring that the blocks in the nonvolatile memory device 100 are evenly used, and, for example, wear leveling may be implemented by a firmware technique that balances the erase counts of physical blocks. Garbage collection may be a technique for ensuring available capacity in the nonvolatile memory device 100 by copying valid data of a block to a new block and then erasing the existing block.

[0082] The packet manager 250 may generate a packet according to a protocol of an interface negotiated with the host or parse various types of information from a packet received from the host. In addition, the buffer memory 220 may temporarily store data to be written to or read from the nonvolatile memory device 100. For example, the buffer memory 220 may be a configuration provided in the memory controller 200. As another example, the buffer memory 220 may be provided outside the memory controller 200.

[0083] The encryption device 260 may perform at least one of an encryption operation and a decryption operation on data input to the memory controller 200 using a symmetric key algorithm. The encryption device 260 may perform encryption and decryption of data using an Advanced Encryption Standard (AES) algorithm. The encryption device 260 may include an encryption module and a decryption module.

[0084] Figure 5 is a flowchart illustrating a process of performing a read operation using OVS in a general storage device.

[0085] Reference Figure 5, a case in which a general storage device performs a read operation on a memory cell connected to the first word line WL1 using a default read level can be provided as an example. For example, the default read level may be a predetermined reference read voltage. When the read operation fails, an OVS read operation for the memory cell connected to the first word line WL1 may be activated. For example, the nonvolatile memory device may enter a defense code. The OVS read operation may be performed by reflecting a predefined predefined table (PDT). When the read operation for the memory cell connected to the first word line WL1 passes through the OVS read operation, the historical read level table (HRT) may be updated. In this case, the offset information of the PDT for the OVS read operation may be updated in the HRT.

[0086] Thereafter, when a read operation is performed on a memory cell connected to the next word line (e.g., the second word line WL2), the OVS read operation can be basically disabled. For example, a read operation can be performed on a memory cell connected to the second word line WL2 in a state where the defense code is released. In this case, a historical read operation can be performed using the updated HRT. Since a general memory device does not reflect the optimal read level shift found in the OVS read operation to the HRT, there is a high probability that the read operation of the memory cell connected to the next word line will fail.

[0087] On the other hand, the memory device 10 according to the example embodiment may reflect the detection information caused by the OVS read operation to the HRT. Therefore, when performing the main read operation and the next read operation, the optimal read level may be applied by reflecting the change table VT including the word line change information stored in the nonvolatile memory device 100 and the HRT.

[0088] Figure 6 is a diagram illustrating a process of extracting a read level according to an OVS operation in a memory device according to example embodiments.

[0089] Reference Figure 6 The storage device 10 can use the first table PDT or the second table OVST to update the third table HRT in real time, and can reflect the change table VT stored in the nonvolatile memory device NVM together, thereby extracting the best read level. Apply the best read level in the NVM to read the memory cell.

[0090] The result information according to the OVS read operation may include the change information of the word line threshold voltage and other degradation information. As an example, the detection information OVSDI may include the result according to the OVS read operation, and the second read level shift OST_ovst corresponding to the degradation information not including the change information of the word line threshold voltage may be reflected in real time in OVST. On the other hand, in the memory device 10 according to the example embodiment, the change information of the word line threshold voltage included in the nonvolatile memory device 100 may not be output to the memory controller 200. For example, the change information of the word line threshold voltage may be included in the change table VT included in the nonvolatile memory device 100, and the change table VT may be selectively updated according to the example embodiment.

[0091] On the other hand, the third read level offset OST_hrt may be determined by accumulating the second read level offset OST_ovst. Alternatively, the third read level offset OST_hrt may be determined by adding the second read level offset OST_ovst to the first read level offset OST_pdt according to the lapse of programming time. On the other hand, the third read level offset OST_hrt may not be determined by simply adding the first read level offset OST_pdt and the second read level offset OST_ovst. For example, the third read level offset OST_hrt may be determined by applying a weight to each of the first read level offset OST_pdt and the second read level offset OST_ovst.

[0092] Figure 7 and Figure 8 is a diagram showing different read levels and corresponding development times of a distribution valley in an OVS operation of a general memory device.

[0093] like Figure 7 As shown, the OVS operation for finding the distribution valley of the states S1 and S2 may be performed through a plurality of read operations. In this case, a plurality of read operations may be performed simultaneously in a plurality of corresponding page buffer groups.

[0094] Reference Figure 8 , in the first page buffer PGB1 and the second page buffer PGB2, the OVS read operation may be performed in such a manner that the read nodes are sequentially latched at the same time point during different development periods to store the read results.

[0095] A precharge operation may be performed from time T0 to time T1. For precharge, the first bit line and the readout node connected to each first page buffer PBG1 may be charged. When the bit line setting signal is activated, the readout node and the first bit line may be precharged to a specific level. When the first bit line setting signal is deactivated to a high level at time T1, the precharge circuit of each first page buffer PBG1 may be turned off. In addition, when the second bit line setting signal is deactivated to a high level at time T2 after time T1, the precharge circuit of each second page buffer PBG2 may be turned off. At this time, the level of each readout node of the first page buffer PBG1 and the level of each readout node of the second page buffer PBG2 may vary based on whether the memory cell is turned on or off based on the magnitude of the current flowing to the corresponding bit line.

[0096] like Figure 8 As shown, each of the first page buffers PBG1 can precharge the sensing node from time T0 to time T1, and can develop the first bit line from time T1 to time T4. On the other hand, each of the second page buffers PBG2 can precharge the sensing node from time T0 to time T1, and can develop the second bit line from time T2 to time T4, which is later than time T1.

[0097] The first read operation may include a latch reset (nS) read operation performed at time T3 and a latch set (S) read operation performed at time T5. The first cell count information may be calculated using the cell count values ​​of the latch reset (nS) read operation and the latch set (S) read operation in the first page buffer PGB1. In addition, the second cell count information may be calculated using the cell count values ​​of the latch reset (nS) read operation and the latch set (S) read operation in the second page buffer PGB2. On the other hand, a detection situation (any one of C1 to C5) corresponding to an optimal read level corresponding to a distribution valley may be determined based on the first cell count information and the second cell count information of the first read operation. In addition, the development time tSODev1 to tSODev5 of the second read operation corresponding to the determined detection situation may be determined.

[0098] Fig. 9 is a diagram illustrating a process of correcting a read level using an OVS table in a memory controller according to example embodiments.

[0099] Reference Fig. 9, an X / Y cell count value is determined according to the distribution of the threshold voltage according to the OVS read operation, and a first conversion of converting the determined X / Y cell count value into a detection condition corresponding to the distribution valley may be performed. For example, in the case of the topmost page, the cell count value may be CC3. In this case, the detection condition of the OVS operation may correspond to the third detection condition C3. In the nonvolatile memory device 100 (refer to Figure 1 ) in the OVS circuit 155 (refer to Figure 1 ) can store or latch a data bit for each detection condition.

[0100] After that, the detection information OVSDI (refer to Figure 1 ) is output from the nonvolatile memory device 100 to the memory controller 200 (refer to Figure 1 ). The memory controller 200 may generate a corresponding read level offset (+20mV) in OVST using the detection information (e.g., OVS detection situation C3). For example, the change information of the word line threshold voltage may be stored in the change table and may not be output to the memory controller. Therefore, the generated read level offset (+20mV) may correspond to a plurality of degradation information other than the change information of the word line threshold voltage. In this case, the memory controller 200 may perform a second conversion operation on the read level offset corresponding to the OVS detection situation by using OVST. Therefore, the memory controller 200 may eventually update the offset according to the OVS read operation to the HRT.

[0101] FIG. 10A to FIG. 10C is a diagram illustrating an OVS operation according to a degree of degradation of a word line threshold voltage in a nonvolatile memory device according to example embodiments.

[0102] FIG. 10A to FIG. 10C is a diagram showing the relationship between the result of the OVS read operation and the OVS detection condition in the nonvolatile memory device 100 according to an example embodiment. As an example, the detection condition can be derived using the first cell count value and the second cell count value obtained by the OVS read operation. In addition, the degree of degradation of the word line threshold voltage can be known. On the other hand, FIG. 10A to FIG. 10C The read skew of multiple word lines may be shown. For example, as the degradation level of the word line threshold voltage increases, the variation of the read skew may increase. The degradation trend of the word line threshold voltage determined based on the variation information of the word line threshold voltage may be similar to the degradation trend of the word line threshold voltage determined based on other multiple degradation information, but the configuration is not limited thereto. FIG. 10A to FIG. 10C Five OVS detection situations are shown in FIG, but this is only an example.

[0103] Reference Fig. 10A, the detection condition derived by the OVS read operation may be a third detection condition. For example, the third detection condition may be a condition in which degradation of the word line threshold voltage hardly progresses.

[0104] Reference Fig. 10B , the detection condition derived by the OVS read operation may be the second detection condition. For example, the second detection condition or the fourth detection condition may be a condition where the threshold voltage has degraded to a certain extent. Therefore, it may be necessary to change the read level used for the read operation.

[0105] Reference Fig. 10C , the detection condition derived by the OVS read operation may be the first detection condition. For example, the first detection condition and the fifth detection condition may be edge conditions, which may be conditions where the word line threshold voltage is in a detectable maximum degradation state. On the other hand, a variation table including variation information of the word line threshold voltage may be generated according to the maximum degradation state. However, this configuration is only an example.

[0106] Fig.11 and Fig.12 is a diagram illustrating an OVS operation using a change table stored in a nonvolatile memory device according to example embodiments.

[0107] As an example, Fig.11 may be a variation table VT showing a read level shift according to a state and a word line when the degradation of the threshold voltage distribution is large, and Fig.12 It can be a table VT showing the variation of the read level shift according to the state and word line when the degradation of the threshold voltage distribution is small. As an example, although in Fig.11 and Fig.12 The variation table is shown based on 127 word lines, but this is only an example. For example, the number of word lines may be more or less, and the read level offset may be set by dividing the read level offset into narrower word line segments.

[0108] The nonvolatile memory device 100 according to example embodiments may include at least one variation table. On the other hand, the nonvolatile memory device 100 may select a variation table to be applied to set the read voltage from one or more variation tables based on the result of the OVS read operation. For example, the selection logic 190 (refer to Figure 1 ) to select a change table including the change information to be reflected. For example, when the degradation degree of the word line threshold voltage is as follows Fig. 10C As shown, the results of the OVS read operation are as significant, the selection logic 190 can select Fig.11 On the other hand, when the degradation degree of the word line threshold voltage is as Fig. 10B If the situation is not serious, you can choose Fig.12However, this is only an example, and the configuration is not limited thereto. For example, the nonvolatile memory device 100 may include only one change table.

[0109] On the other hand, the nonvolatile memory device 100 can set an optimal read level for performing a read operation by reflecting the variation information included in the variation table selected according to the detection situation based on the OVS read operation. The variation information can be reflected in the read level in various ways.

[0110] For example, as described above, a change table including different pieces of change information according to the detection situation can be selected and reflected in the read level. On the other hand, the weight of the change information included in the change table can be determined according to the detection situation based on the OVS read operation. As an example, in the case where the degradation degree of the word line threshold voltage is as follows Fig. 10C The results of the OVS read operation shown are relatively significant. When the optimal read level is set, it can be reflected Fig.11 100% of the variation information included in the variation table shown. On the other hand, when the degradation degree of the word line threshold voltage is as Fig. 10B In less serious cases, it can be reflected Fig.11 50% of the change information included in the change table shown. In detail, when the detection situation is an edge case, the weight reflecting the change information can be higher than the weight when the detection situation is not an edge case. However, this is only an example embodiment, and the weight applied to each detection situation is not limited and can be changed differently.

[0111] Fig.13 is a flowchart illustrating a reading method of a memory device according to example embodiments.

[0112] Refer to Figures 1 to 12 , the read operation of the memory device 10 according to the example embodiment may be as follows Fig.13 As shown in . First, a read request can be received from a host outside the storage device 10. The storage device 10 can determine the history of such a read request. The history buffer can determine whether the currently received read request has previously existed (S110). For example, when the current read request exists in the previous read request stored in the history buffer, a historical read operation (S111) can be performed. In this case, in the historical read operation, the read operation can be performed using the optimal read level included in the historical read level table HRT. On the other hand, in the case where the current read request does not exist in the previous read request stored in the history buffer, a normal read operation (S112) can be performed. In this case, in the normal read operation, the read operation can be performed at the default read level.

[0113] As a result of a historical read operation or a normal read operation, it may be determined whether UECC occurs (S113). In this case, UECC may indicate that the read data cannot be corrected by the error correction circuit 230 (refer to Figure 1 ) is recovered. In the case that UECC does not occur, the read operation can be terminated immediately.

[0114] On the other hand, when UECC occurs, the OVS defense code may be entered. The OVS mode is basically activated, and the nonvolatile memory device 100 (refer to Figure 1 ) can perform a read retry operation according to the activated OVS mode. In this case, the read retry operation may include an OVS read operation and a main read operation. In this case, the OVS read operation may include a process of detecting a cell count value by applying an OVS read level (S115). For example, the OVS read level may be a default read level. On the other hand, through the OVS read operation, the cell count value, the threshold voltage change information of the selected memory cell, and the degradation information of the memory block including the selected memory cell can be extracted. Therefore, even before performing the main read operation, the OVS detection situation according to the degradation can be determined (S116).

[0115] Thereafter, a main read level for performing the main read operation may be determined based on the result of the OVS read operation. For example, the main read level may be determined by reflecting the change information of the change table VT included in the nonvolatile memory device 100 and the information about the plurality of tables (e.g., OVST) included in the memory controller 200 in the OVS read level for performing the OVS read operation. According to the determined main read level, the main read operation may be performed on the selected memory cell (S119). In detail, the main read level for performing the main read operation may be a read level having a value different from the value of the OVS read level for performing the OVS read operation.

[0116] Thereafter, it may be determined whether the main read operation is passed (S120). As a result of this determination, when the main read operation is passed, the historical read level table HRT may be updated (S121), wherein the offset information corresponding to the detection situation has been reflected using OVST in the historical read level table HRT. However, this is only an example. For example, the update condition of the HRT may be different.

[0117] On the other hand, when the main read operation fails, an off-chip valley search operation may be performed for data recovery (S122). In this case, the off-chip valley search may mean finding a distribution valley by sequentially scanning a predetermined voltage section while increasing or decreasing a predetermined voltage.

[0118] A read operation may be performed according to a distributed valley according to an off-chip valley search operation, and it may be determined whether the result of the read operation has failed (S123). For example, when there is no failure, the read operation may be completed. When the result of the read operation has not failed, the historical read level table HRT may be updated (S121). On the other hand, when the read operation fails, a UECC for a read request from the host may be finally generated. The generated UECC may be output to the host. However, this is merely an example. For example, in the case of a feature of a storage device 10 according to an example embodiment (wherein an OVS read operation and a main read operation are respectively performed using different levels applied to the storage device 10), it may also be possible to perform the operation in a manner different from that in the example embodiment. Fig.13 As an example, the conditions for performing OVS readout operations, etc. may vary.

[0119] Fig.14 is a flowchart illustrating a reading method of a memory device according to example embodiments.

[0120] Fig.14 is a diagram showing a method according to an example embodiment Fig.13 . For example, operations S110 to S113, S115, S116, and S119 to S123 may correspond to Fig.13 On the other hand, refer to Fig.14 , the memory device 10 according to the example embodiment extracts the change information of the word line threshold voltage as a result of the OVS read operation, and can determine whether to update the change table VT (S117) by using the extracted change information. Therefore, after selectively updating the change table VT included in the nonvolatile memory device 100 based on the result of the OVS read operation (S118), the main read operation can be performed. On the other hand, the method of updating the change table VT is not limited to any one, and the change table VT can be updated in various methods.

[0121] FIG. 15A to FIG. 15C is a diagram illustrating a reading method of a memory device according to example embodiments.

[0122] FIG. 15A to FIG. 15C , may be a diagram showing the read level shift for the first detection case to the fifth detection case in the first state R1. As an example, Fig.15A may include an OVST for block read level shifting for a memory block, and Fig. 15B and Fig. 15C It can be a variation table VT according to the degradation degree of the word line threshold voltage. As an example, Fig. 15B and Fig. 15C Can correspond to Fig.12 and Fig.11 part.

[0123] FIG. 16A to FIG. 16C is a diagram illustrating a reading method of a memory device according to example embodiments.

[0124] FIG. 16A to FIG. 16C 1 may be a diagram illustrating a read method of the memory device 10 according to example embodiments when an OVS read operation result corresponds to a second detection case.

[0125] Reference Fig.16A and Fig. 16B , a normal read operation on the first word line WL1 can be performed at a default read level of 2V. At this time, since OVS is in a deactivated state, the change in the read level due to OVST and VT can be 0. On the other hand, when UECC occurs in a normal read operation, OVS can be activated and an OVS read operation can be performed, whereby the situation corresponding to the second detection situation can be derived based on the cell count value obtained by the OVS read operation. Fig.15A and Fig. 15B , in the second detection case, the degradation information value of OVST may be -20 mV, and the variation information value of VT may be -30 mV. Therefore, the optimal read level calculated after performing the OVS read operation may be 1.95 V. Thereafter, the main read operation on the first word line WL1 may be performed at the optimal read level.

[0126] Reference Fig. 16C , after completing the read retry operation on the first word line WL1, the read operation on the second word line WL2 can be continuously performed. However, the second word line WL2 can be read by performing the history read without performing the OVS read operation again. However, since the change table VT is included in the nonvolatile memory device 100 and cannot be reflected in the HRT, in the case of performing the history read only using the HRT, the read operation can only be performed at 1.98V.

[0127] The memory device 10 according to the example embodiment may be configured to input a change flag together with a second read command input to the nonvolatile memory device 100 to perform a read operation on the second word line WL2. For example, the problem that the change table VT is not reflected in the HRT may be solved by using the change flag, and the read operation on the second word line WL2 may be performed at 1.95 V. A description of the change flag will be described later.

[0128] FIG. 17A to FIG. 17C is a diagram illustrating a reading method of a memory device according to example embodiments.

[0129] FIG. 17A to FIG. 17CIt may be a diagram showing a reading method of the memory device 10 according to an example embodiment when the OVS read operation result corresponds to the first detection condition. As an example, referring to Fig.15A and Fig. 15C In the first detection case, the degradation information value of OVST may be -40mV, and the change information value of VT may be -50mV. Other configurations may correspond to FIG. 16A to FIG. 16C Description.

[0130] Therefore, the optimal read level for performing a read operation on the first and second word lines WL1 and WL2 may be 1.91 V. However, since the VT variation information value cannot be stored in the HRT of the memory controller 200 , the read operation on the second word line WL2 may be performed at 1.96 V when only the HRT is reflected.

[0131] As described above, in the memory device 10 according to example embodiments, a change flag may be input together with the second read command input to the nonvolatile memory device 100 to perform a read operation on the second word line WL2 by reflecting the change information value of VT.

[0132] Fig.18 is a flowchart illustrating a reading method of a memory device according to example embodiments.

[0133] Refer to Figure 1 to Figure 1 7. You can Fig.18 As shown in , a read operation of the storage device 10 according to an example embodiment is performed. As an example, Fig.18 It may be a diagram illustrating a second read operation on a second word line after a first read operation on a first word line.

[0134] For example, in response to a request from the memory controller 200 (see Figure 1 ) sends a second read command, the nonvolatile memory device 100 ( Figure 1 ) may perform a second read operation using a second read level (S210). On the other hand, the memory controller 200 may determine whether a UECC is generated as a result of the second read operation (S220). For example, in the case where a UECC has not occurred, the read operation may be completed.

[0135] On the other hand, when UECC has occurred, in response to an OVS command sent from the memory controller 200, another optimal read level may be set by an OVS read operation, and a second read operation (S230) may be performed using the set another optimal read level. In this case, the information corresponding to the read level may include the change information stored in the change table and the offset information in the historical read level table (HRT). On the other hand, the offset information in the HRT may be sent from the memory controller 200 together with the first read command.

[0136] Fig.19 is a ladder diagram illustrating a reading method of a memory device according to example embodiments.

[0137] Refer to Figures 1 to 18 , you can Fig.19 The OVS defense code process of the storage device 10 according to the example embodiment is performed as shown in FIG.

[0138] The memory controller CNTL may send a first read command to the nonvolatile memory device NVM according to the input of the OVS defense code (S10). The nonvolatile memory device NVM may perform a first read operation in response to the first read command. For example, the first read operation may be an OVS operation, and the first read operation may include a first OVS read operation and a first main read operation. The nonvolatile memory device NVM may perform a first OVS read operation at a default read level (S11). The nonvolatile memory device NVM may obtain detection information through the first OVS read operation.

[0139] In the memory device 10 according to the example embodiment, the nonvolatile memory device NVM may change the default read level to the read level for performing the first main read operation using the obtained detection information and the change table VT (S12). However, the embodiment is not limited thereto, and the nonvolatile memory device NVM may change the read level by using OVST together. For example, the first main read operation may be performed at the first main read level (S13), and the data read in the first main read operation may be output to the memory controller CNTL (S14).

[0140] Thereafter, the memory controller CNTL transmits a specific command to the nonvolatile memory device NVM (S15), and the nonvolatile memory device NVM may output detection information corresponding to a detection situation as a result of the first OVS read operation to the memory controller CNTL in response to the specific command (S16).

[0141] On the other hand, the memory controller CNTL may determine whether the error correction circuit cannot be used to perform error correction on the read data (S17). For example, when the data read in the first read operation is error-correctable, the detected information and OVST may be used to update the HRT (S18). However, this is only an example. For example, since the change table VT is stored in the nonvolatile memory device NVM, the HRT may not include information of the change table VT.

[0142] In the memory device 10 according to example embodiments, the first read operation may be an operation on a first memory region connected to a first word line. On the other hand, after the first read operation is completed, a second read operation may be performed on a second memory region connected to a second word line.

[0143] Based on the HRT stored in the memory controller CNTL, a second read command for performing a second read operation on the second memory area may be input to the nonvolatile memory device NVM. On the other hand, a change flag for setting an optimal second read level may be input together with the second read command (S19).

[0144] For example, the change flag may include a signal that causes the nonvolatile memory device NVM to perform a second read operation by reflecting the change information of the second word line threshold voltage. In this article, the signal may also be referred to as a value. Therefore, by using the change flag to reflect the change table VT, the read level of the HRT based on the change information of the second word line threshold voltage that is not reflected can be changed to the best second read level, and the second read operation can be performed at the best second read level (S20). Thereafter, the second read data and detection information read in the second read operation can be sent to the memory controller CNTL (S21).

[0145] Fig. 20 is a ladder diagram illustrating a reading method of a memory device according to example embodiments.

[0146] Refer to Figures 1 to 19 , you can Fig. 20 A read operation of the memory device 10 according to an example embodiment is performed as shown in FIG.

[0147] For example, the host may send a read request together with the address ADD to the memory device 10 (S30). The memory controller 200 of the memory device 10 may receive the read request, search the history buffer, determine whether to perform a history read operation or a normal read operation, and send a normal / historical read command corresponding to the determined operation to the nonvolatile memory device 100 (S31). The nonvolatile memory device 100 may perform a read operation in response to the normal / historical read command, and send the corresponding obtained read data to the memory controller 200 (S32).

[0148] Thereafter, the memory controller 200 may perform an error correction operation on the data read by the error correction circuit 230 (S33). In the case where there is no error or the error is correctable, the read data or the corrected data may be transmitted to the host (S34-1).

[0149] On the other hand, in the case where error correction is impossible, the memory controller 200 may send a read retry command to the nonvolatile memory device 100 (S34-2). The nonvolatile memory device 100 may perform a read operation using an OVS read operation in response to the read retry command, and may send the read data to the memory controller 200 (S35). For example, the nonvolatile memory device 100 may perform a read operation using an OVS read operation in response to the read retry command, and may send the read data to the memory controller 200 (S35). Figures 1 to 19 A series of processes S34 - 2 and S35 for performing a read operation using the OVS read operation are described as described above.

[0150] Thereafter, the memory controller 200 may again perform an error correction operation on the data read by the error correction circuit 230 (S36). For example, when there is no error or the error is correctable, the read data or the corrected data may be sent to the host (S37). When a read retry operation is performed using an OVS read operation as in operations S34-2 to S35, the memory controller 200 may send a specific command to the nonvolatile memory device 100 to obtain read retry information having read level information (S38). The nonvolatile memory device 100 may output retry read information in response to the specific command (S39). However, this is merely an example. For example, when a read retry operation is performed according to an off-chip valley search operation, operations S38 and S39 may be omitted.

[0151] On the other hand, the memory controller 200 may eventually update the historical read level table HRT by using the read retry information (S40). Thereafter, when a read request for the address ADD of the memory area to which the same historical read level is applied is received from the host (S41), the memory controller 200 may send a historical read command using the best read level reflected in the historical read level table HRT to the nonvolatile memory device 100 (S42).

[0152] Fig.21 is a block diagram simply illustrating a storage device according to example embodiments.

[0153] Reference Fig.21 ,and Figure 1 Compared to the storage device shown in , the storage device 20 according to the example embodiment may include an artificial intelligence processor 212 that controls the OVS defense code. The artificial intelligence processor 212 may manage the reliability of the non-volatile memory device 100a using a computing algorithm based on machine learning. For example, the artificial intelligence processor 212 may be used to determine the degree of degradation of the threshold voltage through the OVS circuit 155 included in the non-volatile memory device 100a.

[0154] However, the location of the artificial intelligence processor 212 is not necessarily limited to Fig.21 In addition, the artificial intelligence processor 212 may also be used in the memory controller 200a to determine the degree of degradation of the threshold voltage using the shift information in the historical read level table HRT.

[0155] Fig. 22 is a block diagram illustrating a memory system including a memory device according to example embodiments.

[0156] Reference Fig. 22 , the memory system 30 may include a memory device 100b and a memory controller 200b. The memory system 30 may support a plurality of channels CH1 to CHm, and the memory device 100b and the memory controller 200b may be connected through the plurality of channels CH1 to CHm. For example, the memory system 30 may be implemented as a storage device such as a solid state drive (SSD). The memory system 30 may be implemented to continue as follows Figures 1 to 21 OVS defense code as described in .

[0157] The memory device 100b may include a plurality of nonvolatile memory devices NVM11 to NVMmn. Each of the nonvolatile memory devices NVM11 to NVMmn may be connected to one of the plurality of channels CH1 to CHm in a corresponding manner. For example, the nonvolatile memory devices NVM11 to NVM1n may be connected to the first channel CH1 through lines W11 to W1n, and the nonvolatile memory devices NVM21 to NVM2n may be connected to the second channel CH2 through lines W21 to W2n. In example embodiments, each of the nonvolatile memory devices NVM11 to NVMmn may be implemented as an arbitrary memory unit that can be operated according to a separate command from the memory controller 200b. For example, each of the nonvolatile memory devices NVM11 to NVMmn may be implemented as a chip or a bare core, but the embodiment is not limited thereto.

[0158] The memory controller 200b may transmit / receive signals to / from the memory device 100b through a plurality of channels CH1 to CHm. For example, the memory controller 200b may transmit commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the memory device 100b through the channels CH1 to CHm, or may receive data DATAa to DATAm from the memory device 100b through the channels CH1 to CHm.

[0159] The memory controller 200b may select one of the nonvolatile memory devices connected to the corresponding channel through each channel, and may transmit / receive a signal to / from the selected nonvolatile memory device. For example, the memory controller 200b may select the nonvolatile memory device NVM11 from among the nonvolatile memory devices NVM11 to NVM1n connected to the first channel CH1. The memory controller 200b may transmit a command CMDa, an address ADDRa, and data DATAa to the selected nonvolatile memory device NVM11 through the first channel CH1, or may receive data DATAa from the selected nonvolatile memory device NVM11.

[0160] The memory controller 200b may send / receive signals to / from the memory device 100b in parallel through different channels. For example, the memory controller 200b may send a command CMDa to the memory device 100b through the first channel CH1 while sending a command CMDb to the memory device 100b through the second channel CH2. For example, the memory controller 200b may receive data DATAb from the memory device 100b through the second channel CH2 while receiving data DATAa from the memory device 100b through the first channel CH1.

[0161] The memory controller 200b may control the overall operation of the memory device 100b. The memory controller 200b may send signals to the channels CH1 to CHm to control each of the nonvolatile memory devices NVM11 to NVMmn connected to the channels CH1 to CHm. For example, the memory controller 200b may send a command CMDa and an address ADDRa to the first channel CH1 to control a selected one of the nonvolatile memory devices NVM11 to NVM1n.

[0162] Each of the nonvolatile memory devices NVM11 to NVMmn may operate under the control of the memory controller 200b. For example, the nonvolatile memory device NVM11 may program data DATAa according to the command CMDa, the address ADDRa, and the data DATAa provided to the first channel CH1. For example, the nonvolatile memory device NVM21 may read data DATAb according to the command CMDb and the address ADDRb provided to the second channel CH2, and may transmit the read data DATAb to the memory controller 200b.

[0163] Fig. 22 It is shown that the memory device 100b communicates with the memory controller 200b through m channels, and the memory device 100b includes n nonvolatile memory devices respectively corresponding to each channel. However, the number of channels and the number of nonvolatile memory devices connected to one channel may be variously changed.

[0164] Fig.23 is a diagram illustrating an electronic device including a storage device according to example embodiments.

[0165] Fig.23 The electronic device 1000 may be substantially a mobile system such as a portable communication terminal (eg, a mobile phone), a smart phone, a tablet personal computer (PC), a wearable device, a medical device, or an Internet of Things (IOT) device. However, Fig.23 The electronic device 1000 is not necessarily limited to a mobile system, and may be a personal computer (PC), a laptop computer, a server, a media player, a car device such as a navigation device, or the like.

[0166] Reference Fig.23 , the electronic device 1000 may include a main processor 1100, a memory (e.g., 1200a and 1200b), and a storage device (e.g., 1300a and 1300b). In addition, the electronic device 1000 may include at least one of an image capture device (optical input device) 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0167] The main processor 1100 may control all operations of the electronic device 1000, and in more detail, controls operations of other components included in the electronic device 1000. The main processor 1100 may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

[0168] The main processor 1100 may include at least one CPU core 1110, and also include a controller 1120 configured to control memories 1200a and 1200b and / or storage devices 1300a and 1300b. In some embodiments, the main processor 1100 may also include an accelerator block 1130, which is a dedicated circuit for high-speed data operations (e.g., artificial intelligence (AI) data operations). The accelerator block 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may be implemented as a chip physically separated from other components of the main processor 1100.

[0169] The memories 1200a and 1200b may be used as a main memory device of the electronic device 1000. Although each of the memories 1200a and 1200b may include a volatile memory such as a static random access memory (SRAM) and / or a dynamic RAM (DRAM), each of the memories 1200a and 1200b may also include a non-volatile memory such as a flash memory, a phase change RAM (PRAM) and / or a resistive RAM (RRAM). The memories 1200a and 1200b may be implemented in the same package as the main processor 1100.

[0170] The storage devices 1300a and 1300b may be used as nonvolatile memory devices configured to store data regardless of whether power is supplied thereto, and have a larger storage capacity than the memories 1200a and 1200b. The storage devices 1300a and 1300b may include storage memory controllers 1310a and 1310b, respectively, and nonvolatile memories (NVMs) 1320a and 1320b that store data under the control of the storage memory controllers 1310a and 1310b. Although the NVMs 1320a and 1320b may include V-NAND flash memories having a two-dimensional (2D) structure or a three-dimensional (3D) structure, the NVMs 1320a and 1320b may include other types of NVMs, such as PRAM and / or RRAM.

[0171] The storage devices 1300a and 1300b may be physically separated from the main processor 1100 and included in the electronic device 1000 or implemented in the same package as the main processor 1100. In addition, the storage devices 1300a and 1300b may have a type of solid-state device (SSD) or memory card and be removably combined with other components of the electronic device 1000 through an interface such as the connection interface 1480 to be described below. The storage devices 1300a and 1300b may be devices to which a standard protocol such as Universal Flash Storage (UFS), Embedded Multimedia Card (eMMC), or Non-Volatile Memory Express (NVMe) is applied, but are not limited thereto.

[0172] The image capture device 1410 may capture a still image or a moving image. The image capture device 1410 may include a camera, a video camera, and / or a webcam.

[0173] The user input device 1420 may receive various types of data input by a user of the electronic device 1000 and include a touch pad, a keypad, a keyboard, a mouse, and / or a microphone.

[0174] The sensor 1430 may detect various types of physical quantities that may be obtained from the outside of the electronic device 1000 and convert the detected physical quantities into electrical signals. The sensor 1430 may include a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyro sensor.

[0175] The communication device 1440 may transmit and receive signals between other devices outside the electronic device 1000 according to various communication protocols. The communication device 1440 may be implemented to include an antenna, a transceiver, and / or a modem.

[0176] The display 1450 and the speaker 1460 may serve as output devices configured to output visual information and auditory information, respectively, to a user of the electronic device 1000 .

[0177] The power supply device 1470 may appropriately convert power supplied from a battery embedded in the electronic device 1000 and / or an external power source and supply the converted power to each component of the electronic device 1000 .

[0178] The connection interface 1480 may provide a connection between the electronic device 1000 and an external device that is connected to the electronic device 1000 and is capable of transmitting and receiving data to and from the electronic device 1000. The connection interface 1480 may be implemented using various interface schemes such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), NVMe, IEEE1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, Multimedia Card (MMC) interface, eMMC interface, UFS interface, Embedded UFS (eUFS) interface, and Compact Flash (CF) card interface.

[0179] As described above, the nonvolatile memory device according to the example embodiment may include a variation table including variation information according to degradation of the word line threshold voltage. On the other hand, the nonvolatile memory device may internally set the variation information based on the X / Y cell count according to the on-chip valley search (OVS) operation. Therefore, the correction accuracy of the degradation of the word line threshold voltage can be improved, and the memory usage of the memory controller can be reduced.

[0180] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A non-volatile memory device, comprising: a memory block including a first memory region connected to a first word line; as well as Control logic, which includes: an on-chip valley search (OVS) circuit configured to perform an OVS read operation on the memory block; and a first buffer memory configured to store at least one variation table including variation information of threshold voltages of memory cells connected to the first word line obtained from the OVS read operation, Wherein, the control logic is configured as follows: A first read operation is performed on the first memory area in response to a first read command applied by a memory controller, the first read operation including a first OVS read operation in response to the first read command and a first main read operation, the first OVS read operation is performed at a first OVS read level, and the first main read operation is performed at a first main read level reflecting the change information.

2. The nonvolatile memory device according to claim 1, wherein: The control logic is further configured to determine a weight reflecting the change information included in the at least one change table based on a detection situation according to the first OVS read operation.

3. The nonvolatile memory device according to claim 2, wherein: A first weight reflecting change information provided when the detected situation is an edge situation is higher than a second weight reflecting change information provided when the detected situation is not the edge situation.

4. The nonvolatile memory device according to claim 1, wherein: The control logic also includes selection logic configured to select at least one of the at least one variation table based on a result of the first OVS read operation.

5. The nonvolatile memory device according to claim 4, wherein: The selection logic is further configured to select one of the at least one change table based on a detection condition according to the first OVS read operation, and The first main readout level at which the first main readout operation is performed is a read level reflecting the variation information included in the selected at least one variation table.

6. The nonvolatile memory device according to claim 1, wherein: The control logic is further configured to selectively update the at least one variation table based on a result of the first OVS read operation.

7. The nonvolatile memory device according to claim 1, wherein: The memory block also includes a second memory region connected to a second word line, and The control logic is further configured to input a second read command determined based on a historical read level table stored in the memory controller to the second memory area after the first read operation on the first memory area is completed.

8. The nonvolatile memory device according to claim 7, wherein: The at least one variation table further includes variation information of threshold voltages of memory cells connected to the second word line, and The control logic is further configured to perform a second read operation at a read level reflecting the change information.

9. The nonvolatile memory device according to claim 1, wherein: The first OVS readout level at which the first OVS readout operation is to be performed has a different value from the first main readout level.

10. The nonvolatile memory device of claim 9, wherein the first OVS read level is a default read level.

11. A memory controller comprising: processor; a control pin configured to provide a control signal to at least one nonvolatile memory device including a first memory region connected to a first word line; an error correction circuit configured to correct data read from the at least one nonvolatile memory device based on the control signal; as well as a buffer memory configured to store a plurality of tables for compensating a read level of a read operation of the at least one nonvolatile memory device, wherein the processor is configured to input a first read command, the first read command being used to perform a first read operation on the first memory area using at least one change table stored in the at least one non-volatile memory device, wherein the plurality of tables include a historical read level table, and the processor is further configured to update the historical read level table when error correction of the data read by the first read operation succeeds, wherein the at least one nonvolatile memory device further comprises a second memory region connected to a second word line; and the processor is further configured to input a second read command for performing a second read operation on the second memory region to the at least one nonvolatile memory device based on the historical read level table, The processor is further configured to input a change flag together with the second read command to the at least one non-volatile memory device, and The change flag includes a signal that allows the at least one nonvolatile memory device to perform the second read operation by reflecting change information of a threshold voltage of a memory cell connected to the second word line, and the at least one change table includes the change information.

12. The memory controller according to claim 11, further comprising a command selector configured to select a read command based on the historical read level table, the read command to be input to the nonvolatile memory device, in, The read command is configured to adjust information of the at least one change table used in the first read operation of the non-volatile memory device.

13. A method for reading a storage device, the method comprising: In at least one nonvolatile memory device, in response to a first read command received from a memory controller, performing a first on-die valley search (OVS) read operation on selected memory cells; extracting threshold voltage variation information of a selected memory cell and degradation information of a memory block including the selected memory cell; performing a first main read operation at a modified read level based on the variation information and the degradation information; as well as outputting the result of the first OVS read operation and the data of the first master read operation to the memory controller, The first OVS readout operation and the first main readout operation are defined as a first read operation.

14. The method for reading a storage device according to claim 13, wherein: The change information is included in at least one change table stored in the at least one non-volatile memory device. 15 . The reading method of the memory device according to claim 13 , further comprising performing a second reading operation on other selected memory cells by receiving a second reading command after terminating the first reading operation, and outputting second reading data.

16. The method for reading a storage device according to claim 15, wherein: The second read command is output together with a change flag, and The change flag includes a signal for performing the second read operation using change information of threshold voltages of the other selected memory cells included in the at least one nonvolatile memory device. 17 . The storage device reading method according to claim 13 , further comprising updating a history reading level table based on the degradation information after terminating the first reading operation.

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