Methods for improving uniformity of hard mask after etching

Abstract

The present invention provides a method for improving the uniformity of a hard mask after etching, providing a substrate, on which a second oxide layer, a gate, and first to third hard mask layers are stacked in sequence from bottom to top are formed; the third hard mask layer and the second and first hard mask layers below it are opened by photolithography and etching, so that part of the gate is exposed, and then the photoresist layer and the anti-reflective coating are removed; with a high selectivity of the gate relative to the second and third hard mask layers, the exposed gate is etched to form a groove, so that part of the third hard mask layer on the first hard mask layer is removed; with a low selectivity of the gate relative to the third hard mask layer and a high selectivity of the third hard mask layer relative to the second hard mask layer, the third hard mask layer and the second hard mask layer are etched, so that the remaining third hard mask layer is completely removed. The present invention improves the load difference of the residual hard mask layer by changing the structure of the hard mask layer and optimizing the selectivity in the gate etching step.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a method for improving the uniformity of a hard mask after etching. Background Art

[0002] In the current 28nm HV / HK (high voltage / high K dielectric) process, gate etching has a large difference in the thickness of the remaining hard mask layer after etching due to the difference in gate load. This greatly affects the subsequent grinding process. Currently, this load difference is eliminated by adding an additional layer of back etching mask, but the process window is still small.

[0003] Therefore, a method for improving the uniformity of hard mask after etching is needed. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for improving the uniformity of hard mask etching, which is used to solve the problem in the prior art that the thickness of the remaining hard mask layer after etching varies greatly due to the difference in gate loads.

[0005] To achieve the above-mentioned purpose and other related purposes, the present invention provides a method for improving the uniformity of hard mask after etching, comprising:

[0006] Step 1, providing a substrate, on which a second oxide layer, a gate, a first hard mask layer, a second hard mask layer, and a third hard mask layer are sequentially stacked from bottom to top;

[0007] Step 2: opening the third hard mask layer and the second hard mask layer and the first hard mask layer thereunder by photolithography and etching, so that part of the gate is exposed, and then removing the photoresist layer and the anti-reflective coating;

[0008] Step 3, etching the exposed gate to form a groove with a high selectivity of the gate relative to the second hard mask layer and the third hard mask layer, so that the third hard mask layer on a portion of the first hard mask layer is removed, and a portion of the third hard mask layer is retained on another portion of the first hard mask layer;

[0009] Step 4: Etch the third hard mask layer and the second hard mask layer with a low selectivity of the gate relative to the third hard mask layer and a high selectivity of the third hard mask layer relative to the second hard mask layer, so that the remaining third hard mask layer is completely removed and the groove is connected to the second oxide layer.

[0010] Preferably, the substrate in step one is a silicon substrate.

[0011] Preferably, in step 1, materials of the second oxide layer and the second hard mask layer are both silicon dioxide.

[0012] Preferably, the material of the gate in step 1 is polysilicon.

[0013] Preferably, in step 1, the materials of the first hard mask layer and the third hard mask layer are both silicon nitride.

[0014] Preferably, in step 2, the method of opening the third hard mask layer and the second hard mask layer and the first hard mask layer thereunder by photolithography and etching is:

[0015] Sequentially forming a stacked APF film, a nitrogen-free dielectric anti-reflective coating and the photoresist layer on the third hard mask layer;

[0016] Opening a portion of the photoresist layer by photolithography to expose the nitrogen-free dielectric anti-reflective coating thereunder, and then etching the exposed nitrogen-free dielectric anti-reflective coating to expose the APF film thereunder;

[0017] The exposed APF film is etched to expose the third hard mask layer thereunder, and then the exposed third hard mask layer and the second hard mask layer and the first hard mask layer thereunder are etched until the gate thereunder is exposed, and then the APF film is removed.

[0018] Preferably, the etching method in step three is dry etching.

[0019] Preferably, the etching method in step 4 is dry etching.

[0020] Preferably, the method is used in a process of a 28 nanometer technology node.

[0021] Preferably, the method is used in a manufacturing process of a high-voltage high-K device.

[0022] As described above, the method of improving the uniformity of the hard mask after etching of the present invention has the following beneficial effects:

[0023] The present invention improves the load difference of the residual hard mask layer by changing the structure of the hard mask layer and optimizing the selection ratio in the gate etching step. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Shown is a schematic diagram of the photolithography of the present invention;

[0025] Figure 2 Shown is a schematic diagram of etching a nitrogen-free dielectric anti-reflective coating according to the present invention;

[0026] Figure 3 Shown is a schematic diagram of etching the APF film of the present invention;

[0027] Figure 4It is a schematic diagram showing etching the first to third hard mask layers of the present invention;

[0028] Figure 5 Shown is a schematic diagram of removing the APF film of the present invention;

[0029] Figure 6 It is a schematic diagram of etching the gate electrode for the first time according to the present invention;

[0030] Figure 7 It is a schematic diagram of etching the gate for the second time according to the present invention;

[0031] Figure 8 Shown is a schematic diagram of the process flow of the present invention. DETAILED DESCRIPTION

[0032] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] See also Figure 8 The present invention provides a method for improving the uniformity of a hard mask after etching, comprising:

[0034] Step 1, providing a substrate 01, on which a second oxide layer 02, a gate 03, a first hard mask layer 04, a second hard mask layer 05, and a third hard mask layer 06 are sequentially stacked from bottom to top are formed;

[0035] In an embodiment of the present invention, the substrate 01 in step 1 is a silicon substrate.

[0036] In an embodiment of the present invention, in step 1, the materials of the second oxide layer 02 and the second hard mask layer 05 are both silicon dioxide.

[0037] In an embodiment of the present invention, the material of the gate 03 in step 1 is polysilicon.

[0038] In an embodiment of the present invention, the materials of the first hard mask layer 04 and the third hard mask layer 06 in step 1 are both silicon nitride.

[0039] That is, the hard mask layer in the prior art is usually a stacked oxide layer and a nitride layer, and the structure of the hard mask is adjusted to a bottom nitride layer, an oxide layer and a top nitride layer which are deposited in sequence.

[0040] Step 2: Open the third hard mask layer 06 and the second hard mask layer 05 and the first hard mask layer 04 thereunder by photolithography and etching, so that part of the gate 03 is exposed, and then remove the photoresist layer 09 and the anti-reflective coating;

[0041] In an embodiment of the present invention, the method of opening the third hard mask layer 06 and the second hard mask layer 05 and the first hard mask layer 04 thereunder by photolithography and etching in step 2 is:

[0042] An APF film 07, a nitrogen-free dielectric anti-reflective coating 08 and a photoresist layer 09 are sequentially stacked on the third hard mask layer 06;

[0043] A portion of the photoresist layer 09 is opened by photolithography to expose the nitrogen-free dielectric anti-reflective coating 08 underneath, and the following is obtained: Figure 1 The structure shown in FIG. 1 is then etched to expose the exposed nitrogen-free dielectric anti-reflection coating 08, so that the APF film 07 underneath is exposed, and the structure shown in FIG. 1 is obtained. Figure 2 The structure shown;

[0044] The exposed APF film 07 is etched to expose the third hard mask layer 06 thereunder, and the following is obtained: Figure 3 The structure shown in FIG. 1 is obtained by removing the photoresist layer 09 at this time, and then etching the exposed third hard mask layer 06 and the second hard mask layer 05 and the first hard mask layer 04 thereunder until the gate 03 thereunder is exposed, and obtaining the structure shown in FIG. Figure 4 The structure shown in FIG. 1 is then removed, and the APF (advanced patterning film) film 07 is obtained. Figure 5 The structure shown.

[0045] Step 3, see Figure 6 , with a high selectivity of the gate 03 relative to the second hard mask layer 05 and the third hard mask layer 06, the exposed gate 03 is etched to form a groove, so that the third hard mask layer 06 on a portion of the first hard mask layer 04 is removed, and due to the difference in load, a portion of the third hard mask layer 06 is retained on another portion of the first hard mask layer 04. At this time, due to the arrangement of the first to third hard mask layers, the thickness of the second hard mask layer 05 is smaller than that in the prior art;

[0046] In an embodiment of the present invention, the etching method in step three is dry etching.

[0047] Step 4, see Figure 7, with a low selectivity of the gate 03 relative to the third hard mask layer 06 and a high selectivity of the third hard mask layer 06 relative to the second hard mask layer 05, the third hard mask layer 06 and the second hard mask layer 05 are etched, so that the remaining third hard mask layer 06 is completely removed. That is to say, after the third hard mask layer 06 is completely removed, the thickness of the second hard mask layer 05 is thinner, and the height difference between the second hard mask layers 05 is smaller, thereby reducing the load difference, improving the process window, having less impact on subsequent grinding, and the groove is connected to the second oxide layer 02.

[0048] In an embodiment of the present invention, the etching method in step 4 is dry etching.

[0049] In an embodiment of the present invention, the method is used in a process of 28 nanometer technology node.

[0050] In an embodiment of the present invention, a method is used in a manufacturing process of a high-voltage high-K device.

[0051] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0052] In summary, the present invention improves the load difference of the residual hard mask layer by changing the structure of the hard mask layer and optimizing the selectivity in the gate etching step. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0053] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for improving the uniformity of a hard mask after etching, characterized in that: At least: Step 1, providing a substrate, on which a second oxide layer, a gate, and first to third hard mask layers are sequentially stacked from bottom to top are formed; Step 2: opening the third hard mask layer and the second hard mask layer and the first hard mask layer thereunder by photolithography and etching, so that part of the gate is exposed, and then removing the photoresist layer and the anti-reflective coating; Step 3, etching the exposed gate to form a groove with a high selectivity of the gate relative to the second and third hard mask layers, so that the third hard mask layer on a portion of the first hard mask layer is removed, and a portion of the third hard mask layer is retained on another portion of the first hard mask layer; Step 4: Etch the third hard mask layer and the second hard mask layer with a low selectivity of the gate relative to the third hard mask layer and a high selectivity of the third hard mask layer relative to the second hard mask layer, so that the remaining third hard mask layer is completely removed and the groove is connected to the second oxide layer.

2. The method for improving uniformity of hard mask after etching according to claim 1, characterized in that: The substrate in step one is a silicon substrate.

3. The method for improving uniformity of hard mask after etching according to claim 1, characterized in that: In step 1, the materials of the second oxide layer and the second hard mask layer are both silicon dioxide.

4. The method for improving uniformity of hard mask after etching according to claim 1, characterized in that: The material of the gate in step 1 is polysilicon.

5. The method for improving uniformity of hard mask after etching according to claim 1, characterized in that: In step 1, the materials of the first hard mask layer and the third hard mask layer are both silicon nitride.

6. The method for improving uniformity of hard mask after etching according to claim 1, characterized in that: The method for opening the third hard mask layer and the second hard mask layer and the first hard mask layer thereunder by photolithography and etching in step 2 is as follows: forming a stacked APF film, a nitrogen-free dielectric anti-reflective coating and the photoresist layer in sequence on the third hard mask layer; opening part of the photoresist layer by photolithography to expose the nitrogen-free dielectric anti-reflective coating thereunder, and then etching the exposed nitrogen-free dielectric anti-reflective coating to expose the APF film thereunder; etching the exposed APF film to expose the third hard mask layer thereunder, and then etching the exposed third hard mask layer and the second hard mask layer and the first hard mask layer thereunder until the gate thereunder is exposed, and then removing the APF film.

7. The method for improving uniformity of hard mask after etching according to claim 1, characterized in that: The etching method described in step three is dry etching.

8. The method for improving uniformity of hard mask after etching according to claim 1, characterized in that: The etching method described in step 4 is dry etching.

9. The method for improving uniformity of hard mask after etching according to claim 1, characterized in that: The method is used in a process of 28 nanometer technology node.

10. The method for improving uniformity of hard mask after etching according to claim 1, characterized in that: The method is used for the manufacturing process of high-voltage high-K devices.

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