Semiconductor structure and method of forming the same

Abstract

The present disclosure relates to a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises the following steps: forming a stack layer on a top surface of a substrate, the stack layer comprising a plurality of semiconductor layers arranged at intervals along a first direction, the stack layer comprising a transistor region, a capacitor region and a bit line region; forming a capacitor extending along the second direction in the capacitor region; forming a word line extending along the first direction in the transistor region; forming a bit line extending along the third direction in the bit line region. The present disclosure can improve the integration of the semiconductor structure, increase the storage density of the semiconductor structure and improve the performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the transistor to turn on and off, thereby allowing data information stored in the capacitor to be read or written to the capacitor via the bit line.

[0003] DRAM and other semiconductor structures mostly adopt two-dimensional structures, which results in low storage density and integration, making it difficult to meet the semiconductor storage capacity requirements of different fields.

[0004] Therefore, how to improve the integration level of semiconductor structures, thereby improving their performance, is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This disclosure provides semiconductor structures and methods for forming the same in some embodiments, which are used to solve the problem of low integration density of semiconductor structures, thereby improving the storage density and performance of semiconductor structures.

[0006] According to some embodiments, this disclosure provides a method for forming a semiconductor structure, including the following steps:

[0007] A stacked layer is formed on the top surface of a substrate. The stacked layer includes a plurality of semiconductor layers spaced apart along a first direction. The stacked layer includes a transistor region and a capacitor region and a bit line region distributed on opposite sides of the transistor region along a second direction. The semiconductor layers of the transistor region and the capacitor region include semiconductor pillars spaced apart along a third direction. The first direction is perpendicular to the top surface of the substrate. The second direction and the third direction are both parallel to the top surface of the substrate, and the second direction intersects the third direction.

[0008] A capacitor extending along the second direction is formed between two adjacent semiconductor layers within the capacitor region;

[0009] A word line is formed in the transistor region, the word line extending along the first direction and continuously covering the semiconductor pillars spaced apart along the first direction;

[0010] A bit line is formed in the bit line region, the bit line extending along the third direction and covering the surface of the semiconductor layer.

[0011] In some embodiments, the specific steps of forming the stacked layer on the top surface of the substrate include:

[0012] Provide substrate;

[0013] The first sacrificial layer and the semiconductor layer are alternately formed on the top surface of the substrate along the first direction to form the stacked layer;

[0014] The transistor region and the capacitor region of the stacked layer are etched to form a plurality of first trenches exposing the substrate, and the first trenches separate the semiconductor layer of the transistor region and the capacitor region into semiconductor pillars spaced apart along the third direction.

[0015] In some embodiments, the semiconductor layer is made of silicon material including doped ions, and the first sacrificial layer is made of silicon germanide.

[0016] In some embodiments, the specific steps of forming a capacitor extending along the second direction between two adjacent semiconductor layers within the capacitor region include:

[0017] The first sacrificial layer of the capacitor region and the transistor region is removed to form a first gap between two adjacent semiconductor layers in the capacitor region and a second gap between two adjacent semiconductor layers in the transistor region.

[0018] In some embodiments, the stacked layer includes two transistor regions distributed along the second direction on opposite sides of the bit line region, and the side of the transistor region facing away from the bit line region has the capacitor region; the specific steps for removing the first sacrificial layer of the capacitor region and the transistor region include:

[0019] Remove the first sacrificial layer from all said capacitor regions and all said transistor regions.

[0020] In some embodiments, the specific steps for removing the first sacrificial layer from the capacitor region and the transistor region include:

[0021] A second sacrificial layer is formed covering the top surface of the stacked layers;

[0022] The first sacrificial layer of the capacitor region and the transistor region is removed using a lateral etching process.

[0023] In some embodiments, the first gap is connected to the second gap; the specific steps of forming a capacitor extending along the second direction between two adjacent semiconductor layers within the capacitor region include:

[0024] A lower electrode layer is formed that continuously covers the inner walls of the first and second gaps;

[0025] A dielectric layer is formed covering the surface of the lower electrode layer;

[0026] An upper electrode layer is formed covering the surface of the dielectric layer;

[0027] A common electrode layer is formed covering the surface of the upper electrode layer;

[0028] The lower electrode layer, the dielectric layer, the upper electrode layer, and the common electrode layer located in the second gap are removed, and the lower electrode layer, the dielectric layer, the upper electrode layer, and the common electrode layer remaining in the first gap form the capacitor.

[0029] In some embodiments, the semiconductor pillar located in the transistor region includes a channel region, and source and drain regions distributed on opposite sides of the channel region along the second direction, wherein the source region is adjacent to the bit line region and the drain region is adjacent to the capacitor region; the specific steps of forming a word line in the transistor region include:

[0030] A first isolation layer covering the source region and the drain region is formed within the second gap;

[0031] The word line is formed within the second gap, and the word line extends along the first direction and continuously covers the channel areas that are spaced apart along the first direction.

[0032] In some embodiments, the specific steps of forming a first isolation layer covering the source region and the drain region within the second gap include:

[0033] A first isolation layer is formed to fill the second gap;

[0034] Remove the first isolation layer covering the trench area to expose the trench area.

[0035] In some embodiments, before forming the word line within the second gap, the following steps are further included:

[0036] A gate dielectric layer is formed covering the channel region.

[0037] In some embodiments, before forming a bit line in the bit line region, the following steps are further included:

[0038] The first sacrificial layer in the bit line region is removed by a lateral etching process to form a third gap between two adjacent semiconductor layers in the bit line region.

[0039] In some embodiments, the specific steps for forming a bit line in the bit line region include:

[0040] A metal material is deposited along the third gap on the surface of the semiconductor layer to form the bit line, which is a metal silicide.

[0041] The bit lines are annealed.

[0042] In some embodiments, the specific steps for forming the bit line, which is a metal silicide, include:

[0043] Metal material is deposited along the third gap on the upper surface of the semiconductor layer and on the lower surface opposite to the upper surface, wherein the upper surface is the surface of the semiconductor layer facing away from the substrate;

[0044] The stacked layer is heat-treated to form the bit line, the bit line including a first sub-bit line covering the upper surface and a second sub-bit line covering the lower surface, wherein the thickness of the semiconductor layer remaining between the first sub-bit line and the second sub-bit line along the first direction is less than the thickness of the semiconductor pillar along the first direction.

[0045] In some embodiments, after forming a bit line in the bit line region, the following steps are further included:

[0046] A second isolation layer is formed between two adjacent bit lines.

[0047] According to other embodiments, this disclosure also provides a semiconductor structure formed using the semiconductor structure formation method described in any of the preceding embodiments.

[0048] This disclosure provides semiconductor structures and methods for forming the same, which are achieved by forming a stacked layer on the top surface of a substrate. The stacked layer includes multiple semiconductor layers spaced apart along a direction perpendicular to the top surface of the substrate, and each semiconductor layer includes multiple semiconductor pillars spaced apart along a direction parallel to the top surface of the substrate. This results in a three-dimensional array of semiconductor pillars in the stacked layer. Subsequently, by forming horizontal capacitors, vertical word lines, and horizontal bit lines, the traditional two-dimensional semiconductor structure is transformed into a three-dimensional semiconductor structure. This improves the integration density of the semiconductor structure, increases its storage density, and enhances its performance. Furthermore, the bit lines in this disclosure extend along a direction parallel to the top surface of the substrate, and multiple bit lines are spaced apart along a direction perpendicular to the top surface of the substrate. This allows for the use of various materials to form the bit lines, improving the flexibility of the bit line fabrication process and helping to reduce the resistance of the bit lines, thereby further improving the performance of the semiconductor structure. Attached Figure Description

[0049] Appendix Figure 1 This is a flowchart of a method for forming a semiconductor structure according to a specific embodiment of this disclosure;

[0050] Appendix Figure 2A-2T This is a schematic diagram of the main process structure in the formation of the semiconductor structure according to the specific embodiments of this disclosure. Detailed Implementation

[0051] The specific embodiments of the semiconductor structure and its formation method provided in this disclosure will be described in detail below with reference to the accompanying drawings.

[0052] This specific embodiment provides a method for forming a semiconductor structure, with appended... Figure 1 This is a flowchart illustrating the method for forming a semiconductor structure according to a specific embodiment of this disclosure, with appended... Figure 2A-2T This is a schematic diagram of the main process structure during the formation of the semiconductor structure in a specific embodiment of this disclosure. The semiconductor structure described in this embodiment can be, but is not limited to, DRAM. For example... Figure 1 , Figures 2A-2T As shown, the method for forming the semiconductor structure includes the following steps:

[0053] Step S11: A stacked layer 21 is formed on the top surface of the substrate 20. The stacked layer 21 includes a plurality of semiconductor layers 212 spaced apart along a first direction D1. The stacked layer 21 includes a transistor region and a capacitor region and a bit line region distributed on opposite sides of the transistor region along a second direction D2. The semiconductor layers 212 of the transistor region and the capacitor region include semiconductor pillars 30 spaced apart along a third direction D3. The first direction D1 is perpendicular to the top surface of the substrate 20, and the second direction D2 and the third direction D3 are both parallel to the top surface of the substrate 20, and the second direction D2 intersects the third direction D3. Figure 2D As shown. Among them, Figure 2D (a) in the diagram is a top view of the structure. Figure 2D (b) in the diagram is a cross-sectional view of (a) at position AA.

[0054] In some embodiments, the specific steps of forming the stacked layer 21 on the top surface of the substrate 20 include:

[0055] Substrate 20 is provided;

[0056] A first sacrificial layer 211 and a semiconductor layer 212 are alternately formed on the top surface of the substrate 20 along the first direction D1 to form the stacked layer 21, as shown below. Figure 2A As shown, where, Figure 2A (a) in the diagram is a top view of the structure. Figure 2A (b) in the diagram is a cross-sectional view of (a) at position AA;

[0057] The transistor region and the capacitor region of the stacked layer 21 are etched to form a plurality of first trenches exposing the substrate 20, and the first trenches divide the semiconductor layer 212 of the transistor region and the capacitor region into semiconductor pillars 30 spaced apart along the third direction D3, such as Figure 2D As shown.

[0058] Specifically, the substrate 20 may be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example for illustration. In other examples, the substrate 20 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The top surface of the substrate 20 refers to the surface of the substrate 20 used to form the stacked layer 21. The substrate 20 is used to support the device structure on it. In one embodiment, the first sacrificial layer 211 and the semiconductor layer 212 can be alternately formed along the first direction D1 on the top surface of the substrate 20 by epitaxial growth or atomic layer deposition to form the stacked layer 21, such as... Figure 2AAs shown. The number of alternating layers of the first sacrificial layer 211 and the semiconductor layer 212 in the stacked layer 21 can be selected by those skilled in the art according to actual needs. The more alternating layers of the first sacrificial layer 211 and the semiconductor layer 212 in the stacked layer 21, the larger the storage capacity of the formed semiconductor structure. Then, a second sacrificial layer is deposited on the top surface of the stacked layer 21. The second sacrificial layer can be a single-layer structure or a multi-layer structure. In one embodiment, the second sacrificial layer includes a first pad layer 22 covering the top surface of the stacked layer 21 and a second pad layer 23 located on the top surface of the first pad layer 22, such as... Figure 2B As shown, where, Figure 2B (a) in the diagram is a top view of the structure. Figure 2B (b) in the diagram is a cross-sectional view of (a) at position AA.

[0059] Next, a patterned first photoresist layer 24 is formed on the surface of the second pad layer 23, such as... Figure 2C As shown, where, Figure 2C (a) in the diagram is a top view of the structure. Figure 2C (b) is a cross-sectional view of (a) at position AA. The first photoresist layer 24 has a first opening 241 exposing the second pad layer 23 above the transistor region and the capacitor region. The transistor region and the capacitor region in the second pad layer 23, the first pad layer 22, and the stacked layer 21 are etched downwards along the first opening 241, forming a plurality of first trenches penetrating the stacked layer 21 along the first direction D1. The semiconductor layer 212 of the transistor region and the capacitor region is separated into a plurality of semiconductor pillars 30 spaced apart along the third direction D3 by the plurality of first trenches, and the first sacrificial layer 211 of the transistor region and the capacitor region is separated into a plurality of sacrificial pillars 31 spaced apart along the third direction D3, as shown below. Figure 2D As shown. The first pad layer 22 and the second pad layer 23 serve to improve the morphology of the first trench and also to protect the top semiconductor layer 212 of the stacked layers 21 from damage caused by the etching process. The material of the first pad layer 22 may be, but is not limited to, an oxide material (e.g., silicon dioxide), and the material of the second pad layer 23 may be, but is not limited to, a nitride material (e.g., silicon nitride). In this specific embodiment, "multiple" refers to two or more.

[0060] In this specific embodiment, the semiconductor layer 212 of the transistor region and the capacitor region is separated into a plurality of semiconductor pillars 30 arranged at intervals along the third direction D3 by etching. The semiconductor layer 212 of the bit line region is not etched, that is, the semiconductor layer 212 of the bit line region is continuously distributed along the third direction D3 and is not separated.

[0061] In some embodiments, the semiconductor layer 212 is made of silicon material including doped ions, and the first sacrificial layer 211 is made of silicon germanide. The doped ions can be, but are not limited to, phosphorus ions. By using silicon material including doped ions to form the semiconductor layer 212, subsequent doping is eliminated when forming the channel region, source region, and drain region in the transistor, thereby simplifying the semiconductor structure formation process. The silicon material including doped ions has a higher etch selectivity ratio than silicon germanide, facilitating the selective removal of the first sacrificial layer 211 without damaging the semiconductor layer 212.

[0062] Step S12, a capacitor extending along the second direction D2 is formed between two adjacent semiconductor layers 212 within the capacitor region, as shown below. Figure 2H As shown, where, Figure 2H (a) in the diagram is a top view of the structure. Figure 2H (b) in the diagram is a cross-sectional view of (a) at position AA.

[0063] In some embodiments, the specific steps of forming a capacitor extending along the second direction D2 between two adjacent semiconductor layers 212 within the capacitor region include:

[0064] The first sacrificial layer 211 of the capacitor region and the transistor region is removed to form a first gap 25 between two adjacent semiconductor layers 212 in the capacitor region and a second gap 32 between two adjacent semiconductor layers 212 in the transistor region, as shown below. Figure 2E As shown, where, Figure 2E (a) in the diagram is a top view of the structure. Figure 2E (b) in the diagram is a cross-sectional view of (a) at position AA.

[0065] In some embodiments, the stacked layer 21 includes two transistor regions distributed along the second direction D2 on opposite sides of the bit line region, and the side of the transistor region facing away from the bit line region has the capacitor region; the specific steps for removing the first sacrificial layer 211 of the capacitor region and the transistor region include:

[0066] Remove the first sacrificial layer 211 from all said capacitor regions and all said transistor regions.

[0067] In some embodiments, the specific steps for removing the first sacrificial layer 211 from the capacitor region and the transistor region include:

[0068] A second sacrificial layer is formed covering the top surface of the stacked layer 21;

[0069] The first sacrificial layer 211 of the capacitor region and the transistor region is removed by a lateral etching process.

[0070] Specifically, by setting a bit line region in the stacked layer 21, and setting a transistor region on each side of the bit line region along the second direction D2, and setting a capacitor region on the side of each transistor region away from the bit line region, two subsequently formed transistors can share a bit line, thereby further reducing the volume of the semiconductor structure and improving its integration density. Forming a second sacrificial layer covering the top surface of the stacked layer 21 avoids damage to the semiconductor layer 212 on top of the stacked layer 21 during the etching process. The first sacrificial layer 211, which removes the capacitor region and the transistor region, is removed using a lateral etching process, eliminating the need for a mask layer, simplifying the semiconductor structure fabrication process, and reducing the manufacturing cost of the semiconductor structure.

[0071] In some embodiments, the first gap 25 is connected to the second gap 32; the specific steps of forming a capacitor extending along the second direction D2 between two adjacent semiconductor layers 211 within the capacitor region include:

[0072] A lower electrode layer 261 is formed that continuously covers the inner wall of the first gap 25 and the inner wall of the second gap 32;

[0073] A dielectric layer 262 is formed covering the surface of the lower electrode layer 261;

[0074] An upper electrode layer 263 is formed covering the surface of the dielectric layer 262, such as... Figure 2F The above, wherein Figure 2F (a) in the diagram is a top view of the structure. Figure 2F (b) in the diagram is a cross-sectional view of (a) at position AA;

[0075] A common electrode layer 27 is formed covering the surface of the upper electrode layer 263, such as... Figure 2H As shown;

[0076] The lower electrode layer 261, the dielectric layer 262, the upper electrode layer 263, and the common electrode layer 27 located within the second gap 32 are removed. The remaining lower electrode layer 261, dielectric layer 262, upper electrode layer 263, and common electrode layer 27 within the first gap 25 form the capacitor. Figure 2J As shown, where, Figure 2J (a) in the diagram is a top view of the structure. Figure 2J (b) in the diagram is a cross-sectional view of (a) at position AA.

[0077] Specifically, a lateral deposition process can be used to form a lower electrode layer 261 that continuously covers the inner wall of the first void 25, the inner wall of the second void 32, and the top surface of the second liner layer 23. A dielectric layer 262 covering the surface of the lower electrode layer 261 and an upper electrode layer 263 covering the surface of the dielectric layer 262 can also be formed. The materials of the lower electrode layer 261 and the upper electrode layer 262 can be conductive materials such as TiN or tungsten metal, and the material of the dielectric layer 262 can be a material with a high dielectric constant (HK). For example, the material of the dielectric layer 262 may include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO2), lanthanum oxide (LaO), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanium oxide (BaSrTiO3), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3, STO), lithium oxide (Li2O), aluminum oxide (Al2O3), lead scandium tantalum oxide (PbScTaO), lead zinc niobate (PbZnNbO3), or combinations thereof. Subsequently, a conductive material such as polycrystalline silicon is deposited on the surface of the upper electrode layer 263 to form the common electrode layer 27, such as... Figure 2G As shown, where, Figure 2G (a) in the diagram is a top view of the structure. Figure 2G (b) in the diagram is a cross-sectional view of (a) at position AA. After removing the common electrode layer 27, the upper electrode layer 263, the dielectric layer 262, the lower electrode layer 261, and the second pad layer 23 located above the stacked layer 21, the following is obtained: Figure 2H The structure shown.

[0078] Subsequently, a patterned second photoresist layer 28 is formed on the surface of the first pad layer 22, and the second photoresist layer 28 has a second opening 281 exposing the first pad layer 22 and the capacitor, as shown. Figure 2I As shown, where, Figure 2I (a) in the diagram is a top view of the structure. Figure 2I(b) is a cross-sectional view of (a) at position AA. The lower electrode layer 261, the dielectric layer 262, the upper electrode layer 263, and the common electrode layer 27 located within the second gap 32 are removed along the second opening 281. The remaining lower electrode layer 261, dielectric layer 262, upper electrode layer 263, and common electrode layer 27 within the first gap 25 form the capacitor, as shown below. Figure 2J As shown.

[0079] Step S13: A word line 34 is formed in the transistor region. The word line 34 extends along the first direction D1 and continuously covers the semiconductor pillars 30 arranged at intervals along the first direction D1, such as... Figure 2O As shown, where, Figure 2O (a) in the diagram is a top view of the structure. Figure 2O (b) in the diagram is a cross-sectional view of (a) at position AA.

[0080] In some embodiments, the semiconductor pillar 30 located in the transistor region includes a channel region, and source and drain regions distributed on opposite sides of the channel region along the second direction D2, wherein the source region is adjacent to the bit line region and the drain region is adjacent to the capacitor region; the specific steps for forming a word line 34 in the transistor region include:

[0081] A first isolation layer 29 covering the source region and the drain region is formed within the second gap 32;

[0082] The word line 34 is formed in the second gap 32, and the word line 34 extends along the first direction D1 and continuously covers the channel area that is spaced apart along the first direction D1.

[0083] In some embodiments, the specific steps of forming a first isolation layer 29 covering the source region and the drain region within the second gap 32 include:

[0084] A first isolation layer 29 is formed to fill the second void 32, such as Figure 2K As shown, where, Figure 2K (a) in the diagram is a top view of the structure. Figure 2K (b) in the diagram is a cross-sectional view of (a) at position AA;

[0085] Remove the first isolation layer 29 covering the trench area to expose the trench area, such as Figure 2M As shown, where, Figure 2M (a) in the diagram is a top view of the structure. Figure 2M (b) in the diagram is a cross-sectional view of (a) at position AA.

[0086] Specifically, after forming the capacitor, a low dielectric constant material is deposited within the second void 32 and on the surface of the first pad layer 22 to form the first insulating layer 29, such as... Figure 2K As shown. Next, the first isolation layer 29 on the surface of the first pad layer 22 is removed, and a patterned third photoresist layer 40 is formed on the surface of the first pad layer 22, wherein the third photoresist layer 40 has a third opening 401 exposing the first pad 22 and the first isolation layer 29, as shown. Figure 2L As shown. The first isolation layer 29 within the second gap 32 is etched along the third opening 401, exposing the channel region in the transistor region. The source and drain regions remain covered by the first isolation layer 29, as shown. Figure 2M As shown.

[0087] In some embodiments, before forming the word line within the second gap 32, the following steps are further included:

[0088] Forming a gate dielectric layer 33 covering the channel region, such as Figure 2N As shown, where, Figure 2N (a) in the diagram is a top view of the structure. Figure 2N (b) in the diagram is a cross-sectional view of (a) at position AA.

[0089] Specifically, after exposing the channel region, an in-situ water vapor growth process or a deposition process can be used to form the gate dielectric layer 33 on the surface of the channel region. The material of the gate dielectric layer 33 can be, but is not limited to, oxide materials (e.g., silicon dioxide). Subsequently, an atomic layer deposition process can be used to deposit a conductive material such as tungsten metal onto the surface of the gate dielectric layer 33 to form word lines 34 extending along the first direction D1 and continuously covering a plurality of channel regions spaced apart along the first direction D1, such as... Figure 2O As shown.

[0090] Step S14: A bit line 38 is formed in the bit line region. The bit line extends along the third direction D3 and covers the surface of the semiconductor layer 212, such as... Figure 2T As shown, where, Figure 2T (a) in the diagram is a top view of the structure. Figure 2T (b) in the diagram is a cross-sectional view of (a) at position AA. Figure 2T (c) in the diagram is a cross-sectional view of (a) at position BB.

[0091] In some embodiments, before forming the bit line 38 in the bit line region, the following steps are further included:

[0092] The first sacrificial layer 211 in the bit line region is removed using a lateral etching process, forming a third gap 37 between two adjacent semiconductor layers 212 in the bit line region, such as... Figure 2P As shown, where, Figure 2P (a) in the diagram is a top view of the structure. Figure 2P (b) in the diagram is a cross-sectional view of (a) at position AA.

[0093] Specifically, after forming the word line 34, a patterned fourth photoresist layer can be formed on the surface of the first pad layer 22. This fourth photoresist layer has a fourth opening that exposes the first isolation layer 29 and the first pad layer 22 located above the bit line region. Etching downwards along the fourth opening removes the first sacrificial layer 211 in the bit line region, forming a third gap 37 between two adjacent semiconductor layers 212 within the bit line region. Figure 2P As shown.

[0094] In some embodiments, the specific steps of forming the bit line 38 in the bit line region include:

[0095] A metal material is deposited along the third gap on the surface of the semiconductor layer 212 to form the bit line 38, which is a metal silicide.

[0096] The bit line 38 is annealed.

[0097] In some embodiments, the specific steps for forming the bit line, which is a metal silicide, include:

[0098] Metal material is deposited along the third gap 37 on the upper surface of the semiconductor layer 212 and the lower surface opposite to the upper surface, wherein the upper surface is the surface of the semiconductor layer 212 facing away from the substrate 20;

[0099] The stacked layer 21 is heat-treated to form the bit line 38. The bit line 38 includes a first sub-bit line covering the upper surface and a second sub-bit line covering the lower surface. The thickness of the semiconductor layer 212 remaining between the first and second sub-bit lines along the first direction D1 is less than the thickness of the semiconductor pillar 30 along the first direction D1. Figure 2Q As shown, where, Figure 2Q (a) in the diagram is a top view of the structure. Figure 2Q (b) in the diagram is a cross-sectional view of (a) at position AA.

[0100] Specifically, after removing the first pad layer 22, a metal material such as Ti, Co, Ni, or Pt is deposited along the third gap 37 on the upper and lower surfaces of the semiconductor layer 212 in the bit line region, and then subjected to low-temperature heat treatment, thereby causing the silicon material in the semiconductor layer 212 to react with the metal material to generate a high-resistivity metal silicide. Afterwards, the unreacted metal material in the third gap 37 is removed, and the high-resistivity metal silicide is subjected to high-temperature heat treatment to form the bit line 38, which is a low-resistivity metal silicide. Since the bit line 38 is obtained by the reaction of the semiconductor layer 212 with the metal material, the thickness of the semiconductor layer 212 located between two adjacent first sub-bit lines and second sub-bit lines along the first direction D1 is less than the thickness of the semiconductor pillar 30 along the first direction D1. This specific embodiment uses metal silicide to form the bit line, which can effectively reduce the resistance of the bit line 38, thereby improving the electrical performance of the semiconductor structure. After removing the bit line 38 covering the top surface of the stacked layer 21, the following is obtained: Figure 2R The structure shown, in which, Figure 2R (a) in the diagram is a top view of the structure. Figure 2R (b) in the diagram is a cross-sectional view of (a) at position AA.

[0101] In some embodiments, after forming the bit line 38 in the bit line region, the following steps are further included:

[0102] A second isolation layer 39 is formed between two adjacent bit lines 38, such as Figure 2S As shown, where, Figure 2S (a) in the diagram is a top view of the structure. Figure 2S (b) in the diagram is a cross-sectional view of (a) at position AA.

[0103] Specifically, after forming the bit lines 38, a low-dielectric-constant material is deposited within the third gap 37 to form a second isolation layer 39 for isolating adjacent bit lines 38. This embodiment uses a low-dielectric-constant material to form the second isolation layer 39, which reduces parasitic capacitance within the semiconductor structure, lowers signal crosstalk within the semiconductor structure, and allows interconnects to be closer together, providing space for increased chip integration. Secondly, reducing the dielectric constant (k) value can shorten signal propagation delay, thereby increasing chip speed. Subsequently, the stacked layer 21 is etched using the bit lines 38 as the etching medium layer to expose the bit lines 38, facilitating the subsequent signal extraction from the bit lines 38.

[0104] This specific embodiment also provides a semiconductor structure, formed using the semiconductor structure formation method described in any of the preceding embodiments. A schematic diagram of the semiconductor structure provided in this specific embodiment can be found [link to schematic diagram]. Figure 2T .

[0105] This specific embodiment provides a semiconductor structure and its formation method. By forming a stacked layer on the top surface of a substrate, the stacked layer includes multiple semiconductor layers spaced apart along a direction perpendicular to the top surface of the substrate, and each semiconductor layer includes multiple semiconductor pillars spaced apart along a direction parallel to the top surface of the substrate. This results in a three-dimensional array of semiconductor pillars in the stacked layer. Subsequently, by forming horizontal capacitors, vertical word lines, and horizontal bit lines, the traditional two-dimensional semiconductor structure is transformed into a three-dimensional semiconductor structure. This improves the integration density of the semiconductor structure, increases its storage density, and enhances its performance. Furthermore, in this specific embodiment, the bit lines extend along a direction parallel to the top surface of the substrate, and multiple bit lines are spaced apart along a direction perpendicular to the top surface of the substrate. This allows for the use of various materials to form the bit lines, improving the flexibility of the bit line fabrication process and helping to reduce the resistance of the bit lines, thereby further improving the performance of the semiconductor structure.

[0106] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A method for forming a semiconductor structure, characterized in that, Includes the following steps: A stacked layer is formed on the top surface of a substrate. The stacked layer includes a plurality of semiconductor layers spaced apart along a first direction. The stacked layer includes a transistor region and a capacitor region and a bit line region distributed on opposite sides of the transistor region along a second direction. The semiconductor layers of the transistor region and the capacitor region include semiconductor pillars spaced apart along a third direction. The first direction is perpendicular to the top surface of the substrate. The second direction and the third direction are both parallel to the top surface of the substrate, and the second direction intersects the third direction. A capacitor extending along the second direction is formed between two adjacent semiconductor layers within the capacitor region; A word line is formed in the transistor region, the word line extending along the first direction and continuously covering the semiconductor pillars spaced apart along the first direction; A bit line is formed in the bit line region, the bit line extending along the third direction and covering the surface of the semiconductor layer; The specific steps for forming the stacked layer on the top surface of the substrate include: Provide substrate; The first sacrificial layer and the semiconductor layer are alternately formed on the top surface of the substrate along the first direction to form the stacked layer; The transistor region and the capacitor region of the stacked layer are etched to form a plurality of first trenches exposing the substrate, and the first trenches separate the semiconductor layer of the transistor region and the capacitor region into semiconductor pillars spaced apart along the third direction; The semiconductor layer is made of silicon material including doped ions, and the first sacrificial layer is made of silicon germanide.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The specific steps for forming a capacitor extending along the second direction between two adjacent semiconductor layers within the capacitor region include: The first sacrificial layer of the capacitor region and the transistor region is removed to form a first gap between two adjacent semiconductor layers in the capacitor region and a second gap between two adjacent semiconductor layers in the transistor region.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, The stacked layer includes two transistor regions distributed along the second direction on opposite sides of the bit line region, and the side of the transistor region away from the bit line region has the capacitor region; The specific steps for removing the first sacrificial layer from the capacitor region and the transistor region include: Remove the first sacrificial layer from all said capacitor regions and all said transistor regions.

4. The method for forming a semiconductor structure according to claim 2, characterized in that, The specific steps for removing the first sacrificial layer from the capacitor region and the transistor region include: A second sacrificial layer is formed covering the top surface of the stacked layers; The first sacrificial layer of the capacitor region and the transistor region is removed using a lateral etching process.

5. The method for forming a semiconductor structure according to claim 2, characterized in that, The first gap is connected to the second gap; the specific steps of forming a capacitor extending along the second direction between two adjacent semiconductor layers within the capacitor region include: A lower electrode layer is formed that continuously covers the inner walls of the first and second gaps; A dielectric layer is formed covering the surface of the lower electrode layer; An upper electrode layer is formed covering the surface of the dielectric layer; A common electrode layer is formed covering the surface of the upper electrode layer; The lower electrode layer, the dielectric layer, the upper electrode layer, and the common electrode layer located in the second gap are removed, and the lower electrode layer, the dielectric layer, the upper electrode layer, and the common electrode layer remaining in the first gap form the capacitor.

6. The method for forming a semiconductor structure according to claim 2, characterized in that, The semiconductor pillar located in the transistor region includes a channel region and source and drain regions distributed on opposite sides of the channel region along the second direction. The source region is adjacent to the bit line region, and the drain region is adjacent to the capacitor region. The specific steps for forming a word line in the transistor region include: A first isolation layer covering the source region and the drain region is formed within the second gap; The word line is formed within the second gap, and the word line extends along the first direction and continuously covers the channel areas that are spaced apart along the first direction.

7. The method for forming a semiconductor structure according to claim 6, characterized in that, The specific steps of forming a first isolation layer covering the source region and the drain region within the second gap include: forming a first isolation layer that fills the second gap; Remove the first isolation layer covering the trench area to expose the trench area.

8. The method for forming a semiconductor structure according to claim 6, characterized in that, Before forming the character line within the second gap, the following steps are also included: A gate dielectric layer is formed covering the channel region.

9. The method for forming a semiconductor structure according to claim 2, characterized in that, Before forming a bit line within the bit line region, the following steps are also included: The first sacrificial layer in the bit line region is removed by a lateral etching process to form a third gap between two adjacent semiconductor layers in the bit line region.

10. The method for forming a semiconductor structure according to claim 9, characterized in that, The specific steps for forming a bit line within the bit line region include: A metal material is deposited along the third gap on the surface of the semiconductor layer to form the bit line, which is a metal silicide. The bit lines are annealed.

11. The method for forming a semiconductor structure according to claim 9, characterized in that, The specific steps for forming the bit line, which is a metal silicide, include: Metal material is deposited along the third gap on the upper surface of the semiconductor layer and on the lower surface opposite to the upper surface, wherein the upper surface is the surface of the semiconductor layer facing away from the substrate; The stacked layer is heat-treated to form the bit line, the bit line including a first sub-bit line covering the upper surface and a second sub-bit line covering the lower surface, wherein the thickness of the semiconductor layer remaining between the first sub-bit line and the second sub-bit line along the first direction is less than the thickness of the semiconductor pillar along the first direction.

12. The method for forming a semiconductor structure according to claim 1, characterized in that, After forming the bit line within the bit line region, the following steps are also included: A second isolation layer is formed between two adjacent bit lines.

13. A semiconductor structure, characterized in that, The semiconductor structure is formed using the method described in any one of claims 1-12.

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