Chip structure, chip structure packaging method and circuit board module

Abstract

The present invention discloses a chip structure, a packaging method for the chip structure and a circuit board module. The chip structure includes a crystal grain, an insulating layer, a conductive layer and an implanted component. The crystal grain has a first surface, a first power connection portion is provided on the first surface, an insulating layer is provided on the first surface, a first through hole and a mounting hole are provided on the insulating layer, the first through hole corresponds to the position of the first power connection portion to expose at least part of the first power connection portion, and the mounting hole and the first through hole are arranged at intervals. The conductive layer is provided on a side of the insulating layer away from the first surface, the conductive layer is electrically connected to the first power connection portion, the conductive layer has a hollow portion, and the hollow portion corresponds to and is connected to the mounting hole. In the direction from the crystal grain to the conductive layer, the implanted component is at least partially installed in the hollow portion and the mounting hole, and the implanted component is electrically connected to the conductive layer. The chip structure, the packaging method for the chip structure and the circuit board module disclosed by the present invention realize the miniaturization design of the chip structure while realizing the functional requirements of the chip structure.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a chip structure, a packaging method for the chip structure, and a circuit board module. Background Art

[0002] With the development of technology, due to the increasing functional requirements of various electronic devices, the functional integration of chip structures used to support electronic devices to achieve different functions is also getting higher and higher. However, the more functions the chip structure integrates, the larger the size of the chip structure may be. At present, in order to achieve the multifunctional and miniaturized design of the chip structure, system-level packaging, i.e. 3D stacking packaging, is usually adopted, but the chip structure is also limited in thickness. Summary of the invention

[0003] The embodiments of the present invention disclose a chip structure, a packaging method of the chip structure and a circuit board module, which realize the miniaturization design of the chip structure while meeting the functional requirements of the chip structure.

[0004] In order to achieve the above objectives, in a first aspect, the present invention discloses a chip structure, comprising:

[0005] A crystal grain, wherein the crystal grain has a first surface, and a first power connection portion is disposed on the first surface;

[0006] an insulating layer, the insulating layer being disposed on the first surface, the insulating layer being provided with a first through hole and a mounting hole, the first through hole corresponding to the position of the first power connection portion to expose at least a portion of the first power connection portion, and the mounting hole being spaced apart from the first through hole;

[0007] A conductive layer, the conductive layer is disposed on a side of the insulating layer away from the first surface, the conductive layer is electrically connected to the first power connection portion, the conductive layer has a hollow portion, and the hollow portion corresponds to and communicates with the mounting hole; and

[0008] The implanted component is at least partially installed in the hollow portion and the mounting hole along the direction from the grain to the conductive layer, and the implanted component is electrically connected to the conductive layer.

[0009] As an optional implementation, in an embodiment of the present invention, the first surface is further provided with a second power connection portion, the second power connection portion is located in the mounting hole, and the second power connection portion is electrically connected to the conductive layer and the implanted component.

[0010] As an optional implementation, in an embodiment of the present invention, the conductive layer includes multiple layers, the multiple conductive layers are stacked, the insulating layer is provided between two adjacent conductive layers, and a second through hole is also provided on the insulating layer between the two adjacent conductive layers, and the second through hole is used for connecting the two adjacent conductive layers to achieve electrical conduction.

[0011] As an optional implementation, in an embodiment of the present invention, the multiple conductive layers include at least a first conductive layer and a second conductive layer that are adjacently arranged, and along the direction from the crystal grain to the conductive layer, the second conductive layer is located on a side of the first conductive layer away from the crystal grain, and the second conductive layer and the first conductive layer both have the hollow portion, and the hollow portion on the second conductive layer corresponds to and is connected to the hollow portion on the first conductive layer;

[0012] The insulating layer located between the first conductive layer and the second conductive layer is further provided with a second power connection portion, the second power connection portion is located in the mounting hole, and the second power connection portion is electrically connected to the first conductive layer and / or the second conductive layer;

[0013] The implanted element is also electrically connected to the second power connection portion.

[0014] As an optional implementation, in an embodiment of the present invention, the insulating layer is multi-layered, and the multi-layer insulating layer at least includes a first insulating layer arranged on the first surface and a second insulating layer arranged between two adjacent conductive layers, and the mounting hole and the second through hole are arranged in the second insulating layer.

[0015] As an optional implementation, in an embodiment of the present invention, the chip structure further includes a metal ball, the metal ball is arranged on a side of the conductive layer away from the insulating layer, and the metal ball is electrically connected to the conductive layer.

[0016] As an optional implementation, in an embodiment of the present invention, the chip structure also includes a supporting portion, which is electrically connected to the conductive layer, and the supporting portion includes an end face and a first protrusion and a second protrusion that are arranged on the end face and opposite to each other, the first protrusion and the second protrusion extend from the end face away from the conductive layer, and the metal ball is clamped and electrically connected between the first protrusion, the second protrusion and the end face.

[0017] As an optional implementation, in an embodiment of the present invention, the crystal grain further has a second surface and an outer peripheral surface, the second surface is arranged opposite to the first surface, and the outer peripheral surface is connected to the first surface and the second surface;

[0018] The chip structure further includes a plastic encapsulation layer, and the plastic encapsulation layer is coated on the outer peripheral surface and the second surface.

[0019] In a second aspect, the present invention discloses a chip structure packaging method for manufacturing a chip structure, the packaging method comprising:

[0020] Disposing a first electrical connection portion on a first surface of the grain, and covering the first surface with a first insulating layer;

[0021] removing a portion of the first insulating layer to expose at least a portion of the first power connection portion;

[0022] Covering a first conductive layer on a side of the first power connection portion away from the crystal grain, so that the first conductive layer covers the first insulating layer and the first power connection portion, and the first conductive layer is electrically connected to the first power connection portion;

[0023] Disposing a hollow portion on the first conductive layer, the hollow portion corresponding to a position where a portion of the first insulating layer is removed;

[0024] An implanted element is implanted into the hollow portion, and the implanted element is electrically connected to the first conductive layer.

[0025] As an optional implementation, in an embodiment of the present invention, the chip structure further includes a second insulating layer and a second conductive layer, and after the step of providing a hollow portion on the first conductive layer, the step further includes:

[0026] Disposing the second insulating layer on a side of the first conductive layer away from the first insulating layer, so that the second insulating layer covers the first conductive layer and the hollow portion;

[0027] removing a portion of the second insulating layer to expose at least a portion of the first conductive layer;

[0028] Disposing the second conductive layer on a side of the second insulating layer away from the first conductive layer, so that the second conductive layer is electrically connected to the exposed first conductive layer;

[0029] The second insulating layer at the hollow portion is removed, an implanted element is implanted into the hollow portion, and the implanted element is electrically connected to the first conductive layer and / or the second conductive layer.

[0030] As an optional implementation manner, in an embodiment of the present invention, after the step of providing the second conductive layer on the side of the second insulating layer away from the first conductive layer, the method further includes:

[0031] A support portion is provided on a side of the second conductive layer away from the second insulating layer and electrically connected to the second conductive layer, and a metal ball is provided on a side of the support portion away from the second conductive layer and electrically connected to the second conductive layer through the support portion.

[0032] As an optional implementation, in an embodiment of the present invention, the packaging method further includes:

[0033] Before the first power connection portion is provided on the first surface of the die, a second surface of the die opposite to the first surface and an outer peripheral surface connected to the first surface and the second surface are plastic-sealed.

[0034] As an optional implementation manner, in an embodiment of the present invention, the method of removing part of the first insulating layer to expose at least part of the first power connection portion is:

[0035] Laser etching or chemical etching is used to remove a portion of the first insulating layer to expose at least a portion of the first power connection portion.

[0036] In a third aspect, the present invention discloses a circuit board module, comprising a circuit board and the chip structure as described in the first aspect above, wherein the circuit board is arranged on a side of the conductive layer away from the crystal grain, and the circuit board is electrically connected to the conductive layer.

[0037] As an optional implementation, in an embodiment of the present invention, the chip structure includes a metal ball, and along the direction from the grain to the conductive layer, when the implanted component protrudes from the metal ball, a side of the circuit board facing the conductive layer is provided with an avoidance structure corresponding to the implanted component, and the avoidance structure is used to avoid the implanted component.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] The chip structure, chip structure packaging method and circuit board module provided by the embodiments of the present invention stack a conductive layer along one side of the thickness direction of the grain and use an insulating layer to achieve an insulating connection between the conductive structures, so that the chip structure can be miniaturized while meeting the circuit layout requirements. At the same time, since the implanted component is at least partially arranged in the hollow portion and the mounting hole, the protruding height of the implanted component on the conductive layer can be reduced, that is, the overall thickness of the chip structure can be reduced, and the miniaturized design of the chip structure can be further achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 A schematic structural diagram of a chip structure (having a conductive layer) provided in the first aspect of this embodiment;

[0042] Figure 2 A schematic structural diagram of a chip structure (having multiple conductive layers) provided in the first aspect of this embodiment;

[0043] Figure 3 A schematic diagram of packaging of a chip structure with multiple conductive layers provided in the first aspect of the present embodiment;

[0044] Figure 4 A flow chart of a packaging method provided in the second aspect of this embodiment;

[0045] Figure 5 Another flow chart of the packaging method provided in the second aspect of this embodiment;

[0046] Figure 6 This is a schematic diagram of the structure of the circuit board module provided in the third aspect of this embodiment.

[0047] Description of main reference numerals

[0048] 1. Crystal grain; 11. First surface; 12. Second surface; 13. Peripheral surface; 2. Insulating layer; 21. First insulating layer; 22. Second insulating layer; 23. Third insulating layer; 2a. First through hole; 2b. Mounting hole; 2c. Second through hole; 3. Conductive layer; 31. First conductive layer; 32. Second conductive layer; 33. Third conductive layer; 3a. Hollow portion; 4. Implanted component; 5. First power connection portion; 6. Second power connection portion; 7. Metal ball; 8. Support portion; 81. End face; 82. First protruding portion; 83. Second protruding portion; 9. Plastic encapsulation layer; 100. Chip structure; 200. Circuit board module; 210. Circuit board; 211. Avoidance structure. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0050] In the present invention, the directions or positional relationships indicated by the terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal" and the like are based on the directions or positional relationships shown in the drawings. These terms are mainly used to better describe the present invention and its embodiments, and are not used to limit the indicated devices, elements or components to have a specific direction, or to be constructed and operated in a specific direction.

[0051] In addition, some of the above terms may be used to express other meanings in addition to indicating orientation or positional relationship. For example, the term "on" may also be used to express a certain dependency or connection relationship in some cases. For those skilled in the art, the specific meanings of these terms in the present invention can be understood according to specific circumstances.

[0052] In addition, the terms "installed", "set", "provided with", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0053] In addition, the terms "first", "second", etc. are mainly used to distinguish different devices, elements or components (the specific types and structures may be the same or different), and are not used to indicate or imply the relative importance and quantity of the indicated devices, elements or components. Unless otherwise specified, "plurality" means two or more.

[0054] The technical solution of the present invention will be further described below in conjunction with embodiments and drawings.

[0055] Please combine Figures 1 to 3In a first aspect, the present embodiment provides a chip structure 100, which includes a crystal grain 1, an insulating layer 2, a conductive layer 3, and an implanted component 4. The crystal grain 1 has a first surface 11, on which a first electrical connection portion 5 is provided; the insulating layer 2 is provided on the first surface 11, and the insulating layer 2 is provided with a first through hole 2a and a mounting hole 2b, wherein the first through hole 2a corresponds to the position of the first electrical connection portion 5 to expose at least a portion of the first electrical connection portion 5, and the mounting hole 2b is arranged at an interval with the first through hole 2a. The conductive layer 3 is provided on a side of the insulating layer 2 away from the first surface 11, and the conductive layer 3 is electrically connected to the first electrical connection portion 5, and the conductive layer 3 has a hollow portion 3a, which corresponds to and is connected to the mounting hole 2b. In the direction from the crystal grain 1 to the conductive layer 3, the implanted component 4 is at least partially located in the mounting hole 2b and the hollow portion 3a, and the implanted component 4 is electrically connected to the conductive layer 3.

[0056] Considering that the chip structure 100 is being designed, the design of the conductive circuit on the chip structure 100 is relatively complicated under the requirement of chip functional diversity. At the same time, in order to achieve the miniaturization of the chip structure 100, it can be considered to stack the conductive circuit of the chip structure 100 along the thickness direction of the grain 1, so as to effectively reduce the surface area of ​​the chip structure 100. Based on this, the present application sets an insulating layer 2 to achieve the insulation of the first power connection part 5 and the conductive layer 3 at the position where no electrical connection is required; at the same time, by setting a first through hole 2a on the insulating layer 2, the first power connection part 5 is electrically connected to the conductive layer 3 at the required position, so that the arrangement of the conductive circuit of the first power connection part 5 and the conductive layer 3 can meet the design requirements.

[0057] Furthermore, considering that the stacking arrangement of the crystal grain 1, the first power connection portion 5, the insulating layer 2 and the conductive layer 3 in the thickness direction of the crystal grain 1 can reduce the surface area of ​​the chip structure 100, it will increase the overall thickness of the chip structure 100. At the same time, since some implanted components 4 are required to be arranged in the chip structure 100 to realize some functions of the chip structure 100, and the thickness of the implanted components 4 is obviously thicker than the insulating layer 2 and the conductive layer 3, when the implanted components 4 are electrically connected to the conductive layer 3, the thickness of the chip structure 100 will be obviously increased.

[0058] Based on this, the present application further provides a hollow portion 3a on the conductive layer 3, and provides a mounting hole 2b on the insulating layer 2 corresponding to and connected to the hollow portion 3a, so as to install the implanted component 4 in the mounting hole 2b, so that at least part of the implanted component 4 in the direction from the grain 1 to the conductive layer 3 is located in the mounting hole 2b and the hollow portion 3a. At this time, the thickness of the part of the implanted component 4 protruding from the conductive layer 3 becomes smaller, thereby effectively reducing the influence of the implanted component 4 on the overall size of the chip structure 100, so as to further realize the miniaturized design of the chip structure 100.

[0059] It can be understood that the thickness of each structure mentioned above refers to the size of the grain 1, the insulating layer 2, the conductive layer 3 and the implanted element 4 along the direction from the grain 1 to the conductive layer 3 (eg Figure 1 in the X direction).

[0060] The first power connection portion 5 may be a solder joint, a pad, a pin, etc. The implanted component 4 may include but is not limited to a capacitor, an inductor, a resistor, or a device that needs to be electrically connected to the chip structure 100 to achieve the functional requirements of the chip structure 100, etc. In this embodiment, the types of the first power connection portion 5 and the implanted component 4 are not limited.

[0061] Optionally, the number of the first power connection part 5, the first through hole 2a, the hollow part 3a, the mounting hole 2b and the implanted component 4 can be multiple, and the hollow part 3a and the mounting hole 2b can be located in the middle or at the edge. At the same time, when there are multiple implanted components 4, the number of the hollow parts 3a and the mounting holes 2b can be set to match the number of implanted components 4, that is, one implanted component 4 is set in each hollow part 3a and the mounting hole 2b at the same time, or multiple implanted components 4 can be set in one hollow part 3a and the mounting hole 2b.

[0062] It can be understood that the electrical connection method between the first through hole 2a and the first power connection portion 5 and the conductive layer 3 may include but is not limited to: the conductive layer 3 extends into the first through hole 2a and directly contacts the first power connection portion 5 to achieve electrical connection, or a conductive member (such as a metal column, a flexible circuit board, a conductive wire, etc.) is arranged in the first through hole 2a, and one end of the conductive member is connected to the conductive layer 3, and the other end is connected to the first power connection portion 5 to achieve electrical connection between the conductive layer 3 and the first power connection portion 5.

[0063] This embodiment is described by taking the example that the conductive layer 3 extends into the first through hole 2a and directly contacts the first electrical connection portion 5 to achieve electrical connection.

[0064] Considering that the first through hole 2a needs to realize the electrical connection between the first power connection portion 5 and the conductive layer 3, based on this, in order to facilitate the conductive layer 3 to extend into the first through hole 2a, in some embodiments, the first through hole 2a has an inclined wall surface so that the aperture of the first through hole 2a is along the direction from the grain 1 to the conductive layer 3 (such as Figure 1 The X direction in the first through hole 2a gradually increases, so as to play a guiding role when the conductive layer 3 is arranged in the first through hole 2a, so as to facilitate the electrical connection between the conductive layer 3 and the first electrical connection portion 5. It can be understood that the number and arrangement positions of the first through holes 2a can be adjusted according to the conductive line requirements of the chip structure 100, and are not specifically limited in this embodiment.

[0065] Optionally, the first through hole 2a may be formed by laser etching, chemical etching or other methods of removing the material of the insulating layer. The specific implementation of the first through hole 2a is not limited in this embodiment.

[0066] Optionally, the hollow portion 3a on the conductive layer 3 can be formed when forming the conductive line or conductive pattern of the conductive layer 3, that is, the hollow portion 3a is formed synchronously after the conductive layer 3 is formed. Of course, it can be understood that in other embodiments, the hollow portion 3a can also be formed by removing part of the material of the conductive layer 3 after the conductive layer 3 is formed.

[0067] Optionally, since the implanted component 4 is installed in the mounting hole 2b, in order to facilitate the installation of the implanted component 4, the mounting hole 2b has an inclined wall surface so that the opening of the mounting hole 2b is along the direction from the grain 1 to the conductive layer 3 (such as Figure 1 The X direction in the figure gradually increases, thereby facilitating the installation of the implanted component 4.

[0068] Optionally, the mounting hole 2b may be formed by laser etching or chemical etching or other methods by removing the material of the insulating layer. The specific implementation of the mounting hole 2b is not limited in this embodiment.

[0069] Optionally, the conductive layer 3 can be set to be one layer or multiple layers according to actual functional requirements. When the conductive layer 3 is multiple layers, the circuit layout area of ​​the chip structure 100 can be increased when the surface area of ​​the chip structure 100 is limited to meet the functional requirements of the chip structure 100.

[0070] In an optional example, when the conductive layer 3 is a single layer and the electrical connection position of the implanted component 4 is on the side facing the first surface 11, in order to facilitate the electrical connection between the implanted component 4 and the conductive layer 3, a second electrical connection portion 6 may be provided on the first surface 11, the second electrical connection portion 6 is located in the mounting hole 2b, and the second electrical connection portion 6 is electrically connected to the conductive layer 3 and the implanted component 4. In this way, by providing the second electrical connection portion 6 on the first surface 11 and electrically connecting the second electrical connection portion 6 to the conductive layer 3, the electrical connection between the implanted component 4 and the conductive layer 3 can be facilitated.

[0071] In addition, considering that the connection structures of the two structures that need to be electrically connected need to correspond to each other in order to achieve electrical connection between the two. That is, if the electrical connection structure on the chip structure 100 that is electrically connected to the implanted component 4 is fixed, then the types of implanted components 4 that the chip structure 100 can connect to will be limited. Therefore, the present application further provides a second electrical connection portion 6 on the first surface 11, and the type and position of the second electrical connection portion 6 can be designed corresponding to the electrical connection structure of the implanted component 4 that needs to be electrically connected, that is, the type and position of the second electrical connection portion 6 can be flexibly adjusted, so as to adapt to different implanted components 4, so that the chip structure 100 can connect to various implanted components 4, thereby facilitating the realization of different functions of the chip structure 100.

[0072] Optionally, the second power connection portion 6 may be a welding point, or may be a pad or other power connection component that can achieve electrical connection between the implanted component 4 and the conductive layer 3. In this embodiment, the specific structure of the second power connection portion 6 is not limited.

[0073] Of course, if the electrical connection position of the implanted component 4 is located on its own outer peripheral surface, at this time, the part of the outer peripheral surface of the implanted component 4 arranged in the hollow portion 3a is directly in contact with the conductive layer 3 to achieve electrical connection, and there is no need to additionally set up the second electrical connection portion 6, which can simplify the design of the conductive circuit of the chip structure 100.

[0074] In another optional example, the conductive layer 3 includes multiple layers, and when the multiple conductive layers 3 are stacked, the insulating layer 2 is provided between two adjacent conductive layers 3, so as to achieve an insulating connection at a position where electrical conduction is not required between the two adjacent conductive layers 3 through the insulating layer 2. Accordingly, a second through hole 2c is provided on the insulating layer 2, so as to achieve electrical conduction at a required position between the two adjacent conductive layers 3 through the second through hole 2c.

[0075] It can be understood that the manner in which the two adjacent conductive layers 3 are electrically connected and conducted through the second through hole 2c may include but is not limited to: one of the two adjacent conductive layers 3 extends into the second through hole 2c and directly contacts the other conductive layer 3 to achieve electrical connection, or a conductive member (such as a metal column, a flexible circuit board, a conductive wire, etc.) is arranged in the second through hole 2c, and one end of the conductive member is connected to one of the conductive layers 3, and the other end is connected to the other conductive layer 3 to achieve electrical connection between the two adjacent conductive layers 3.

[0076] Optionally, since the second through hole 2c needs to realize electrical connection between two adjacent conductive layers 3, in order to facilitate the arrangement of the conductive layer 3, the second through hole 2c has an inclined wall surface so that the opening of the second through hole 2c is along the direction from the grain 1 to the conductive layer 3 (such as Figure 1The X direction in the middle (in the X direction) gradually increases, so that it can play a guiding role when the conductive layer 3 is arranged in the second through hole 2c, so as to realize the electrical connection between two adjacent conductive layers 3. It can be understood that the number and arrangement positions of the second through holes 2c can be adjusted according to the conductive line requirements of the chip structure 100, and are not specifically limited in this embodiment.

[0077] When the conductive layer 3 has multiple layers, in one example, the conductive layer 3 has two layers (eg Figure 2 As shown in (a) in FIG. 1 , the conductive layer 3 includes a first conductive layer 31 and a second conductive layer 32 disposed adjacent to each other. Along the direction from the crystal grain 1 to the conductive layer 3, the second conductive layer 32 is located on the side of the first conductive layer 31 away from the crystal grain 1. The second conductive layer 32 and the first conductive layer 31 both have a hollow portion 3a (see FIG. 1 ). Figure 3 (c)), and the hollow portion 3a on the second conductive layer 32 corresponds to and is connected with the hollow portion 3a on the first conductive layer 31. At this time, the insulating layer 2 also has two layers, and the insulating layer 2 includes a first insulating layer 21 located on the first surface 11 and a second insulating layer 22 located between the first conductive layer 31 and the second conductive layer 32. The mounting hole 2b on the second insulating layer 22 corresponds to and is connected with the hollow portion 3a of the first conductive layer 31 and the second conductive layer 32. When the implanted component 4 is electrically connected to the conductive layer 3 through the second power connection portion 6, at this time, the second power connection portion 6 can be arranged on the side of the first insulating layer 21 away from the first surface 11, and in the mounting hole 2b of the insulating layer 2 located between the first conductive layer 31 and the second conductive layer 32, and the second power connection portion 6 can be electrically connected to the implanted component 4.

[0078] It can be understood that at this time, the second power connection portion 6 can be electrically connected to the first conductive layer 31 to achieve electrical connection between the implanted component 4 and the first conductive layer 31; or, the second power connection portion 6 can be electrically connected to the second conductive layer 32 to achieve electrical connection between the implanted component 4 and the second conductive layer 32; or, the second power connection portion 6 can be electrically connected to the first conductive layer 31 and the second conductive layer 32 at the same time to achieve electrical connection between the implanted component 4 and the first conductive layer 31 and the second conductive layer 32 at the same time. It can be understood that the electrical connection method between the second power connection portion 6 and the first conductive layer 31 and the second conductive layer 32 can be selected according to the needs of the conductive circuit, and is not specifically limited in this embodiment.

[0079] In another example, when the conductive layer 3 is three layers (such as Figure 2As shown in (b) in the figure, the conductive layer 3 includes a first conductive layer 31, a second conductive layer 32 and a third conductive layer 33. In the direction from the crystal grain 1 to the conductive layer 3, the second conductive layer 32 is located on the side of the first conductive layer 31 away from the crystal grain 1, and the third conductive layer 33 is located on the side of the second conductive layer 32 away from the first conductive wire layer. At this time, the insulating layer 2 also has three layers, and the insulating layer 2 includes a first insulating layer 21 located on the first surface 11, a second conductive layer 32 located between the first conductive layer 31 and the second conductive layer 32, and a third insulating layer 23 located between the second conductive layer 32 and the third conductive layer 33. At the same time, the mounting hole 2b on the second insulating layer 22 corresponds to and is connected to the mounting hole 2b on the third insulating layer 23, and is connected to the hollow portion 3a (see the hollow portion 3a) on the first conductive layer 31, the second conductive layer 32 and the third conductive layer 33. Figure 3 The second power connection portion 6 is located in the mounting hole 2b of the second insulating layer 22 and is located on the side of the first insulating layer 21 away from the first surface 11. The implanted component 4 is located in the mounting hole 2b and is electrically connected to the second power connection portion 6. The second power connection portion 6 can be electrically connected to any one conductive layer 3 or two conductive layers 3 according to the needs of the conductive circuit, or even electrically connected to three conductive layers 3 at the same time, which is not limited in this embodiment.

[0080] When the conductive layer 3 is two or three layers, the location of the implanted component 4 is only an example. That is, when the conductive layer 3 is multi-layered, the implanted component 4 can be installed in one conductive layer 3 and the insulating layer 2, or the implanted component 4 can also be installed in multiple conductive layers 3 and the insulating layer 2, in which case the thickness of the implanted component 4 can be prevented from affecting the overall thickness of the chip structure 100 to a greater extent. It is understandable that when the conductive layer 3 has more layers, the location of the implanted component 4 can be adjusted according to actual needs, which is not limited in this embodiment.

[0081] Please refer to the Figures 1 to 3 In some embodiments, in order to realize electrical connection between the chip structure 100 and other devices, the chip structure 100 further includes a metal ball 7. The metal ball 7 can be disposed on the side of the conductive layer 3 away from the insulating layer 2 by a ball planting process, and the metal ball 7 is electrically connected to the conductive layer 3. The electrical connection method of the metal ball 7 between two devices makes it easier to realize the miniaturization design of the overall structure after the combination of different devices.

[0082] Specifically, the metal ball 7 may be a tin ball, a copper ball, a silver ball or other metal material with conductive properties. In this embodiment, the specific material of the metal ball 7 is not limited.

[0083] Furthermore, in order to improve the stability of the electrical connection between the metal ball 7 and the conductive layer 3, the chip structure 100 further includes a support portion 8, which is located between the metal ball 7 and the conductive layer 3, so that the metal ball 7 is electrically connected to the conductive layer 3 through the support portion 8. Influenced by the functional requirements of the chip structure 100, the connection area between the conductive layer 3 and the metal ball 7 may be relatively small, and the shape of the metal ball 7 may make the electrical connection between the metal ball 7 and the conductive layer 3 unstable. Therefore, by adding the support portion 8 between the metal ball 7 and the conductive layer 3, the electrical connection stability between the metal ball 7 and the conductive layer 3 can be improved.

[0084] Optionally, the support portion 8 may be made of the same metal material as the metal ball 7, or a metal material different from the metal ball 7, or a conductive ceramic having a conductive function, etc. In this embodiment, the support portion 8 is not specifically limited.

[0085] In some embodiments, the support portion 8 includes an end surface 81 and a first protrusion 82 and a second protrusion 83 disposed on the end surface 81 and arranged opposite to each other, the first protrusion 82 and the second protrusion 83 extend from the end surface 81 away from the conductive layer 3 to clamp the metal ball 7, thereby improving the connection stability of the metal ball 7 on the end surface 81 of the support portion 8 and preventing the metal ball 7 from falling off the support portion 8. At the same time, the metal ball 7 is electrically connected between the first protrusion 82, the second protrusion 83 and the end surface 81, so as to realize electrical connection with the metal ball 7 through the end surface 81, the first protrusion 82 and the second protrusion 83, thereby improving the electrical connection stability between the support portion 8 and the metal ball 7, and further improving the electrical connection stability between the metal ball 7 and the conductive layer 3.

[0086] In one example, the first protrusion 82 and the second protrusion 83 may be arranged opposite to each other at intervals, so that the force on the metal ball 7 can be more balanced, thereby improving the connection stability between the metal ball 7 and the first protrusion 82 and the second protrusion 83. It can be understood that the first protrusion 82 and the second protrusion 83 may be arranged opposite to each other at intervals in a pair, or may be arranged opposite to each other in two, three or more pairs.

[0087] In another example, the first protrusion 82 and the second protrusion 83 may also be interconnected and arranged opposite to each other. In this case, the first protrusion 82 and the second protrusion 83 may be combined with the end surface 81 to form a groove for accommodating the metal ball 7, so that the metal ball 7 can be arranged in the groove, which can effectively improve the connection stability and electrical connection stability between the metal ball 7 and the support portion 8.

[0088] Optionally, the surfaces of the first protrusion 82 and the second protrusion 83 facing each other may be inclined surfaces, so as to guide the metal ball 7 when the metal ball 7 is set, so as to further improve the connection stability between the metal ball 7 and the support portion 8.

[0089] In some embodiments, since the conductive circuits required by the chip structure 100 are too complex, in order to accommodate more conductive circuits, the crystal grain 1 has a second surface 12 opposite to the first surface 11 and a peripheral surface 13 connected to the first surface 11 and the second surface 12. The chip structure 100 also includes a plastic encapsulation layer 9 coated on the second surface 12 and the peripheral surface 13. The plastic encapsulation layer 9 disposed on the periphery of the peripheral surface 13 can also be used to carry part of the conductive circuit, that is, the crystal grain 1 can adopt a fan-out packaging process, so that under the premise of maintaining the plastic encapsulation reliability and realizing the effective protection of the crystal grain by the plastic encapsulation layer 9, the plastic encapsulation layer 9 can also expand the area of ​​the crystal grain 1 that can be used to carry the conductive circuit, such as the first power connection portion 5, which is conducive to providing more space for the design of the conductive circuit.

[0090] Specifically, the material of the plastic encapsulation layer 9 may be a polymer resin material, such as Ajinomoto Build-up Film (ABF), benzocyclobutene (BCB), bismaleimide triazine (BT), epoxy resin, polyester, polyimide and / or polytetrafluoroethylene. Alternatively, the material of the plastic encapsulation layer 9 may also be a reinforcing material for polymer resin materials, such as a glass fiber reinforcing material.

[0091] The chip structure 100 provided by the first aspects of the present embodiment realizes miniaturized packaging of the chip structure 100 by stacking the conductive layer 3 and the insulating layer 2 along the thickness direction of the grain 1. In addition, since the conductive layer 3 of the insulating layer 2 is provided with a connected mounting hole 2b and a hollow portion 3a, the implanted component 4 can be arranged in the mounting hole 2b, so as to reduce the influence of the implanted component 4 on the overall size of the chip structure 100, so as to further realize the miniaturized design of the chip structure 100.

[0092] Please combine Figure 3 , Figure 4 and Figure 5 In a second aspect, this embodiment provides a packaging method for packaging the chip structure 100 described in the first aspect.

[0093] In one embodiment, the packaging method includes:

[0094] 301 , a first power connection portion 5 is provided on the first surface 11 of the crystal grain 1 , and a first insulating layer 21 is covered on the first surface 11 ;

[0095] The purpose of this step is to set the first power connection portion 5 on the first surface 11 of the crystal grain 1, so as to serve as a basis for subsequent electrical connection with the first conductive layer 31. At the same time, the setting of the first insulating layer 21 can achieve the insulation setting of the first power connection portion 5 and the first conductive layer 31, thereby avoiding the setting of the first power connection portion 5 on the first conductive layer 31.

[0096] Optionally, the first power connection portion 5 may be made of metal or metal alloy and may include but not limited to solder joints, pads, pins, etc. When the first power connection portion 5 is disposed on the first surface 11, it may contact the circuit on the first surface 11 to achieve electrical conduction.

[0097] In addition, the first insulating layer 21 may be a polymer resin material, such as Ajinomoto Build-up Film (ABF), benzocyclobutene (BCB), bismaleimide triazine (BT), epoxy resin, polyester, polyimide and / or polytetrafluoroethylene. Alternatively, the material of the first insulating layer 21 may also be a reinforcing material for polymer resin materials, such as a glass fiber reinforcing material.

[0098] 302, removing part of the first insulating layer 21 to expose at least part of the first power connection portion 5;

[0099] The purpose of this step is to form a first through hole 2 a for exposing at least a portion of the first power connection portion 5 and a mounting hole 2 b for mounting the implanted component 4 on the first insulating layer 21 .

[0100] 303 , covering the first conductive layer 31 on the side of the first power connection portion 5 away from the crystal grain 1 , so that the first conductive layer 31 covers the first insulating layer 21 and the first power connection portion 5 , and the first conductive layer 31 is electrically connected to the first power connection portion 5 ;

[0101] The purpose of this step is to achieve electrical connection between the first conductive layer 31 and the first power connection portion 5 , that is, the first conductive layer 31 is electrically connected to the first power connection portion 5 through the first through hole 2 a on the first insulating layer 21 .

[0102] Optionally, the first conductive layer 31 may be made of a single metal material or a metal alloy material, such as copper, gold, silver, and copper alloy.

[0103] Furthermore, the electrical connection method between the first power connection portion 5 and the first conductive layer 31 achieved by the first through hole 2a may include but is not limited to: the first conductive layer 31 extends into the first through hole 2a and directly contacts the first power connection portion 5 to achieve electrical connection, or a conductive member (such as a metal column, a flexible circuit board, a conductive wire, etc.) is arranged in the first through hole 2a, and one end of the conductive member is connected to the first conductive layer 31, and the other end is connected to the first power connection portion 5 to achieve electrical connection between the first conductive layer 31 and the first power connection portion 5.

[0104] 304. A hollow portion 3a is provided on the first conductive layer 31, wherein the hollow portion 3a corresponds to a position where a portion of the first insulating layer 21 is removed;

[0105] The hollow portion 3a formed in this step provides a location for the implanted element 4, and the hollow portion 3a corresponds to the mounting hole 2b.

[0106] 305 , implant the implanted component 4 into the hollow portion 3 a and the position where a portion of the first insulating layer 21 is removed, and the implanted component 4 is electrically connected to the first conductive layer 31 .

[0107] Since the hollow portion 3a corresponds to the mounting hole 2b, when the implanted component 4 is installed in the mounting hole 2b, the implanted component 4 can be directly electrically connected to the first conductive layer 31 at the position of the hollow portion 3a, or a second power connection portion 6 can be provided in the mounting hole 2b, and the implanted component 4 can be electrically connected to the first conductive layer 31 through the second power connection portion 6.

[0108] Furthermore, when the functions to be implemented by the chip structure 100 are different, the chip structure 100 is usually provided with multiple insulating layers 2 and conductive layers 3. When the chip structure 100 has multiple insulating layers 2 and conductive layers 3, the above packaging method further includes, after the step of providing the hollow portion 3a on the first conductive layer 31:

[0109] 306. Dispose a second insulating layer 22 on a side of the first conductive layer 31 away from the first insulating layer 21, so that the second insulating layer 22 covers the first conductive layer 31 and the hollow portion 3a;

[0110] The purpose of this step is to realize the functional diversity of the chip structure 100 , that is, when multiple conductive layers are required, the second insulating layer 22 can realize the insulation setting between the first conductive layer 31 and the second conductive layer 32 , thereby not affecting the setting of the second conductive layer 32 .

[0111] It can be understood that the material and configuration of the second insulating layer 22 can refer to the material and configuration of the first insulating layer 21 , and will not be described in detail here.

[0112] 307 , removing a portion of the second insulating layer 22 to expose at least a portion of the first conductive layer 31 ;

[0113] The purpose of this step is to form a second through hole 2c in the second insulating layer 22 so as to achieve electrical connection between the second conductive layer 32 and the first conductive layer 31 through the second through hole 2c.

[0114] 308. Dispose a second conductive layer 32 on a side of the second insulating layer 22 away from the first conductive layer 31, so that the second conductive layer 32 is electrically connected to the exposed first conductive layer 31;

[0115] The purpose of this step is to achieve electrical connection between the second conductive layer 32 and the first conductive layer 31 .

[0116] 309 . Remove the second insulating layer 22 at the hollow portion 3 a , implant the implanted component 4 into the hollow portion 3 a , and electrically connect the implanted component 4 to the first conductive layer 31 or the second conductive layer 32 , or to both the first conductive layer 31 and the second conductive layer 32 .

[0117] The purpose of this step is that when the insulating layer 2 and the conductive layer 3 have multiple layers, the second insulating layer 22 can be formed with a mounting hole 2b corresponding to the hollow portion 3a, so that the mounting hole 2b of the first insulating layer 21 corresponds to the mounting hole 2b of the second insulating layer, so that the implanted component 4 can be installed in the mounting hole 2b of the multi-layer insulating layer 2 and the hollow portion 3a of the conductive layer 3. Furthermore, the implanted component 4 can be embedded in the multi-layer conductive layer 3 and the multi-layer insulating layer 2 at the same time, thereby avoiding the setting of the implanted component 4 to affect the overall size of the chip structure 100, especially the size along the direction from the grain 1 to the conductive layer 3.

[0118] The implanted element 4 can be electrically connected to the first conductive layer 31, the second conductive layer 32, or both. The specific connection method can be selected according to actual needs and is not specifically limited in this embodiment.

[0119] In order to facilitate the electrical connection between the chip structure 100 and other structures and realize the miniaturization of the overall structure, the packaging method further comprises, after the step of disposing the second conductive layer 32 on the side of the second insulating layer 22 away from the first conductive layer 31:

[0120] 310. A support portion 8 is provided on a side of the second conductive layer 32 facing away from the second insulating layer 22 , the support portion 8 is electrically connected to the second conductive layer 32 , and a metal ball 7 is provided on a side of the support portion 8 facing away from the second conductive layer 32 , the metal ball 7 is electrically connected to the second conductive layer 32 through the support portion 8 .

[0121] The purpose of this step is to improve the electrical connection stability between the metal ball 7 and the second conductive layer 32 by setting the support portion 8. In addition, the purpose of setting the metal ball 7 in this step is to provide an electrical connection basis when the chip structure 100 is connected to other circuit board structures.

[0122] Optionally, the metal ball 7 can be connected to the support part 8 by using a ball planting process, and the arrangement of the metal ball 7 is conducive to realizing a miniaturized arrangement when the chip structure 100 is connected to other circuit board structures. The support part 8 and the metal ball 7 can be made of the same conductive material, such as copper for both the support part 8 and the metal ball 7; or different conductive materials can be used, such as gold for the support part 8 and copper for the metal ball 7.

[0123] Specifically, the above-mentioned steps of setting the support portion 8 and the metal ball 7 may be performed after step 308 and before step 309, or after step 309, but the metal ball 7 should not be implanted after the mounting hole 2b is formed and before the implanted component 4 is installed. If the metal ball 7 is implanted after the mounting hole 2b is formed, impurities may fall into the mounting hole 2b during the implantation of the metal ball 7, thereby causing the subsequent installation of the implanted component 4 in the mounting hole 2b to be blocked or the electrical connection to fail, which may affect the production efficiency and production quality of the chip structure 100.

[0124] Optionally, when the chip structure 100 has only the first insulating layer 21 and the first conductive layer 31, the manufacturing method of the chip structure 100 can be as follows: Figure 4 As shown, the support portion 8 and the metal ball 7 can be provided after step 305; when the chip structure 100 has a first insulating layer 21, a first conductive layer 31, a second insulating layer 22, and a second conductive layer 32, the manufacturing method of the chip structure 100 can be as follows Figure 5 As shown, the support portion 8 and the metal ball 7 can be arranged after step 309; when the structure of the chip structure 100 is more complex, the above-mentioned steps of arranging the first insulating layer 21, the first conductive layer 31, the second insulating layer 22, and the second conductive layer 32 can be repeated to form a multi-layer structure of the chip structure 100 to meet the functional requirements of the chip structure 100. And when the first insulating layer 21, the first conductive layer 31, the second insulating layer 22, and the second conductive layer 32 have multiple layers, the support portion 8 and the metal ball 7 can be arranged on the conductive layer 3 farthest from the grain 1, so as to facilitate the electrical connection between the chip structure 100 and other structures. Of course, if the structural design requires, the arrangement form of the support portion 8 and the metal ball 7 can also be the same as the arrangement form of the implanted component 4, that is, through the embedded design, the miniaturization design of the chip structure 100 can be further realized.

[0125] In some embodiments, the packaging method further comprises:

[0126] 311 . The grain 1 has a second surface 12 and an outer peripheral surface 13 . The second surface 12 is arranged opposite to the first surface 11 . The outer peripheral surface 13 is connected to the first surface 11 and the second surface 12 . A plastic sealing layer 9 is arranged on the second surface 12 and the outer peripheral surface 13 .

[0127] The purpose of this step is to wrap and protect the die 1 through the plastic encapsulation layer 9. At the same time, since the plastic encapsulation layer 9 has a surface flush with the first surface 11 of the die 1, when the first power connection part 5 is set on the first surface 11 of the die 1, if there is insufficient space on the first surface 11 of the die 1, the first power connection part 5 can be set on both the die 1 and the plastic encapsulation layer 9, thereby increasing the wiring space of the conductive circuit of the chip structure.

[0128] Optionally, the material of the plastic encapsulation layer 9 may be a polymer resin material, such as Ajinomoto Build-up Film (ABF), benzocyclobutene (BCB), bismaleimide triazine (BT), epoxy resin, polyester, polyimide and / or polytetrafluoroethylene. Alternatively, the material of the plastic encapsulation layer 9 may also be a reinforcing material for polymer resin materials, such as a glass fiber reinforcing material.

[0129] Furthermore, the above-mentioned method of removing part of the first insulating layer 21 to expose at least part of the first power connection portion 5 is:

[0130] Laser etching or chemical etching is used to remove part of the material of the first insulating layer 21 corresponding to the first power connection portion 5 to form the first through hole 2a and the mounting hole 2b. The laser etching method can improve the processing accuracy and the processing efficiency. The chemical etching method can protect the first conductive layer 31, thereby avoiding damage to the first conductive layer 31.

[0131] Furthermore, the method of removing part of the second insulating layer 22 and exposing at least part of the first conductive layer 31 can also be achieved by, for example, chemical etching, laser etching or other methods of removing the part of the material, so that the second insulating layer 22 forms the second through hole 2c and the mounting hole 2b. The hollow portion 3a can be formed when the conductive line or conductive pattern of the first conductive layer 31 is formed, that is, after the first conductive layer 31 is formed, the hollow portion 3a is formed simultaneously. Of course, it can be understood that in other embodiments, the hollow portion 3a can also be formed after the first conductive layer 31 is formed by removing part of the material of the first conductive layer 31.

[0132] See also Figure 6 In a third aspect, the present embodiment discloses a circuit board module 200, which includes the chip structure 100 and a circuit board 210 described in the first aspect, wherein the circuit board 210 is located on a side of the conductive layer 3 away from the die 1, and the circuit board 210 is electrically connected to the conductive layer 3. The circuit board module 200 having the chip structure 100 can realize a miniaturized design of the circuit board module 200 while realizing functional diversity.

[0133] Furthermore, when the chip structure 100 includes the metal ball 7, and the implanted component 4 protrudes from the metal ball 7 in the direction from the crystal grain 1 to the conductive layer 3, a side of the circuit board 210 facing the conductive layer 3 is provided with a avoidance structure 211 corresponding to the implanted component 4 to avoid the implanted component 4. In this way, when the circuit board 210 and the implanted component 4 are installed and connected, interference between the two can be avoided, and the installation reliability of the circuit board 210 and the implanted component 4 can be effectively ensured. At the same time, the setting of the avoidance structure 211 can reduce the overall thickness of the circuit board module 200 along the thickness direction of the circuit board 210, making the overall structure of the circuit board module 200 more compact.

[0134] Optionally, the avoidance structure 211 can be a groove provided on the circuit board 210, or a through hole, or a depression formed on the surface of the circuit board 210, etc. Its specific form can be selected according to actual conditions and is not limited in this embodiment.

[0135] It is understandable that when the metal ball 7 is not provided on the chip structure 100, the chip structure 100 and the circuit board 210 can also be electrically connected through a conductive line, such as gold wire, etc.; they can also be electrically connected through a flexible circuit board. In this embodiment, the specific connection method between the chip structure 100 and the circuit board 210 is not limited.

[0136] In some embodiments, when the chip structure 100 includes the metal ball 7, in order to improve the electrical connection stability between the metal ball 7 and the conductive layer 3, a support portion 8 may be further provided between the conductive layer 3 and the metal ball 7. Specifically, the arrangement of the support portion 8 may refer to the structure of the support portion 8 described in the first aspect above, and will not be described in detail here.

[0137] The circuit board module 200 provided in the third aspect of this embodiment can realize a miniaturized design while achieving functional diversity.

[0138] The chip structure, the packaging method of the chip structure and the circuit board module disclosed in the embodiments of the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the chip structure, the packaging method of the chip structure and the circuit board module of the present invention and their core ideas; at the same time, for general technical personnel in this field, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A chip structure, characterized in that: include: A crystal grain, wherein the crystal grain has a first surface, and a first power connection portion is disposed on the first surface; an insulating layer, the insulating layer being disposed on the first surface, the insulating layer being provided with a first through hole and a mounting hole, the first through hole corresponding to the position of the first power connection portion to expose at least a portion of the first power connection portion, and the mounting hole being spaced apart from the first through hole; A conductive layer, the conductive layer is disposed on a side of the insulating layer away from the first surface, the conductive layer is electrically connected to the first power connection portion, and the conductive layer has a hollow portion, and the hollow portion corresponds to and communicates with the mounting hole; An implanted component, along the direction from the grain to the conductive layer, the implanted component is at least partially installed in the hollow portion and the mounting hole, and the implanted component is electrically connected to the conductive layer, and a portion of the outer peripheral surface of the implanted component is directly connected to the conductive layer; as well as A metal ball, wherein the metal ball is disposed on a side of the conductive layer away from the insulating layer through a ball planting process, and the metal ball is electrically connected to the conductive layer; The metal ball and the implanted element are both located on a side of the insulating layer away from the first surface, and the projections of the metal ball and the implanted element on the first surface are spaced apart; The inner wall surface of the first through hole is inclined, and the conductive layer extends to the first through hole and is directly connected to the first electrical connection portion, so that the metal ball is electrically connected to the first electrical connection portion.

2. The chip structure according to claim 1, characterized in that: The first surface is also provided with a second electrical connection portion, the second electrical connection portion is located in the mounting hole, and the second electrical connection portion is electrically connected to the conductive layer and the implanted component.

3. The chip structure according to claim 1, characterized in that: The conductive layer includes multiple layers, the multiple conductive layers are stacked, the insulating layer is arranged between two adjacent conductive layers, and a second through hole is also provided on the insulating layer between the two adjacent conductive layers, and the second through hole is used for connecting the two adjacent conductive layers to achieve electrical conduction.

4. The chip structure according to claim 3, characterized in that: The multilayer conductive layer at least comprises a first conductive layer and a second conductive layer arranged adjacent to each other, and along the direction from the crystal grain to the conductive layer, the second conductive layer is located on a side of the first conductive layer away from the crystal grain, and both the second conductive layer and the first conductive layer have the hollow portion, and the hollow portion on the second conductive layer corresponds to and is connected to the hollow portion on the first conductive layer; The insulating layer located between the first conductive layer and the second conductive layer is further provided with a second power connection portion, the second power connection portion is located in the mounting hole, and the second power connection portion is electrically connected to the first conductive layer and / or the second conductive layer; The implanted element is also electrically connected to the second power connection portion.

5. The chip structure according to claim 3, characterized in that: The insulating layer is multi-layered, and the multi-layer insulating layer at least includes a first insulating layer arranged on the first surface and a second insulating layer arranged between two adjacent conductive layers. The mounting hole and the second through hole are arranged in the second insulating layer.

6. The chip structure according to any one of claims 1 to 5, characterized in that: The chip structure also includes a supporting portion, which is electrically connected to the conductive layer. The supporting portion includes an end face and a first protrusion and a second protrusion that are arranged on the end face and opposite to each other. The first protrusion and the second protrusion extend from the end face away from the conductive layer. The metal ball is clamped and electrically connected between the first protrusion, the second protrusion and the end face.

7. The chip structure according to any one of claims 1 to 5, characterized in that: The crystal grain further comprises a second surface and an outer peripheral surface, the second surface is arranged opposite to the first surface, and the outer peripheral surface is connected to the first surface and the second surface; The chip structure further includes a plastic encapsulation layer, and the plastic encapsulation layer is coated on the outer peripheral surface and the second surface.

8. A chip structure packaging method for manufacturing the chip structure according to any one of claims 1 to 7, characterized in that: The packaging method comprises: Disposing a first electrical connection portion on a first surface of the grain, and covering the first surface with a first insulating layer; removing a portion of the first insulating layer to expose at least a portion of the first power connection portion; Covering a first conductive layer on a side of the first power connection portion away from the crystal grain, so that the first conductive layer covers the first insulating layer and the first power connection portion, and the first conductive layer is electrically connected to the first power connection portion; Disposing a hollow portion on the first conductive layer, the hollow portion corresponding to a position where a portion of the first insulating layer is removed; An implanted element is implanted into the hollow portion so that the implanted element is electrically connected to the first conductive layer.

9. The packaging method according to claim 8, characterized in that: The chip structure further includes a second insulating layer and a second conductive layer, and after the step of providing a hollow portion on the first conductive layer, the step further includes: Disposing the second insulating layer on a side of the first conductive layer away from the first insulating layer, so that the second insulating layer covers the first conductive layer and the hollow portion; removing a portion of the second insulating layer to expose at least a portion of the first conductive layer; Disposing the second conductive layer on a side of the second insulating layer away from the first conductive layer, so that the second conductive layer is electrically connected to the exposed first conductive layer; The second insulating layer at the hollow portion is removed, an implanted element is implanted into the hollow portion, and the implanted element is electrically connected to the first conductive layer and / or the second conductive layer.

10. The packaging method according to claim 9, characterized in that: After the step of providing the second conductive layer on the side of the second insulating layer away from the first conductive layer, the step further includes: A support portion is provided on a side of the second conductive layer away from the second insulating layer and electrically connected to the second conductive layer, and a metal ball is provided on a side of the support portion away from the second conductive layer and electrically connected to the second conductive layer through the support portion.

11. The packaging method according to any one of claims 8 to 10, characterized in that: The packaging method further comprises: Before the first power connection portion is provided on the first surface of the die, a second surface of the die opposite to the first surface and an outer peripheral surface connected to the first surface and the second surface are plastic-sealed.

12. The packaging method according to any one of claims 8 to 10, characterized in that: The method of removing part of the first insulating layer to expose at least part of the first power connection portion is: Laser etching or chemical etching is used to remove a portion of the first insulating layer to expose at least a portion of the first power connection portion.

13. A circuit board module, characterized in that: It comprises a circuit board and a chip structure as claimed in any one of claims 1 to 7, wherein the circuit board is electrically connected to the conductive layer.

14. The circuit board module according to claim 13, characterized in that: The circuit board is provided with an avoidance structure at a position corresponding to the implanted component, and the avoidance structure is used to avoid the implanted component.

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