Array substrate, display panel and display device

Abstract

The present invention discloses an array substrate, a display panel and a display device. The array substrate includes a driving circuit layer; the driving circuit layer is used to form a first reference signal line, a second reference signal line and a pixel circuit arranged in an array; the pixel circuit includes a driving transistor, a first switch unit and a second switch unit, the first switch unit is connected between the first reference signal line and the gate of the driving transistor, the second switch unit is connected between the second reference signal line and the anode of the light-emitting device, and the first reference signal line and the second reference signal line extend along the column direction of the pixel circuit arrangement; the first switch unit in the pixel circuits of two adjacent columns is connected to the same first reference signal line, and the second switch unit in the pixel circuits of two adjacent columns is connected to the same second reference signal line. When the array substrate is used to form a display panel, it is beneficial to improve the pixel density of the display panel on the basis of ensuring the display effect.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] Active-matrix organic light emitting diode (AMOLED) display panels have been widely used in the display field because they are superior to liquid crystal display panels in terms of display color saturation, power consumption and bending. During the display process of the AMOLED display panel, the pixel circuit drives the light-emitting device to emit light for display. The pixel circuit may include a gate initialization transistor and an anode initialization transistor, the gate initialization transistor is used to initialize the gate of the driving transistor in the pixel circuit, and the anode initialization transistor is used to initialize the anode of the light-emitting device to improve the mura phenomenon of the display panel.

[0003] In the prior art, as the requirements for the display effect of the display panel increase, the display panel can be provided with two initialization signal lines, which can provide different initialization signals for the gate initialization transistor and the anode initialization transistor respectively, thereby improving the initialization accuracy of the gate of the driving transistor and the anode of the light-emitting device, thereby improving the display effect of the display panel. However, there are certain defects. Summary of the invention

[0004] The present invention provides an array substrate, a display panel and a display device, which are beneficial to improving the pixel density of the display panel while ensuring the display effect of the display panel, and are beneficial to simplifying the circuit arrangement on the array substrate.

[0005] In a first aspect, an embodiment of the present invention provides an array substrate, comprising a driving circuit layer; the driving circuit layer is used to form a first reference signal line, a second reference signal line and a pixel circuit arranged in an array; the pixel circuit comprises a driving transistor, a first switch unit and a second switch unit, the first switch unit is connected between the first reference signal line and the gate of the driving transistor, and the first switch unit is used to control the conduction state between the first reference signal line and the gate of the driving transistor; the second switch unit is connected between the second reference signal line and the anode of the light-emitting device, and the second switch unit is used to control the conduction state between the second reference signal line and the anode of the light-emitting device;

[0006] The first reference signal line and the second reference signal line extend along the column direction of the pixel circuit arrangement; the first switch units in the pixel circuits of two adjacent columns are connected to the same first reference signal line, and the second switch units in the pixel circuits of two adjacent columns are connected to the same second reference signal line.

[0007] Optionally, the first switch unit and the second switch unit in two adjacent columns of pixel circuits in the same row are mirror-imaged in the pixel circuits, so as to facilitate the first switch unit and the second switch unit in two adjacent columns of pixel circuits to share the first reference signal line and the second reference signal line.

[0008] Optionally, the first reference signal lines and the second reference signal lines are alternately arranged along a row direction of the pixel circuits.

[0009] Optionally, two columns of the first switch units connected to the same first reference signal line are respectively arranged on both sides of the first reference signal line, and two columns of the second switch units connected to the same second reference signal line are respectively arranged on both sides of the second reference signal line. This reduces the space of the array substrate occupied by the initialization signal line, which is beneficial for improving the pixel density of the display panel.

[0010] Optionally, the first switch unit includes a first transistor, and the second switch unit includes a second transistor;

[0011] The first transistor is connected between the first reference signal line and the gate of the driving transistor, and the second transistor is connected between the second reference signal line and the anode of the light emitting device. An implementation of the first switch unit and the second switch unit is provided.

[0012] Optionally, the array substrate further includes a substrate, the pixel circuit further includes a capacitor; and the driving circuit layer includes:

[0013] A semiconductor layer, disposed on the substrate, the semiconductor layer being used to form an active layer of the driving transistor;

[0014] A first conductive layer, disposed on a side of the semiconductor layer away from the substrate, the first conductive layer being used to form a gate of the driving transistor;

[0015] A second conductive layer, disposed on a side of the first conductive layer away from the semiconductor layer, the second conductive layer being used to form the capacitor;

[0016] The third conductive layer is arranged on a side of the second conductive layer away from the first conductive layer, and the third conductive layer is used to form the first reference signal line and the second reference signal line. The specific film layer structure of the driving circuit layer is disclosed.

[0017] Optionally, the array substrate further includes a data signal line, and the third conductive layer is also used to form the data signal line.

[0018] Optionally, the array substrate further includes a data signal line, and the driving circuit layer further includes a fourth conductive layer;

[0019] The fourth conductive layer is disposed on a side of the third conductive layer away from the second conductive layer, and the fourth conductive layer is used to form the data signal line;

[0020] Preferably, the array substrate further comprises a power signal line, and the fourth conductive layer is also used to form the power signal line. By forming the data signal line and the power signal line from the fourth conductive layer, the conductive layer can be reduced.

[0021] In a second aspect, an embodiment of the present invention further provides a display panel, comprising the array substrate provided by any embodiment of the first aspect.

[0022] In a third aspect, an embodiment of the present invention further provides a display device, comprising the display panel provided by any embodiment of the second aspect.

[0023] The technical solution of the embodiment of the present invention is to initialize the gate of the driving transistor by the first reference signal provided by the first reference signal line, and to initialize the anode of the light-emitting device by the second reference signal provided by the second reference signal line, so as to improve the data writing accuracy of the pixel circuit, thereby improving the display effect when the pixel circuit drives the light-emitting device to emit light for display. At the same time, the first switch units in the pixel circuits of two adjacent columns are connected to the same first reference signal line, and the second switch units in the pixel circuits of two adjacent columns are connected to the same second reference signal line, so as to reduce the number of the first reference signal lines and the second reference signal lines on the array substrate, thereby reducing the space occupied by the first reference signal lines and the second reference signal lines on the array substrate, and more space can be used to set the pixel circuit in the same area, so as to improve the pixel density of the display panel when the array substrate is used to form the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of a pixel circuit structure provided by the prior art;

[0025] Figure 2 A schematic diagram of the structure of an array substrate provided by the prior art;

[0026] Figure 3 A schematic structural diagram of an array substrate provided by an embodiment of the present invention;

[0027] Figure 4 A schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0028] Figure 5 A schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention;

[0029] Figure 6 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0030] Figure 7 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0032] Figure 1 The following is a schematic diagram of a pixel circuit structure provided by the prior art. Figure 1 As shown, the pixel circuit includes a driving transistor Mdr, a data writing transistor M1, a threshold compensation transistor M2, a first light emission control transistor M3, a second light emission control transistor M4, a gate initialization transistor M5, an anode initialization transistor M6 and a storage capacitor Cst. The driving transistor Mdr, the data writing transistor M1, the threshold compensation transistor M2, the first light emission control transistor M3, the second light emission control transistor M4, the gate initialization transistor M5, and the anode initialization transistor M6 are exemplarily shown to be P-type transistors, such as LTPO transistors. The specific connection relationship is as follows Figure 1As shown. During the operation of the pixel circuit, in the first initialization stage, the first scan signal provided by the first scan signal line S1 controls the gate initialization transistor M5 to turn on, and the first initialization signal provided by the first initialization signal line vref1 is transmitted to the gate of the driving transistor Mdr through the gate initialization transistor M5 to initialize the gate of the driving transistor Mdr. In the data writing stage, the second scan signal provided by the second scan signal line S2 controls the data writing transistor M1 and the threshold compensation transistor M2 to turn on, and the data voltage Vdata charges the storage capacitor Cst through the data writing transistor M1, the driving transistor Mdr and the threshold compensation transistor M2, thereby storing the sum of the data voltage Vdata and the threshold voltage of the driving transistor Mdr in the storage capacitor Cst, realizing the writing of the data voltage Vdata and the threshold compensation of the driving transistor Mdr. In the second initialization stage, the third scan signal provided by the third scan signal line S3 controls the anode initialization transistor M6 to turn on, and the second initialization signal provided by the second initialization signal line vref2 is transmitted to the anode of the light-emitting device D1 through the anode initialization transistor M6 to initialize the anode of the light-emitting device D1. In the light-emitting stage, the light-emitting control signal provided by the light-emitting control signal line EM controls the first light-emitting control transistor M3 and the second light-emitting control transistor M4 to be turned on, and the driving transistor Mdr forms a driving current according to the first voltage provided by the first voltage input terminal Vdd and the gate potential, and transmits the driving current to the anode of the light-emitting device D1 through the second light-emitting control transistor M4, driving the light-emitting device D1 to emit light.

[0033] Figure 2 The following is a schematic diagram of the structure of an array substrate provided by the prior art. Figure 2 As shown, a plurality of first initialization signal lines vref1 and a plurality of second initialization signal lines vref2 are provided on the array substrate, and the pixel circuits arranged in an array are arranged. The first initialization signal line vref1 and the second initialization signal line vref2 are provided on the second conductive layer of the array substrate, and extend along the row direction of the pixel circuit. The first initialization signal line vref1 is connected to the gate initialization transistor M5, and is used to provide a first initialization signal for the gate initialization transistor M5 in a row of pixel circuits. The second initialization signal line vref2 is connected to the anode initialization transistor M6, and is used to provide a second initialization signal for the anode initialization transistor M6 in a row of pixel circuits. The inventor has found through research that since the first initialization signal line vref1 and the second initialization signal line vref2 are provided on the array substrate at the same time, relative to one initialization signal line corresponding to one row of pixel circuits, the number of initialization signal lines on the array substrate is increased, and the space of the array substrate occupied by the initialization signal lines is increased, thereby reducing the space for setting the pixel circuits on the array substrate, which is not conducive to setting more pixel circuits on the array substrate under the same area, and further not conducive to improving the pixel density of the display panel.

[0034] In view of the above technical problems, an embodiment of the present invention provides an array substrate. Figure 3 A schematic diagram of the structure of an array substrate provided by an embodiment of the present invention, Figure 4 FIG. 1 is a schematic diagram of a pixel circuit provided by an embodiment of the present invention. Figure 3 and Figure 4 As shown, the array substrate includes a driving circuit layer; the driving circuit layer is used to form a first reference signal line VREF1, a second reference signal line VREF2 and a pixel circuit P1 arranged in an array; the pixel circuit P1 includes a driving transistor Tdr, a first switch unit 120 and a second switch unit 130, the first switch unit 120 is connected between the first reference signal line VREF1 and the gate of the driving transistor Tdr, and the first switch unit 120 is used to control the conduction state between the first reference signal line VREF and the gate of the driving transistor Tdr; the second switch unit 130 The second switch unit 130 is connected between the second reference signal line VREF2 and the anode of the light-emitting device E1, and is used to control the conduction state between the second reference signal line VREF2 and the anode of the light-emitting device E1; the first reference signal line VREF1 and the second reference signal line VREF2 extend along the column direction Y in which the pixel circuits P1 are arranged; the first switch units 120 in the pixel circuits P1 of two adjacent columns are connected to the same first reference signal line VREF1, and the second switch units 130 in the pixel circuits P1 of two adjacent columns are connected to the same second reference signal line VREF2.

[0035] Specifically, refer to Figure 4, the array substrate may include a substrate 110, and the driving circuit layer is arranged on the substrate 110. The pixel circuit P1 includes a driving transistor Tdr, a first switch unit 120, a second switch unit 130, a data writing transistor T3, a compensation transistor T4, a first light emission control transistor T5, a second light emission control transistor T6 and a capacitor C1, a first end of the first switch unit 120 is connected to a first reference signal line VREF1, a control end of the first switch unit 120 is connected to a first scan signal line SCAN1, a second end of the first switch unit 120 is connected to a second electrode of the compensation transistor T4, a gate of the driving transistor Tdr and a first electrode of the capacitor C1, a first end of the second switch unit 130 is connected to a second reference signal line VREF2, a second end of the second switch unit 130 is connected to an anode of the light emitting device E1 and a second electrode of the second light emission control transistor T6, and a control end of the second switch unit 130 is connected to a third scan signal line SCAN1. The first electrode of the data writing transistor T3 is connected to the data voltage line VDATA, the second electrode of the data writing transistor T3 is connected to the first electrode of the driving transistor Tdr and the second electrode of the first light emitting control transistor T5, the gate of the data writing transistor T3 is connected to the second scanning signal line SCAN2, the first electrode of the compensation transistor T4 is connected to the second electrode of the driving transistor Tdr and the first electrode of the second light emitting control transistor T6, the gate of the compensation transistor T4 is connected to the second scanning signal line SCAN2, the first electrode of the first light emitting control transistor T5 and the second electrode of the capacitor C1 are connected to the first power signal line VDD, the gate of the first light emitting control transistor T5 and the gate of the second light emitting control transistor T6 are connected to the light emitting control signal line EM1, and the cathode of the light emitting device E1 is connected to the second power signal line VSS.

[0036] The working process of the pixel circuit includes a first initialization stage, a data writing stage, a second initialization stage and a light emitting stage. In the first initialization stage, the first scanning signal provided by the first scanning signal line SCAN1 controls the first switch unit 120 to turn on the first reference signal line VREF1 and the gate of the driving transistor Tdr, so that the first reference signal provided by the first reference signal line VREF1 is transmitted to the gate of the driving transistor Tdr, and the gate of the driving transistor Tdr is initialized. At the end of the first initialization stage, the driving transistor Tdr is turned on. In the data writing stage, the second scanning signal provided by the second scanning signal line SCAN2 controls the data writing transistor T3 and the compensation transistor T4 to turn on, and the data voltage provided by the data signal line VDATA is written to the gate of the driving transistor Tdr through the data writing transistor T3, the driving transistor Tdr and the compensation transistor T4, so as to realize data writing and threshold voltage compensation of the driving transistor Tdr, and the capacitor C1 maintains the gate potential of the driving transistor Tdr. In the second initialization stage, the third scan signal provided by the third scan signal line SCAN3 controls the second switch unit 130 to turn on the second reference signal line VREF2 and the anode of the light-emitting device E1, so that the second reference signal provided by the second reference signal line VREF2 is transmitted to the anode of the light-emitting device E1, and the anode of the light-emitting device E1 is initialized. Thus, the gate of the driving transistor Tdr and the anode of the light-emitting device E1 can be initialized respectively. Then in the light-emitting stage, the light-emitting control signal provided by the light-emitting control signal line EM1 controls the first light-emitting control transistor T5 and the second light-emitting control transistor T6 to turn on, and the first power signal provided by the first power signal line VDD is transmitted to the first electrode of the driving transistor Tdr. The driving transistor Tdr forms a driving current according to the first power signal of the first electrode and the data voltage after the gate compensates the threshold voltage, and transmits the driving current to the anode of the light-emitting device E1 through the second light-emitting control transistor T6, driving the light-emitting device E1 to emit light. In the above process, the first reference signal provided by the first reference signal line VREF1 and the second reference signal provided by the second reference signal line VREF2 respectively initialize the gate of the driving transistor Tdr and the anode of the light-emitting device E1, which can improve the data writing accuracy of the pixel circuit, thereby improving the display effect when the pixel circuit drives the light-emitting device E1 to emit light for display.

[0037] On this basis, reference Figure 3, the first reference signal line VREF1 and the second reference signal line VREF2 extend along the column direction Y in which the pixel circuits P1 are arranged, so that the first reference signal line VREF1 and the second reference signal line VREF2 can provide the first reference signal and the second reference signal for at least one column of pixel circuits P1, respectively. When the first switch units 120 in the pixel circuits P1 of two adjacent columns are connected to the same first reference signal line VREF1, and the second switch units 130 in the pixel circuits P1 of two adjacent columns are connected to the same second reference signal line VREF2, the first reference signal line VREF1 and the second reference signal line VREF2 can provide the first reference signal and the second reference signal for the two columns of pixel circuits P1, respectively, and the number of the first reference signal lines VREF1 and the second reference signal lines VREF2 can be reduced, thereby reducing the space occupied by the first reference signal lines VREF1 and the second reference signal lines VREF2 on the array substrate, and more space can be provided for the pixel circuits P1 under the same area, and thus when the array substrate is used to form a display panel, it is beneficial to improve the pixel density of the display panel.

[0038] The technical solution of the embodiment of the present invention is to initialize the gate of the driving transistor by the first reference signal provided by the first reference signal line, and to initialize the anode of the light-emitting device by the second reference signal provided by the second reference signal line, so as to improve the data writing accuracy of the pixel circuit, thereby improving the display effect when the pixel circuit drives the light-emitting device to emit light for display. At the same time, the first switch units in the pixel circuits of two adjacent columns are connected to the same first reference signal line, and the second switch units in the pixel circuits of two adjacent columns are connected to the same second reference signal line, so as to reduce the number of the first reference signal lines and the second reference signal lines on the array substrate, thereby reducing the space occupied by the first reference signal lines and the second reference signal lines on the array substrate, and more space can be used to set the pixel circuit in the same area, so as to improve the pixel density of the display panel when the array substrate is used to form the display panel.

[0039] Continue to refer Figure 3 The positions of the first switch unit 120 and the second switch unit 130 in two adjacent columns of pixel circuits P1 in the same row are mirror-imaged in the pixel circuit P1.

[0040] Specifically, each pixel circuit P1 includes a first switch unit 120 and a second switch unit 130, and the first switch unit 120 and the second switch unit 130 can be arranged along the row direction X in which the pixel circuits P1 are arranged. When the first switch unit 120 and the second switch unit 130 of two adjacent columns of pixel circuits P1 share a reference signal line, the positions of the first switch unit 120 and the second switch unit 130 in the two adjacent columns in the pixel circuit P1 are mirrored. For example, Figure 3 As shown, Figure 3 The second switch unit 130 in the first column of pixel circuits P1 is connected to the second switch unit 130 in the second column of pixel circuits P1 through a conductive line, and the second switch unit 130 in the first column of pixel circuits P1 is connected to the second reference signal line VREF2, so that the second switch unit 130 in the first column of pixel circuits P1 and the second switch unit 130 in the second column of pixel circuits P1 share a second reference signal line VREF2. At this time, the second switch unit 130 in the first column of pixel circuits P1 and the second switch unit 130 in the second column of pixel circuits P1 are mirror-imaged in the positions in the pixel circuit P1. Specifically, the second switch unit 130 in the first column of pixel circuits P1 and the second switch unit 130 in the second column of pixel circuits P1 are adjacently arranged along the row direction X in which the pixel circuits P1 are arranged, so that when the second switch unit 130 in the first column of pixel circuits P1 is connected to the second switch unit 130 in the second column of pixel circuits P1 through a conductive line, the length of the conductive line can be reduced, which is beneficial to the line setting on the array substrate. Similarly, Figure 3 The first switch unit 120 in the second column of pixel circuits P1 is connected to the first switch unit 120 in the third column of pixel circuits P1 through a conductive line, and the first switch unit 120 in the third column of pixel circuits P1 is connected to the first reference signal line VREF1, so that the first switch unit 120 in the second column of pixel circuits P1 and the first switch unit 120 in the third column of pixel circuits P1 share a first reference signal line VREF1. At this time, the positions of the first switch unit 120 in the second column of pixel circuits P1 and the first switch unit 120 in the third column of pixel circuits P1 in the pixel circuit P1 are mirrored. Specifically, the first switch unit 120 in the second column of pixel circuits P1 and the first switch unit 120 in the third column of pixel circuits P1 are adjacently arranged along the row direction X in which the pixel circuits P1 are arranged, so that when the first switch unit 120 in the second column of pixel circuits P1 is connected to the first switch unit 120 in the third column of pixel circuits P1 through a conductive line, the length of the conductive line can be reduced, which is beneficial to the line setting on the array substrate.

[0041] Continue to refer Figure 3 The first reference signal line VREF1 and the second reference signal line VREF2 are alternately arranged along a row direction X in which the pixel circuits are arranged.

[0042] Specifically, Figure 3As shown, when the first switch unit 120 and the second switch unit 130 in two adjacent columns of pixel circuits P1 are mirror-imaged in the positions in the pixel circuit P1, the first reference signal line VREF1 and the second reference signal line VREF2 can be alternately arranged along the row direction X of the pixel circuit arrangement, so that the first reference signal line VREF1 is arranged between the two mirror-imaged first switch units 120, and the second reference signal line VREF2 is arranged between the two mirror-imaged second switch units 130, which is conducive to simplifying the connection line between the first switch unit 120 and the first reference signal line VREF1, and is conducive to simplifying the connection line between the second switch unit 130 and the second reference signal line VREF2, and further conducive to simplifying the line arrangement on the array substrate.

[0043] Continue to refer Figure 3 The two columns of first switch units 120 connected to the same first reference signal line VREF1 are respectively arranged on both sides of the first reference signal line VREF1, and the two columns of second switch units 130 connected to the same second reference signal line VREF2 are respectively arranged on both sides of the second reference signal line VREF2.

[0044] Specifically, Figure 3 As shown, when the first switch unit 120 and the second switch unit 130 of two adjacent columns of pixel circuits P1 share a reference signal line, along the row direction X in which the pixel circuits P1 are arranged, the first reference signal line VREF1 shared by the first switch units 120 in the two adjacent columns of pixel circuits P1 is located between the two columns of first switch units 120 connected thereto, and the second reference signal line VREF2 shared by the second switch units 130 in the two adjacent columns of pixel circuits P1 is located between the two columns of second switch units 130 connected thereto, so that when the first switch unit 120 is connected to the first reference signal line VREF1, it is helpful to simplify the connection line between the first switch unit 120 and the first reference signal line VREF1. And when the second switch unit 130 is connected to the second reference signal line VREF2, it is helpful to simplify the connection line between the second switch unit 130 and the second reference signal line VREF2, thereby helping to simplify the line arrangement on the array substrate. For example, as Figure 3 As shown, Figure 3 The second switch unit 130 in the first column of pixel circuits P1 and the second switch unit 130 in the second column of pixel circuits P1 share the same second reference signal line VREF2. At this time, along the row direction X in which the pixel circuits P1 are arranged, the second reference signal line VREF2 is set between the second switch unit 130 in the first column of pixel circuits P1 and the second switch unit 130 in the second column of pixel circuits P1. Figure 3The first switch unit 120 in the second column of pixel circuits P1 and the first switch unit 120 in the third column of pixel circuits P1 share the same first reference signal line VREF1. At this time, along the row direction X in which the pixel circuits P1 are arranged, the first reference signal line VREF1 is arranged between the first switch unit 120 in the second column of pixel circuits P1 and the first switch unit 120 in the third column of pixel circuits P1.

[0045] Figure 5 FIG. 1 is a schematic diagram of another pixel circuit provided by an embodiment of the present invention. Figure 5 As shown, the first switch unit 120 includes a first transistor T1, and the second switch unit 130 includes a second transistor T2; the first transistor T1 is connected between the first reference signal line VREF1 and the gate of the driving transistor Tdr, and the second transistor T2 is connected between the second reference signal line VREF2 and the anode of the light emitting device E1.

[0046] Specifically, Figure 5 exemplarily shows that the first transistor T1 and the second transistor T2 are P-type transistors. When the first scan signal provided by the first scan signal line SCAN1 is at a low level, the first transistor T1 is turned on, so that the first reference signal provided by the first reference signal line VREF1 is transmitted to the gate of the driving transistor Tdr, and the gate of the driving transistor Tdr is initialized. When the third scan signal provided by the third scan signal line SCAN3 is at a low level, the second transistor T2 is turned on, so that the second reference signal provided by the second reference signal line VREF2 is transmitted to the anode of the light-emitting device E1, and the anode of the light-emitting device E1 is initialized. Among them, each scan signal line can provide a scan signal for a row of pixel circuits P1. When the first scan signal line SCAN1 provides a first scan signal for a row of pixel circuits P1, the third scan signal line SCAN3 can provide a first scan signal line for the next row of pixel circuits P1.

[0047] Continue to refer Figures 3 to 5 , the driving circuit layer includes:

[0048] A semiconductor layer S1 is disposed on the substrate 110, and the semiconductor layer S1 is used to form an active layer of the driving transistor Tdr;

[0049] A first conductive layer M1 is disposed on a side of the semiconductor layer S1 away from the substrate 110 , and the first conductive layer M1 is used to form a gate of the driving transistor Tdr;

[0050] A second conductive layer M2 is disposed on a side of the first conductive layer M1 away from the semiconductor layer S1, and the second conductive layer M2 is used to form a capacitor C1;

[0051] The third conductive layer M3 is disposed on a side of the second conductive layer M2 away from the first conductive layer M1 . The third conductive layer M3 is used to form a first reference signal line VREF1 and a second reference signal line VREF2 .

[0052] Specifically, the semiconductor layer S1 is used to form an active layer of a transistor in the pixel circuit P1. Figure 3 As shown, the pixel circuit P1 includes a driving transistor Tdr, and the semiconductor layer S1 can form an active layer of the driving transistor Tdr. According to different doping concentrations of the semiconductor layer S1, a channel region, a source region, and a drain region of the active layer of the driving transistor Tdr can be formed respectively. The pixel circuit P1 can also include a data writing transistor T3, a compensation transistor T4, a first light-emitting control transistor T5, and a second light-emitting control transistor T6. The active layer of each transistor can be formed by patterning the semiconductor layer S1. When the first switching unit 120 includes a first transistor T1 and the second switching unit 130 includes a second transistor T2, the semiconductor layer S1 can also be used to form the active layer of the first transistor T1 and the second transistor T2. In addition, by heavily doping a portion of the semiconductor layer S1, the semiconductor layer S1 can be used for a conductive line. For example, as Figure 3 As shown, when the first switch units 120 in the pixel circuits P1 of two adjacent columns are connected to the same first reference signal line VREF1, the semiconductor layer S1 may be heavily doped to form a first conductive line L1, so that the first switch units 120 in the pixel circuits P1 of two adjacent columns are connected through the first conductive line L1, and then one of the first switch units 120 is connected to the first reference signal line VREF1. Similarly, when the second switch units 130 in the pixel circuits P1 of two adjacent columns are connected to the same second reference signal line VREF2, the semiconductor layer S1 may be heavily doped to form a second conductive line L2, so that the second switch units 130 in the pixel circuits P1 of two adjacent columns are connected through the second conductive line L2, and then one of the second switch units 130 is connected to the second reference signal line VREF2.

[0053] The material of the first conductive layer M1 can be metal. The first conductive layer M1 can be used to form the gate of the driving transistor Tdr. The pixel circuit P1 can also include a data writing transistor T3, a compensation transistor T4, a first light emission control transistor T5, and a second light emission control transistor T6. The first conductive layer M1 can simultaneously form the gates of the data writing transistor T3, the compensation transistor T4, the first light emission control transistor T5, and the second light emission control transistor T6 by patterning. Similarly, when the first switching unit 120 includes a first transistor T1 and the second switching unit 130 includes a second transistor T2, the first conductive layer M1 can also form the gates of the first transistor T1 and the second transistor T2 by patterning. In addition, the first conductive layer M1 can also be used to form a plate of the capacitor C1 in the pixel circuit P1, a scanning signal line, and a light emission control signal line, so as to provide a scanning signal and a light emission control signal for a row of pixel circuits P1. For example, as Figure 3 As shown, the first switch unit 120 includes a first transistor T1, and the second switch unit 130 includes a second transistor T2. The first transistor T1 and the second transistor T2 are arranged along the row direction X in which the pixel circuits P1 are arranged. The first transistor T1 is the first transistor T1 in the pixel circuit P1 of the next row, and the second transistor T2 is the second transistor T2 in the pixel circuit P1 of the current row. At this time, the scanning signal line connected to the first transistor T1 and the second transistor T2 in the same row can be the third scanning signal line SCAN3 of the pixel circuit P1 of the current row, or the first scanning signal line SCAN1 of the pixel circuit P1 of the next row. In addition, the scanning signal line connected to the data writing transistor T3 and the compensation transistor T4 in the same pixel circuit P1 is the second scanning signal line SCAN2 in the pixel circuit P1 of the current row, and the signal line connected to the first light emission control transistor T5 and the second light emission control transistor T6 in the same pixel circuit P1 is the light emission control signal line EM1 in the pixel circuit P1 of the current row.

[0054] The material of the second conductive layer M2 can be metal, and the second conductive layer M2 can be used to form another electrode plate of the capacitor C1 in the pixel circuit P1. At this time, the vertical projection of the second conductive layer M2 in the thickness direction of the substrate 110 overlaps with the vertical projection of the part of the first conductive layer M1 used to form a plate of the capacitor C1 in the thickness direction of the substrate 110 to form the capacitor C1.

[0055] The first reference signal line VREF1 and the second reference signal line VREF2 extend along the column direction Y of the pixel circuit P1. The material of the third conductive layer M3 may be metal. The third conductive layer M3 may be used to separately form the first reference signal line VREF1 and the second reference signal line VREF2 to avoid excessive overlap between the first reference signal line VREF1 and the second reference signal line VREF2 and the scanning signal lines (including the first scanning signal line SCAN1, the second scanning signal line SCAN2 and the third scanning signal line SCAN3) and the light-emitting control signal line EM1 formed by the first conductive layer M1, thereby avoiding a short circuit between the first reference signal line VREF1 and the second reference signal line VREF2 and the scanning signal lines and the light-emitting control signal line EM1, thereby ensuring the normal operation of the pixel circuit P1.

[0056] Continue to refer Figures 3 to 5 The array substrate further includes a data signal line VDATA, and the driving circuit layer further includes a fourth conductive layer M4; the fourth conductive layer M4 is disposed on a side of the third conductive layer M3 away from the second conductive layer M2, and the fourth conductive layer M4 is used to form the data signal line VDATA.

[0057] Specifically, the fourth conductive layer M4 can be used to form a data signal line VDATA, and the data signal line VDATA extends along the column direction Y in which the pixel circuits P1 are arranged, and is used to provide a data voltage for a column of pixel circuits P1. On the array substrate, there are many data signal lines VDATA. By arranging the first reference signal line VREF1 and the second reference signal line VREF2 in different layers from the data signal line VDATA, the risk of short circuit between the first reference signal line VREF1 and the second reference signal line VREF2 and the data signal line VDATA can be reduced, and at the same time, the arrangement of the first reference signal line VREF1 and the second reference signal line VREF2 in the third conductive layer M3 is simplified, and the arrangement of the data signal line VDATA in the fourth conductive layer M4 is simplified.

[0058] It should be noted that the material of the fourth conductive layer M4 may be metal, and the material of the third conductive layer M3 and the material of the fourth conductive layer M4 may be the same as or different from each other, which is not limited here.

[0059] Continue to refer Figures 3 to 5 The array substrate also includes a power signal line VDD, and the fourth conductive layer M4 is also used to form the power signal line VDD.

[0060] Specifically, the power signal line VDD extends along the column direction Y of the pixel circuit P1, and its extension direction is the same as the extension direction of the data signal line VDATA. The fourth conductive layer M4 can also be used to form the power signal line VDD, so that the power signal line VDD and the data signal line VDATA are arranged on the same layer, which reduces the conductive layer arrangement on the array substrate while avoiding the short circuit between the data signal line VDATA and the power signal line VDD.

[0061] On the basis of the above technical solutions, optionally, the data signal line VDATA of the array substrate may also be formed by the third conductive layer M3.

[0062] Specifically, the first reference signal line VREF1 and the second reference signal line VREF2 extend along the column direction Y of the pixel circuit P1, and the data signal line VDATA also extends along the column direction Y of the pixel circuit P1. When the third conductive layer M3 is used to form the first reference signal line VREF1 and the second reference signal line VREF2, it can also be used to form the data signal line VDATA. The first reference signal line VREF1, the second reference signal line VREF2 and the data signal line VDATA can be arranged on the same layer on the basis of avoiding a short circuit between the first reference signal line VREF1 and the second reference signal line VREF2 and the data signal line VDATA.

[0063] When the fourth conductive layer M4 of the array substrate is used to form the power signal line VDD, a grid-shaped extended power signal line VDD can be formed on the fourth conductive layer M4, which is beneficial to reducing the voltage drop from the power signal line VDD to the pixel circuit P1, thereby facilitating improving the display uniformity of the display panel formed by the array substrate.

[0064] An embodiment of the present invention further provides a display panel. Figure 6 FIG. 1 is a schematic diagram of a display panel provided by an embodiment of the present invention. Figure 6 As shown, the display panel 10 includes an array substrate 11 provided by any embodiment of the present invention.

[0065] Specifically, the display panel 10 further includes a plurality of light-emitting units 12 located on a side of the driving circuit layer away from the substrate 110. The pixel circuits P1 formed in the driving circuit layer are arranged in one-to-one correspondence with the light-emitting units 12. The pixel circuits P1 are used to provide a driving current to the corresponding light-emitting units 12 to drive the corresponding light-emitting units 12 to emit light. The array substrate 11 is the array substrate 11 provided in any embodiment of the present invention, and therefore has the same beneficial effects as the array substrate 11 provided in any embodiment of the present invention, which will not be described in detail herein. The display panel 10 can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, etc.

[0066] An embodiment of the present invention further provides a display device. Figure 7 FIG. 1 is a schematic diagram of a display device provided by an embodiment of the present invention. Figure 7 As shown, the display device 20 includes the display panel 10 provided by any embodiment of the present invention.

[0067] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. An array substrate, characterized in that: It includes a driving circuit layer; the driving circuit layer is used to form a first reference signal line, a second reference signal line and a pixel circuit arranged in an array; The pixel circuit includes a driving transistor, a first switch unit and a second switch unit, wherein the first switch unit is connected between the first reference signal line and the gate of the driving transistor, and the first switch unit is used to control the conduction state between the first reference signal line and the gate of the driving transistor; the second switch unit is connected between the second reference signal line and the anode of the light-emitting device, and the second switch unit is used to control the conduction state between the second reference signal line and the anode of the light-emitting device; The first reference signal line and the second reference signal line extend along the column direction of the pixel circuit arrangement; the first switch units in the pixel circuits of two adjacent columns are connected to the same first reference signal line, and the second switch units in the pixel circuits of two adjacent columns are connected to the same second reference signal line.

2. The array substrate according to claim 1, characterized in that: The positions of the first switch unit and the second switch unit in two adjacent columns of pixel circuits in the same row are mirror-imaged in the pixel circuits.

3. The array substrate according to claim 2, characterized in that: The first reference signal lines and the second reference signal lines are alternately arranged along a row direction in which the pixel circuits are arranged.

4. The array substrate according to claim 1, characterized in that: The two columns of the first switch units connected to the same first reference signal line are respectively arranged on both sides of the first reference signal line, and the two columns of the second switch units connected to the same second reference signal line are respectively arranged on both sides of the second reference signal line.

5. The array substrate according to claim 1, characterized in that: The first switch unit includes a first transistor, and the second switch unit includes a second transistor; The first transistor is connected between the first reference signal line and the gate of the driving transistor, and the second transistor is connected between the second reference signal line and the anode of the light emitting device.

6. The array substrate according to any one of claims 1 to 5, characterized in that: The array substrate further includes a substrate, the pixel circuit further includes a capacitor; and the driving circuit layer includes: A semiconductor layer, disposed on the substrate, the semiconductor layer being used to form an active layer of the driving transistor; A first conductive layer, disposed on a side of the semiconductor layer away from the substrate, the first conductive layer being used to form a gate of the driving transistor; A second conductive layer, disposed on a side of the first conductive layer away from the semiconductor layer, the second conductive layer being used to form the capacitor; The third conductive layer is disposed on a side of the second conductive layer away from the first conductive layer, and the third conductive layer is used to form the first reference signal line and the second reference signal line.

7. The array substrate according to claim 6, characterized in that: It also includes a data signal line, and the third conductive layer is also used to form the data signal line.

8. The array substrate according to claim 6, characterized in that: It also includes a data signal line, and the driving circuit layer also includes a fourth conductive layer; the fourth conductive layer is arranged on a side of the third conductive layer away from the second conductive layer, and the fourth conductive layer is used to form the data signal line.

9. The array substrate according to claim 8, characterized in that: It also includes a power signal line, and the fourth conductive layer is also used to form the power signal line.

10. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 9.

11. A display device, characterized in that: Comprising the display panel according to claim 10.

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