Flip-chip light emitting diode and method for preparing the same

Abstract

The invention provides a flip-chip light-emitting diode and a preparation method thereof. The metal reflection layer and the insulating reflection layer of the ODR reflection layer are used to form a MIS capacitor structure with an epitaxial layer. The second electrode is connected to a relatively high potential and the third electrode is connected to a relatively low potential, so that the light-emitting layer in the epitaxial layer emits light. At the same time, the first electrode is connected to a relatively high potential and the third electrode is connected to a relatively low potential, so that electrons gather from the first semiconductor layer of the epitaxial layer to the light-emitting layer and holes gather from the second semiconductor layer of the epitaxial layer to the light-emitting layer, thereby improving the hole injection efficiency, increasing the radiation recombination efficiency in the light-emitting layer, and improving the photoelectric conversion efficiency without reducing the transmission efficiency of the radiation recombination luminescence, and the cost is low. The invention only slightly improves the existing flip-chip light-emitting diode and will not significantly increase the complexity of the structure and the preparation process.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a flip-chip light emitting diode and a preparation method thereof. Background Art

[0002] Improving the photoelectric conversion efficiency of light-emitting diodes is a technical focus that has attracted much attention at present, especially for light-emitting diodes based on III-N materials (compound materials formed by III-N materials and nitrogen, such as GaN, AlGaN and other materials). Since P-type doping activation of III-N materials is relatively difficult, the hole concentration of the P-type semiconductor layer of the epitaxial layer is one to two orders of magnitude lower than the electron concentration of the N-type semiconductor layer, and the effective mass of holes is also greater than the effective mass of electrons. At the same time, the mobility of holes is also significantly lower than that of electrons. Therefore, how to obtain a higher hole concentration and a better hole injection effect is one of the key issues in solving the photoelectric conversion efficiency of light-emitting diodes.

[0003] Compared with upright LEDs, flip-chip LEDs can alleviate the current congestion phenomenon and the chip's thermal conductivity. Flip-chip LEDs usually prepare an ohmic contact layer and a metal or DBR (Distributed Bragg Reflectors) reflective layer on the P-type semiconductor layer. However, the reflectivity of the metal or DBR reflective layer is not optimal, and the reflectivity of the DBR reflective layer is also related to the angle. Therefore, the use of ODR (Omni-Directional Reflector) reflectors can improve these problems, but it is necessary to form an array of through holes in the ODR, and the current expansion layer is electrically connected to the ohmic contact layer after passing through the through holes. For the area outside the through hole (the area directly connected to the non-current expansion layer), the carrier transport effect is relatively poor under high current, resulting in poor hole injection effect, which will affect the electro-optical conversion efficiency of the flip-chip LED under high working current density. Summary of the invention

[0004] The object of the present invention is to provide a flip-chip light emitting diode and a preparation method thereof, so as to solve the problem of low photoelectric conversion efficiency of the existing flip-chip light emitting diode.

[0005] In order to achieve the above object, the present invention provides a flip-chip light emitting diode, comprising:

[0006] substrate;

[0007] The epitaxial layer is located on the substrate and includes a first semiconductor layer, a light-emitting layer and a second semiconductor layer arranged in sequence from bottom to top;

[0008] The ODR reflective layer comprises an insulating reflective layer and a metal reflective layer sequentially stacked on the epitaxial layer, wherein the metal reflective layer, the insulating reflective layer and the epitaxial layer constitute a MIS capacitor structure; and

[0009] The first electrode, the second electrode and the third electrode which are insulated from each other are electrically connected to the metal reflective layer, the second semiconductor layer and the first semiconductor layer respectively.

[0010] Optionally, also include:

[0011] A plurality of grooves, penetrating the second semiconductor layer and the light emitting layer and exposing the first semiconductor layer;

[0012] a plurality of first through holes, penetrating the ODR reflective layer and exposing the second semiconductor layer;

[0013] a plurality of second through holes, penetrating the ODR reflective layer and communicating with the corresponding grooves; and,

[0014] The dielectric layer is located on the ODR reflective layer and at least covers the sidewalls of the first through-hole and the second through-hole corresponding to the metal reflective layer, and is used for electrically isolating the first electrode, the second electrode and the third electrode.

[0015] Optionally, the first electrode is located on the dielectric layer and passes through the dielectric layer to be electrically connected to the metal reflective layer; the dielectric layer comprises a first current spreading layer and a second current spreading layer which are insulated from each other, the second electrode is located on the dielectric layer and passes through a portion of the thickness of the dielectric layer to be electrically connected to the first current spreading layer, the first current spreading layer passes through the remaining thickness of the dielectric layer and fills the first perforation to be electrically connected to the second semiconductor layer; the third electrode is located on the dielectric layer and passes through a portion of the thickness of the dielectric layer to be electrically connected to the second current spreading layer, the second current spreading layer passes through the remaining thickness of the dielectric layer and fills the second perforation and the groove to be electrically connected to the first semiconductor layer.

[0016] Optionally, the dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer stacked in sequence on the metal reflective layer, the first current spreading layer is located between the first dielectric layer and the second dielectric layer, penetrates the first dielectric layer and fills the first perforation, and is electrically connected to the second semiconductor layer, the second current spreading layer is located between the second dielectric layer and the third dielectric layer, penetrates the second dielectric layer and the first dielectric layer and fills the second perforation and the groove, and is electrically connected to the first semiconductor layer.

[0017] Optionally, also include:

[0018] The first ohmic contact layer is located on the second semiconductor layer and at the bottom of each of the first through-holes. After the first current spreading layer fills the first through-holes, it is electrically connected to the second semiconductor layer through the first ohmic contact layer.

[0019] Optionally, the material of the first ohmic contact layer is a metal material; and / or the thickness of the first ohmic contact layer is 10 nm to 200 nm.

[0020] Optionally, the material of the first ohmic contact layer is a transparent conductive material, and the first ohmic contact layer is further covered with a first etching protection layer; and / or the thickness of the first ohmic contact layer is 10 nm to 200 nm.

[0021] Optionally, also include:

[0022] The second ohmic contact layer is located on the first semiconductor layer and in each of the grooves. After the second current spreading layer fills the second through-hole and the grooves, it is electrically connected to the first semiconductor layer through the second ohmic contact layer.

[0023] Optionally, a second etching protection layer is further formed on the first current spreading layer and the second current spreading layer.

[0024] Optionally, the material of the second etching protection layer includes Pt; and / or the thickness of the second etching protection layer is greater than 200 nm.

[0025] Optionally, a first adhesion layer is provided between the bottom surface of the first current spreading layer and / or the second current spreading layer and the dielectric layer; and / or a second adhesion layer is provided between the top surface of the first current spreading layer and / or the second current spreading layer and the dielectric layer.

[0026] Optionally, the material of the first adhesion layer and / or the second adhesion layer is at least one of Ti, Cr and Ni; the thickness of the first adhesion layer and / or the second adhesion layer is 5 nm to 50 nm.

[0027] Optionally, the materials of the first dielectric layer, the second dielectric layer and the third dielectric layer are SiO2, SiN x , at least one of AlN, BN and diamond; and / or, the thicknesses of the first dielectric layer, the second dielectric layer and the third dielectric layer are respectively 200nm~2μm.

[0028] Optionally, the insulating reflective layer is a single-layer reflective film or is formed by two layers of reflective films with different refractive indices being alternately distributed.

[0029] Optionally, the material of the reflective film is SiO2, Al2O3, HfO2, SiNx , AlN, BN or MgF2; and / or, the thickness of the reflective film is λ / 4n, wherein λ is the light emitting wavelength of the light emitting layer and n is the refractive index of the reflective film.

[0030] Optionally, when the flip-chip light emitting diode is in use, the first electrode is connected to a first potential, the second electrode is connected to a second potential, the third electrode is connected to a third potential, and both the first potential and the second potential are greater than the third potential.

[0031] Optionally, the difference between the first potential and the third potential is 3V to 10V.

[0032] The present invention also provides a method for preparing a flip-chip light-emitting diode, comprising:

[0033] providing a substrate;

[0034] forming an epitaxial layer, wherein the epitaxial layer is located on the substrate, and the epitaxial layer includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer arranged in sequence from bottom to top;

[0035] forming an ODR reflective layer, wherein the ODR reflective layer comprises an insulating reflective layer and a metal reflective layer sequentially stacked on the epitaxial layer, wherein the metal reflective layer, the insulating reflective layer and the epitaxial layer constitute a MIS capacitor structure; and,

[0036] A first electrode, a second electrode and a third electrode which are insulated from each other are formed. The first electrode, the second electrode and the third electrode are electrically connected to the metal reflective layer, the second semiconductor layer and the first semiconductor layer respectively.

[0037] Optionally, the step of forming the ODR reflective layer includes:

[0038] Etching the second semiconductor layer and the light emitting layer to form a plurality of grooves exposing the first semiconductor layer;

[0039] forming the insulating reflective layer on the second semiconductor layer; and,

[0040] The metal reflection layer is formed on a portion of the insulating reflection layer. The metal reflection layer has a plurality of third through holes and a plurality of fourth through holes. The third through holes expose the insulating reflection layer, and the fourth through holes are connected to the groove.

[0041] Optionally, after forming the groove and before forming the insulating reflective layer, the method further includes:

[0042] A first ohmic contact layer is formed on a portion of the second semiconductor layer, and each of the third through holes is aligned with the first ohmic contact layer.

[0043] Optionally, the material of the first ohmic contact layer is a metal material; and / or the thickness of the first ohmic contact layer is 10 nm to 200 nm.

[0044] Optionally, after forming the first ohmic contact layer, a first etching protection layer is further formed on the first ohmic contact layer.

[0045] Optionally, the material of the first ohmic contact layer is a transparent conductive material; and / or the thickness of the first ohmic contact layer is 10 nm to 200 nm.

[0046] Optionally, when forming the first ohmic contact layer, a second ohmic contact layer is also formed on the first semiconductor layer in each of the grooves, and each of the fourth through holes exposes the second ohmic contact layer.

[0047] Optionally, the step of forming the first electrode, the second electrode and the third electrode which are insulated from each other includes:

[0048] Forming a first dielectric layer on the metal reflective layer, the first dielectric layer also filling the third through-hole, the fourth through-hole and the groove, the first dielectric layer having a plurality of fifth through-holes and a plurality of sixth through-holes, the fifth through-holes aligning with the third through-holes and exposing the second semiconductor layer, the sixth through-holes aligning with the fourth through-holes and exposing the first semiconductor layer;

[0049] forming a first current spreading layer on a portion of the first dielectric layer, wherein the first current spreading layer fills the fifth through-hole and is electrically connected to the second semiconductor layer;

[0050] forming a second dielectric layer on the first current spreading layer and the first dielectric layer, wherein the second dielectric layer further fills the sixth through-hole, and the second dielectric layer has a plurality of seventh through-holes, wherein the seventh through-holes are aligned with the sixth through-holes and expose the first semiconductor layer;

[0051] forming a second current spreading layer on a portion of the second dielectric layer, wherein the second current spreading layer fills the seventh through hole and is electrically connected to the first semiconductor layer;

[0052] forming a third dielectric layer on the second current spreading layer and the second dielectric layer; and,

[0053] A first electrode, a second electrode and a third electrode are formed on the third dielectric layer, the first electrode penetrates the third dielectric layer, the second dielectric layer and the first dielectric layer and is electrically connected to the metal reflective layer, the second electrode penetrates the third dielectric layer and the second dielectric layer and is electrically connected to the first current spreading layer, and the third electrode penetrates the third dielectric layer and is electrically connected to the second current spreading layer.

[0054] Optionally, a second etching protection layer is further formed on the first current spreading layer and the second current spreading layer.

[0055] Optionally, the material of the second etching protection layer includes Pt; and / or the thickness of the second etching protection layer is greater than 200 nm.

[0056] Optionally, a first adhesion layer is provided between the bottom surface of the first current spreading layer and / or the second current spreading layer and the dielectric layer; and / or a second adhesion layer is provided between the top surface of the first current spreading layer and / or the second current spreading layer and the dielectric layer.

[0057] Optionally, the material of the first adhesion layer and / or the second adhesion layer is at least one of Ti, Cr and Ni; the thickness of the first adhesion layer and / or the second adhesion layer is 5 nm to 50 nm.

[0058] Optionally, the materials of the first dielectric layer, the second dielectric layer and the third dielectric layer are SiO2, SiN x , at least one of AlN, BN and diamond; and / or, the thicknesses of the first dielectric layer, the second dielectric layer and the third dielectric layer are respectively 200nm~2μm.

[0059] Optionally, the insulating reflective layer is a single-layer reflective film or is formed by two layers of reflective films with different refractive indices being alternately distributed.

[0060] Optionally, the material of the reflective film is SiO2, Al2O3, HfO2, SiN x , AlN, BN or MgF2; and / or, the thickness of the reflective film is λ / 4n, wherein λ is the light emitting wavelength of the light emitting layer and n is the refractive index of the reflective film.

[0061] Optionally, when the flip-chip light emitting diode is in use, the first electrode is connected to a first potential, the second electrode is connected to a second potential, the third electrode is connected to a third potential, and both the first potential and the second potential are greater than the third potential.

[0062] Optionally, the difference between the first potential and the third potential is 3V to 10V.

[0063] Optionally, after forming the groove and before forming the insulating reflective layer, the method further includes:

[0064] Etching the second semiconductor layer, the light emitting layer and the second semiconductor layer to form a scribe line exposing the substrate; and,

[0065] After forming the first electrode, the second electrode and the third electrode, the substrate is cut along the scribe line to form a single flip-chip light emitting diode.

[0066] In the flip-chip light-emitting diode and the preparation method thereof provided by the present invention, the metal reflective layer and the insulating reflective layer of the ODR reflective layer are used to form a MIS (Metal-Insulator-Semiconductor) capacitor structure with the epitaxial layer. When the flip-chip light-emitting diode is in use, the second electrode can be connected to a relatively high potential and the third electrode can be connected to a relatively low potential, so that the light-emitting layer in the epitaxial layer emits light. At the same time, the first electrode is connected to a relatively high potential and the third electrode is connected to a relatively low potential, so that electrons are gathered from the first semiconductor layer of the epitaxial layer to the light-emitting layer, and holes are gathered from the second semiconductor layer of the epitaxial layer to the light-emitting layer, thereby improving the hole injection efficiency, increasing the radiation recombination efficiency in the light-emitting layer, and improving the photoelectric conversion efficiency without reducing the transmission efficiency of the radiation recombination luminescence, and the cost is low. In addition, since the ODR reflective layer can improve the light extraction efficiency, the ODR reflective layer is widely used in the current flip-chip light-emitting diodes. The present invention only slightly improves the existing flip-chip light-emitting diodes and will not significantly increase the complexity of the structure and the preparation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Figure 1 A flow chart of a method for preparing a flip-chip light-emitting diode provided in Embodiment 1 of the present invention;

[0068] Figure 2 to Figure 11 A schematic structural diagram corresponding to corresponding steps of the method for preparing a flip-chip light-emitting diode provided in the first embodiment of the present invention;

[0069] Figures 12 to 19 A schematic structural diagram corresponding to corresponding steps of the method for preparing a flip-chip light-emitting diode provided in the second embodiment of the present invention;

[0070] Wherein, the accompanying drawings are marked as follows:

[0071] 100-substrate; 200-epitaxial layer; 200a-groove; 201-buffer layer; 202-low defect density layer; 203-stress adjustment layer; 204-first semiconductor layer; 205-light-emitting layer; 206-second semiconductor layer; 214-second ohmic contact layer; 216-first ohmic contact layer; 301-insulating reflective layer; 302-metal reflective layer; 302a-third perforation; 302b-fourth perforation; 401-first dielectric Layer; 401a-fifth perforation; 401b-sixth perforation; 402-second dielectric layer; 402a-seventh perforation; 402b-eighth perforation; 402c-ninth perforation; 403-third dielectric layer; 403a-tenth perforation; 403b-eleventh perforation; 403c-twelfth perforation; 501-first current spreading layer; 502-second current spreading layer; 601-first electrode; 602-second electrode; 603-third electrode. DETAILED DESCRIPTION

[0072] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0073] Embodiment 1

[0074] Fig.11 The schematic diagram of the structure of the flip-chip light emitting diode provided in this embodiment. Fig.11 As shown, the flip-chip light emitting diode comprises a substrate 100, an epitaxial layer 200, an ODR reflective layer 300, a dielectric layer, a first electrode 601, a second electrode 602 and a third electrode 603. The ODR reflective layer 300 comprises an insulating reflective layer 301 and a metal reflective layer 302.

[0075] Next, this embodiment will be described using the flip-chip LED as a deep ultraviolet flip-chip LED (luminous wavelength is 200nm-320nm) as an example, but it should be understood that the flip-chip LED is not limited to a deep ultraviolet flip-chip LED, but can also be a flip-chip LED in other luminous bands such as ultraviolet and visible light (luminous wavelength is 320nm-600nm), which will not be explained one by one here.

[0076] Specifically, the substrate 100 is an epitaxial heterogeneous transparent substrate, and its material can be any one of Ga2O3, SiC, sapphire, ZnO and LiGaO2, and its thickness can be 300μm to 2mm, but it should not be limited thereto.

[0077] The surface of the substrate 100 can be prepared with a micro-nano pattern, thereby improving the luminous efficiency. The micro-nano pattern can be prepared directly on the surface of the substrate 100, or a film layer such as an AlN film can be deposited on the substrate 100 in advance, and the micro-nano pattern is prepared on the pre-deposited film layer. The characteristic size range of the prepared micro-nano pattern can be hundreds of nanometers to several microns, and the pattern array mode can be any one of parallel straight lines, curved lines, squares and hexagonal arrangements.

[0078] The epitaxial layer 200 is located on the substrate 100, and includes a first semiconductor layer 204, a light-emitting layer 205, and a second semiconductor layer 206 arranged in sequence from bottom to top. In this embodiment, the first semiconductor layer 204 is an N-type semiconductor layer, and the second semiconductor layer 206 is a P-type semiconductor layer. Among them, the first semiconductor layer 204 is an n-AlGaN layer, the second semiconductor layer 206 is a p-AlGaN layer, and the light-emitting layer 205 is a multi-quantum well layer (MQW), which can be formed by stacking AlGaN structures with a gradient Al component, and the corresponding light-emitting wavelength range is 200nm to 320nm.

[0079] Furthermore, in this embodiment, the epitaxial layer 200 further comprises a buffer layer 201, a low defect density layer 202 and a stress adjustment layer 203 which are sequentially arranged from bottom to top, and the buffer layer 201, the low defect density layer 202 and the stress adjustment layer 203 are stacked and located between the substrate 100 and the first semiconductor layer 204. The buffer layer 201 may be an AlN layer, the low defect density layer 202 may be a thicker non-intentionally doped AlN layer, and the stress adjustment layer 203 may be an AlGaN superlattice structure, specifically: an AlGaN superlattice structure with a gradual change in Al composition (gradually decreasing) is prepared from the low defect density layer 202 to the first semiconductor layer 204. x Ga 1-x N / A y Ga 1-y N superlattice structure, wherein 0<y<x<1, thereby continuing to reduce the stress difference between the substrate 100 and the first semiconductor layer 204 caused by the difference in lattice and thermal expansion coefficient.

[0080] It should be understood that other film layers may be formed in the epitaxial layer 200, for example, an EBL electron blocking layer may be formed between the light emitting layer 205 and the second semiconductor layer 206, which will not be explained one by one here. The thickness of the epitaxial layer 200 may be 5 μm to 10 μm, but it should not be limited thereto.

[0081] The epitaxial layer 200 has grooves 200a therein, and the grooves 200a penetrate through the second semiconductor layer 206 and the light emitting layer 205 and expose the first semiconductor layer 204. The grooves 200a are arranged in an array.

[0082] Please continue reading Fig.11 The second semiconductor layer 206 has a first ohmic contact layer 216, which is a patterned film layer. The first ohmic contact layer 216 makes ohmic contact with the second semiconductor layer 206, thereby achieving excellent electrical connection. Each of the grooves 200a has a second ohmic contact layer 214, which is a patterned film layer. The second ohmic contact layer 214 makes ohmic contact with the first semiconductor layer 204, thereby achieving excellent electrical connection.

[0083] In this embodiment, the material of the first ohmic contact layer 216 may be a metal material, such as Ag, NiAg, NiAu, NiAl or PdAu, etc., and the thickness may be 10 nm to 200 nm, but it should not be limited thereto.

[0084] In this embodiment, the material of the second ohmic contact layer 214 may be at least one of V, Hf, Ti, Cr, Al, Ni, Au and Pt, and the thickness may be 100 nm to 2 μm, but should not be limited thereto.

[0085] Further, the ODR reflective layer 300 is located on the second semiconductor layer 206, and includes an insulating reflective layer 301 and a metal reflective layer 302 stacked in sequence on the second semiconductor layer 206. The insulating reflective layer 301 covers the second semiconductor layer 206 and the first ohmic contact layer 216 and extends to cover the sidewall of the groove 200a; the metal reflective layer 302 only covers part of the insulating reflective layer 301, specifically, covers the area where the insulating reflective layer 301 avoids the first ohmic contact layer 216, and the metal reflective layer 302 does not enter the groove 200a. The metal reflective layer 302, the insulating reflective layer 301 and the epitaxial layer 200 can form a MIS capacitor structure.

[0086] In this embodiment, the insulating reflective layer 301 enters the groove 200a and covers the side wall of the groove 200a, but there is a gap between the insulating reflective layer 301 and the second ohmic contact layer 214 in the lateral direction, but it should not be limited to this. The insulating reflective layer 301 can also be in close contact with the side wall of the second ohmic contact layer 214; and, as an optional embodiment, the insulating reflective layer 301 can also only cover the second semiconductor layer 206 without entering the groove 200a, and the metal reflective layer 302 can also enter the groove 200a and cover the side wall of the groove 200a, but cannot contact the second ohmic contact layer 214. These optional embodiments do not affect the implementation of the present invention.

[0087] from Fig.11 It can be seen that the ODR reflective layer 300 can be regarded as having a plurality of first perforations and a plurality of second perforations, wherein each of the first perforations is aligned with the first ohmic contact layer 216, and the first perforations penetrate the metal reflective layer 302 and the insulating reflective layer 301 to expose the first ohmic contact layer 216; each of the second perforations is aligned with the second ohmic contact layer 214, and the second perforations penetrate the metal reflective layer 302 and the insulating reflective layer 301 and connect to the groove to expose the second ohmic contact layer 214.

[0088] In this embodiment, the insulating reflective layer 301 can be a single-layer reflective film or a DBR reflective structure formed by alternating two layers of reflective films with different refractive indices. The material of the reflective film can be SiO2, Al2O3, HfO2, SiN x , AlN, BN or MgF2; the thickness of the reflective film is λ / 4n, wherein λ is the light emitting wavelength of the light emitting layer 205, and n is the refractive index of the reflective film.

[0089] In this embodiment, the material of the metal reflective layer 302 may be at least one of Ag, Al, Mg and Rh, and the thickness may be 50-500 nm, but it should not be limited thereto.

[0090] As an optional embodiment, a third adhesion layer and an anti-oxidation layer ( Fig.11 The third adhesion layer is used to adhere the metal reflective layer 302 and the anti-oxidation layer, and the anti-oxidation layer can prevent the metal reflective layer 302 from being oxidized.

[0091] Furthermore, the material of the third adhesion layer may be at least one of Ti, Ni and Cr, and the thickness may be However, it should not be limited thereto; the material of the anti-oxidation layer may be Pt and / or TiW, and the thickness may be But it should not be limited to this.

[0092] Please continue reading Fig.11 The ODR reflective layer 300 is covered with a dielectric layer, and the dielectric layer covers the ODR reflective layer 300 and the first through-hole and the second through-hole whose side walls correspond to the metal reflective layer 302 .

[0093] In this embodiment, since the insulating reflective layer 301 covers the sidewalls of the groove 200a, the dielectric layer can cover the sidewalls of the second perforation and the portion of the insulating reflective layer 301 located in the groove 200a; however, it should be understood that if the insulating reflective layer 301 is only located on the second semiconductor layer 206 and does not enter the groove 200a, the dielectric layer needs to enter the groove 200a and cover the sidewalls of the groove 200a; or, if the metal reflective layer 302 also enters the groove 200a, the dielectric layer needs to enter the groove 200a and cover the metal reflective layer 302.

[0094] In this embodiment, the dielectric layer includes a first current spreading layer 501 and a second current spreading layer 502, and the first current spreading layer 501 and the second current spreading layer 502 are electrically isolated by the dielectric layer. The first current spreading layer 501 passes through a portion of the dielectric layer and fills the first through-hole, thereby being electrically connected to the first ohmic contact layer 216, and the second current spreading layer 502 passes through a portion of the dielectric layer and fills the second through-hole and the groove 200a, thereby being electrically connected to the second ohmic contact layer 214. The first electrode 601, the second electrode 602 and the third electrode 603 are all located on the dielectric layer. The first electrode 601 penetrates the dielectric layer and is electrically connected to the metal reflective layer 302; the second electrode 602 penetrates a portion of the dielectric layer and is electrically connected to the first current spreading layer 501, and the second electrode 602 is electrically connected to the second semiconductor layer 206 through the first current spreading layer 501 and the first ohmic contact layer 216; the third electrode 603 penetrates a portion of the dielectric layer and is electrically connected to the second current spreading layer 502, and the third electrode 603 is electrically connected to the first semiconductor layer 204 through the second current spreading layer 502 and the second ohmic contact layer 214. In this way, the first electrode 601 can be used as one electrode of the MIS capacitor structure, the second electrode 602 can be used as the P electrode of the flip-chip light-emitting diode, and the third electrode 603 can be used as the other electrode of the MIS capacitor structure and the N electrode of the flip-chip light-emitting diode at the same time. The third electrode 603 can be shared or separated into two separate electrodes.

[0095] In this embodiment, the material of the first current spreading layer 501 and the second current spreading layer 502 may be at least one of Ti, Cr, Ni, Al, Au and Pt, and the thickness may be 300nm-2um, but it should not be limited thereto.

[0096] As an optional embodiment, a second etching protection layer ( Fig.11 The second etching protection layer can prevent the first current spreading layer 501 and the second current spreading layer 502 from being damaged when etching the dielectric layer. The material of the second etching protection layer can be PtTi, PtCr, etc. The thickness of Pt can be greater than 200nm, and the thickness of Ti and Cr is 5nm to 50nm.

[0097] As an optional embodiment, a first adhesion layer ( Fig.11 The first adhesion layer can improve the adhesion effect between the bottom surface of the first current spreading layer 501 and / or the second current spreading layer 502 and the dielectric layer. The material of the first adhesion layer can be at least one of Ti, Cr and Ni, and the thickness is 5nm to 50nm.

[0098] As an optional embodiment, a second adhesion layer ( Fig.11 The second adhesion layer can improve the adhesion effect between the top surface of the first current spreading layer 501 and / or the second current spreading layer 502 and the dielectric layer. The material of the second adhesion layer can be at least one of Ti, Cr and Ni, and the thickness is 5nm to 50nm.

[0099] In this embodiment, the materials of the first electrode 601 , the second electrode 602 and the third electrode 603 may be Au and / or Sn, and the thickness may be 500 nm to 20 μm, but it should not be limited thereto.

[0100] Specifically, the dielectric layer includes a first dielectric layer 401 , a second dielectric layer 402 , and a third dielectric layer 403 which are sequentially stacked on the ODR reflective layer 300 from bottom to top.

[0101] Specifically, the first dielectric layer 401 is located on the ODR reflective layer 300, covers the metal reflective layer 302, the first through-hole and the sidewall of the second through-hole corresponding to the metal reflective layer 302, and also enters the groove 200a, covering the insulating reflective layer 301 in the groove 200a. The first current spreading layer 501 is located on the first dielectric layer 401, covers a portion of the first dielectric layer 401, and the first current spreading layer 501 passes through the first dielectric layer 401 and fills the first through-hole, and the bottom of the first current spreading layer 501 contacts the first ohmic contact layer 216 to achieve electrical connection.

[0102] The second dielectric layer 402 is located on the first dielectric layer 401, covering the first current spreading layer 501 and the remaining portion of the first dielectric layer 401. The second current spreading layer 502 is located on the second dielectric layer 402, covering a portion of the second dielectric layer 402, and the second current spreading layer 502 passes through the second dielectric layer 402 and fills the second through-hole and the groove 200a, and the bottom of the second current spreading layer 502 contacts the second ohmic contact layer 214 to achieve electrical connection.

[0103] The third dielectric layer 403 is located on the second dielectric layer 402, covering the second current spreading layer 502 and the remaining part of the second dielectric layer 402. The first electrode 601, the second electrode 602 and the third electrode 603 are all located on the third dielectric layer 403, and all cover a part of the third dielectric layer 403. The first electrode 601 sequentially passes through the third dielectric layer 403, the second dielectric layer 402 and the first dielectric layer 401, and the bottom of the first electrode 601 contacts the metal reflective layer 302 to achieve electrical connection; the second electrode 602 sequentially passes through the third dielectric layer 403 and the second dielectric layer 402, and the bottom of the second electrode 602 contacts the first current spreading layer 501 to achieve electrical connection; the third electrode 603 passes through the third dielectric layer 403, and the bottom of the third electrode 603 contacts the second current spreading layer 502 to achieve electrical connection.

[0104] from Fig.11 As can be seen from the figure, the first electrode 601, the second electrode 602 and the third electrode 603 are insulated from each other.

[0105] In this embodiment, the materials of the first dielectric layer 401, the second dielectric layer 402 and the third dielectric layer 403 can be SiO2, SiN xAt least one of AlN, BN and diamond may have a thickness of 200 nm to 2 μm, but should not be limited thereto. Optionally, the materials and thicknesses of the first dielectric layer 401, the second dielectric layer 402 and the third dielectric layer 403 may be the same or different.

[0106] In this embodiment, when the flip-chip light-emitting diode is in use, the second electrode 602 is connected to a second potential, and the third electrode 603 is connected to a third potential, and the second potential is greater than the third potential, thereby providing a forward working current for the flip-chip light-emitting diode, so that the light-emitting layer 205 emits light; at the same time, the first electrode 601 is connected to a first potential, and the first potential is greater than the third potential, thereby providing a forward working current for the MIS capacitor structure, so that electrons gather from the first semiconductor layer 204 to the light-emitting layer 205, and holes gather from the second semiconductor layer 206 to the light-emitting layer 205, which is equivalent to improving the hole injection efficiency and increasing the radiation recombination efficiency in the light-emitting layer 205. The photoelectric conversion efficiency of the flip-chip light-emitting diode is improved without reducing the transmission efficiency of the radiation recombination luminescence, and the cost is low, which is of great significance for realizing the industrialization of large-size flip-chip light-emitting diodes. If there is no MIS capacitor structure, only the holes in the second semiconductor layer 206 at the position of the second ohmic contact layer 216 and its vicinity are injected into the light-emitting layer 205, and the holes in the area far away from the second ohmic contact layer 216 are not effectively utilized. Furthermore, since the ODR reflective layer 300 can improve light extraction efficiency, the ODR reflective layer 300 is widely used in current flip-chip LEDs. The present invention only slightly improves the existing flip-chip LEDs and will not significantly increase the complexity of the structure and the manufacturing process.

[0107] Optionally, the difference between the first potential and the third potential may be 3V to 10V, but should not be limited thereto.

[0108] Figure 1 The flowchart of the method for preparing the flip-chip light-emitting diode provided in this embodiment is as follows: Figure 1 As shown, the method for preparing the flip-chip light-emitting diode comprises:

[0109] Step S100: providing a substrate;

[0110] Step S200: forming an epitaxial layer, wherein the epitaxial layer is located on the substrate, and the epitaxial layer includes a first semiconductor layer, a light emitting layer, and a second semiconductor layer arranged in sequence from bottom to top;

[0111] Step S300: forming an ODR reflective layer, wherein the ODR reflective layer comprises an insulating reflective layer and a metal reflective layer sequentially stacked on the epitaxial layer, wherein the metal reflective layer, the insulating reflective layer and the epitaxial layer constitute a MIS capacitor structure; and

[0112] Step S400: forming a first electrode, a second electrode and a third electrode which are insulated from each other, wherein the first electrode, the second electrode and the third electrode are electrically connected to the metal reflective layer, the second semiconductor layer and the first semiconductor layer respectively.

[0113] Figure 2 to Figure 11 The following is a schematic diagram of the structure corresponding to the corresponding steps of the method for preparing a flip-chip light-emitting diode provided in this embodiment. Figure 2 to Figure 11 The method for preparing the flip-chip light-emitting diode provided in this embodiment is described in detail.

[0114] See also Figure 2 , perform step S100 to provide the substrate 100. At this time, the substrate 100 may be a 1-inch to 8-inch wafer, and may have a thickness of 300 μm to 2 mm, but is not limited thereto.

[0115] Next, step S200 is performed to form the epitaxial layer 200 on the substrate 100. Specifically, the buffer layer 201, the low defect density layer 202, the stress adjustment layer 203, the first semiconductor layer 204, the light emitting layer 205 and the second semiconductor layer 206 are sequentially formed on the substrate 100. Specifically, the buffer layer 201 can be prepared by a low temperature growth process or a sputtering process, and the low defect density layer 202, the stress adjustment layer 203, the first semiconductor layer 204, the light emitting layer 205 and the second semiconductor layer 206 can be prepared by a metal chemical vapor deposition process, a laser-assisted molecular beam epitaxy process, a laser sputtering process or a hydride vapor phase epitaxy process.

[0116] See also Figure 3 , the second semiconductor layer 206 and the light emitting layer 205 are etched downward until the first semiconductor layer 204 is exposed, so as to form a plurality of the grooves 200a. Specifically, the step of forming the grooves 200a includes: processing the grooves 200a in the second semiconductor layer 206 and the light emitting layer 205 by photolithography and dry etching processes, and the depth of the grooves 200a needs to exceed the light emitting layer 205 and expose the first semiconductor layer 204.

[0117] As an optional embodiment, after the groove 200a is formed, the entire epitaxial layer 200 may be etched until the substrate 100 is exposed. After the etching is completed, a scribe groove ( Figure 3The scribing grooves can be used to define the area of ​​a single flip-chip light-emitting diode, which is convenient for subsequent scribing.

[0118] See also Figure 4 , perform step S300 to form a second ohmic contact layer 214 in each of the grooves 200a, and form a first ohmic contact layer 216 on the second semiconductor layer 206. The second ohmic contact layer 214 and the first ohmic contact layer 216 may be formed by an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process, or a chemical vapor deposition process to form an ohmic contact material in a corresponding area.

[0119] Optionally, after forming the second ohmic contact layer 214, the second ohmic contact layer 214 may be annealed to enhance the ohmic contact effect between the second ohmic contact layer 214 and the first semiconductor layer 204; after forming the first ohmic contact layer 216, the first ohmic contact layer 216 may also be annealed to enhance the ohmic contact effect between the first ohmic contact layer 216 and the second semiconductor layer 206. The annealing of the second ohmic contact layer 214 and / or the first ohmic contact layer 216 may be performed in an atmosphere of an inert gas such as N2, the annealing temperature of the annealing of the first ohmic contact layer 216 may be 450° C. to 600° C., and the annealing time may be 2 min to 20 min; the annealing temperature of the annealing of the second ohmic contact layer 214 may be 700° C. to 1100° C., and the annealing time may be 30 s to 2 min.

[0120] See also Figure 5 , an insulating reflective layer 301 is formed on the second semiconductor layer 206, and the insulating reflective layer 301 covers the second semiconductor layer 206, the first ohmic contact layer 216 and the sidewall of the groove 200a. The insulating reflective layer 301 can be formed by: using an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process or a chemical vapor deposition process to fully deposit an insulating reflective material ( Figure 5 (not shown), and then a portion of the insulating reflective material on the second ohmic contact layer 214 and in the groove 200a is removed by an etching process, and the remaining insulating reflective material constitutes the insulating reflective layer 301.

[0121] Please continue reading Figure 5, a metal reflective layer 302 is formed on the insulating reflective layer 301, and the metal reflective layer 302 has a plurality of third through-holes 302a and a plurality of fourth through-holes 302b. The third through-holes 302a penetrate the metal reflective layer 302 and expose the insulating reflective layer 301, and each of the third through-holes 302a is aligned with the first ohmic contact layer 216; each of the fourth through-holes 302b penetrates the metal reflective layer 302 and is connected to one of the grooves 200a, thereby exposing the second ohmic contact layer 214. The formation process of the metal reflective layer 302 can be: forming a metal reflective material ( Figure 5 (not shown), then a portion of the metal reflective material on the insulating reflective layer 301 and the metal reflective material in the groove 200a are removed by photolithography and etching processes, and the remaining metal reflective material constitutes the metal reflective layer 302.

[0122] The insulating reflective layer 301 and the metal reflective layer 302 constitute the ODR reflective layer 300 .

[0123] See also Figure 6 , perform step S400 to form a first dielectric layer 401 on the metal reflective layer 302, the first dielectric layer 401 also fills the third through-hole 302a, the fourth through-hole 302b and the groove 200a, and the first dielectric layer 401 has a plurality of fifth through-holes 401a and a sixth through-hole 401b, the fifth through-hole 401a is aligned with the third through-hole 302a and exposes the first ohmic contact layer 216, and the sixth through-hole 401b is aligned with the fourth through-hole 302b and exposes the second ohmic contact layer 214. The formation process of the first dielectric layer 401 can be: using an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process or a chemical vapor deposition process to fully deposit the first dielectric material ( Figure 6 (not shown), then the third through-hole 302a, the fourth through-hole 302b and part of the first dielectric material in the groove 200a are removed by photolithography and etching processes, and the remaining first dielectric material constitutes the first dielectric layer 401.

[0124] See also Figure 7, forming a first current spreading layer 501 on the first dielectric layer 401, wherein the first current spreading layer 501 covers a portion of the first dielectric layer 401 and fills the fifth through-hole 401a. The first current spreading layer 501 may be formed by: using an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process or a chemical vapor deposition process to deposit a first current spreading material ( Figure 7 (not shown), then a portion of the first current spreading material on the first dielectric layer 401 and the first current spreading material in the sixth through-hole 401b are removed by photolithography and etching processes, and the remaining first current spreading material constitutes the first current spreading layer 501.

[0125] See also Figure 8 , forming a second dielectric layer 402 on the first current spreading layer 501 and the first dielectric layer 401, the second dielectric layer 402 also fills the sixth through-hole 401b, and the second dielectric layer 402 has a plurality of seventh through-holes 402a, a plurality of eighth through-holes 402b and a plurality of ninth through-holes 402c. The seventh through-hole 402a is aligned with the sixth through-hole 401b and exposes the second ohmic contact layer 214, the eighth through-hole 402b exposes the first current spreading layer 501, and the ninth through-hole 402c exposes the first dielectric layer 401. The formation process of the second dielectric layer 402 can be: using an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process or a chemical vapor deposition process to fully deposit a second dielectric material ( Figure 8 (not shown), and then use photolithography and etching processes to remove part of the second dielectric material on the first dielectric layer 401, on the first current spreading layer 501 and in the sixth through-hole 401b, and the remaining second dielectric material constitutes the second dielectric layer 402.

[0126] Forming the eighth through-hole 402b and the ninth through-hole 402c in this step can reduce the difficulty of subsequent etching, but forming the eighth through-hole 402b and the ninth through-hole 402c in this step can also be omitted.

[0127] See also Fig. 9, forming a second current spreading layer 502 on the second dielectric layer 402, wherein the second current spreading layer 502 covers a portion of the second dielectric layer 402 and fills the seventh through-hole 402a. The second current spreading layer 502 may be formed by: using an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process or a chemical vapor deposition process to deposit a second current spreading material ( Fig. 9 (not shown), then use photolithography and etching processes to remove part of the second current spreading material on the second dielectric layer 402 and the second current spreading material in the eighth through-hole 402b and the ninth through-hole 402c, and the remaining second current spreading material constitutes the second current spreading layer 502.

[0128] See also Fig.10 , forming a third dielectric layer 403 on the second current spreading layer 502 and the second dielectric layer 402, the third dielectric layer 403 also fills the eighth through-hole 402b and the ninth through-hole 402c. The third dielectric layer 403 has a plurality of tenth through-holes 403a, a plurality of eleventh through-holes 403b and a plurality of twelfth through-holes 403c. The tenth through-hole 403a exposes the second current spreading layer 502, the eleventh through-hole 403b is aligned with the eighth through-hole 402b and exposes the first current spreading layer 501, and the twelfth through-hole 403c is aligned with the ninth through-hole 402c and extends downward to expose the metal reflective layer 302. The formation process of the third dielectric layer 403 can be: using an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process or a chemical vapor deposition process to fully deposit a third dielectric material ( Fig.10 (not shown), then use a photolithography and etching process to remove the third dielectric material in the ninth through-hole 402c and etch downward until the metal reflective layer 302 is exposed, and remove part of the third dielectric material on the second current spreading layer 502 and the first current spreading layer 501, and the remaining third dielectric material constitutes the third dielectric layer 403.

[0129] See also Fig.11, a first electrode 601, a second electrode 602 and a third electrode 603 are formed on the third dielectric layer 403 to be insulated from each other. The first electrode 601 fills the twelfth through-hole 403c to be electrically connected to the metal reflective layer 302; the second electrode 602 fills the eleventh through-hole 403b and is electrically connected to the second semiconductor layer 206 through the first current spreading layer 501 and the first ohmic contact layer 216; the third electrode 603 fills the tenth through-hole 403a and is electrically connected to the first semiconductor layer 204 through the second current spreading layer 502 and the second ohmic contact layer 214. The steps of forming the first electrode 601, the second electrode 602 and the third electrode 603 include: forming a photoresist mask to cover the area where the electrode does not need to be formed, then using an electron beam evaporation process to form a conductive material, and then using a stripping process to remove the photoresist mask and the conductive material on the photoresist mask, and the conductive material in the area not covered by the photoresist mask is retained, thereby forming the first electrode 601, the second electrode 602 and the third electrode 603.

[0130] Furthermore, the substrate 100 is cut along the scribe line by using a grinding wheel or a laser (water-guided laser, laser surface cutting), so as to separate individual flip-chip light-emitting diodes.

[0131] Embodiment 2

[0132] Fig.19 The schematic diagram of the structure of the flip-chip light emitting diode provided in this embodiment. Fig.19 As shown, the difference from the first embodiment is that in this embodiment, the flip-chip light emitting diode is an ultraviolet flip-chip light emitting diode, and the material of the first ohmic contact layer 216 is a transparent conductive material.

[0133] Specifically, in this embodiment, the first semiconductor layer 204 is an n-GaN layer, the second semiconductor layer 206 is a p-GaN layer, and the light-emitting layer 205 is a multi-quantum well layer (MQW), which can be formed by stacking an InGaN structure with a gradient In component, and the corresponding light-emitting wavelength range is 320nm to 400nm. The buffer layer 201 can be a GaN layer, the low defect density layer 202 can be a thicker non-intentionally doped GaN layer, and the stress adjustment layer 203 can be an AlGaN superlattice structure, specifically: AlGaN with a gradient Al component (gradually decreasing) is prepared from the low defect density layer 202 to the first semiconductor layer 204. x Ga 1-x N superlattice structure, wherein 0<x<0.2, thereby reducing the stress difference between the substrate 100 and the first semiconductor layer 204 caused by the difference in lattice and thermal expansion coefficient.

[0134] It should be understood that other film layers may be formed in the epitaxial layer 200, for example, an EBL electron blocking layer may be formed between the light emitting layer 205 and the second semiconductor layer 206, which will not be explained one by one here. The thickness of the epitaxial layer 200 may be 5 μm to 10 μm, but it should not be limited thereto.

[0135] Furthermore, since the first semiconductor layer 204 is an n-GaN layer with a high electron concentration inside the film layer, the second ohmic contact layer is omitted in this embodiment, that is, the second current spreading layer 502 directly contacts the first semiconductor layer 204, which can also achieve better electrical connection.

[0136] Of course, as an optional embodiment, the second ohmic contact layer may also be prepared on the first semiconductor layer 204, and the second current spreading layer 502 is still electrically connected to the first semiconductor layer 204 through the second ohmic contact layer, which does not affect the implementation of the present invention.

[0137] Furthermore, in this embodiment, the material of the first ohmic contact layer 216 may be ITO, IFO, IZO, AZO, GZO or GTO, and the thickness may be 10 nm to 200 nm.

[0138] Furthermore, the first ohmic contact layer 216 is also covered with a first etching protection layer ( Fig.19 The first etching protection layer can protect the first ohmic contact layer 216 from being damaged when etching the dielectric layer (usually F-based gas is used for etching), thereby ensuring the electrical connection between the first current spreading layer 501 and the first ohmic contact layer 216. The material of the first etching protection layer can be at least one of Cr, Al, Pt and Ti.

[0139] Figures 12 to 19 The schematic diagram of the structure corresponding to the corresponding steps of the method for preparing the flip-chip light-emitting diode provided in this embodiment. Next, Figures 12 to 19 The method for preparing the flip-chip light-emitting diode provided in this embodiment is described in detail.

[0140] See also Fig.12 On the basis of forming the scribe grooves in step S100 and step S200 in the first embodiment, a first ohmic contact layer 216 is formed only on the second semiconductor layer 206. The first ohmic contact layer 216 may be formed by an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process or a chemical vapor deposition process to form an ohmic contact material in a corresponding area.

[0141] Optionally, after forming the first ohmic contact layer 216, the first ohmic contact layer 216 may be annealed to enhance the ohmic contact effect between the first ohmic contact layer 216 and the second semiconductor layer 206. The annealing of the first ohmic contact layer 216 may be performed in an atmosphere of an inert gas such as N2, the annealing temperature may be 450° C. to 600° C., and the annealing time may be 2 min to 20 min.

[0142] See also Fig.13 , an insulating reflective layer 301 is formed on the second semiconductor layer 206, and the insulating reflective layer 301 covers the second semiconductor layer 206, the first ohmic contact layer 216 and the inner wall of the groove 200a. The insulating reflective layer 301 can be formed by: using an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process or a chemical vapor deposition process to fully deposit an insulating reflective material ( Fig.13 (not shown in the figure), the insulating reflective material constitutes the insulating reflective layer 301.

[0143] Please continue reading Fig.13 , a metal reflective layer 302 is formed on the insulating reflective layer 301, and the metal reflective layer has a plurality of third through-holes 302a and a plurality of fourth through-holes 302b. The third through-holes 302a penetrate the metal reflective layer 302 and expose the insulating reflective layer 301, and each of the third through-holes 302a is aligned with the first ohmic contact layer 216; each of the fourth through-holes 302b is connected to one of the grooves 200a, thereby exposing the insulating reflective layer 301 in the groove 200a. The formation process of the metal reflective layer 302 can be: forming a metal reflective material ( Fig.13 (not shown), then a portion of the metal reflective material on the insulating reflective layer 301 and the metal reflective material in the groove 200a are removed by photolithography and etching processes, and the remaining metal reflective material constitutes the metal reflective layer 302.

[0144] The insulating reflective layer 301 and the metal reflective layer 302 constitute the ODR reflective layer 300 .

[0145] See also Fig.14, perform step S400 to form a first dielectric layer 401 on the metal reflective layer 302, the first dielectric layer 401 also fills the third through-hole 302a, the fourth through-hole 302b and the groove 200a, and the first dielectric layer 401 has a plurality of fifth through-holes 401a and a sixth through-hole 401b, the fifth through-hole 401a is aligned with the third through-hole 302a and exposes the first ohmic contact layer 216, and the sixth through-hole 401b is aligned with the fourth through-hole 302b and directly exposes the first semiconductor layer 204. The formation process of the first dielectric layer 401 can be: using an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process or a chemical vapor deposition process to fully deposit the first dielectric material ( Fig.14 ), and then use photolithography and etching processes to remove the third through-hole 302a, the fourth through-hole 302b and part of the first dielectric material in the groove 200a, and also etch the insulating reflective layer 301 downward along the groove 200 until the first semiconductor layer 204 is exposed. After etching, the remaining first dielectric material constitutes the first dielectric layer 401.

[0146] See also Fig.15 , forming a first current spreading layer 501 on the first dielectric layer 401, wherein the first current spreading layer 501 covers a portion of the first dielectric layer 401 and fills the fifth through-hole 401a. The first current spreading layer 501 may be formed by: using an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process or a chemical vapor deposition process to deposit a first current spreading material ( Fig.15 (not shown), then a portion of the first current spreading material on the first dielectric layer 401 and the first current spreading material in the sixth through-hole 401b are removed by photolithography and etching processes, and the remaining first current spreading material constitutes the first current spreading layer 501.

[0147] See also Fig.16, forming a second dielectric layer 402 on the first current spreading layer 501 and the first dielectric layer 401, the second dielectric layer 402 also fills the sixth through-hole 401b, and the second dielectric layer 402 has a plurality of seventh through-holes 402a, a plurality of eighth through-holes 402b and a plurality of ninth through-holes 402c. The seventh through-hole 402a is aligned with the sixth through-hole 401b and exposes the first semiconductor layer 204, the eighth through-hole 402b exposes the first current spreading layer 501, and the ninth through-hole 402c exposes the first dielectric layer 401. The formation process of the second dielectric layer 402 can be: using an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process or a chemical vapor deposition process to fully deposit a second dielectric material ( Fig.16 (not shown), and then use photolithography and etching processes to remove part of the second dielectric material on the first dielectric layer 401, on the first current spreading layer 501 and in the sixth through-hole 401b, and the remaining second dielectric material constitutes the second dielectric layer 402.

[0148] Forming the eighth through-hole 402b and the ninth through-hole 402c in this step can reduce the difficulty of subsequent etching, but forming the eighth through-hole 402b and the ninth through-hole 402c in this step can also be omitted.

[0149] See also Fig.17 , forming a second current spreading layer 502 on the second dielectric layer 402, wherein the second current spreading layer 502 covers a portion of the second dielectric layer 402 and fills the seventh through-hole 402a. The second current spreading layer 502 may be formed by: using an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process or a chemical vapor deposition process to deposit a second current spreading material ( Fig.17 (not shown), then use photolithography and etching processes to remove part of the second current spreading material on the second dielectric layer 402 and the second current spreading material in the eighth through-hole 402b and the ninth through-hole 402c, and the remaining second current spreading material constitutes the second current spreading layer 502.

[0150] See also Fig.18, forming a third dielectric layer 403 on the second current spreading layer 502 and the second dielectric layer 402, the third dielectric layer 403 also fills the eighth through-hole 402b and the ninth through-hole 402c. The third dielectric layer 403 has a plurality of tenth through-holes 403a, a plurality of eleventh through-holes 403b and a plurality of twelfth through-holes 403c. The tenth through-hole 403a exposes the second current spreading layer 502, the eleventh through-hole 403b is aligned with the eighth through-hole 402b and exposes the first current spreading layer 501, and the twelfth through-hole 403c is aligned with the ninth through-hole 402c and extends downward to expose the metal reflective layer 302. The formation process of the third dielectric layer 403 can be: using an electron beam evaporation process, a sputtering process, an atomic layer deposition process, a plasma assisted process, an ion beam assisted deposition process or a chemical vapor deposition process to fully deposit a third dielectric material ( Fig.18 (not shown), then use a photolithography and etching process to remove the third dielectric material in the ninth through-hole 402c and etch downward until the metal reflective layer 302 is exposed, and remove part of the third dielectric material on the second current spreading layer 502 and the first current spreading layer 501, and the remaining third dielectric material constitutes the third dielectric layer 403.

[0151] See also Fig.19 , and simultaneously forming a first electrode 601, a second electrode 602, and a third electrode 603 which are insulated from each other on the third dielectric layer 403. The first electrode 601 fills the twelfth through-hole 403c to be electrically connected to the metal reflective layer 302; the second electrode 602 fills the eleventh through-hole 403b, and is electrically connected to the second semiconductor layer 206 through the first current spreading layer 501 and the first ohmic contact layer 216; the third electrode 603 fills the tenth through-hole 403a, and is electrically connected to the first semiconductor layer 204 through the second current spreading layer 502. The steps of forming the first electrode 601, the second electrode 602, and the third electrode 603 include: forming a photoresist mask to cover the area where the electrode is not required to be formed, then forming a conductive material by an electron beam evaporation process, and then removing the photoresist mask and the conductive material on the photoresist mask by a stripping process, and the conductive material in the area not covered by the photoresist mask is retained, thereby forming the first electrode 601, the second electrode 602, and the third electrode 603.

[0152] Furthermore, the substrate 100 is cut along the scribe line by using a grinding wheel or a laser (water-guided laser, laser surface cutting), so as to separate individual flip-chip light-emitting diodes.

[0153] In summary, in the flip-chip light-emitting diode and the preparation method thereof provided in the embodiment of the present invention, the metal reflective layer and the insulating reflective layer of the ODR reflective layer are used to form a MIS (Metal-Insulator-Semiconductor) capacitor structure with the epitaxial layer. When the flip-chip light-emitting diode is in use, the second electrode can be connected to a relatively high potential and the third electrode can be connected to a relatively low potential, so that the light-emitting layer in the epitaxial layer emits light. At the same time, the first electrode is connected to a relatively high potential and the third electrode is connected to a relatively low potential, so that electrons gather from the first semiconductor layer of the epitaxial layer to the light-emitting layer, and holes gather from the second semiconductor layer of the epitaxial layer to the light-emitting layer, thereby improving the hole injection efficiency, increasing the radiation recombination efficiency in the light-emitting layer, and improving the photoelectric conversion efficiency without reducing the transmission efficiency of the radiation recombination luminescence, and the cost is low. In addition, since the ODR reflective layer can improve the light extraction efficiency, the ODR reflective layer is widely used in the current flip-chip light-emitting diodes. The present invention only slightly improves the existing flip-chip light-emitting diodes and will not significantly increase the complexity of the structure and the preparation process.

[0154] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0155] It should also be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0156] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0157] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates otherwise. In addition, the implementation of the method and / or device in the embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims

1. A flip-chip light emitting diode, characterized in that: include: substrate; The epitaxial layer is located on the substrate and includes a first semiconductor layer, a light-emitting layer and a second semiconductor layer arranged in sequence from bottom to top; The ODR reflective layer comprises an insulating reflective layer and a metal reflective layer sequentially stacked on the epitaxial layer, wherein the metal reflective layer, the insulating reflective layer and the epitaxial layer constitute a MIS capacitor structure; and The first electrode, the second electrode and the third electrode which are insulated from each other are electrically connected to the metal reflective layer, the second semiconductor layer and the first semiconductor layer respectively.

2. The flip-chip light emitting diode according to claim 1, characterized in that: Also includes: A plurality of grooves, penetrating the second semiconductor layer and the light emitting layer and exposing the first semiconductor layer; a plurality of first through holes, penetrating the ODR reflective layer and exposing the second semiconductor layer; a plurality of second through holes, penetrating the ODR reflective layer and communicating with the corresponding grooves; and, The dielectric layer is located on the ODR reflective layer and at least covers the sidewalls of the first through-hole and the second through-hole corresponding to the metal reflective layer, and is used for electrically isolating the first electrode, the second electrode and the third electrode.

3. The flip-chip light emitting diode according to claim 2, characterized in that: The first electrode is located on the dielectric layer and passes through the dielectric layer to be electrically connected to the metal reflective layer; the dielectric layer has a first current spreading layer and a second current spreading layer insulated from each other, the second electrode is located on the dielectric layer and passes through a portion of the thickness of the dielectric layer to be electrically connected to the first current spreading layer, the first current spreading layer passes through the remaining thickness of the dielectric layer and fills the first through-hole and then is electrically connected to the second semiconductor layer; the third electrode is located on the dielectric layer and passes through a portion of the thickness of the dielectric layer to be electrically connected to the second current spreading layer, the second current spreading layer passes through the remaining thickness of the dielectric layer and fills the second through-hole and the groove and then is electrically connected to the first semiconductor layer.

4. The flip-chip light emitting diode according to claim 3, characterized in that: The dielectric layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked sequentially on the metal reflective layer. The first current spreading layer is located between the first dielectric layer and the second dielectric layer, penetrates the first dielectric layer, fills the first through-hole, and is electrically connected to the second semiconductor layer. The second current spreading layer is located between the second dielectric layer and the third dielectric layer, penetrates the second dielectric layer and the first dielectric layer, fills the second through-hole and the groove, and is electrically connected to the first semiconductor layer.

5. The flip-chip light emitting diode according to claim 3, characterized in that: Also includes: The first ohmic contact layer is located on the second semiconductor layer and at the bottom of each of the first through-holes. After the first current spreading layer fills the first through-holes, it is electrically connected to the second semiconductor layer through the first ohmic contact layer.

6. The flip-chip light emitting diode according to claim 5, characterized in that: The material of the first ohmic contact layer is a metal material; and / or the thickness of the first ohmic contact layer is 10 nm to 200 nm.

7. The flip-chip light emitting diode according to claim 5, characterized in that: The material of the first ohmic contact layer is a transparent conductive material, and the first ohmic contact layer is further covered with a first etching protection layer; and / or the thickness of the first ohmic contact layer is 10 nm to 200 nm.

8. The flip-chip light emitting diode according to claim 5, characterized in that: Also includes: The second ohmic contact layer is located on the first semiconductor layer and in each of the grooves. After the second current spreading layer fills the second through-hole and the grooves, it is electrically connected to the first semiconductor layer through the second ohmic contact layer.

9. The flip-chip light emitting diode according to claim 3, characterized in that: A second etching protection layer is also formed on the first current spreading layer and the second current spreading layer.

10. The flip-chip light emitting diode according to claim 9, characterized in that: The material of the second etching protection layer includes Pt; and / or the thickness of the second etching protection layer is greater than 200 nm.

11. The flip-chip light emitting diode according to claim 3, characterized in that: A first adhesion layer is provided between the bottom surface of the first current spreading layer and / or the second current spreading layer and the dielectric layer; and / or a second adhesion layer is provided between the top surface of the first current spreading layer and / or the second current spreading layer and the dielectric layer.

12. The flip-chip light emitting diode according to claim 11, characterized in that: The material of the first adhesion layer and / or the second adhesion layer is at least one of Ti, Cr and Ni; the thickness of the first adhesion layer and / or the second adhesion layer is 5nm-50nm.

13. The flip-chip light emitting diode according to claim 4, characterized in that: The materials of the first dielectric layer, the second dielectric layer and the third dielectric layer are SiO2, SiN x , at least one of AlN, BN and diamond; and / or, the thicknesses of the first dielectric layer, the second dielectric layer and the third dielectric layer are respectively 200nm~2μm.

14. The flip-chip light emitting diode according to claim 1, wherein: The insulating reflective layer is a single-layer reflective film or is formed by two layers of reflective films with different refractive indices being alternately distributed.

15. The flip-chip light emitting diode according to claim 14, characterized in that: The material of the reflective film is SiO2, Al2O3, HfO2, SiN x , AlN, BN or MgF2; and / or, the thickness of the reflective film is λ / 4n, wherein λ is the light emitting wavelength of the light emitting layer and n is the refractive index of the reflective film.

16. The flip-chip light emitting diode according to any one of claims 1 to 15, characterized in that: When the flip-chip light emitting diode is in use, the first electrode is connected to a first potential, the second electrode is connected to a second potential, the third electrode is connected to a third potential, and both the first potential and the second potential are greater than the third potential.

17. The flip-chip light emitting diode according to claim 16, wherein: The difference between the first potential and the third potential is 3V to 10V.

18. A method for preparing a flip-chip light-emitting diode, characterized in that: include: providing a substrate; forming an epitaxial layer, wherein the epitaxial layer is located on the substrate, and the epitaxial layer includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer arranged in sequence from bottom to top; forming an ODR reflective layer, wherein the ODR reflective layer comprises an insulating reflective layer and a metal reflective layer sequentially stacked on the epitaxial layer, wherein the metal reflective layer, the insulating reflective layer and the epitaxial layer constitute a MIS capacitor structure; and, A first electrode, a second electrode and a third electrode are formed which are insulated from each other. The first electrode, the second electrode and the third electrode are electrically connected to the metal reflective layer, the second semiconductor layer and the first semiconductor layer respectively.

19. The method for preparing a flip-chip light emitting diode according to claim 18, characterized in that: The steps of forming the ODR reflective layer include: Etching the second semiconductor layer and the light emitting layer to form a plurality of grooves exposing the first semiconductor layer; forming the insulating reflective layer on the second semiconductor layer; and, The metal reflection layer is formed on a portion of the insulating reflection layer. The metal reflection layer has a plurality of third through holes and a plurality of fourth through holes. The third through holes expose the insulating reflection layer, and the fourth through holes are connected to the groove.

20. The method for preparing a flip-chip light emitting diode according to claim 19, characterized in that: After forming the groove and before forming the insulating reflective layer, the method further includes: A first ohmic contact layer is formed on a portion of the second semiconductor layer, and each of the third through holes is aligned with the first ohmic contact layer.

21. The method for preparing a flip-chip light emitting diode according to claim 20, characterized in that: The material of the first ohmic contact layer is a metal material; and / or the thickness of the first ohmic contact layer is 10 nm to 200 nm.

22. The method for preparing a flip-chip light emitting diode according to claim 20, characterized in that: After the first ohmic contact layer is formed, a first etching protection layer is further formed on the first ohmic contact layer.

23. The method for preparing a flip-chip light emitting diode according to claim 22, characterized in that: The material of the first ohmic contact layer is a transparent conductive material; and / or the thickness of the first ohmic contact layer is 10 nm to 200 nm.

24. The method for preparing a flip-chip light emitting diode according to claim 20, characterized in that: When forming the first ohmic contact layer, a second ohmic contact layer is also formed on the first semiconductor layer in each of the grooves, and each of the fourth through holes exposes the second ohmic contact layer.

25. The method for preparing a flip-chip light-emitting diode according to any one of claims 19 to 24, characterized in that: The steps of forming the first electrode, the second electrode and the third electrode which are insulated from each other include: Forming a first dielectric layer on the metal reflective layer, the first dielectric layer also filling the third through-hole, the fourth through-hole and the groove, the first dielectric layer having a plurality of fifth through-holes and a plurality of sixth through-holes, the fifth through-holes being aligned with and connected to the third through-holes, and the sixth through-holes being aligned with and connected to the fourth through-holes; forming a first current spreading layer on a portion of the first dielectric layer, wherein the first current spreading layer fills the fifth through-hole and is electrically connected to the second semiconductor layer; forming a second dielectric layer on the first current spreading layer and the first dielectric layer, wherein the second dielectric layer also fills the sixth through-hole, and the second dielectric layer has a plurality of seventh through-holes, wherein the seventh through-holes are aligned with and connected to the sixth through-holes; forming a second current spreading layer on a portion of the second dielectric layer, wherein the second current spreading layer fills the seventh through hole and is electrically connected to the first semiconductor layer; forming a third dielectric layer on the second current spreading layer and the second dielectric layer; and, A first electrode, a second electrode and a third electrode are formed on the third dielectric layer, the first electrode penetrates the third dielectric layer, the second dielectric layer and the first dielectric layer and is electrically connected to the metal reflective layer, the second electrode penetrates the third dielectric layer and the second dielectric layer and is electrically connected to the first current spreading layer, and the third electrode penetrates the third dielectric layer and is electrically connected to the second current spreading layer.

26. The method for preparing a flip-chip light emitting diode according to claim 25, characterized in that: A second etching protection layer is also formed on the first current spreading layer and the second current spreading layer.

27. The method for preparing a flip-chip light emitting diode according to claim 26, characterized in that: The material of the second etching protection layer includes Pt; and / or the thickness of the second etching protection layer is greater than 200 nm.

28. The method for preparing a flip-chip light emitting diode according to claim 25, characterized in that: A first adhesion layer is provided between the bottom surface of the first current spreading layer and / or the second current spreading layer and the dielectric layer; and / or a second adhesion layer is provided between the top surface of the first current spreading layer and / or the second current spreading layer and the dielectric layer.

29. The method for preparing a flip-chip light emitting diode according to claim 28, characterized in that: The material of the first adhesion layer and / or the second adhesion layer is at least one of Ti, Cr and Ni; the thickness of the first adhesion layer and / or the second adhesion layer is 5nm-50nm.

30. The method for preparing a flip-chip light emitting diode according to claim 25, characterized in that: The materials of the first dielectric layer, the second dielectric layer and the third dielectric layer are SiO2, SiN x , at least one of AlN, BN and diamond; and / or, the thicknesses of the first dielectric layer, the second dielectric layer and the third dielectric layer are respectively 200nm~2μm.

31. The method for preparing a flip-chip light emitting diode according to claim 18, characterized in that: The insulating reflective layer is a single-layer reflective film or is formed by two layers of reflective films with different refractive indices being alternately distributed.

32. The method for preparing a flip-chip light emitting diode according to claim 31, characterized in that: The material of the reflective film is SiO2, Al2O3, HfO2, SiN x , AlN, BN or MgF2; and / or, the thickness of the reflective film is λ / 4n, wherein λ is the light emitting wavelength of the light emitting layer and n is the refractive index of the reflective film.

33. The method for preparing a flip-chip light emitting diode according to claim 18, characterized in that: When the flip-chip light emitting diode is in use, the first electrode is connected to a first potential, the second electrode is connected to a second potential, the third electrode is connected to a third potential, and both the first potential and the second potential are greater than the third potential.

34. The method for preparing a flip-chip light emitting diode according to claim 33, characterized in that: The difference between the first potential and the third potential is 3V to 10V.

35. The method for preparing a flip-chip light-emitting diode according to any one of claims 19 to 24, characterized in that: After forming the groove and before forming the insulating reflective layer, the method further includes: Etching the second semiconductor layer, the light emitting layer and the second semiconductor layer to form a scribe line exposing the substrate; and, After forming the first electrode, the second electrode and the third electrode, the substrate is cut along the scribe line to form a single flip-chip light emitting diode.

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