Back contact BC solar cell structure and preparation method thereof

Abstract

The invention belongs to the technical field of solar power generation, and particularly relates to a back contact BC solar cell structure and a preparation method thereof. A tunneling SiO2 layer and a phosphorus-doped N + poly layer with high crystallization rate and low parasitic absorption are arranged in a back N region of the cell; the P region is sequentially provided with an i: a-Si layer, a P: a-Si sub-layer and a P-uc-SiOxCy sub-layer; the front surface of the cell is provided with a laminated gradient silicon nitride antireflection passivation film; the back N region adopts the SiO2 layer and the N + poly field structure with high crystallization rate and low parasitic absorption to replace an i: a-Si + N: a: Si field structure of a traditional HBC to improve the current density, and the back N region adopts the suede light trapping structure to replace a polishing structure to improve the current density. A low-temperature silicon nitride antireflection film is additionally arranged on the upper layer of the TCO transparent conductive film to improve passivation and current density, silicon nitride coverage antireflection is carried out on the isolation regions of the P region and the N region to improve passivation and current density, the back efficiency of the cell is improved, and the double-sided rate is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar power generation, and in particular relates to a back-contact BC solar cell structure and a preparation method thereof. Background Art

[0002] Photovoltaic power generation is a system that uses solar cells to directly convert sunlight energy into electrical energy based on the principle of the photovoltaic effect. The basic structure of a solar cell is a large-area planar PN junction. When sunlight shines on the PN junction, the PN junction absorbs light energy to excite electrons and holes, and then generates voltage in the PN junction to achieve photoelectric conversion. Therefore, the core structure that realizes the conversion of sunlight energy and electrical energy in crystalline silicon cells is the PN junction.

[0003] As PERC cells gradually approach the limit efficiency of 24.5%, the industry has begun to seek the next generation of crystalline silicon cell technology. The current mainstream technologies are Topcon (tunneling oxide passivation contact), HJT (heterojunction), and IBC (interdigitated back contact). Unlike Topcon and HJT, which improve cell efficiency by changing the passivation method, IBC cells transfer all the cell grid lines to the back, reduce the grid line shading area, increase current density, and increase cell efficiency. IBC cells are platform technologies, which are superimposed with Topcon technology to form TBC and with HJT technology to form HBC.

[0004] HBC cells inherit the difficulties of HJT and IBC production processes, such as long process steps, complex manufacturing, and narrow process windows. TBC cells need to solve problems such as back electrode isolation and uniformity of polysilicon passivation quality. Since the technical routes of the two battery structures are quite different, the existing solutions can only choose to prepare one of the battery structures that changes the passivation method and reduces the gate lines.

[0005] Therefore, how to provide a battery structure that takes into account the advantages of both TBC batteries and HBC batteries is a technical problem that urgently needs to be solved in this field.

[0006] It should be noted that the above information disclosed in this background technology section is only used to understand the background technology of the present application concept, and therefore, the above description is not considered to constitute information of the prior art. Summary of the invention

[0007] The embodiments of the present disclosure at least provide a back-contact BC solar cell structure and a method for preparing the same.

[0008] In a first aspect, an embodiment of the present disclosure provides a method for preparing a back-contact BC solar cell, comprising the following steps: step S1, performing double-sided texturing on a silicon wafer to prepare a clean silicon wafer surface with a low-reflectivity pyramid texturing morphology; step S2, oxidizing the back side of the silicon wafer from bottom to top to prepare a tunneling SiO2 layer, and then depositing a phosphorus-doped N+poly layer from bottom to top on the tunneling SiO2 layer, and then depositing a phosphorus-doped N+poly layer from top to bottom on the front side of the silicon wafer, and then depositing a SiO2 mask layer from top to bottom on the phosphorus-doped N+poly layer; step S 3. Laser oxidize the phosphorus-doped N+poly layer on the back of the silicon wafer to prepare a SiO2 mask layer; step S4, perform alkaline polishing on the silicon wafer to remove the tunneling SiO2 layer and the phosphorus-doped N+poly layer in the area without the SiO2 mask layer on the back and the SiO2 mask layer on the front, and etch to expose the back silicon base; step S5, perform high-temperature annealing on the silicon wafer to activate the high-temperature crystallization of amorphous silicon and promote the doping atoms, so that the phosphorus-doped N+poly layer on the front of the silicon wafer and the phosphorus-doped N+poly layer on the back form an N+ front passivation field and an N+ inner expansion layer respectively, and high-temperature oxidation The front phosphorus-doped N+poly layer is removed to SiO2 to obtain the FSF layer, and then pickled; step S6, depositing a layer of i: a-Si layer from top to bottom on the back of the pickled silicon wafer, HPT cleaning the deposited surface and then depositing the P: a-Si layer from top to bottom; step S7, using inkjet printing to prepare a patterned mask on the amorphous surface of the P region on the back of the silicon wafer; step S8, using ion etching to remove the amorphous silicon in the P region on the back of the silicon wafer without the patterned mask; step S9, using an organic solvent to ultrasonically clean the silicon wafer and remove the patterned mask on the back ; Step S10, HPT cleaning the back of the silicon wafer and depositing a layer of TCO transparent conductive film; Step S11, laser etching the back of the silicon wafer to isolate the N area from the P area; Step S12, depositing an aluminum oxide layer on the front of the silicon wafer, and then depositing a laminated gradient silicon nitride anti-reflection passivation film on the front and back of the silicon wafer respectively; Step S13, using laser grooving, partially opening windows in the laminated gradient silicon nitride anti-reflection passivation film in the N area and P area on the back of the silicon wafer to expose the TCO transparent conductive film, and screen-printing low-temperature metal slurry in the grooved area for curing light injection.

[0009] In an optional implementation, the reflectivity of the surface of the silicon wafer after polishing in step S1 is 9-12%; the size of the tower base is 1-3 μm, and the tower height is 0.5-3 μm.

[0010] In an optional embodiment, in step S2, the thickness of the tunneling SiO2 layer on the back of the silicon wafer is 0.8-1.5 nm, the thickness of the phosphorus-doped N+poly layer is 50-300 nm, and the doping concentration is 1E+20 cm -3 ~2E+21cm -3: The thickness of the SiO2 mask layer on the front side of the silicon wafer is 10-50nm, the thickness of the phosphorus-doped N+poly layer is 5-10nm, and the doping concentration is 1E+19cm -3 ~1E+20cm -3 .

[0011] In an optional implementation, in step S3, the thickness of the SiO2 mask layer on the back side of the silicon wafer is 5-15 nm, and the width of the oxidized region is 100-400 μm.

[0012] In an optional implementation, in step S4, the reflectivity of the corroded area is 35-45%; the tower base size of the corroded area is 5-15 μm; and the corrosion depth of the corroded area is 0.5-2 μm.

[0013] In an optional embodiment, in step S5, the temperature for high-temperature crystallization is 850-910°C; the time for high-temperature crystallization is 30-60 minutes; the temperature for high-temperature oxidation is 800-850°C; and the time for high-temperature oxidation is 10-30 minutes.

[0014] In an optional embodiment, in step S6, the thickness of the i:a-Si layer is 2-10 nm; the P:a-Si layer includes P:a-Si layers and P-uc-SiO x C y Layering; wherein the thickness of the P: a-Si layer is 10-20nm and the doping concentration is 1E+18cm -3 ~5E+18cm -3 :The P-uc-SiO x C y The layer thickness is 20-50nm and the doping concentration is 5E+18cm -3 ~2E+19cm -3 .

[0015] In an optional embodiment, in step S7, the patterned mask prepared by the ink has a width of 100-500 μm and a height of 10-20 μm.

[0016] In an optional implementation, in step S11, the laser power is 300-600 W, and the etching width is 10-20 μm.

[0017] In an optional implementation, in step S13, the width of the laser groove is 10-30 μm.

[0018] The beneficial effects of the present invention are that the method for preparing the back contact BC solar cell has the following advantages:

[0019] 1. The amorphous interdigitated structure of the P region of the present invention is prepared by inkjet printing + ion etching + organic cleaning. The hydrogenated amorphous silicon has no acid or alkali contact, and the risk of performance failure is extremely low;

[0020] 2. The N-region poly is prepared by in-situ doping PVD coating, without wrapping, plating and expanding, and no additional wrapping, plating and expanding process is required;

[0021] 3. The N-region and P-region of the present invention use substrates with different morphologies, which is more conducive to laser grooving positioning and identification, and prepares the N-region polyP-region amorphous interdigitated arrangement structure, reducing the risk of battery leakage and offset;

[0022] 4. The process of the present invention does not involve laser bombardment of hydrogenated amorphous materials, and the risk of performance failure is extremely low.

[0023] In the second aspect, the embodiment of the present disclosure also provides a back-contact BC solar cell structure prepared by the method as described above, wherein the back N region of the cell is provided with a tunneling SiO2 layer and a phosphorus-doped N+poly layer with high crystallization rate and low parasitic absorption; the P region is provided with i: a-Si layer, P: a-Si layer and P-uc-SiO x C y Layering; the front side of the battery is provided with a laminated gradient silicon nitride anti-reflection passivation film.

[0024] The beneficial effects of the present invention are that the back contact BC solar cell structure has the following advantages:

[0025] 1. The back N region of the present invention adopts a tunneling SiO2 layer and an N+poly field structure with a high crystallization rate and low parasitic absorption to replace the i:a-Si+N:a:Si field structure of the traditional HBC to improve the current density, and the back N region adopts a velvet light trapping structure to replace the polishing structure to improve the current density, and the metal electrode contact area is increased to reduce the contact resistance and improve the fill factor, and a layer of low-temperature silicon nitride anti-reflection film is added to the upper layer of the TCO transparent conductive film to improve passivation and current density, and the P region and N region isolation region are covered with silicon nitride for anti-reflection to improve passivation and current density. The P region uses an i:a-Si+P:a-Si+P-uc-SiOxCy emitter film layer structure to replace the traditional i:a-Si+P:a-Si, and the introduction of microcrystalline boron-doped carbon oxide silicon reduces the parasitic absorption of the film layer to improve the current density, improve the efficiency of the back side of the battery, and improve the bifaciality;

[0026] 2. The front side uses a low-temperature gradient SiNx+aluminum oxide passivation anti-reflection film to replace the intrinsic amorphous silicon+SiNx to reduce the parasitic absorption of amorphous silicon. The back N area uses a velvet light-trapping structure to replace the polishing structure to increase the current density. A layer of low-temperature silicon nitride anti-reflection film is added to the upper layer of the TCO transparent conductive film to improve passivation and current density. The P area and N area isolation area are covered with silicon nitride for anti-reflection to improve passivation and current density. The P area uses i:a-Si+P:a-Si+P-uc-SiOxCy emitter film structure to replace the traditional i:a-Si+P:a-Si. The introduction of microcrystalline boron-doped carbon oxide silicon reduces the parasitic absorption of the film layer and increases the current density, reduces the overall optical loss of the BC battery, and improves the overall current density of the battery.

[0027] 3. The present invention adopts amorphous silicon passivation interface and emitter preparation only in the back P-region junction area, Al2O3+SiNx passivation interface in the front, and SiO2+poly structure passivation interface in the back N-region. Compared with the traditional HBC battery covered with all amorphous silicon, the risk of ultraviolet attenuation is greatly reduced;

[0028] 4. The front and back sides of this battery structure are covered with a water vapor and acid-base resistant SiNx film layer, without TCO exposure that is sensitive to water vapor and acid-base, making component packaging easier and reducing the risk of failure;

[0029] 5. The N-region junction area of ​​the present invention adopts SiO2+poly passivation contact structure. During the high-temperature annealing and crystallization process of poly, it has the impurity gettering effect to improve the quality of silicon wafers, and does not require the additional impurity gettering process of traditional HBC battery preparation;

[0030] 6. The P-region junction area on the back of the battery of the present invention is passivated with amorphous silicon, and the front side is made of low-temperature silicon nitride to reduce aluminum oxide damage. The overall passivation upper limit is higher than that of traditional TBC batteries and is not inferior to that of HBC batteries.

[0031] 7. After the N-region and P-region are isolated by laser grooving in the present invention, an insulating material SiNx is used for secondary isolation, which greatly reduces the risk of BC battery leakage.

[0032] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0033] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 A schematic diagram of a process flow provided for an embodiment of the present disclosure;

[0036] Figure 2 A schematic diagram of a battery structure provided in an embodiment of the present disclosure;

[0037] Figure 3 A schematic diagram of a process flow provided for an embodiment of the present disclosure;

[0038] Figure 4 A schematic diagram of a battery structure provided in an embodiment of the present disclosure;

[0039] Figure 5 A schematic diagram of a battery structure provided in an embodiment of the present disclosure;

[0040] Figure 6 A schematic diagram of a process flow provided for an embodiment of the present disclosure;

[0041] Figure 7 A schematic diagram of a battery structure provided in an embodiment of the present disclosure;

[0042] Figure 8 A schematic diagram of a battery structure provided in an embodiment of the present disclosure;

[0043] Fig. 9 A schematic diagram of a process flow provided for an embodiment of the present disclosure;

[0044] Fig.10 A schematic diagram of a battery structure provided in an embodiment of the present disclosure;

[0045] Fig.11 A schematic diagram of a battery structure provided in an embodiment of the present disclosure;

[0046] Fig.12 A schematic diagram of a process flow provided for an embodiment of the present disclosure;

[0047] Fig.13 A schematic diagram of a battery structure provided in an embodiment of the present disclosure;

[0048] Fig.14 A schematic diagram of a process flow provided for an embodiment of the present disclosure;

[0049] Fig.15 A schematic diagram of a battery structure provided in an embodiment of the present disclosure;

[0050] Fig.16 A schematic diagram of a process flow provided for an embodiment of the present disclosure;

[0051] Fig.17 A schematic diagram of a battery structure provided in an embodiment of the present disclosure;

[0052] Fig.18 A schematic diagram of a battery structure provided in an embodiment of the present disclosure;

[0053] Fig.19 A schematic diagram of a process flow provided for an embodiment of the present disclosure;

[0054] Fig. 20 A schematic diagram of a battery structure provided in an embodiment of the present disclosure;

[0055] Fig.21 A schematic diagram of a battery structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0057] As used herein, the phrases "in one embodiment," "according to one embodiment," "in some embodiments," and the like generally refer to the fact that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure. Therefore, a particular feature, structure, or characteristic may be included in more than one embodiment of the present disclosure, so that these phrases do not necessarily refer to the same embodiment. As used herein, the terms "example," "exemplary," and the like are used to "serve as an example, instance, or illustration." Any implementation, aspect, or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or superior to other implementations, aspects, or designs. On the contrary, the use of the terms "example," "exemplary," and the like is intended to present concepts in a concrete manner.

[0058] Herein, example embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. As used herein, expressions such as "at least one of..." modify the entire list of elements when following a list of elements, rather than modifying individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0059] The terms used herein are only used to describe specific exemplary configurations and are not intended to be limited. As used herein, the singular articles "one", "an" and "the" may also be intended to include plural forms, unless it is clearly indicated above that this is not the case. The terms "comprise", "include" and "have" are inclusive, and therefore specify the presence of features, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or combinations thereof. The method steps, processes and operations described herein should not be interpreted as necessarily requiring them to be performed in the specific order discussed or shown, unless specifically identified as an execution order. Additional or alternative steps may be adopted.

[0060] Terminology explanation:

[0061] HBC: The Chinese name of IBC battery is cross-finger back contact battery. The emitter, back field and corresponding positive and negative electrodes are integrated on the back of the battery in a cross-finger shape. This structure avoids the metal grid electrode from blocking light, maximizes the use of incident light, and increases the short-circuit current of the battery. HBC technology is a combination of HJT technology and IBC technology, which can increase current density and battery efficiency without losing passivation.

[0062] The characteristics of IBC batteries are that there is no electrode on the front side of the battery, and the positive and negative electrode grid lines are integrated on the back side in a fork-like shape. The main features of the battery are: 1. The use of high minority carrier lifetime silicon wafers to prevent carriers from being recombined before being transmitted to the PN junction; 2. The positive and negative electrodes are integrated on the back side, and the grid line pattern morphology has a large design window; 3. The front side anti-reflection stack film & front surface field design maximizes optical utilization and reduces front surface recombination; 4. The back N and P regions are arranged in a fork-like shape, the P region (emitter) collects holes, and the N region (back field) captures electrons.

[0063] Advantages of IBC batteries: 1. There is no grid line blocking the front, the photon absorption level is high, and the current density is high; 2. Combined with HJT technology, the battery current density is improved without passivation loss, and the battery efficiency is improved; 3. Combined with Topcon technology, the positive and negative electrodes can be prepared with passivation contact structures without large current density loss to improve the passivation level; 4. Both the positive and negative electrodes are on the back, which can increase the grid line width, reduce the contact resistance, improve FF, and have no significant effect on the current; 5. There is no grid line design on the front of the battery, the battery is beautiful, and the BIPV (building integrated photovoltaic) application scenario has obvious advantages.

[0064] Disadvantages of BC cells: 1. Low bifaciality of the cell (the grid line is integrated on the back, resulting in an increase in the back shading area and a large difference in efficiency between the front and back sides); 2. Complex process, multiple steps, expensive equipment, high cost, and low yield (the traditional HBC cell preparation process includes: texturing and cleaning--front i: a-Si--front SiNx--back i: a-Si--back P: a-Si--back mask--laser grooving--etching--back i: a-Si--back N: a-Si--laser film opening--etching--back TCO--laser film opening to isolate PN area--printing and curing--light injection) (conventional TBC cell preparation The process includes: double-sided polishing - tunneling oxide layer preparation - intrinsic poly deposition - boron diffusion - laser ablation - alkali polishing - tunneling oxide layer preparation - intrinsic poly deposition - phosphorus diffusion - laser ablation - alkali washing - laser ablation - single-sided chain acid - texturing - anti-reflection passivation film - printing and sintering); 3. The poly interdigitated arrangement structure in the N and P regions on the back is difficult to prepare (it is difficult for the laser to accurately locate the film opening area and the film opening depth); 4. BC batteries have high requirements for silicon wafer quality and front surface body passivation (carriers are separated from the PN junction and need to pass through the front surface and body of the silicon wafer to reach the back. Defects in the front surface of the battery will recombine the carriers before they reach the PN junction).

[0065] Existing technology 1: Xuzhou Pule New Energy (patent number CN 115050855 A)

[0066] Scheme steps: 1. Double-sided texturing; 2. Back-side polishing; 3. Double-sided deposition of i:a-Si; 4. Back-side patterned boron paste printing and drying; 5. Back-side patterned phosphorus paste printing and drying; 6. Laser doping of N-zone and P-zone; 7. Ultrasonic cleaning of slurry with organic water mixed solution; 8. Back-side TCO deposition; 9. Laser grooving to isolate N-zone and P-zone; 10. Front-side deposition of SiO / SiON / SiN stacked film; 11. Screen printing, curing and sintering.

[0067] Concept: 1. From top to bottom: SiN / SiON / SiO---i: a-Si---suede surface---silicon base---polished surface---i: a-Si---P: a-Si---Na: ​​Si---TCO---silver paste HBC battery structure;

[0068] 2. i: a-Si is deposited on the back of the battery, and the boron slurry and phosphorus slurry are cross-printed using a screen. After drying, laser doping, and cleaning, the poly interdigitated arrangement structure of the N and P regions on the back of the battery is completed.

[0069] shortcoming:

[0070] 1. Use doping slurry as the doping source. Due to its special fluidity and corrosiveness, it requires the use of professional scrapers, scrapers, special non-metallic mesh, and non-market mass production auxiliary materials;

[0071] 2. In order to meet the printing requirements, the doping slurry often adds more organic solvents to achieve curing. Organic solvents will affect the diffusion effect of boron and phosphorus doping, and the diffusion uniformity is poor;

[0072] 3. To meet the printing requirements, more organic solvents are often added to the doped slurry, which has a strong odor, requires high ventilation on site, and requires high protective measures for employees;

[0073] 4. It is difficult to control the doping amount and doping depth of amorphous silicon by laser boron-phosphorus slurry, which can easily damage the underlying hydrogenated amorphous silicon and affect the passivation of the battery.

[0074] 5. The ARC anti-reflection film is prepared at a high temperature of >200°C on the front side, which can easily lead to a decrease in the passivation of amorphous silicon;

[0075] 6. The front side adopts the anti-reflection passivation film design of SiNx+i:a-Si, which has large parasitic absorption and large battery current loss;

[0076] 7. In this process, amorphous silicon is exposed for a long time without a protective film, which affects the passivation of the battery.

[0077] Prior art 2: Aikang (CN 218849510 U)

[0078] Scheme steps: 1. Cleaning and texturing; 2. Preparation of silicon oxide and intrinsic amorphous silicon on the back; 3. High-temperature phosphorus diffusion, crystallization of the amorphous on the back into phosphorus-doped polysilicon; 4. Laser etching; 5. Poly cleaning, de-plating and expansion, alkali polishing and cleaning of the laser ablation area until the N-type silicon base is washed; 6. Intrinsic amorphous silicon deposition on the front; 7. Preparation of silicon nitride on the front; 8. Preparation of intrinsic amorphous silicon and P:a-Si by back mask-grooving-deposition-etching technology; 9. Preparation of TCO by back mask-grooving-deposition-etching technology; 10. Screen electrode printing and curing.

[0079] concept:

[0080] The back N-region and P-region are prepared by the traditional mask-groove-deposition-etching method, and the N-region adopts the polo passivation contact structure of SiO and N+poly to replace the i:a-Si+N:a:Si battery structure.

[0081] shortcoming:

[0082] 1. The front side adopts the anti-reflection passivation film design of SiNx+i:a-Si, which has large parasitic absorption and large battery current loss;

[0083] 2. The H passivation effect of the polo passivation contact structure interface of SiO and N+poly in the back N region is poor;

[0084] 3. The N+poly preparation of the back N region uses high-temperature tubular equipment, which involves wrapping, expansion and plating.

[0085] The defects existing in the above solutions are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the present disclosure for the above problems below should be the contributions made by the inventor to the present disclosure during the disclosure process.

[0086] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0087] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0088] Step S1, double-sided texturing of the silicon wafer is performed to prepare a low reflectivity pyramid texture morphology and a clean silicon wafer surface, please refer to Figure 1 The process flow shown in Figure 2 The specific process of the silicon wafer shown is as follows:

[0089] Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-15%) to clean the surface of the silicon wafer to remove dirt on the surface of the silicon wafer. The process temperature is 55℃-70℃ and the process time is 2min-5min.

[0090] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0091] A mixed solution of potassium hydroxide (1%-10%) and additives (0.5%-5%) is used to form a low-reflectivity pyramid velvet morphology on the surface of the silicon wafer and remove cutting damage. The process temperature is 60°C-85°C and the process time is (3min-5min).

[0092] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0093] Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-20%) to clean the surface of the silicon wafer to remove additive residues. The process temperature is 55℃-70℃ and the process time is 2min-5min.

[0094] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0095] The surface of the silicon wafer is cleaned with a mixed solution of hydrofluoric acid (1%-10%) and hydrochloric acid (1%-10%), the process temperature is room temperature, and the process time is 3min-5min;

[0096] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0097] Use slow pulling to remove dirt from the surface of the silicon wafer and dehydrate the silicon wafer. The cleaning time is 0.5min-1min and the cleaning temperature is 20℃-70℃.

[0098] Place the silicon wafer in a drying tank, purge at high temperature to dry the surface of the silicon wafer. Purge gas: nitrogen or compressed air, temperature: 80℃-100℃, drying time: 5min-15min;

[0099] Wafer weight reduction: 0.3g-0.6g; (taking 182.2 size wafer as an example)

[0100] Surface reflectivity: 9%-12%;

[0101] Tower base size: 1um-3um;

[0102] Tower height: 0.5um-3um.

[0103] Step S2: deposit a layer of tunneling SiO2 and a layer of phosphorus-doped poly on the back of the silicon wafer, deposit a layer of phosphorus-doped poly on the front, and a layer of SiO2 mask. Figure 3 The process flow shown in Figure 4 The specific process of the silicon wafer shown is as follows:

[0104] The back of the double-sided textured silicon wafer is first oxidized from bottom to top by flat-plate PECVD to prepare a tunneling SiO2 layer, and then a phosphorus-doped poly layer is deposited from bottom to top on the back of the silicon wafer by flat-plate PVD. Then, a phosphorus-doped poly layer is deposited from top to bottom on the front of the silicon wafer by flat-plate PVD. Finally, a SiO2 mask layer is deposited from top to bottom on the front of the silicon wafer by flat-plate PVD.

[0105] The double-sided textured silicon wafer is placed on a hollow carrier, gate valve 1 is opened, and the wafer is transferred into the loading chamber for evacuation, gate valve 2 is opened, and the wafer is transferred to the PECVD1 reaction chamber 1 to oxidize the surface of the silicon wafer from bottom to top to prepare a layer of tunneling SiO2;

[0106] Open gate valve 3, transfer the carrier into transition chamber 1 (gas isolation), open gate valve 4, first transfer to buffer chamber 1, then transfer to PVD1 reaction chamber 2 to deposit phosphorus-doped poly on the back from bottom to top, then transfer to PVD2 reaction chamber 3 to deposit phosphorus-doped poly on the front from bottom to top, then transfer to PVD3 reaction chamber 4 to deposit SiO2 mask on the front from bottom to top, and finally transfer to buffer chamber 2 to complete the film preparation;

[0107] Open gate valve 5, transfer the carrier to unloading chamber 1, fill the atmosphere with N2, open gate valve 6, transfer the carrier out of the chamber, and collect the silicon wafers;

[0108] PECVD1 reaction chamber 1: PECVD method to oxidize silicon wafers, using oxygen as process gas, process temperature: 150℃-350℃, process pressure: 5Pa-20Pa, power: 100W-500W;

[0109] PVD1 reaction chamber 2: When preparing phosphorus-doped poly by PVD, silicon target and argon are used as working gas, phosphine is used as doping gas, process temperature: 150℃-300℃, process pressure: 0.3Pa-2Pa, power: 10000W-40000W;

[0110] PVD2 reaction chamber 3: When preparing phosphorus-doped poly by PVD, silicon target and argon are used as working gas, phosphine is used as doping gas, process temperature: 150℃-300℃, process pressure: 0.3Pa-2Pa, power: 10000W-40000W;

[0111] PVD3 reaction chamber 4: When preparing SiO2 by PVD, silicon target and argon are used as working gas, O2 is used as doping gas, process temperature: 150℃-300℃, process pressure: 0.3Pa-2Pa, power: 10000W-40000W;

[0112] Back tunneling silicon oxide: thickness: 0.8nm-1.5nm;

[0113] Back side phosphorus-doped poly: thickness: 50nm-300nm doping concentration: 1E+20cm -3 ~2E+21cm -3 ;

[0114] Front phosphorus-doped poly: thickness: 5nm-10nm doping concentration: 1E+19cm -3 ~1E+20cm -3 ;

[0115] Front silicon oxide mask: thickness: 10nm-50nm;

[0116] Equipment structure:

[0117] The vacuum blocking technology of "transition-isolation-coating-isolation" is adopted to meet the process pressure of different film layer preparation, and avoid process abnormalities caused by "cross-gas" between process gases of different film layer preparation. A single machine can meet the film preparation of different film layers with different process methods, and combine the back PECVD preparation of SiO2, the front and back PVD preparation of phosphorus-doped poly, and the front PVD preparation of SiO2 into one;

[0118] Function of transition chamber: adjust pressure to meet the switching of different process pressure conditions / blocking of gas medium in different process chambers;

[0119] Function of buffer chamber: secondary isolation and blocking of different gas media.

[0120] Step S3, laser oxidation of the back N region to prepare a patterned silicon oxide mask, Figure 5 The specific process of the silicon wafer shown is as follows:

[0121] Laser-induced oxidation technology is used to form a patterned silicon oxide mask on the N-region poly on the back of the silicon wafer. The battery is placed on a horizontal platform, and a pulsed ultraviolet nanosecond laser is used to locally oxidize the polysilicon to prepare a patterned silicon oxide mask.

[0122] Laser power: 300W-600W;

[0123] Silicon oxide mask: thickness: 5nm-15nm, oxidation area width: 100um-400um, can be freely adjusted.

[0124] Step S4, alkali polishing removes the tunnel oxide layer and phosphorus-doped poly in the back area without SiO2 mask, and corrodes the silicon base to a certain depth, see Figure 6 The process flow shown in Figure 7 The specific process of the silicon wafer shown is as follows:

[0125] Use a mixed solution of potassium hydroxide (1%-10%) and alkaline polishing additive (0.5%-5%) to clean. Potassium hydroxide is used to corrode and remove the tunneling oxide layer and phosphorus-doped poly in the back area without SiO2 mask, and continue to corrode the silicon base to a certain depth. The process temperature is 55℃-70℃ and the process time is 0.5min-1.5min.

[0126] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0127] Use a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-20%) to clean the surface of the silicon wafer to remove additive residues. The process temperature is 55℃-70℃ and the process time is 2min-5min.

[0128] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0129] A mixed solution of hydrofluoric acid (0.1%-2%), hydrochloric acid (0.1%-2%) and O3 (10ppm-50ppm) is used to clean the surface of the silicon wafer. At the same time, the weak etching system of O3 and HF lubricates the surface of the silicon wafer, reduces burr defects on the surface of the silicon wafer, and is more conducive to the passivation of amorphous silicon. The process temperature is 15℃-25℃, and the process time is 2min-3min.

[0130] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0131] The surface of the silicon wafer is cleaned with a mixed solution of hydrofluoric acid (1%-10%) and hydrochloric acid (1%-10%), the process temperature is room temperature, and the process time is 3min-5min;

[0132] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0133] Use slow pulling to remove dirt from the surface of the silicon wafer and dehydrate the silicon wafer. The cleaning time is 0.5min-1min and the cleaning temperature is 20℃-70℃.

[0134] Place the silicon wafer in a drying tank, purge at high temperature to dry the surface of the silicon wafer. Purge gas: nitrogen or compressed air, temperature: 80℃-100℃, drying time: 5min-15min;

[0135] Cleaning method: The silicon wafer enters the solution vertically, the direction of the silicon wafer laser line is perpendicular to the solution surface, and the detachment of drug residues on the silicon wafer surface is not affected by the groove morphology on the back side;

[0136] Reflectivity of corroded area: 35%-45%;

[0137] The size of the tower base in the corroded area: 5um-15um;

[0138] Corrosion depth of corroded area: 0.5um-2um.

[0139] Step S5, the silicon wafer is placed in a high temperature annealing furnace tube, at a certain temperature and time, the amorphous silicon is first crystallized at high temperature to activate the doping atoms, and then the front N+poly is oxidized to PSG at high temperature, and a mixed solution of hydrofluoric acid + hydrochloric acid is used to remove the oxide layer formed by annealing on the front and back sides, and the following is obtained: Figure 8 The specific process of the silicon wafer shown is as follows:

[0140] Insert the silicon wafer horizontally or vertically into the quartz boat and transfer it to the high-temperature furnace tube through the silicon carbide slurry;

[0141] The doped amorphous silicon film is crystallized into polysilicon through high-temperature annealing. The phosphorus atoms on the back are activated to reduce the resistivity of the film layer and penetrate the silicon oxide to form an N+ back field. The phosphorus atoms on the front are activated and pushed forward to the silicon wafer to form an N+ front passivation field.

[0142] Oxidation with oxygen at high temperature, the thinner poly on the front side is oxidized to SiO2 and then removed, and the thicker poly on the back side has no effect;

[0143] The surface of the silicon wafer is cleaned with a mixed solution of hydrofluoric acid (1%-10%) and hydrochloric acid (1%-10%), the process temperature is room temperature, and the process time is 3min-5min;

[0144] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0145] Use slow pulling to remove dirt from the surface of the silicon wafer and dehydrate the silicon wafer. The cleaning time is 0.5min-1min and the cleaning temperature is 20℃-70℃.

[0146] Place the silicon wafer in a drying tank, purge at high temperature to dry the surface of the silicon wafer. Purge gas: nitrogen or compressed air, temperature: 80℃-100℃, drying time: 5min-15min;

[0147] Cleaning method: The silicon wafer enters the solution vertically, the direction of the silicon wafer laser line is perpendicular to the solution surface, and the detachment of drug residues on the silicon wafer surface is not affected by the morphology of the back groove;

[0148] High temperature crystallization advancement temperature: 850℃-910℃;

[0149] High temperature crystallization advancement time: 30min-60min;

[0150] High temperature oxidation temperature: 800℃-850℃;

[0151] High temperature oxidation time: 10min-30min.

[0152] Step S6, ia:Si / P:a-Si deposition on the back of the silicon wafer, see Fig. 9 The process flow shown in Fig.10 The specific process of the silicon wafer shown is as follows:

[0153] A layer of i: a-Si is first deposited from top to bottom on the back of the pickled silicon wafer by flat-plate PECVD, and then the deposited surface is cleaned by HPT (H ion cleaning), and then P: a-Si is first deposited from top to bottom on the back of the silicon wafer by flat-plate PECVD. The deposition includes (a layer of P: a-Si, a layer of P-uc-SiOx C y );

[0154] After double-sided alkaline polishing, the silicon wafer is placed on a hollow carrier plate, the gate valve 7 is opened, and the wafer is transferred into the loading chamber for evacuation, the gate valve 8 is opened, and the wafer is transferred into the buffer preheating chamber 3, and then transferred to the PECVD2 reaction chamber 5 to deposit ia:Si from top to bottom, and then transferred to the HPT cleaning buffer chamber 4, where H ions clean the deposited surface to complete the i:a-Si preparation;

[0155] Open the gate valve 9, transfer the carrier into the transition chamber 2 (gas isolation), open the gate valve 10, first transfer it to the buffer 5, and then transfer it to the PECVD3 reaction chamber 6 to deposit a layer of P: a-Si and a layer of P-uc-SiO from top to bottom. x C y , and then transferred to buffer 6 to complete the preparation of P: a-Si;

[0156] Open the gate valve 11, transfer the carrier to the unloading chamber 2, backfill to the atmosphere with nitrogen, open the gate valve 12, and transfer the carrier out of the chamber;

[0157] PECVD2 reaction chamber 5: Preparation of i:a-Si by PECVD method, using SiH4 and H2 as process gases, process temperature: 100℃-250℃, process pressure: 10Pa-50Pa, SiH4:H2 flow ratio: 1:10-1:30, power: 50W-300W;

[0158] PECVD3 reaction chamber 6: PECVD method to prepare P: a-Si, P: a-Si is divided into two layers: conventional B-doped amorphous silicon (Pa:Si), B-doped microcrystalline carbon oxide silicon (P-uc-SiO x C y );

[0159] Conventional B-doped amorphous silicon (P: a-Si) is prepared with SiH4, H2, and B2H6 as process gases, process temperature: 100℃-250℃, process pressure: 10Pa-50Pa, SiH4:H2:B2H6 (2%) flow ratio: 1:20:5-1:30:15, power: 50W-300W;

[0160] Preparation of B-doped microcrystalline silicon oxide (P-uc-SiOxCy), using SiH4, H2, B2H6, CO2, TMB as process gases, process temperature: 100℃-250℃, process pressure: 50Pa-100Pa, SiH4:H2:B2H6 (2%) flow ratio: 1:30:10-1:60:30, CO2 and TMB as micro-doping gas flow: 5sccm-20sccm, power: 300w-500W;

[0161] HPT cleaning buffer chamber 4: PECVD method is used to ionize H to clean the deposited surface of the silicon wafer, with H2 as the process gas.

[0162] Process temperature: 100℃-250℃, process pressure: 50Pa-100Pa, power: 50W-400W;

[0163] i: a-Si thickness: 2nm-10nm, freely adjustable;

[0164] P: a-Si thickness: 10nm-20nm, P-uc-SiO x C y Thickness: 20nm-50nm, thickness can be freely adjusted;

[0165] P: a-Si doping concentration: 1E+18cm -3 ~5E+18cm -3 :P-uc-SiO x C y Doping concentration: 5E+18cm -3 -2E+19cm -3 , the doping amount can be freely adjusted.

[0166] Step S7, using inkjet printing technology to prepare a patterned mask on the amorphous surface of the P region to obtain Fig.11 The specific process of the silicon wafer shown is as follows:

[0167] Using non-contact inkjet printing technology, non-contact printing ink is applied to the amorphous P region on the back of the silicon wafer to form a patterned ink mask;

[0168] Ink width: 100um-500um

[0169] Ink height: 10um-20um.

[0170] Step S8, ion etching to remove the amorphous silicon in the back area without ink mask, see Fig.12 The process flow shown in Fig.13 The specific process of the silicon wafer shown is as follows:

[0171] RIE ion etching technology is used to remove amorphous silicon in the back area without ink mask and to etch part of the ink mask;

[0172] After contactless inkjet printing, the silicon wafer is placed on a hollow carrier with the back side facing upwards, the gate valve 13 is opened, the wafer is transferred to the loading chamber 3 for evacuation, the gate valve 14 is opened, the wafer is transferred to the ion etching chamber for ion etching, the gate valve 15 is opened, the wafer is transferred to the unloading chamber 3, the atmosphere is backfilled with nitrogen, the gate valve 16 is opened, and the carrier is transferred out of the chamber;

[0173] Ion etching chamber: Nitrogen trifluoride is used as the working gas, and the radio frequency power supply excites the plasma, bombarding the back of the silicon wafer to etch the amorphous silicon in the unmasked area.

[0174] Step S9: ultrasonically clean the silicon wafer with organic solvent to remove the ink mask on the back side. Fig.14 The process flow shown in Fig.15 The specific process of the silicon wafer shown is as follows:

[0175] Use isopropyl alcohol + water mixed solution to ultrasonically clean and remove the ink mask on the back. The cleaning time is 2min-3min and the cleaning temperature is 40℃-60℃.

[0176] Use water washing to remove drug residues and dirt on the surface, cleaning time: 2min-3min;

[0177] Use slow pulling to remove dirt from the surface of the silicon wafer and dehydrate the silicon wafer. The cleaning time is 0.5min-1min and the cleaning temperature is 20℃-70℃.

[0178] Place the silicon wafer in a drying tank and purge it at high temperature to dry the surface of the silicon wafer. The purge gas is nitrogen or compressed air. The temperature is 80℃-100℃ and the drying time is 5min-15min.

[0179] Step S10: HPT cleaning is performed on the back of the silicon wafer, and a TCO transparent conductive film is deposited on the back. Fig.16 The process flow shown in Fig.17 The specific process of the silicon wafer shown is as follows:

[0180] The back of the silicon wafer is subjected to HPT (H ion cleaning) by flat-plate PECVD method, and then a layer of TCO transparent conductive film is deposited;

[0181] The cleaned silicon wafer is placed with the back side facing upwards in the hollow carrier plate, the gate valve 17 is opened to enter the loading vacuum chamber, the gate valve 18 is opened to enter the HPT cleaning buffer chamber 7, and the H ions clean the front and back sides of the silicon wafer;

[0182] Open the gate valve 19, transfer the carrier to the transition chamber 2 to evacuate (gas isolation), open the gate valve 20, transfer the carrier to the buffer chamber 2 (secondary isolation), transfer the carrier to the PVD4 reaction chamber 7, deposit a layer of TCO from bottom to top, and then transfer to the buffer chamber 9 to complete the preparation of the TCO transparent conductive film;

[0183] The gate valve 21 is opened, and the carrier is transferred to the unloading chamber 4. The atmosphere is backfilled with nitrogen, and the gate valve 22 is opened, and the carrier is transferred out of the chamber.

[0184] Step S11, laser etching TCO, N region and P region isolation, to obtain Fig.18 The specific process of the silicon wafer shown is as follows:

[0185] Laser ablation technology is used to pattern-etch the TCO at the junction of the P and N regions on the back. The battery is placed on a horizontal platform, and a pulsed ultraviolet nanosecond laser is used to pattern-etch the TCO at the junction of the P and N regions on the back.

[0186] Laser power: 300w-600w;

[0187] Etching width: 10um-20um, freely adjustable.

[0188] Step S12, depositing aluminum oxide on the front side and depositing a laminated gradient silicon nitride anti-reflection passivation film on the front and back sides, see Fig.19 The process flow shown in Fig. 20 The specific process of the silicon wafer shown is as follows:

[0189] First, a layer of aluminum oxide is deposited on the front side of the silicon wafer by using a flat plate or tubular ALD or plate PECVD method, and then a layer of front and back deposited silicon nitride laminated gradient film is deposited on the front and back sides of the silicon wafer by using a flat plate PECVD method.

[0190] After the laser ablation isolation, the silicon wafer is placed on the hollow carrier with the front side facing upwards, the gate valve 23 is opened, the carrier is transferred to the preheating loading chamber 5 for evacuation and preheating, the gate valve 24 is opened, the carrier is transferred to the PECVD4 reaction chamber 8, and a layer of aluminum oxide is deposited from top to bottom on the front side by PECVD method to complete the aluminum oxide preparation;

[0191] Open the gate valve 25, transfer the carrier to the transition chamber 3 first, evacuate (gas isolation), open the gate valve 26, transfer to the buffer chamber 10, and then transfer to the PECVD5 reaction chamber 9, deposit a layer of high H content SiNx from top to bottom on the front side, a layer of high Si content SiNx, a layer of high N content SiNx from bottom to top on the back side, and then transfer to the buffer chamber 11 to complete the preparation of double-sided laminated gradient silicon nitride anti-reflection passivation film;

[0192] Open the gate valve 26, transfer the carrier to the unloading chamber 5, use nitrogen to backfill the atmosphere, open the gate valve 27, and transfer the carrier out of the chamber;

[0193] PECVD4 reaction chamber 8: Alumina is prepared by PECVD, with trimethylaluminum and laughing gas as working gases, process temperature: 150℃-250℃, process pressure: 20Pa-50Pa, trimethylaluminum / laughing gas flow ratio: 1:1-3:1, power: 100W-500W;

[0194] PECVD5 reaction chamber 9: SiNx laminated gradient passivation anti-reflection film is prepared by PECVD method, which is divided into three layers;

[0195] SiNx-1: SiH4, H2, and NH3 are used as process gases, and high H2 ratio, high pressure, and high power are used to prepare high H content silicon nitride and passivate the silicon wafer interface. The process temperature is 100℃-250℃, the process pressure is 80Pa-120Pa, and the SiH4 / NH3 / H2 flow ratio is 1:1:6-2:2:20; power is 200W-300W;

[0196] SiNx-2: SiH4 and NH3 are used as process gases, and high Si content and high density silicon nitride are prepared at low pressure and low power with high SiH4 ratio to protect high H content silicon nitride. At the same time, low power coating reduces SiNx-1 passivation damage. Process temperature: 100℃-250℃, process pressure: 30Pa-50Pa, SiH4 / NH3 flow ratio: 2:1-6:1, power: 100W-200W;

[0197] SiNx-3: SiH4 and NH3 are used as process gases, and high NH3 ratio, low pressure and low power are used to prepare high N content silicon nitride, reduce the overall film refractive index, reduce the front reflectivity of the battery, and increase the current density. The process temperature is 100℃-250℃, the process pressure is 30Pa-50Pa, the SiH4 / NH3 flow ratio is 1:2-1:6, and the power is 100W-200W.

[0198] Step S13, laser grooving, partially opening windows of SiNx in the N-region and P-region to expose TCO, screen printing low-temperature metal slurry in the grooving area, curing and light injection, and obtaining Fig.21 The specific process of the silicon wafer shown is as follows:

[0199] Laser grooving technology is used to partially open the SiNx in the N and P regions to expose the TCO;

[0200] Print metal paste in the window area of ​​the N and P areas on the back side;

[0201] After printing, the silicon wafer is transferred to a curing oven, dried and cured to form an ohmic contact with the TCO;

[0202] The battery is transferred to the annealing furnace, where annealing light is injected to excite H and improve passivation;

[0203] Complete BC battery preparation;

[0204] Laser slotting width: 10um-30um.

[0205] In summary, the back N region of the present invention adopts a tunneling SiO2 layer and an N+poly field structure with a high crystallization rate and low parasitic absorption to replace the i:a-Si+N:a:Si field structure of the traditional HBC to improve current density, the back N region adopts a velvet light trapping structure to replace the polishing structure to improve current density, and the metal electrode contact area is increased to reduce contact resistance and improve fill factor, a layer of low-temperature silicon nitride anti-reflection film is added to the upper layer of the TCO transparent conductive film to improve passivation and current density, the P region and N region isolation region are covered with silicon nitride for anti-reflection to improve passivation and current density, the P region uses i:a-Si+P:a-Si+P-uc-SiOxCy emitter film layer structure to replace the traditional i:a-Si+P:a-Si, the introduction of microcrystalline boron-doped carbon oxide silicon reduces the parasitic absorption of the film layer and improves the current density, thereby improving the back efficiency of the battery and the bifaciality.

[0206] Based on the above ideal embodiments of the present invention, the relevant staff can make various changes and modifications without departing from the technical concept of the present invention through the above description. The technical scope of the present invention is not limited to the contents of the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A method for preparing a back contact BC solar cell, characterized in that: The steps include: Step S1, performing double-sided texturing on a silicon wafer to prepare a clean silicon wafer surface with a low-reflectivity pyramid texturing morphology; Step S2, oxidizing the back side of the silicon wafer from bottom to top to prepare a tunneling SiO2 layer, then depositing a phosphorus-doped N+poly layer from bottom to top on the tunneling SiO2 layer, then depositing a phosphorus-doped N+poly layer from top to bottom on the front side of the silicon wafer, and then depositing a SiO2 mask layer from top to bottom on the phosphorus-doped N+poly layer; Step S3, laser oxidation of the phosphorus-doped N+poly layer on the back of the silicon wafer to prepare a SiO2 mask layer; Step S4, performing alkaline polishing and cleaning on the silicon wafer to remove the tunneling SiO2 layer and the phosphorus-doped N+poly layer in the back area without the SiO2 mask layer and the SiO2 mask layer on the front side, and corrode to expose the back silicon substrate; Step S5, annealing the silicon wafer at high temperature, activating the high-temperature crystallization of amorphous silicon and advancing the doping atoms, so that the front phosphorus-doped N+poly layer and the back phosphorus-doped N+poly layer of the silicon wafer form an N+ front passivation field and an N+ inner expansion layer respectively, and oxidizing the front phosphorus-doped N+poly layer to the SiO2 mask layer at high temperature and then removing it to obtain the FSF layer, and performing pickling treatment; Step S6, depositing an i: a-Si layer from top to bottom on the back of the pickled silicon wafer, performing HPT cleaning on the deposited surface, and then depositing a P: a-Si layer from top to bottom; Step S7, preparing a patterned mask on the amorphous surface of the P region on the back side of the silicon wafer by inkjet printing; Step S8, using ion etching to remove the amorphous silicon in the P region on the back side of the silicon wafer without the patterned mask; Step S9, ultrasonically cleaning the silicon wafer with an organic solvent and removing the patterned mask on the back side; Step S10, performing HPT cleaning on the back side of the silicon wafer and depositing a layer of TCO transparent conductive film; Step S11, performing laser etching on the back side of the silicon wafer to isolate the N region from the P region; Step S12, depositing an aluminum oxide layer on the front side of the silicon wafer, and then depositing a laminated gradient silicon nitride anti-reflection passivation film on the front side and the back side of the silicon wafer respectively; Step S13, using laser grooving, partially opening windows in the laminated gradient silicon nitride anti-reflection passivation film in the N and P regions on the back of the silicon wafer to expose the TCO transparent conductive film, and screen-printing low-temperature metal paste in the grooving area for curing and light injection.

2. The method for preparing a back contact BC solar cell according to claim 1, characterized in that: The reflectivity of the surface of the silicon wafer after polishing in step S1 is 9-12%; The tower base size is 1-3μm and the tower height is 0.5-3μm.

3. The method for preparing a back contact BC solar cell according to claim 1, characterized in that: In the step S2, The thickness of the tunneling SiO2 layer on the back of the silicon wafer is 0.8-1.5nm, the thickness of the phosphorus-doped N+poly layer is 50-300nm, and the doping concentration is 1E+20cm -3 ~2E+21cm -3 : The thickness of the SiO2 mask layer on the front side of the silicon wafer is 10-50nm, the thickness of the phosphorus-doped N+poly layer is 5-10nm, and the doping concentration is 1E+19cm -3 ~1E+20cm -3 .

4. The method for preparing a back contact BC solar cell according to claim 1, characterized in that: In the step S3, The thickness of the SiO2 mask layer on the back of the silicon wafer is 5-15 nm, and the width of the oxidized region is 100-400 μm.

5. The method for preparing a back contact BC solar cell according to claim 1, characterized in that: In the step S4, The reflectivity of the corroded area is 35-45%; The size of the tower base in the corroded area is 5-15 μm; The corrosion depth of the corroded area is 0.5-2μm.

6. The method for preparing a back contact BC solar cell according to claim 1, characterized in that: In the step S5, The temperature for high temperature crystallization advancement is 850-910℃; The time for high temperature crystallization advancement is 30-60min; The temperature of high temperature oxidation is 800-850℃; The high temperature oxidation time is 10-30min.

7. The method for preparing a back contact BC solar cell according to claim 1, characterized in that: In step S6, i: The thickness of the a-Si layer is 2-10 nm; The P:a-Si layer includes a P:a-Si layer and a P-uc-SiO x C y Layering; in The thickness of the P:a-Si layer is 10-20nm, and the doping concentration is 1E+18cm -3 ~5E+18cm -3 : The P-uc-SiO x C y The layer thickness is 20-50nm and the doping concentration is 5E+18cm -3 ~2E+19cm -3 .

8. The method for preparing a back contact BC solar cell according to claim 1, characterized in that: In step S7, The patterned mask prepared from the ink has a width of 100-500 μm and a height of 10-20 μm.

9. The method for preparing a back contact BC solar cell according to claim 1, characterized in that: In the step S11, The laser power is 300-600W, and the etching width is 10-20μm; In step S13, The width of the laser groove is 10-30μm.

10. A back contact BC solar cell structure prepared by the method according to any one of claims 1 to 9, characterized in that: The back N region of the cell is provided with a tunneling SiO2 layer and a phosphorus-doped N+poly layer with high crystallinity and low parasitic absorption; The P region is composed of i: a-Si layer, P: a-Si layer and P-uc-SiO x C y Layering; The front side of the battery is provided with a laminated gradient silicon nitride anti-reflection passivation film.

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