Integrated circuit and method for synchronous rectification control of a bridgeless power factor improvement circuit

Abstract

Integrated circuit and method for synchronous rectification control of a bridgeless power factor improvement circuit. An integrated circuit and method for synchronous rectification control of a bridgeless power factor improvement circuit in a critical mode is provided, in which power factor improvement control and synchronous rectification control are provided in a simple manner. A differential circuit is connected between the main electrodes of an NMOSFET (Q2) of a half-bridge circuit, and the voltage variation between the main electrodes of the NMOSFET (Q2) is detected by the differential circuit, whereby the discharge current period of the reactor (L1) is measured. A predetermined time is subtracted from the measured discharge current period of the reactor (L1), and is assigned to the next on-pulse width of the synchronous rectification switch of the half-bridge circuit. Thereby, the on-pulse signal for synchronous rectification can be reliably detected, and thus control of the power factor improvement circuit with high conversion efficiency can be performed with a small-scale control circuit.

Description

Technical Field

[0001] The present invention relates to a bridgeless power factor improvement circuit having a series circuit of a reactor and a switching element having an applied input voltage, and a synchronous rectifier element connected to the connection point of the reactor and the switching element to convert the input voltage into an output voltage and output it. Background Technology

[0002] In home appliances such as LCD TVs and OLED TVs, power factor correction (PFC) circuits and DC / DC converters are used as units to generate a stable output voltage from an AC input power supply. In particular, bridgeless PFC is employed in the power factor correction circuit based on the viewpoints of high efficiency and small size.

[0003] While achieving high efficiency in PFC also requires low noise, such as Figure 8 , 9 As shown, for the control circuit of bridgeless PFC, Patent Document 1 discloses a control circuit composed of a circuit that is intended to perform zero-voltage switching control.

[0004] Figure 8 Patent document 1 illustrates a totem-pole type PFC circuit that operates using critical mode switching. In this circuit, one switch operates as an active switch forming the primary current path of a MOSFET with a diode or return circuit, and a second totem-pole switch operates as a freewheeling or synchronous rectification switch. The active switch and the synchronous rectification switch alternate their functions each time the input voltage switches between positive and negative. However, when the device voltage of the active switch is greater than zero, the operation of the active switch introduces switching losses. Furthermore, during periods when the device voltage of the active switch is negative, the timing of the active switch switching is later, and considering the additional conduction losses, the efficiency decreases due to the non-zero switching of the active switch.

[0005] Therefore, a control method is used to facilitate zero-voltage switching of the active switch in a bridgeless totem-pole power factor correction converter. The on-time of the synchronous rectifier switch is determined based on the balance of absolute voltage × time in each switching cycle, and is selectively adjusted or offset according to the voltage across the active switch for the next switching cycle. Figure 9 As shown, when the active switch voltage exceeds the threshold, the synchronous rectifier switch conduction time increases; when the active switch voltage is negative, the synchronous rectifier switch conduction time decreases during the next switching cycle.

[0006] like Figure 9As shown, the control device and method in Patent Document 1 delays the on-time of the synchronous rectifier switch when the device voltage of the active switch exceeds a predetermined threshold voltage greater than zero. Furthermore, it adjusts to zero-current switching by selectively shortening the on-time of the synchronous rectifier switch until the negative voltage of the active switch returns to zero. Additionally, if the device voltage of the active switch is between zero and the predetermined threshold voltage, no adjustment is made to the on-time of the synchronous rectifier switch.

[0007] Patent Document 1: JP6529045

[0008] According to Patent Document 1, to facilitate zero-voltage switching of the active switch, the device voltage of the active switch is determined twice for each switch to be either above a predetermined threshold or below 0V. Based on this determination result, the offset time of the next synchronous rectifier switch on-time is selected. However, this requires expensive control circuitry, such as a CPU with high processing power and fast processing speed, for the determination operation of determining twice for each switch and for selecting the device voltage of the active switch based on the two thresholds.

[0009] In particular, when used in power factor improvement circuits employing interleave methods that facilitate high-power, low-profile installation in large LCD / OLED TVs, two of the aforementioned detection and control circuits are required, which is more expensive.

[0010] Here, as a simple method, it is possible to control the active switch to turn on and off only during the conduction time of the next cycle based on the above calculations without detecting the device voltage near zero of the active switch, thus sacrificing some losses of the active switch. However, in methods for detecting input and output voltages, since it is common practice to make the voltage detection circuit high impedance to reduce circuit losses, it is susceptible to noise.

[0011] For example, such as Figure 4 As shown, compared to the original timing A (during period a) when the active switch is turned off, timing D (d during period d) occurs due to erroneous operation caused by noise. During this time, a larger amount of negative current flows in the reactor current IL, increasing the losses of the synchronous rectifier switch. This negative current is regenerated from the output smoothing capacitor to the AC input power supply side. More power, including this regenerated power, must be supplied to the output side through the next switch, further increasing the losses in the power factor correction circuit. In the worst case, this can sometimes lead to damage to the active switch, synchronous rectifier switch, etc. Summary of the Invention

[0012] In view of the above problems, the objective of the present invention is to provide control in the synchronous rectification control of a bridgeless power factor improvement circuit in critical mode using a simple method without input voltage detection.

[0013] To address the aforementioned issues, an integrated circuit for synchronous rectification control of a bridgeless power factor improvement circuit performing critical mode is provided, characterized in that...

[0014] In the bridgeless power factor improvement circuit of the critical mode,

[0015] An output smoothing capacitor and a half-bridge circuit composed of the first NMOSFET and the second NMOSFET are connected between the two terminals of the series circuit of the first diode and the second diode.

[0016] One terminal of the AC power supply is connected to the junction of the first diode and the second diode.

[0017] The other terminal of the AC power supply is connected to one terminal of the first reactor, and the other terminal of the first reactor is connected to the connection point of the first NMOSFET and the second NMOSFET in the half-bridge circuit.

[0018] A differentiating circuit consisting of a capacitor and a resistor is connected between the main electrodes of the second NMOSFET in the half-bridge circuit.

[0019] The integrated circuit detects the output voltage of the output smoothing capacitor and compares it with a predetermined reference voltage. Based on the error signal between the output voltage and the predetermined reference voltage, it controls the conduction and disconnection of the half-bridge circuit.

[0020] For the conduction time of the synchronous rectifier switch of the half-bridge circuit, the period from the moment the active switch of the half-bridge circuit is turned off to the time until the differential signal generated by the differentiating circuit is output is measured, and the time obtained by subtracting a predetermined time from the measured time is allocated to the next conduction time of the synchronous rectifier switch.

[0021] Furthermore, an integrated circuit for synchronous rectification control of a bridgeless / interleaved power factor improvement circuit performing critical mode is characterized by,

[0022] In the bridgeless / interleaved power factor improvement circuit of the critical mode,

[0023] An output smoothing capacitor is connected between the two terminals of the series circuit of the first and second diodes. A first half-bridge circuit consisting of the first and second NMOSFETs is used as the main control side, and a second half-bridge circuit consisting of the third and fourth NMOSFETs is used as the controlled side.

[0024] One terminal of the AC power supply is connected to the junction of the first diode and the second diode.

[0025] The other terminal of the AC power supply is connected to one terminal of the first reactor and the second reactor. The other terminal of the first reactor is connected to the connection point of the first NMOSFET and the second NMOSFET of the first half-bridge circuit. The other terminal of the second reactor is connected to the connection point of the third NMOSFET and the fourth NMOSFET of the second half-bridge circuit.

[0026] A differentiating circuit consisting of a capacitor and a resistor is connected between the main electrodes of the second NMOSFET in the first half-bridge circuit.

[0027] The integrated circuit detects the output voltage of the output smoothing capacitor and compares it with a predetermined reference voltage. Based on the error signal between the output voltage and the predetermined reference voltage, it controls the conduction and disconnection of the first half-bridge circuit and the second half-bridge circuit.

[0028] For the conduction time of the synchronous rectifier switch of the first half-bridge circuit, the period from the moment the active switch of the first half-bridge circuit is turned off to the time until the differential signal generated by the differentiating circuit is output is measured, and then allocated to the next conduction time of the synchronous rectifier switch of the second half-bridge circuit.

[0029] According to the present invention, in the bridgeless power factor improvement circuit in critical mode, the on-time of the synchronous rectifier switch is set to be shorter than the original value, and the voltage change of the active switch is detected, thereby accurately detecting the period of synchronous rectification. This enables the control of a power factor improvement circuit with high conversion efficiency with a small-scale control circuit (CPU).

[0030] Furthermore, the use of a differentiating circuit in the detection of voltage changes in active switches reduces impedance without increasing losses, and enables the suppression of erroneous actions due to noise in a simple way without input voltage detection.

[0031] Furthermore, in the bridgeless / interleaved power factor improvement circuit in critical mode, the on-time of the synchronous rectifier switch on the master side is set to be shorter than the original value, and the voltage change of the active switch on the master side is detected. Thus, the accurate synchronous rectification period is detected, and this detection time is applied to the on-time of the synchronous rectifier switch on the slave side. As a result, the interleaved power factor improvement circuit with high conversion efficiency can be controlled with a small-scale control circuit (CPU). Attached Figure Description

[0032] Figure 1This is a structural diagram illustrating the bridgeless power factor improvement circuit of Embodiment 1 of the present invention.

[0033] Figure 2 It is shown Figure 1 The diagram shows the action waveforms of each part in Embodiment 1 of the present invention.

[0034] Figure 3 This is a diagram showing the ideal waveform of the operating waveform of the bridgeless power factor improvement circuit according to Embodiment 1 of the present invention.

[0035] Figure 4 This is a waveform diagram showing the operation waveform of a bridgeless power factor improvement circuit with a delay in the detection timing of the conduction signal.

[0036] Figure 5 This is a structural diagram illustrating the interleaved / bridgeless power factor improvement circuit of Embodiment 2 of the present invention.

[0037] Figure 6 It is shown Figure 5 The diagram shows the action waveforms of each part in Embodiment 2 of the present invention.

[0038] Figure 7 This is a structural diagram illustrating the interleaved / bridgeless power factor improvement circuit of Embodiment 3 of the present invention.

[0039] Figure 8 This is a circuit structure diagram illustrating existing technology.

[0040] Figure 9 It is shown Figure 8 The diagram shows the operating principle of the prior art control.

[0041] Label Explanation

[0042] 1: Bridgeless power factor improvement circuit in critical mode; 1a, 1b: Bridgeless / interleaved power factor improvement circuit in critical mode; AC: AC input power supply; A / D: AD converter; C1, C3: Capacitors; C2: Output smoothing capacitor; CAL1: Arithmetic unit; Cont1, Cont1a, Cont1b: Integrated circuits; CD1: Constant unit; CP1: Comparator; D1, D2: Diodes; ED1, ED2: Switches; L1, L2: Reactors; Load: Load; OSC1, OSC2: Oscillators; PD1, PD2: Phase detectors; Q1~Q6: N-channel MOSFETs; R1~R7: Resistors; SW1, SW2, SW3: Switches; Timer: Timer; Vrm, Vrp: Reference voltages. Detailed Implementation

[0043] (Implementation Method 1)

[0044] Figure 1 Implementation method 1 is a bridgeless power factor improvement circuit in critical mode.

[0045] Figure 1 Implementation method 1 consists of diodes D1 and D2, a first reactor L1, N-channel MOSFETs Q1 to Q2, resistors R1 and capacitor C3 constituting a differentiating circuit, output smoothing capacitor C2, output voltage detection resistors R2 and R3, and an integrated circuit Cont1 with various functions.

[0046] In the bridgeless power factor improvement circuit 1 of the present invention, a noise reduction capacitor C1 is connected between the two ends of the L and N terminals of the AC power supply AC, and one terminal of the first reactor L1 is connected to the L terminal side.

[0047] The N-terminal of the AC power supply is connected to the connection point of the series circuit of diodes D1 and D2. The cathode of diode D1 is connected to the positive terminal of the output voltage, and the anode of diode D2 is connected to the negative terminal of the output voltage, which becomes GND.

[0048] A half-bridge circuit of N-channel MOSFETs Q1 and Q2, and series resistor circuits R2 and R3 for detecting the output voltage are connected between the two terminals of the series circuit of diodes D1 and D2.

[0049] The other terminal of the first reactor L1 is connected to the connection point of the N-channel MOSFETs Q1 and Q2.

[0050] In addition, a capacitor C3 and a resistor R1 with a differentiating circuit are connected between the connection point of N-channel MOSFETs Q1 and Q2 and the anode of diode D2, i.e., GND.

[0051] The integrated circuit Cont1 is connected to the L terminal and Vin terminal of the AC power supply, and is also connected to the gate terminal and H01 and LO1 terminals of the N-channel MOSFETs Q1 to Q2, respectively. It is connected to the connection point and RC terminal of the capacitor C3 and resistor R1 of the differentiating circuit, as well as the connection point and VO terminal of the series resistor circuit R2 and R3 used to detect the output voltage.

[0052] Next, refer to Figure 1 and Figure 2 The overall operation of the bridgeless power factor improvement circuit 1 according to the embodiment of the present invention is explained.

[0053] The structure of the embodiment of the present invention consists of an inductor L1, N-channel MOSFETs Q1 and Q2, a capacitor C3 and a resistor R1 of a differentiating circuit.

[0054] Either of the N-channel MOSFETs Q1 and Q2 operates as an active switch or a synchronous rectifier switch depending on the voltage polarity of the L and N terminals of the AC power supply. For example, when the L terminal is positive and the N terminal is negative, N-channel MOSFET Q2 becomes an active switch, and N-channel MOSFET Q1 becomes a synchronous rectifier switch, with diode D2 conducting and diode D1 cut off. Therefore, when the L terminal is negative and the N terminal is positive, the active switch and synchronous rectifier switch functions alternately, with diode D1 conducting and diode D2 cut off.

[0055] Next, the structure and function of integrated circuit Cont1 will be explained.

[0056] First, the A / D converter of integrated circuit Cont1 detects the voltage divider signal of the series resistor circuit R2 and R3, which serves as the output voltage signal, and sends its data to the arithmetic unit CAL1.

[0057] The arithmetic unit CAL1 compares the voltage divider signal with a specified reference voltage (not shown), performs filtering on the error signal between the voltage divider signal and the specified reference voltage, and generates an ON (conduction) time signal. The ON time signal is sent to the oscillator OSC1.

[0058] The oscillator OSC1 generates pulses for active switching and synchronous rectifier switching based on the ON time (conduction time) and OFF time (disconnection time).

[0059] The switch SW1 switches the output of the active switching pulse and the synchronous rectification switching pulse sent from the oscillator OSC1 to the N-channel MOSFETs Q1 and Q2 based on the output signal of the phase detector PD1.

[0060] Here, the phase detector PD1 detects the voltage at the L terminal of the AC power supply to determine the polarity of the positive or negative terminal, and outputs a signal corresponding to the input polarity to the switch SW1, the edge detector ED2, and the reference voltage Vrm.

[0061] Next, the voltage waveform at the connection point of capacitor C3 and resistor R1 in the differentiating circuit is input to the RC terminal and then via resistor Rc1 to the non-inverting terminal of comparator CP1. Resistor Rc2 and reference voltage Vrp are connected between this non-inverting terminal and GND, and the reference voltage Vrm is connected to the inverting terminal. Thus, the input terminals of comparator CP1 are superimposed with DC signals, detecting the polarity of the signal from the differentiating circuit and sending a signal to the edge detector ED2.

[0062] Here, the reference voltage Vrm is switched to a value H, which is higher than the reference voltage Vr, or a value L, which is lower than the reference voltage Vr, based on the output signal of the phase detector PD1. For example, when the voltage at the L terminal of the AC power supply is positive, the reference voltage Vrm is switched to the H side; when it is negative, the reference voltage Vrm is switched to the L side. Thus, the voltage waveform of the differentiating circuit can detect the polarity of the charging or discharging direction of capacitor C3 via the RC terminal.

[0063] Furthermore, the reason for switching the reference voltage Vrm based on the voltage polarity of the L terminal of the AC power supply is that the NMOSFET Q2, connected in parallel with the differentiating circuit, switches between an active switch and a synchronous rectifier switch. In the active switch mode, the timing of the discharge of capacitor C3 in the differentiating circuit is detected, thereby detecting when the current flowing through reactor L1 becomes zero. Similarly, in the synchronous rectifier switch mode, the timing of the charging of capacitor C3 in the differentiating circuit is detected, thereby detecting when the current flowing through reactor L1 becomes zero.

[0064] Edge detector ED2 processes the signal from comparator CP1 into a trigger pulse and sends it as a stop signal to the timer. At this time, depending on the voltage polarity of the L terminal of the AC power supply, the reference voltage Vrm becomes either the H side or the L side. Therefore, the output of comparator CP1 becomes either a falling edge signal (H→L) or a rising edge signal (L→H). Edge detector ED2 switches between rising and falling edges based on the signal from phase detector PD1, thereby accurately detecting the signal from comparator CP1.

[0065] In addition, the timer is started on the falling edge of the active switching pulse of the oscillator OSC1.

[0066] In addition, the timer can also be started using the rising edge of the synchronous rectifier switch pulse of the oscillator OSC1.

[0067] The timer uses two signals—a start signal from the oscillator OSC1 and a stop signal from the edge detector ED2—to measure the reset time of the current flowing through the reactor L1. The timer's measurement data is then sent to the oscillator OSC1 as a slightly shorter value obtained by subtracting a predetermined constant from the constant converter CD1. In other words, the timer's measurement data forms the basis for the on-time data of the synchronous rectifier switch.

[0068] Next, the operation of the power factor improvement circuit will be explained.

[0069] exist Figure 1 In the above, we assume that terminal L is the positive terminal and terminal N is the negative terminal. Figure 2 The waveform is also represented under the same conditions.

[0070] The A / D converter of integrated circuit Cont1 detects the voltage divider signal of the series resistor circuit R2 and R3 as the output voltage signal, and sends its data to the arithmetic unit CAL1.

[0071] The arithmetic logic unit (CAL1) compares the voltage divider signal with a specified reference voltage (not shown), performs filtering on the error signal between the voltage divider signal and the specified reference voltage, and generates a conduction time signal. This conduction time signal is sent to the oscillator OSC1. The oscillator OSC1 sets up an active switch signal based on the conduction time signal and outputs it. Based on the OFF time 1 from the constant CD1, it sends a synchronous rectification switch signal to the switch SW1. The switch SW1, based on the output signal of the phase detector PD1, outputs an active switch turn-on pulse signal Vgs_Q2 to the NMOSFET Q2 and a synchronous rectification switch pulse signal Vgs_Q1 to the NMOSFET Q1.

[0072] With the NMOSFET Q2 turned on, the current IL1 flowing through the reactor L1 is determined by the input voltage applied to the reactor, i.e., the rectified voltage of the AC power supply AC, and the turn-on pulse signal Vgs_Q2, which determines the peak current.

[0073] Here, the transient response is slightly slower, but by keeping the pulse width of the turn-on pulse signal Vgs_Q2 constant for more than half a cycle of the commercial frequency of the AC power supply, the peak current flowing for the current IL1 flowing through the reactor L1 corresponds to the input voltage. That is, the peak current waveform is similar to the input voltage.

[0074] Furthermore, based on the detection by the differentiating circuit Figure 2 The V_RC waveform, obtained by measuring the drain-source voltage of Vds_Q2, is used. At time t5, comparator CP1 generates a pulse CP1out, which sends a stop signal to timer via edge detector ED2. Then, after sending an OFF time of 1 from timer to oscillator OSC1 via constant CD1, the active switch is turned on / triggered again at time t6. Regarding time t5, the point at which the drain-source voltage of the active switch Vds_Q2 begins to decrease is the point at which the current IL1 flowing through reactor L1 becomes zero.

[0075] In addition, there is a delay period from the end of the pulse CP1out of comparator CP1 until the next turn-on of the active switch. However, since the regenerative current of reactor L1 flows into the AC input power supply side during this period, the reactor current IL1 will not be interrupted.

[0076] Therefore, in critical mode, the conduction control of the reactor current IL1 flowing through reactor L1 can be achieved. Since the peak current of reactor current IL1, as previously described, is similar to the input voltage, the average value of reactor current IL1, i.e., the waveform of the input current of AC power supply AC, becomes similar to the input voltage, thus improving the power factor. This yields values ​​that also fully meet the higher harmonic standards.

[0077] Next, approximately simultaneously with the turn-off time t3 of the active switch's turn-on pulse signal Vgs_Q2, the synchronous rectifier switch's turn-on pulse signal Vgs_Q1 is output, turning on the synchronous rectifier switch's N-channel MOSFET Q1. Consequently, the reactor current IL1 of reactor L1 flows through the output smoothing capacitor C2 via the synchronous rectifier switch (or the parasitic diode of the N-channel MOSFET Q1).

[0078] Here, the conduction period of the synchronous rectifier switch N-channel MOSFET Q1 is longer than the release period. Figure 3 The period a during which the energy stored in reactor L1 is shortened. Figure 2 The illustrated period c is the amount of time. This is the OFF time 1, which will be the shortened data obtained by subtracting the specified constant (corresponding to period c) from the data of OFF time 2 generated by the timer by the constant CD1 and sent to the oscillator OSC1.

[0079] Originally, the synchronous rectifier switch N-channel MOSFET Q1 preferably operates under conduction for the entire period of a, but if Figure 4 As shown, due to erroneous operation caused by noise or drastic changes in input voltage, the conduction period of the synchronous rectifier switch may be prolonged compared to period a.

[0080] Furthermore, the duration of 'a' is measured each time by a timer and used as a reference value for the next turn-on pulse time of the synchronous rectifier switch N-channel MOSFET Q1. Figure 2 (Times t9~t10).

[0081] However, based on the reasons mentioned above, such as Figure 2 As shown, the turn-on pulse signal Vgs_Q1 of the synchronous rectifier switch N-channel MOSFET Q1 generates a period b (time t3~t4) that is shorter than the period of a by a specified time c. The period of a can be reliably measured by the differentiating circuit.

[0082] Here, at the specified time c (times t4 to t5), the synchronous rectifier switch is in the off state. However, at this time, the reactor current IL1 flows through the parasitic diode of the synchronous rectifier switch, i.e., the N-channel MOSFET Q1. Therefore, a loss occurs due to the forward voltage of the parasitic diode, but the current value of the reactor current IL1 drops to zero amperes, so it does not become a significant loss.

[0083] In addition, such as Figure 3 As shown, a predetermined dead time is set between the turn-on pulse signal Vgs_Q2 of the active switch N-channel MOSFET Q2 and the turn-on pulse signal Vgs_Q1 of the synchronous rectifier switch N-channel MOSFET Q1, so that the active switch N-channel MOSFET Q2 and the synchronous rectifier switch N-channel MOSFET Q1 are simultaneously turned on and not short-circuited.

[0084] The above, in Figure 2 The waveform was displayed under the condition that the L terminal of the AC power supply is positive and the N terminal is negative. However, when the polarity of the L terminal and the N terminal is reversed, according to the signal of the phase detector PD1, the active switch is switched to Q1 and the synchronous rectifier switch is switched to Q2 via the switches SW1 and SW2 to perform the same operation.

[0085] Furthermore, since the V_RC waveform of the differentiating circuit is reversed from the negative waveform to the positive waveform, the reference voltage Vrm is switched to a value L lower than the reference voltage Vr in order to obtain the CP1out pulse, based on the signal of the phase detector PD1.

[0086] (Implementation Method 2)

[0087] Figure 5 Implementation method 2 is a bridgeless / interleaved power factor improvement circuit in critical mode.

[0088] Figure 5 Implementation method 2 consists of diodes D1 and D2, first reactor L1, second reactor L2, N-channel MOSFETs Q1 to Q4, resistor R1 and capacitor C3 constituting a differentiating circuit, output smoothing capacitor C2, output voltage detection resistors R2 and R3, and an integrated circuit Cont1a with various functions.

[0089] In the critical mode bridgeless / interleaved power factor improvement circuit 1a of the present invention, a noise reduction capacitor C1 is connected between the two ends of the L and N terminals of the AC power supply AC, and one terminal of the first reactor L1 and the second reactor L2 is connected to the L terminal side.

[0090] The N-terminal of the AC power supply is connected to the connection point of the series circuit of diodes D1 and D2. The cathode of diode D1 is connected to the positive terminal of the output voltage, and the anode of diode D2 is connected to the negative terminal of the output voltage, which becomes GND.

[0091] A half-bridge circuit consisting of N-channel MOSFETs Q1, Q2, Q3, and Q4, and series resistors R2 and R3 for detecting the output voltage are connected between the two terminals of the series circuit of diodes D1 and D2.

[0092] The other terminal of the first reactor L1 is connected to the connection point of N-channel MOSFETs Q1 and Q2, and the other terminal of the second reactor L2 is connected to the connection point of N-channel MOSFETs Q3 and Q4.

[0093] In addition, a capacitor C3 and a resistor R1 with a differentiating circuit are connected between the connection point of N-channel MOSFETs Q1 and Q2 and the anode of diode D2, i.e., GND.

[0094] The integrated circuit Cont1a is connected to the L terminal and Vin terminal of the AC power supply, the gate terminal and H01, LO1, HO2, and LO2 terminals of the N-channel MOSFETs Q1 to Q4, respectively, and is connected to the connection point and RC terminal of the capacitor C3 and resistor R1 of the differentiating circuit, as well as the connection point and VO terminal of the series resistor circuit R2 and R3 used to detect the output voltage.

[0095] Next, refer to Figure 5 and Figure 6 The overall operation of the bridgeless / interleaved power factor improvement circuit 1a according to an embodiment of the present invention is explained.

[0096] The structure of this invention comprises a main control circuit and a controlled circuit. The main control circuit consists of an inductor L1, N-channel MOSFETs Q1 and Q2, a capacitor C3 and a resistor R1 in the differentiating circuit, and the controlled circuit consists of an inductor L2, N-channel MOSFETs Q3 and Q4. The phase difference between the switching cycles of the main control circuit and the controlled circuit is set to 180 degrees, and the on / off control is performed by an integrated circuit Cont1a, which controls the switching to reduce the output ripple voltage.

[0097] The N-channel MOSFETs Q1, Q2, or Q3, Q4 operate as either active switches or synchronous rectifier switches depending on the voltage polarity of the L and N terminals of the AC power supply. For example, when the L terminal is positive and the N terminal is negative, N-channel MOSFETs Q2 and Q4 act as active switches, while N-channel MOSFETs Q1 and Q3 act as synchronous rectifier switches, with diode D2 conducting and diode D1 cut off. Therefore, when the L terminal is negative and the N terminal is positive, the active switch and synchronous rectifier switch functions alternately, with diode D1 conducting and diode D2 cut off.

[0098] Next, the structure and function of the integrated circuit Cont1a will be explained.

[0099] First, the A / D converter of integrated circuit Cont1a detects the voltage divider signal of the series resistor circuit R2 and R3, which serves as the output voltage signal, and sends its data to the arithmetic unit CAL1.

[0100] The arithmetic logic unit (CAL1) compares the voltage divider signal with a specified reference voltage (not shown), performs filtering on the error signal between the voltage divider signal and the specified reference voltage, and generates an ON time signal. The ON time signal is sent to oscillators OSC1 and OSC2. Oscillator OSC1 is used in the main control circuit (N-channel MOSFETs Q1 and Q2), and oscillator OSC2 is used in the controlled circuit (N-channel MOSFETs Q3 and Q4).

[0101] Oscillator OSC1 generates active switching pulses and synchronous rectifier switching pulses for the main control circuit based on the ON and OFF times. Additionally, it outputs trigger pulses to oscillator OSC2.

[0102] Oscillator OSC2 generates active switching pulses and synchronous rectifier switching pulses for the controlled circuit based on the ON and OFF times. Furthermore, based on the trigger pulse received from oscillator OSC1, the phase of the output pulse is delayed by 180 degrees compared to oscillator OSC1.

[0103] Switch SW1 switches between the active switching pulses and synchronous rectification switching pulses sent from oscillator OSC1 to the N-channel MOSFETs Q1 and Q2, based on the output signal of phase detector PD1. Similarly, switch SW2 switches between the active switching pulses and synchronous rectification switching pulses sent from oscillator OSC2 to the N-channel MOSFETs Q3 and Q4, based on the output signal of phase detector PD1.

[0104] Here, the phase detector PD1 detects the voltage at the L terminal of the AC power supply to determine the polarity of the positive or negative terminal, and outputs a signal corresponding to the input polarity to the switch SW1, SW2, edge detector ED2, and reference voltage Vrm.

[0105] Next, the voltage waveform at the connection point of capacitor C3 and resistor R1 in the differentiating circuit is input to the RC terminal and then via resistor Rc1 to the non-inverting terminal of comparator CP1. Resistor Rc2 and reference voltage Vrp are connected between this non-inverting terminal and GND, and the reference voltage Vrm is connected to the inverting terminal. Thus, the input terminals of comparator CP1 are superimposed with DC signals, detecting the polarity of the signal from the differentiating circuit and sending a signal to the edge detector ED2.

[0106] Here, the reference voltage Vrm is switched to a value H, which is higher than the reference voltage Vr, or a value L, which is lower than the reference voltage Vr, based on the output signal of the phase detector PD1. For example, when the voltage at the L terminal of the AC power supply is positive, the reference voltage Vrm is switched to the H side; when it is negative, the reference voltage Vrm is switched to the L side. Thus, the voltage waveform of the differentiating circuit can detect the polarity of the charging or discharging direction of capacitor C3 via the RC terminal.

[0107] Furthermore, the reason for switching the reference voltage Vrm based on the voltage polarity of the L terminal of the AC power supply is that the NMOSFET Q2, connected in parallel with the differentiating circuit, switches between an active switch and a synchronous rectifier switch. In the active switch mode, the timing of the discharge of capacitor C3 in the differentiating circuit is detected, thereby detecting when the current flowing through reactor L1 becomes zero. Similarly, in the synchronous rectifier switch mode, the timing of the charging of capacitor C3 in the differentiating circuit is detected, thereby detecting when the current flowing through reactor L1 becomes zero.

[0108] Edge detector ED2 processes the signal from comparator CP1 into a trigger pulse and sends it as a stop signal to the timer. At this time, depending on the voltage polarity of the L terminal of the AC power supply, the reference voltage Vrm becomes either the H side or the L side. Therefore, the output of comparator CP1 becomes either a falling edge signal (H→L) or a rising edge signal (L→H). Edge detector ED2 switches between rising and falling edges based on the signal from phase detector PD1, thereby accurately detecting the signal from comparator CP1.

[0109] In addition, the timer is started on the falling edge of the active switching pulse of the oscillator OSC1.

[0110] In addition, the timer can also be started using the rising edge of the synchronous rectifier switch pulse of the oscillator OSC1.

[0111] The timer uses a start signal from oscillator OSC1 and a stop signal from edge detector ED2 to measure the reset time of the current flowing through reactor L1. The timer's measurement data is sent directly to oscillator OSC2, while oscillator OSC1 receives a slightly shorter value obtained by subtracting a specified constant from constant circuit CD1. In other words, the timer's measurement data forms the basis for the on-time data of the synchronous rectifier switch.

[0112] Next, based on the operation of the main control circuit, the operation of the bridgeless / interleaved power factor improvement circuit 1a in critical mode will be explained.

[0113] exist Figure 5 In the above, we assume that terminal L is the positive terminal and terminal N is the negative terminal. Figure 6 The waveform is also represented under the same conditions.

[0114] The A / D converter of integrated circuit Cont1a detects the voltage divider signal of the series resistor circuit R2 and R3 as the output voltage signal, and sends its data to the arithmetic unit CAL1.

[0115] The arithmetic logic unit (CAL1) compares the voltage divider signal with a specified reference voltage (not shown), performs filtering on the error signal between the voltage divider signal and the specified reference voltage, and generates a conduction time signal. This conduction time signal is sent to the oscillator OSC1. The oscillator OSC1 sets up an active switch signal based on the conduction time signal and outputs it. Based on the OFF time 1 from the constant CD1, it sends a synchronous rectification switch signal to the switch SW1. The switch SW1, based on the output signal of the phase detector PD1, outputs an active switch turn-on pulse signal Vgs_Q2 to the NMOSFET Q2 and a synchronous rectification switch pulse signal Vgs_Q1 to the NMOSFET Q1.

[0116] With the NMOSFET Q2 turned on, the current IL1 flowing through the reactor L1 is determined by the input voltage applied to the reactor, i.e., the rectified voltage of the AC power supply AC, and the turn-on pulse signal Vgs_Q2, which determines the peak current.

[0117] Here, the transient response is slightly slower, but by keeping the pulse width of the turn-on pulse signal Vgs_Q2 constant for more than half a cycle of the commercial frequency of the AC power supply, the peak current flowing for the current IL1 flowing through the reactor L1 corresponds to the input voltage. That is, the peak current waveform is similar to the input voltage.

[0118] Furthermore, based on the detection by the differentiating circuit Figure 6 The V_RC waveform, obtained by measuring the drain-source voltage of Vds_Q2, is used to generate a pulse CP1out at time t5, which sends a stop signal to the timer via edge detector ED2. Then, after sending an OFF time of 1 from the timer to the oscillator OSC1 via constant CD1, the active switch is turned on / triggered again at time t6. Regarding time t5, the point at which the drain-source voltage of the active switch Vds_Q2 begins to decrease is the point at which the reactor current IL1 flowing through reactor L1 becomes zero.

[0119] In addition, there is a delay period from the end of the pulse CP1out of comparator CP1 until the next turn-on of the active switch. However, since the regenerative current of reactor L1 flows into the AC input power supply side during this period, the reactor current IL1 will not be interrupted.

[0120] Therefore, it is possible to control the conduction of the current IL1 flowing through the reactor L1 in critical mode. Since the peak current of the reactor current IL1, as described earlier, is similar to the input voltage, the average value of the reactor current IL1, i.e., the waveform of the input current of the AC power supply AC, becomes similar to the input voltage, thus improving the power factor. This yields values ​​that also fully meet the higher harmonic standards.

[0121] Next, approximately simultaneously with the turn-off time t3 of the active switch's turn-on pulse signal Vgs_Q2, the synchronous rectifier switch's turn-on pulse signal Vgs_Q1 is output, turning on the synchronous rectifier switch's N-channel MOSFET Q1. Consequently, the current IL1 of reactor L1 flows through the output smoothing capacitor C2 via the synchronous rectifier switch (or the parasitic diode of the N-channel MOSFET Q1).

[0122] Here, the conduction period of the synchronous rectifier switch N-channel MOSFET Q1 is longer than the release period. Figure 3 The energy stored in reactor L1 during period a is shortened by the amount of period c. This shortened period c is the OFF time 1 obtained by constant CD1 from the data of OFF time 2 generated by timer, minus the specified constant (corresponding to period c), and sent to oscillator OSC1.

[0123] Originally, the synchronous rectifier switch N-channel MOSFET Q1 preferably operates under conduction for the entire period of a, but if Figure 4 As shown, due to erroneous operation caused by noise or drastic changes in input voltage, the conduction period of the synchronous rectifier switch may be prolonged compared to period a.

[0124] Furthermore, the period of 'a' is measured each time by a timer and is allocated to the conduction pulse time of the synchronous rectifier switch N-channel MOSFET Q3 in the controlled circuit that follows the switching of the master control circuit. Figure 6 (Times t7~t8).

[0125] That is, it can be used flexibly as a reference value for the next conduction period of the synchronous rectifier switch.

[0126] Based on the above reasons, such as Figure 6 As shown, the turn-on pulse signal Vgs_Q1 of the synchronous rectifier switch N-channel MOSFET Q1 generates a period b (time t3~t4) that is shorter than the period of a by a specified time c. The period of a can be reliably measured by the differentiating circuit.

[0127] Here, at the specified time c (times t4 to t5), the synchronous rectifier switch of the main control circuit is in the open state. However, at this time, the reactor current IL1 flows through the parasitic diode of the synchronous rectifier switch, i.e., the N-channel MOSFET Q1. Therefore, a loss occurs due to the forward voltage of the parasitic diode, but the current value of the reactor current IL1 drops to zero amperes, so it will not become a significant loss.

[0128] In addition, such as Figure 3 As shown, a predetermined dead time is set between the turn-on pulse signal Vgs_Q2 of the active switch N-channel MOSFET Q2 and the turn-on pulse signal Vgs_Q1 of the synchronous rectifier switch N-channel MOSFET Q1, so that the active switch N-channel MOSFET Q2 and the synchronous rectifier switch N-channel MOSFET Q1 are simultaneously turned on without short-circuiting.

[0129] In the controlled circuit, oscillator OSC2 generates the turn-on pulse signal Vgs_Q4 of the active switch N-channel MOSFET Q4, which has a pulse signal of the same width as the turn-on pulse signal Vgs_Q2 of the active switch in the main control circuit, with a phase difference of 180 degrees relative to Vgs_Q2. This signal is then transmitted via switch SW2. (Times t2 to t7 correspond to times t1 to t3.)

[0130] Furthermore, the synchronous rectifier switch's turn-on pulse signal Vgs_Q3 is generated by the oscillator OSC2 for a period 'a' from the moment 't7' of the active switch Q4's turn-off pulse signal Vgs_Q4, separated by a dead time, up to time t8. During this period 'a', the OFF time 2 of the aforementioned timer signal is directly input to the oscillator OSC2 and transmitted via the switch SW2 as the synchronous rectifier switch's turn-on pulse signal Vgs_Q3.

[0131] The above, in Figure 6 The waveform was displayed under the condition that the L terminal side of the AC power supply is positive and the N terminal side is negative. However, when the polarity of the L terminal and the N terminal is reversed, according to the signal of the phase detector PD1, the active switch is switched to Q1 and Q3 via the switchers SW1 and SW2, and the synchronous rectifier switch is switched to Q2 and Q4 to perform the same action.

[0132] Furthermore, since the V_RC waveform of the differentiating circuit is reversed from the negative waveform to the positive waveform, the reference voltage Vrm is switched to a value L lower than the reference voltage Vr in order to obtain the CP1out pulse, based on the signal of the phase detector PD1.

[0133] (Implementation Method 3)

[0134] Figure 7 The illustrated implementation method 3 and Figure 5 The difference in Embodiment 2 is that diodes D1 and D2 are replaced with N-channel MOSFETs Q5 and Q6. Otherwise, the structure is the same as in Embodiment 2.

[0135] In detail, this involves replacing the diode with an N-channel MOSFET, adding resistors R4 to R6 to detect the positive and negative polarities of the L and N terminals of the AC input power supply, and changing the integrated circuit Cont1a to integrated circuit Cont1b.

[0136] In embodiment 3, diodes D1 and D2 are replaced by N-channel MOSFETs Q5 and Q6 as switches for synchronous rectification at the commercial frequency. Here, integrated circuit Cont1a outputs drive signals AO1 and AO2 as follows: when the L terminal of the AC input power supply is positive, N-channel MOSFET Q5 is turned off and N-channel MOSFET Q6 is turned on; when the N terminal of the AC input power supply is positive, N-channel MOSFET Q6 is turned off and N-channel MOSFET Q5 is turned on.

[0137] In the AC input power supply polarity detection, resistors R4 and R5 are connected in series between the L terminal and GND, and resistors R6 and R7 are connected in series between the N terminal and GND. The connection point of each series resistor is connected to the phase detector PD2 of the integrated circuit Cont1b. The phase detector PD2 detects the polarity of the AC input power supply by comparing it with an internal reference voltage (not shown) or with the voltage at the connection point of the series resistors.

[0138] Although the circuit components used to detect the positive and negative polarities of the L and N terminals of the AC input power supply are increased, the forward voltage loss of diodes D1 and D2 is replaced by the on-resistance loss of the N-channel MOSFET, which can significantly reduce the loss. As a result, under high load power, it has the effect of improving the efficiency of the power factor improvement circuit and eliminating the need for heat sinks for diodes D1 and D2.

[0139] The embodiments of the present invention have been described above. However, the above embodiments are merely illustrative examples to concretize the technical concept of the present invention and do not limit the various structures and combinations to the above content. The present invention can be modified and implemented in various ways without departing from its spirit.

[0140] For example, the phase detectors PD1 and PD2 in embodiments 2 and 3 perform voltage detection, but it can also be current detection or detection based on capacitor coupling, etc.

[0141] Industrial availability

[0142] In summary, the integrated circuit for synchronous rectification control of the power factor improvement circuit of the present invention is preferably used in a bridgeless power factor improvement circuit in critical mode and a bridgeless / interleaved power factor improvement circuit in critical mode. Therefore, it can be used in power supplies for LCD, OLED TV devices, etc., that utilize this integrated circuit.

Claims

1. An integrated circuit for controlling a bridgeless power factor correction circuit in critical mode, the integrated circuit performing synchronous rectification control of the bridgeless power factor correction circuit in critical mode, characterized in that, In the bridgeless power factor improvement circuit of the critical mode, An output smoothing capacitor and a half-bridge circuit composed of the first NMOSFET and the second NMOSFET are connected between the two terminals of the series circuit of the first diode and the second diode. One terminal of the AC power supply is connected to the junction of the first diode and the second diode. The other terminal of the AC power supply is connected to one terminal of the first reactor, and the other terminal of the first reactor is connected to the connection point of the first NMOSFET and the second NMOSFET in the half-bridge circuit. A differentiating circuit consisting of a capacitor and a resistor is connected between the main electrodes of the second NMOSFET in the half-bridge circuit. The integrated circuit detects the output voltage of the output smoothing capacitor and compares it with a predetermined reference voltage. Based on the error signal between the output voltage and the predetermined reference voltage, it controls the conduction and disconnection of the half-bridge circuit. For the conduction time of the synchronous rectifier switch of the half-bridge circuit, the period from the moment the active switch of the half-bridge circuit is turned off to the time until the differential signal generated by the differentiating circuit is output is measured, and the time obtained by subtracting a predetermined time from the measured time is allocated to the next conduction time of the synchronous rectifier switch.

2. An integrated circuit for controlling a bridgeless / interleaved power factor improvement circuit in critical mode, the integrated circuit performing synchronous rectification control of the bridgeless / interleaved power factor improvement circuit in critical mode, characterized in that, In the bridgeless / interleaved power factor improvement circuit of the critical mode, An output smoothing capacitor is connected between the two terminals of the series circuit of the first and second diodes. A first half-bridge circuit consisting of the first and second NMOSFETs is used as the main control side, and a second half-bridge circuit consisting of the third and fourth NMOSFETs is used as the controlled side. One terminal of the AC power supply is connected to the junction of the first diode and the second diode. The other terminal of the AC power supply is connected to one terminal of the first reactor and the second reactor. The other terminal of the first reactor is connected to the connection point of the first NMOSFET and the second NMOSFET of the first half-bridge circuit. The other terminal of the second reactor is connected to the connection point of the third NMOSFET and the fourth NMOSFET of the second half-bridge circuit. A differentiating circuit consisting of a capacitor and a resistor is connected between the main electrodes of the second NMOSFET in the first half-bridge circuit. The integrated circuit detects the output voltage of the output smoothing capacitor and compares it with a predetermined reference voltage. Based on the error signal between the output voltage and the predetermined reference voltage, it controls the conduction and disconnection of the first half-bridge circuit and the second half-bridge circuit. For the conduction time of the synchronous rectifier switch of the first half-bridge circuit, the period from the moment the active switch of the first half-bridge circuit is turned off to the time until the differential signal generated by the differentiating circuit is output is measured, and then allocated to the next conduction time of the synchronous rectifier switch of the second half-bridge circuit.

3. The integrated circuit for controlling the bridgeless / interleaved power factor improvement circuit in critical mode according to claim 2, characterized in that, The integrated circuit measures the conduction time of the synchronous rectifier switch of the first half-bridge circuit from the moment the active switch of the first half-bridge circuit is turned off until the differential signal generated by the differentiating circuit is output. The time obtained by subtracting a predetermined time from the measured time is allocated to the next conduction time of the synchronous rectifier switch of the first half-bridge circuit.

4. An integrated circuit for controlling a bridgeless / interleaved power factor improvement circuit in critical mode, the integrated circuit performing synchronous rectification control of the bridgeless / interleaved power factor improvement circuit in critical mode, characterized in that, In the bridgeless / interleaved power factor improvement circuit of the critical mode, The circuit consists of a first half-bridge circuit (comprising the first and second NMOSFETs) connected in parallel, serving as the main control side; a second half-bridge circuit (comprising the third and fourth NMOSFETs) serving as the controlled side; a third half-bridge circuit (comprising the fifth and sixth NMOSFETs) used for synchronous rectification of the AC voltage from the AC power supply; and an output smoothing capacitor. One terminal of the AC power supply is connected to the junction of the 5th NMOSFET and the 6th NMOSFET. The other terminal of the AC power supply is connected to one terminal of the first reactor and the second reactor. The other terminal of the first reactor is connected to the connection point of the first NMOSFET and the second NMOSFET of the first half-bridge circuit. The other terminal of the second reactor is connected to the connection point of the third NMOSFET and the fourth NMOSFET of the second half-bridge circuit. A differentiating circuit consisting of a capacitor and a resistor is connected between the main electrodes of the second NMOSFET in the first half-bridge circuit. The integrated circuit detects the output voltage of the output smoothing capacitor and compares it with a predetermined reference voltage. Based on the error signal between the output voltage and the predetermined reference voltage, it controls the conduction and disconnection of the first half-bridge circuit and the second half-bridge circuit. For the conduction time of the synchronous rectifier switch of the first half-bridge circuit, the period from the moment the active switch of the first half-bridge circuit is turned off to the time until the differential signal generated by the differentiating circuit is output is measured, and then allocated to the next conduction time of the synchronous rectifier switch of the second half-bridge circuit.

5. The integrated circuit for controlling the bridgeless / interleaved power factor improvement circuit in critical mode according to claim 4, characterized in that, The integrated circuit measures the conduction time of the synchronous rectifier switch of the first half-bridge circuit from the moment the active switch of the first half-bridge circuit is turned off until the differential signal generated by the differentiating circuit is output. The time obtained by subtracting a predetermined time from the measured time is allocated to the next conduction time of the synchronous rectifier switch of the first half-bridge circuit.

6. A method for controlling a bridgeless / interleaved power factor improvement circuit in critical mode, wherein synchronous rectification control of the bridgeless / interleaved power factor improvement circuit in critical mode is characterized in that, In the bridgeless / interleaved power factor improvement circuit of the critical mode, An output smoothing capacitor is connected between the two terminals of the series circuit of the first rectifier element and the second rectifier element; a first half-bridge circuit consisting of the first NMOSFET and the second NMOSFET serves as the main control side; and a second half-bridge circuit consisting of the third NMOSFET and the fourth NMOSFET serves as the controlled side. One terminal of the AC power supply is connected to the connection point of the first rectifier element and the second rectifier element. The other terminal of the AC power supply is connected to one terminal of the first reactor and the second reactor. The other terminal of the first reactor is connected to the connection point of the first NMOSFET and the second NMOSFET of the first half-bridge circuit. The other terminal of the second reactor is connected to the connection point of the third NMOSFET and the fourth NMOSFET of the second half-bridge circuit. A differentiating circuit consisting of a capacitor and a resistor is connected between the main electrodes of the second NMOSFET in the first half-bridge circuit. The control circuit detects the output voltage of the output smoothing capacitor and compares it with a specified reference voltage. Based on the error signal between the output voltage and the specified reference voltage, it controls the conduction and disconnection of the first half-bridge circuit and the second half-bridge circuit. For the conduction time of the synchronous rectifier switch of the first half-bridge circuit, the period from the moment the active switch of the first half-bridge circuit is turned off to the time until the differential signal generated by the differentiating circuit is output is measured, and then allocated to the next conduction time of the synchronous rectifier switch of the second half-bridge circuit.

7. The method for controlling a bridgeless / interleaved power factor improvement circuit in critical mode according to claim 6, characterized in that, For the conduction time of the synchronous rectifier switch of the first half-bridge circuit, the period from the time the active switch of the first half-bridge circuit is turned off to the time until the differential signal generated by the differential circuit is output is measured, and the time obtained by subtracting a predetermined time from the measured time is allocated to the next conduction time of the synchronous rectifier switch of the first half-bridge circuit.

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