Dynamic load balancing for real-time deep learning analytics operations

Abstract

Apparatuses, systems, and techniques for balancing processing load among multiple hardware accelerators. In at least one embodiment, operations performed on batches of frames in a video (e.g., as part of a video analytics pipeline) are distributed by a load balancer among a first hardware accelerator and a second hardware accelerator.

Description

[0001] Priority Statement

[0002] This application claims the benefits of U.S. Patent Application No. 17 / 330,710, filed May 26, 2021, entitled “DYNAMIC LOAD BALANCES FOR REAL-TIME DEEP LEARNING ANALYTICS”, and U.S. Provisional Application No. 63 / 060,666, filed August 3, 2020, entitled “DYNAMIC LOAD BLANCING ON GPUS FOR DEEP LEARNING BASED REAL-TIME VIDEO ANALYTICS APPLICATIONS”, the entire contents of which are incorporated herein by reference. Background Technology

[0003] A typical video analytics application consists of multiple processing elements operating in parallel, each generating a portion of the information within the overall application. However, many of these processing elements have specific requirements for the resolution and format of the video frames. This introduces numerous transformations (e.g., scaling, format conversion, camera correction, dedistortion, etc.) that must be performed on the video frames throughout their lifecycle in the processing pipeline. Furthermore, each element must complete processing of the workload (e.g., a batch of video frames) within an average timeframe. Failure to complete processing on time can introduce latency into the processing and ultimately lead to the periodic dropping of video frames to keep up with the input frame rate. This, in turn, can result in information loss and / or the inability to perform certain operations (e.g., in real-time). Attached Figure Description

[0004] Figure 1 An example of load balancing between hardware accelerators according to at least one embodiment is shown;

[0005] Figure 2 An example of a deep learning video analytics pipeline utilizing load balancing among hardware accelerators according to at least one embodiment is shown;

[0006] Figure 3 An example of a table for tracking information during load balancing among hardware accelerators, according to at least one embodiment, is shown;

[0007] Figure 4 A flowchart illustrating load balancing between hardware accelerators according to at least one embodiment is shown;

[0008] Figure 5AThe inference and / or training logic according to at least one embodiment is illustrated;

[0009] Figure 5B The inference and / or training logic according to at least one embodiment is illustrated;

[0010] Figure 6 The training and deployment of a neural network according to at least one embodiment are illustrated;

[0011] Figure 7 An example data center system according to at least one embodiment is shown;

[0012] Figure 8A An example of an autonomous vehicle according to at least one embodiment is shown;

[0013] Figure 8B The illustration shows an embodiment according to at least one of the embodiments. Figure 8A Examples of camera positions and field of view in autonomous vehicles;

[0014] Figure 8C This is an illustration based on at least one embodiment. Figure 8A A block diagram of an example system architecture for an autonomous vehicle;

[0015] Figure 8D The illustration, according to at least one embodiment, is for one or more cloud-based servers and Figure 8A A diagram of a system for communication between autonomous vehicles;

[0016] Figure 9 This is a block diagram illustrating a computer system according to at least one embodiment;

[0017] Figure 10 This is a block diagram illustrating a computer system according to at least one embodiment;

[0018] Figure 11 A computer system according to at least one embodiment is shown;

[0019] Figure 12 A computer system according to at least one embodiment is shown;

[0020] Figure 13A A computer system according to at least one embodiment is shown;

[0021] Figure 13B A computer system according to at least one embodiment is shown;

[0022] Figure 13C A computer system according to at least one embodiment is shown;

[0023] Figure 13DA computer system according to at least one embodiment is shown;

[0024] Figure 13E and Figure 13F A shared programming model according to at least one embodiment is shown;

[0025] Figure 14 An exemplary integrated circuit and a related graphics processor according to at least one embodiment are shown;

[0026] Figure 15A and Figure 15B An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown;

[0027] Figure 16A and Figure 16B Additional exemplary graphics processor logic according to at least one embodiment is shown;

[0028] Figure 17 A computer system according to at least one embodiment is shown;

[0029] Figure 18A A parallel processor according to at least one embodiment is shown;

[0030] Figure 18B A partitioning unit according to at least one embodiment is shown;

[0031] Figure 18C A processing cluster according to at least one embodiment is shown;

[0032] Figure 18D A graphics multiprocessor according to at least one embodiment is shown;

[0033] Figure 19 A multi-graphics processing unit (GPU) system according to at least one embodiment is illustrated;

[0034] Figure 20 A graphics processor according to at least one embodiment is shown;

[0035] Figure 21 It is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0036] Figure 22 A deep learning application processor according to at least one embodiment is shown;

[0037] Figure 23 A block diagram of an example neuromorphic processor is shown according to at least one embodiment;

[0038] Figure 24At least a portion of a graphics processor according to one or more embodiments is shown;

[0039] Figure 25 At least a portion of a graphics processor according to one or more embodiments is shown;

[0040] Figure 26 At least a portion of a graphics processor according to one or more embodiments is shown;

[0041] Figure 27 It is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0042] Figure 28 It is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0043] Figure 29A and Figure 29B The diagram illustrates thread execution logic according to at least one embodiment, which includes an array of processing elements of a graphics processor core;

[0044] Figure 30 A parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0045] Figure 31 A general-purpose processing cluster (“GPC”) according to at least one embodiment is illustrated;

[0046] Figure 32 A memory partition unit of a parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0047] Figure 33 A streaming multiprocessor according to at least one embodiment is illustrated;

[0048] Figure 34 This is an example data flow diagram of an advanced computing pipeline according to at least one embodiment;

[0049] Figure 35 This is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, according to at least one embodiment;

[0050] Figure 36 Example illustrations of an advanced computing pipeline for processing imaging data according to at least one embodiment;

[0051] Figure 37A Includes example data flow diagrams of virtual instruments supporting ultrasound equipment according to at least one embodiment;

[0052] Figure 37BIncludes example data flow diagrams of virtual instruments supporting CT scanners according to at least one embodiment;

[0053] Figure 38A A data flow diagram illustrating the process for training a machine learning model according to at least one embodiment is shown; and

[0054] Figure 38B This is an example illustration of a client-server architecture that utilizes a pre-trained annotation model to enhance an annotation tool, according to at least one embodiment. Detailed Implementation

[0055] Embodiments of this disclosure provide a novel solution to overcome the need for manually tweaking and / or transforming configurations, reduce bottlenecks, and increase streaming density by implementing a load balancer to distribute work across available hardware accelerators, including various hardware accelerators described in more detail below. In embodiments, the load balancer is used to improve the performance of one or more AI pipelines where cascaded neural networks and computer vision (CV) algorithms require different formats and frame resolutions as input. In various embodiments, the load balancer distributes work (e.g., operations to be performed on a batch of N frames comprising frames from one or more video inputs (e.g., cameras or video files) across multiple hardware accelerators to improve efficiency, enable real-time applications, prevent bottlenecks, and reduce underutilization of computing resources. In one example, the load balancer processes work from one or more components of a video analytics pipeline to increase streaming density, thereby allowing the video analytics pipeline to be deployed in real-time applications. In various embodiments, the hardware accelerators include video image synthesizers (VICs), central processing units (CPUs), graphics processing units (GPUs), data processing units (DPUs), or other hardware (e.g., field-programmable gate arrays (FPGAs)). For example, a load balancer (e.g., a process executed by the CPU) can distribute work to one or more VICs, one or more DPUs, and one or more GPUs to perform various operations of an application.

[0056] In various embodiments, the operations include those performed by an application executed by a computing device. In one example, the application includes a deep learning (DL) pipeline that takes video as input and performs video analysis (e.g., object detection, classification, etc.). In such examples, the various components in the DL pipeline have different requirements for processing the video (e.g., a batch of frames of the video). For example, the DL pipeline may include neural networks that require specific formats, resolutions, color spaces, or other requirements. To meet these requirements, according to at least one embodiment, various operations are performed on the video and / or batches of frames in the video to enable processing by the various components of the DL pipeline. For example, these operations may include image scaling, color space conversion, gamma correction, image transformation, camera correction (e.g., removal of fisheye / lens distortion, de-distortion of 360-degree camera frames, etc.), or any other operation that allows video processing.

[0057] Therefore, in various embodiments, the load balancer distributes the performance of operations across hardware accelerators. Furthermore, in various embodiments, the load balancer is agnostic to the application and / or user and requires no tuning and / or configuration. In one example, the load balancer transparently distributes operations based at least in part on various factors such as the current load on the hardware accelerator, compute requirements, percentage of hardware accelerator usage, deadlines associated with operations, or other factors. Additionally, in embodiments, the load balancer includes various preferences and / or configurations. For example, the load balancer may include usage limits associated with specific hardware accelerators, preferred hardware accelerators, preferred hardware accelerators for specific operations, per-process usage limits, and other configurations.

[0058] In various embodiments, the load balancer assigns client identifiers to applications and / or components within applications. As described in more detail below, in embodiments, the client identifier includes information identifying a client (e.g., an application, process, or other component) that submits work to be performed by a hardware accelerator. In various embodiments, the load balancer maintains a client table that includes hardware accelerators assigned to perform work submitted by clients and the average time spent performing the work for each hardware accelerator. In one example, all clients are assigned to a VIC, and after a period of time, the average time spent performing the work is determined. In such examples, if the average time spent performing the work exceeds a threshold, the client is assigned to another hardware accelerator, such as a GPU. In various embodiments, this process is repeated until the average time for all clients is below the threshold. As described in more detail below, according to at least one embodiment, the threshold may be determined at least in part based on various factors such as the frame rate of the video and / or the frame processing deadline. In various embodiments, the load balancer determines after a period of time whether one or more clients can be reassigned to a VIC. In one example, if the average time of clients assigned to the VIC falls below a threshold, the load balancer will determine to reassign one or more clients from other hardware accelerators to the VIC. In one embodiment, the load balancer determines which clients to reassign to the VIC based at least in part on various factors such as the load on other hardware accelerators due to clients, whether processing work on the VIC is faster, or other factors. In another embodiment, the load balancer periodically or non-periodically distributes load (e.g., work generated by clients) among multiple hardware accelerators such as VICs and GPUs.

[0059] Various techniques have been described in the preceding and following descriptions. For illustrative purposes, specific configurations and details have been elaborated to provide a thorough understanding of the possible ways to implement these techniques. However, it is also apparent that the techniques described below can also be practiced in different configurations without specific details. Furthermore, well-known features may be omitted or simplified to avoid obscuring the techniques described.

[0060] The techniques described and suggested in this disclosure can improve the field of load balancing among hardware accelerators by providing systems for load balancing among hardware accelerators to improve system efficiency, especially in the context of performing deep learning with limited computing resources. Furthermore, the techniques described and suggested in this disclosure can improve the performance speed of deep learning pipelines, video analytics, and other applications utilizing hardware acceleration on various computing systems. Moreover, the techniques described and suggested in this disclosure must be rooted in computer technology to overcome problems arising, particularly with real-time deep learning analytics, under limited computing resources.

[0061] Figure 1 An environment 100 according to at least one embodiment is illustrated, wherein a load balancer 104 distributes work units 120 among hardware accelerators. In various embodiments, one or more clients 106A-106C provide one or more work units 120 to a processor 102. For example, one or more clients 106A-106C include threads of a collection of applications, such as a video analytics pipeline 108 or other applications executed by the processor. In various embodiments, the video analytics pipeline 108 includes a deep learning pipeline, as described below. Figure 2 More detailed description. Furthermore, in various embodiments, the components in environment 100 (e.g., processor 102, hardware accelerator, etc.) are computer systems (e.g., as described below in conjunction with...). Figure 11 The components in the computer system 1100 are described in more detail below. Furthermore, in various embodiments, the processor 102 includes various computing resources (e.g., one or more circuits), such as those combined with… Figure 10 The processor 1010 is described.

[0062] In various embodiments, processor 102 executes load balancer 104. In these embodiments, load balancer 104 is an application or other executable code that, due to execution by processor 102, distributes work units between first hardware accelerator 110 and second hardware accelerator 112. In various embodiments, first hardware accelerator 110 and second hardware accelerator 112 include video image synthesizers (VICs), central processing units (CPUs), graphics processing units (GPUs), or other hardware (e.g., field-programmable gate arrays (FPGAs) or data processing units (DPUs)). Furthermore, as... Figure 1 As shown, in various embodiments, the first hardware accelerator 110 and the second hardware accelerator 112 include multiple hardware accelerators. For example, environment 100 includes three VICs (e.g., the first hardware accelerator 110) and three GPUs (e.g., the second hardware accelerator 112). In various embodiments, the first hardware accelerator 110 and / or the second hardware accelerator 112 represent a category and / or type of computing resources (e.g., GPU, CPU, VIC, FPGA, DPU, or other circuitry). As described in more detail below, the load balancer 104 includes a set of logical and / or heuristic methods (e.g., programming logic) for allocating work units 120 to the first hardware accelerator 110 and / or the second hardware accelerator 112. For example, the load balancer 104 allocates work units 120 to the first hardware accelerator 110, and then, when overload is detected in the first hardware accelerator 110 (e.g., increased latency, utilization, etc.), the load balancer 104 allocates at least a portion of the work units 120 to the second hardware accelerator 112.

[0063] As described in more detail below, in an embodiment, load balancer 104 determines the load on the first hardware accelerator 110 and / or the second hardware accelerator 112 when the time interval expires and assigns one or more clients 106A-106C to the specific hardware accelerator. In various embodiments, the first hardware accelerator 110 and / or the second hardware accelerator 112 includes various processing units, such as those described below. Figures 13A-13F A more detailed description of the GPU. In various embodiments, work unit 120 includes the transformation and / or compositing of batches of video frames. For example, a batch of frames may include 10 frames from a video file, video stream, camera, or other video source. Furthermore, as described in this disclosure, according to embodiments, the transformation includes various operations, such as converting video frames and / or images from a first format to a second format, scaling video frames and / or images (e.g., increasing, decreasing, or otherwise modifying resolution), modifying the color space of video frames and / or images, or modifying one or more attributes of video frames and / or images. In embodiments, work unit 120 is performed against an input set of pixels (e.g., input video frames and / or images). For example, each VIC processor cycles through multiple input pixels.

[0064] In various embodiments, load balancer 104 generates or otherwise obtains statistics associated with one or more clients 106A-106C, applications (e.g., applications executed by processor 102 or other systems communicatively coupled to processor 102), work unit 120, hardware accelerators (e.g., first hardware accelerator 110 and / or second hardware accelerator 112), or other components in environment 100. For example, as follows: Figure 3 As shown, load balancer 104 maintains a table including statistics (e.g., the average amount of time spent processing one or more work units 120). In various embodiments, load balancer 104 includes a set of heuristics that include operations performed at least in part based on the statistics. In one example, if the average time spent processing a particular work unit 120 is higher than a threshold, one heuristic in the set of heuristics indicates that a particular client be moved to a different hardware accelerator. In various embodiments, the set of heuristics defines strategies for balancing the load across hardware accelerators. In other embodiments, the set of heuristics is implemented as rules or other logic that cause load balancer 104 to perform the various operations described in this disclosure.

[0065] Furthermore, in embodiments, the load balancer 104 is agnostic to one or more users associated with the application. According to at least one embodiment, the load balancer 104 obtains transformation information at least in part based on application programming interface (API) calls generated by one or more clients 106A-106C. For example, client 106A submits an API call to convert a batch of frames from a first format to a second format. In another example, client 106A submits an API call to scale a batch of frames. In this way, in various embodiments, the load balancer 104 maintains information associated with a set of transformation and / or other operation requests from one or more clients 106A-106C. Furthermore, in various embodiments, the load balancer 104 maintains historical statistical calculation requirements for various transformations performed on various hardware accelerators (e.g., GPUs and / or VICs). In one example, the load balancer 104 maintains statistical metrics (e.g., average, minimum, maximum, etc.) for all transformations (e.g., scaling, conversion, camera correction, color correction, etc.) of one or more clients 106A-106B. In another example, the load balancer maintains a rolling average of the amount of time taken by the hardware accelerator to perform the transformation (e.g., the last N transformation performed).

[0066] Furthermore, in embodiments, load balancer 104 determines or otherwise obtains (e.g., via system calls or other mechanisms) the current load of the first hardware accelerator 110 and / or the second hardware accelerator 112. In one example, load balancer 104 estimates the load of a particular hardware accelerator based at least in part on maintained statistics (e.g., current processing time vs. historical processing time). In another example, load balancer 104 obtains load information directly from the hardware accelerator.

[0067] In various embodiments, the load balancer distributes transformations and / or operations among the various hardware accelerators (e.g., the first hardware accelerator 110 and / or the second hardware accelerator 112) based at least in part on various factors, such as the current load of the first hardware accelerator 110 and / or the second hardware accelerator 112, the computational requirements of a particular transformation and / or operation, the percentage of usage of the first hardware accelerator 110 and / or the second hardware accelerator 112, information indicating a deadline for completing a particular transformation and / or operation, or other information associated with the components shown in environment 100. In one example, the transformations and / or operations are distributed transparently (e.g., without input or notification to clients 106A-106C or other applications and / or users). In various embodiments, the load balancer 104 includes configuration information that can be modified by the user. In one example, the user and / or application modify the load balancer's configuration information to specify usage limits for a particular hardware accelerator (e.g., keeping it below its load threshold percentage). In various embodiments, other configuration information includes preferred hardware accelerators for a particular transformation, processing duration, allocation, or other options for controlling the performance of the transformation and / or operation.

[0068] In embodiments, load balancer 104 utilizes a first hardware accelerator 110 as the preferred hardware accelerator for all or part of the work units 120 (e.g., transformations). In one example, where the first hardware accelerator is a VIC, load balancer 104 initially allocates all work units 120 to the VIC until load balancer 104 determines that the utilization (e.g., load) of the VIC exceeds a threshold. In various embodiments, if the utilization percentage of the hardware accelerator (e.g., the percentage of the maximum amount of computation that can be performed) is not available, load balancer 104 uses a utilization percentage metric (proxy), such as frame processing deadline (e.g., the maximum amount of time a hardware accelerator can spend before causing latency in an application or a particular client), to determine whether to reallocate the load (e.g., move the incoming work unit 120 to a second hardware accelerator 112). In one example, the frame processing deadline depends on the video processing frame rate associated with the video analytics pipeline 108 (e.g., approximately 33 milliseconds for a video stream of 30 frames per second). In various embodiments, load balancer 104 assigns clients from one or more of clients 106A-106C. For example, load balancer 104 assigns client 106A to a first hardware accelerator 110, resulting in all work units 120 provided by client 106A being assigned to the first hardware accelerator 110 until load balancer 104 determines to assign client 106A to a second hardware accelerator 112. Figure 3As shown, load balancer 104 maintains tables of clients, hardware accelerators assigned to clients, and the average time (e.g., if available) spent processing work units provided by clients to hardware accelerators.

[0069] In various embodiments, for an API call received from one or more clients 106A-106C, load balancer 104 determines the time spent completing work unit 120 (e.g., the transformation requested in the API call). Furthermore, in such embodiments, the time spent includes both the amount of time spent in the execution queue and the amount of time spent during execution. In one example, the average time used is calculated over a moving window of the transformation (e.g., the final N transformations, where N = 4). In embodiments, the threads of the processor associated with load balancer 104 are woken up after the time interval expires and, at least in part, determine, based on the table and the frame processing deadline, to reallocate hardware accelerators (e.g., first hardware accelerator 110 and / or second hardware accelerator 112) to one or more clients 106A-106C. For example, load balancer 104 reallocates hardware accelerators to one or more clients 106A-106C to maximize utilization and / or meet frame processing deadlines.

[0070] In various embodiments, load balancer 104 obtains utilization information (e.g., activity, percentage, load, utilization, etc.) associated with hardware accelerators via system calls, websockets, or other communications, and uses this utilization information to determine load balancing operations (e.g., assigning clients 106A-106C to hardware accelerators). In embodiments, load balancer 104 implements per-process and / or per-client limits on the usage of hardware accelerators for work units 120 (e.g., conversions). Furthermore, in various embodiments, load balancer 104 receives requests from applications for information associated with clients 106A-106C (e.g., client environment, client ID, or other identifying information) from load balancer 104. In embodiments, in response to this information, the application can cause load balancer 104 to assign a specific client to a specific hardware accelerator, prevent load balancer 104 from assigning a specific client to a specific hardware accelerator, or allow the specific client to be assigned to any hardware accelerator.

[0071] In various embodiments, load balancer 104 executes as a separate and / or dedicated process or as a separate thread within an application process executed by processor 102. Furthermore, in embodiments, one or more clients 106A-106C request specific hardware accelerators from load balancer 104 to process work unit 120 via inter-process communication (IPC). In such embodiments, execution is initiated by one or more clients 106A-106C, and one or more clients 106A-106C report execution details back to load balancer 104 via IPC. In such embodiments, when one or more clients 106A, 106C initiate the execution of work unit 120 and communicate with load balancer 104, load balancer 104 determines or otherwise obtains statistics. Statistics include, for example, the load on the hardware accelerator, and the total load being generated on the hardware accelerator by a particular client. Furthermore, in various embodiments, statistics are maintained for each client and each hardware accelerator, including the average load generated by work units submitted by clients and executed on a particular hardware accelerator, and the average amount of time required to execute work units submitted by clients and executed on a particular hardware accelerator. In various embodiments, statistics are sampled at various intervals. For example, load balancer 104 may utilize statistics generated in the last few sampling intervals (e.g., with higher weights for the application) and historical data (e.g., with lower weights for the application). In such embodiments, the duration of the sampling interval for work units 120 obtained from a particular client to be executed on a hardware accelerator and / or hardware accelerator type (e.g., the load balancer has assigned the particular client to any one of the first hardware accelerator 110 and / or the second hardware accelerator 112). In one example, the hardware accelerator assigned to a particular client changes from one sampling interval to another.

[0072] Figure 2 An environment 200 in which a parallel processing pipeline is executed according to at least one embodiment is illustrated. In various embodiments, the parallel processing pipeline includes a combination of... Figure 1 The described video analytics pipeline 108, deep learning pipeline, artificial intelligence pipeline, or other pipelines in which operations can be executed in parallel. In one example, the parallel processing pipeline performs real-time streaming video analytics. In such an example, the video analytics application (e.g., an application that executes all or part of the parallel processing pipeline) includes multiple processing elements that operate in parallel and are responsible for generating data or other information for use in the application. Figure 2As shown, the parallel processing pipeline includes multiple components (e.g., video source 202, video converters 204A and 204B, multiplexer 206, main detector 208, object tracker 210, auxiliary classifiers 212A and 212C, and renderer 216).

[0073] Furthermore, in some embodiments, portions of the component (in) Figure 2 (Seen in crosshairs) has various required data for processing (e.g., a specific resolution or format of a video frame). For example, the main detector 208 may require video frames of a first format, while the object tracker 210 may require video frames of a second format, which introduces the need to perform transformations or other processing on the video source 202 to enable processing. Various computer systems include hardware accelerators such as VICs and GPUs to perform such transformations as described in this disclosure. In various embodiments, components in the parallel processing pipeline must complete the processing of a unit of work (e.g., a batch of video frames) within a time interval or in an average amount of time (which may include padding or otherwise scalable). In such embodiments, the amount of time to complete processing one or more units of work is determined by the parallel processing pipeline architecture and frame rate of the video source 202 and / or the video output. In various embodiments, failure to complete processing within a specific time interval results in the introduction of latency in the parallel processing pipeline and may ultimately result in the dropping of one or more video frames to maintain processing of the video source 202.

[0074] In embodiments, the parallel processing pipeline is executed by any suitable processing system or unit (e.g., GPU, VIC, Parallel Processing Unit (PPU), CPU, DPU, FPGA, etc.) in any suitable manner, including sequential, parallel, and / or variations thereof. In various embodiments, video source 202 includes digital data encoding representing images (e.g., video). Furthermore, video source 202 includes, for example, one or more images, also referred to as frames, which together form video. In various embodiments, video source 202 is implemented using any suitable digital video format such as Advanced Video Coding (AVC), Moving Picture Experts Group (MPEG) format, and / or variations thereof. In one example, video source 202 includes a sequence of images in any suitable raster image file format (e.g., bitmap image file, JPEG (Joint Picture Experts Group) file) and / or vector image file format (e.g., SVG (Scalable Vector Graphics) file). According to various embodiments, video source 202 includes compressed or uncompressed data. Furthermore, in various embodiments, the video source 202 is generated by one or more video and / or image capture devices and / or obtained from one or more video and / or image capture devices, such as one or more systems like autonomous vehicles, robots, surveillance systems, medical imaging systems, satellite imaging systems, etc., as described in more detail below (e.g., Figures 8A-8DFurthermore, in embodiments, video source 202 includes files or other data stored in a storage device. For example, video source 202 represents video using any suitable color scheme (e.g., red-green-blue (RGB), NV12-like YUV format, black and white (BW), grayscale, and / or variations thereof). Additionally, in various embodiments, video source 202 includes network-based cameras, surveillance systems, traffic cameras, industrial cameras, drones, and autonomous vehicles.

[0075] In various embodiments, the parallel processing pipeline obtains or otherwise provides video source 202 from one or more systems associated with various video and / or image capture devices. In some examples, the parallel processing pipeline is part of a system including video capture hardware and / or software, wherein the parallel processing pipeline obtains video source 202 from the video capture hardware and / or software. For example, video source 202 is obtained by or otherwise provided to the system performing the parallel processing pipeline, such as physically (e.g., via a wired connection to a device associated with the parallel processing pipeline), remotely (e.g., via a wireless communication network to a device associated with the parallel processing pipeline), and / or variations thereof. In various embodiments, the parallel processing pipeline includes additional components, fewer components, and / or alternative components. For example, the parallel processing pipeline includes a decoder to obtain compressed frames from video source 202. In other examples, the parallel processing pipeline does not include multiplexer 206.

[0076] In various embodiments, the video conversion components 204A and 204B of the parallel processing pipeline process the video source 202 and convert it to a specific format (e.g., a requested video format or a video format required by a specific element of the parallel processing pipeline). In embodiments, the video conversion components 204A and 204B include a collection of one or more hardware and / or software computing resources with instructions that, due to execution by one or more processors, cause the system to perform one or more video processing operations. In examples, the video conversion components 204A and 204B determine frames from the video source 202 for conversion from one format to another. In some examples where the video source 202 is compressed, the video conversion component 204A decompresses the video source 202 to determine frames in the video. In other examples, the video source 202 includes one or more components to decompress or otherwise decode frames in the video.

[0077] In various embodiments, the video conversion 204A component outputs frames (e.g., frames from video source 202) to the main detector 208. In various embodiments, the main detector 208 processes a batch of frames to detect objects within the frames. In embodiments, the main detector 208 is a collection of one or more hardware and / or software computing resources having instructions that cause the system to perform one or more object detection operations due to execution by one or more processors. For example, the main detector 208 utilizes various neural network models for object detection. Non-limiting examples of such neural network models may include perceptron models, radial basis function networks (RBNs), autoencoders (AEs), Boltzmann machines (BMs), restricted Boltzmann machines (RBMs), deep belief networks (DBNs), deep convolutional networks (DCNs), extreme learning machines (ELMs), deep residual networks (DRNs), and / or variations thereof. In one example, the main detector 208 determines the features of the batch of frames. In another example, the main detector 208 determines the bounding boxes of objects depicted in one or more frames. According to embodiments, an object refers to any suitable entity or object in a scene represented in one or more frames, such as a person, environmental object, vehicle, robot, and / or variations thereof. Furthermore, in at least one embodiment, a bounding box refers to an indication of the location and / or position of an object represented in an image. For example, a bounding box defines a set of coordinates corresponding to the corners of a particular bounding box that includes all or part of the objects depicted in one or more frames. Additionally, according to embodiments, a bounding box indicates the extent or region of an image (e.g., a frame) that includes the depiction of the object. In various embodiments, the main detector 208 determines bounding boxes for any number of objects represented in one or more frames and outputs the bounding boxes and / or bounding box information (e.g., coordinates or other geometric information representing the bounding boxes) to the object tracker 210.

[0078] In some embodiments, the master detector 208 does not determine bounding boxes for every frame, but only for a subset of frames, wherein the determined bounding boxes are output to the object tracker 210. In embodiments, the object tracker 210 includes a collection of one or more hardware and / or software computing resources, including instructions that cause the system to perform one or more computer vision processes due to execution by one or more processors. For example, the object tracker 210 executes one or more computer vision algorithms that determine the bounding boxes of one or more frames based on the bounding boxes of one or more previous frames and / or the bounding boxes of one or more subsequent frames to track the positions of multiple objects on neighboring frames. In various embodiments, the master detector 208 and / or the object tracker 210 are configured with parameters (e.g., tracking distance) that determine which frames will be processed by the master detector 208 and / or the object tracker 210. For example, the tracking distance may indicate the number of frames between frames to be processed by the master detector 208 and may be any suitable integer value. In another example, a tracking distance of 0 indicates that the main detector 208 will process every frame of the video source 202, a tracking distance of 1 indicates that the main detector 208 will process the video source 202 every other frame, and so on.

[0079] In various embodiments, object tracker 210 determines bounding boxes for frames of video source 202 that have not been processed by main detector 208. For example, main detector 208 determines bounding boxes for every other frame in video source 202 (e.g., the first frame, the third frame, the fifth frame, etc.), and object tracker 210 determines bounding boxes for the remaining frames of video source 202 (e.g., the second frame, the fourth frame, the sixth frame, etc.). In various embodiments, object tracker 210 performs various object tracking procedures, such as one or more kernel-based tracking procedures and / or contour tracking procedures, to determine the bounding boxes of objects in a frame based on the bounding boxes of objects in the previous frame and / or the bounding boxes of objects in subsequent frames.

[0080] In one example, object tracker 210 determines the bounding boxes of any number of objects in any suitable number of frames based on the bounding boxes determined by master detector 208. In various embodiments, master detector 208 and / or object tracker 210 provide information (e.g., bounding boxes) to one or more auxiliary classifiers 212A-221C. One or more auxiliary classifiers 212A-221C may include, for example, various neural network models trained to identify and / or classify objects depicted in images (e.g., frames), such as perceptron models, radial basis function networks (RBNs), autoencoders (AEs), Boltzmann machines (BMs), restricted Boltzmann machines (RBMs), deep belief networks (DBNs), deep convolutional networks (DCNs), extreme learning machines (ELMs), deep residual networks (DRNs), logistic regression models, naive Bayes models, stochastic gradient descent models, K-nearest neighbor models, decision tree models, random forest models, support vector machine models, and / or variations thereof. For example, for a given frame (e.g., a frame of video source 202) and a first bounding box indicating a first object of the frame (e.g., determined by the main detector 208 and / or object tracker 210), one of one or more auxiliary classifiers 212A-221C determines the category of the object depicted in the bounding box.

[0081] In various embodiments, renderer 216 generates video data that may include information generated by main detector 208, object tracker 210, and / or one or more auxiliary classifiers 212A-212C. In one example, renderer 216 displays the generated video data. As described in this disclosure, components in the parallel processing pipeline need to transform frames to generate such data. In various embodiments, these transformations are performed by hardware accelerators, which include various hardware processing components, such as one or more PPUs, GPUs, etc. In one example, the hardware accelerator includes computer hardware specifically designed to perform one or more processes (e.g., the transformations described above).

[0082] Figure 3 Table 300 is shown, illustrating the usage by a load balancer to maintain statistics during load balancing operations. In various embodiments, the load balancer includes the above-described combination... Figure 1 The load balancer 104 is described. In various embodiments, the load balancer maintains tables including information associated with client 302, the current hardware accelerator 304 assigned to a particular client, the average time spent on a first hardware accelerator 306, and the average time spent on a second hardware accelerator 308. In one example, the client includes information as described above. Figure 1The clients 106A-106C are described above. In various embodiments, the information maintained in the table includes identifiers associated with the client (e.g., thread names). For example, the operating system assigns identifiers to threads in applications executed by the system.

[0083] In various embodiments, the load balancer assigns a specific client (e.g., a "tracker") to a specific hardware accelerator (e.g., a "first"). As described above, the system performing the load balancer may include multiple hardware accelerators suitable for performing operations on behalf of the clients. Therefore, in various embodiments, a specific row in Table 300 indicates the hardware accelerator assigned to a specific client in the first time interval 308. As described above, in various embodiments, in the second time interval 310, the load balancer determines one or more clients assigned to another hardware accelerator based at least in part on the average time spent on the specific hardware accelerator. For example, as... Figure 3 As shown, during the second time interval 310, the load balancer determines, at least in part, to assign clients (e.g., "Tiler" and "Primary") to the second hardware accelerator based on the average time spent by the first accelerator 306. As described above, the average time spent includes the amount of time taken by the hardware accelerator to complete a set of operations (e.g., the first four operations by the client).

[0084] refer to Figure 4 , Figure 4 This is an example method for load balancing among multiple hardware accelerators according to some embodiments of this disclosure. It should be understood that such and other arrangements described herein are illustrative by way of example only. Other arrangements and elements (e.g., machines, interfaces, functions, commands, groupings of functions, etc.) may be used in addition to or as alternatives to those shown, and some elements may be omitted entirely. Furthermore, many of the elements described herein are functional entities that can be implemented as discrete or distributed components or in combination with other components, and implemented in any suitable combination and at any suitable location. The various functions described herein as being performed by entities can be performed by hardware, firmware, and / or software. For example, various functions can be performed by a processor executing instructions stored in memory. Furthermore, Figure 4 The various functions shown can be executed in various orders (e.g., serial or parallel) or can be ignored entirely.

[0085] Now for reference Figure 4Each box in the method 400 described herein includes a computational process that can be performed using any combination of hardware, firmware, and / or software. For example, various functions can be performed by a processor executing instructions stored in memory. The method can also be implemented as computer-usable instructions stored on a computer storage medium. These methods can be provided by a standalone application, service, or hosted service (standalone or in combination with another hosted service), or a plug-in to another product, etc. Furthermore, as an example, a method related to… Figure 1 The load balancer 104 is related to the methods 400. However, these methods may be additionally or alternatively implemented by any system or any combination of systems, including but not limited to those described herein.

[0086] Figure 4 This is a flowchart illustrating a method 400 for load balancing among multiple hardware accelerators according to some embodiments of the present disclosure. At block 402, method 400 includes assigning a client to a first hardware accelerator. In embodiments, the load balancer causes an operation submitted by the client to be processed by the first hardware accelerator. In one example, the load balancer initially assigns the client to a VIC. As described above, in such an example, after a time interval, the average time spent by the VIC processing the transformation (e.g., performing an operation) is determined. In various embodiments, information is stored in a table, for example, in combination with... Figure 3 Table 300 describes this.

[0087] According to one embodiment, at box 404, the load balancer determines whether any clients exceed a threshold (e.g., a frame processing threshold). If one or more clients exceed the threshold, at box 406, the load balancer reassigns the clients to a second hardware accelerator. In various embodiments, the load balancer assigns the client that spent the least time on the first hardware accelerator to the second hardware accelerator. In other embodiments, the load balancer assigns the client that spent the most time on the first hardware accelerator to the second hardware accelerator. At box 408, the load balancer waits for a time interval to allow the reassignment to take effect. After the time interval, the load balancer returns to box 404 and determines whether one or more clients exceed a usage threshold (e.g., for the first or second hardware accelerator). In various embodiments, method 400 is repeated until no client exceeds the threshold. Returning to box 404, if the average time spent by the client is below the threshold, at box 410, the load balancer selects one or more clients currently assigned to the second hardware accelerator (if any) to reassign to the first hardware accelerator. In box 412, the load balancer determines whether one or more selected clients and / or client-requested operations (e.g., transformations) can be reassigned to the first hardware accelerator. If the clients can be reassigned, in box 414, the load balancer reassigns the clients to the first hardware accelerator; otherwise, the load balancer proceeds to box 408. In various embodiments, the load balancer may not be able to reassign clients to the first hardware accelerator due to the average amount of time spent configuring and / or processing operations.

[0088] In various embodiments, method 400 is modified. For example, the application and / or user can specify one or more preferred hardware accelerators and cause work belonging to a particular client to be assigned to one or more preferred hardware accelerators. In various embodiments, preferences include ranking or sorting lists. In other embodiments, clients are assigned to hardware accelerators randomly or pseudo-randomly. In other embodiments, the load balancer may still reallocate clients if a threshold is not exceeded. For example, if the maximum number of clients assigned to a hardware accelerator is exceeded or percentage utilization is exceeded. Furthermore, in various embodiments, the load balancer determines the efficiency of the hardware accelerators and assigned clients based on efficiency. For example, if a particular hardware accelerator is processing a particular transformation faster, the load balancer will assign clients requesting that particular transformation to that particular load balancer. Furthermore, in various embodiments, if the load balancer cannot reallocate clients, it slows down the application and / or one or more clients.

[0089] Reasoning and training logic

[0090] Figure 5AInference and / or training logic 515 for performing inference and / or training operations associated with one or more embodiments is shown. The following is in conjunction with... Figure 5A and / or Figure 5B Provide details about reasoning and / or training logic 515.

[0091] In at least one embodiment, inference and / or training logic 515 may include, but is not limited to, code and / or data storage 501 for storing forward and / or output weights and / or input / output data, and / or other parameters configuring neurons or layers of a neural network trained for and / or used for inference in one or more embodiments. In at least one embodiment, training logic 515 may include or be coupled to code and / or data storage 501 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic, including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 501 stores weight parameters and / or input / output data of each layer of a neural network trained or used in one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using one or more embodiments. In at least one embodiment, any portion of the code and / or data storage 501 may be included within other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0092] In at least one embodiment, any portion of the code and / or data storage 501 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 501 may be a cache memory, dynamic random-addressable memory (“DRAM”), static random-addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 501 is internal or external to the processor, for example, or composed of DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip or off-chip storage space, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0093] In at least one embodiment, the inference and / or training logic 515 may include, but is not limited to, code and / or data storage 505 to store backpropagation and / or output weights and / or input / output data neural networks corresponding to neurons or layers of a neural network trained and / or used for inference in one or more embodiments. In at least one embodiment, during training and / or inference using one or more embodiments, the code and / or data storage 505 stores weight parameters and / or input / output data for each layer of a neural network trained or used in one or more embodiments during backpropagation of input / output data and / or weight parameters. In at least one embodiment, the training logic 515 may include or be coupled to code and / or data storage 505 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)).

[0094] In at least one embodiment, code (such as graph code) causes the architecture of the neural network corresponding to that code to load weights or other parameter information into the processor ALU. In at least one embodiment, any portion of the code and / or data storage 505 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data storage 505 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 505 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice between the code and / or data storage 505 being internal or external to the processor, for example, whether it consists of DRAM, SRAM, flash memory, or some other type of storage, depends on whether the available storage is on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the data batch size used in the inference and / or training of the neural network, or some combination of these factors.

[0095] In at least one embodiment, code and / or data storage 501 and code and / or data storage 505 may be separate storage structures. In at least one embodiment, code and / or data storage 501 and code and / or data storage 505 may be the same storage structure. In at least one embodiment, code and / or data storage 501 and code and / or data storage 505 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 501 and code and / or data storage 505 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0096] In at least one embodiment, the inference and / or training logic 515 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 510 (including integer and / or floating-point units) for performing logical and / or mathematical operations at least in part based on or instructed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from layers or neurons within a neural network) stored in activation storage 520, which are functions of input / output and / or weight parameter data stored in code and / or data storage 501 and / or code and / or data storage 505. In at least one embodiment, activation is activated in response to execution instructions or other code, and linear algebraic and / or matrix-based mathematical generation performed by ALU 510 is stored in activation storage 520, wherein weight values ​​stored in code and / or data storage 505 and / or code and / or data storage 501 are used as operands with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, and any or all of these can be stored in code and / or data storage 505 or code and / or data storage 501 or other on-chip or off-chip storage.

[0097] In at least one embodiment, one or more processors or other hardware logic devices or circuits include one or more ALUs 510, while in another embodiment, one or more ALUs 510 may be located outside the processor or other hardware logic device or the circuitry that uses them (e.g., a coprocessor). In at least one embodiment, one or more ALUs 510 may be included within an execution unit of a processor, or otherwise included in a group of ALUs accessible by the execution unit of the processor, which may be within the same processor or distributed among different processors of different types (e.g., a central processing unit, a graphics processing unit, a fixed-function unit, etc.). In at least one embodiment, code and / or data storage 501, code and / or data storage 505, and activation storage 520 may share a processor or other hardware logic device or circuitry, while in another embodiment, they may be located in different processors or other hardware logic devices or circuitry, or in some combination of the same and different processors or other hardware logic devices or circuitry. In at least one embodiment, any portion of activation storage 520 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Furthermore, inference and / or training code may be stored together with other code accessible to the processor or other hardware logic or circuitry, and may be retrieved and / or processed using the processor’s fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0098] In at least one embodiment, the active memory 520 may be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the active memory 520 may be wholly or partially located inside or outside one or more processors or other logic circuits. In at least one embodiment, the choice of whether the active memory 520 is internal to or external to the processor may depend on the availability of on-chip or off-chip storage, the latency requirements for training and / or inference functions, the batch size of data used in inference and / or training the neural network, or some combination of these factors. For example, it may include DRAM, SRAM, flash memory, or other memory types.

[0099] In at least one embodiment, Figure 5A The inference and / or training logic 515 shown can be used in conjunction with an application-specific integrated circuit (“ASIC”), such as those from Google. Processing unit, from Graphcore TM Inference processing units (IPUs) or from Intel Corp. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 5AThe inference and / or training logic 515 shown can be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as field programmable gate array (“FPGA”) or data processing unit (DPU).

[0100] Figure 5B Inference and / or training logic 515 according to at least one embodiment is illustrated. In at least one embodiment, the inference and / or training logic 515 may include, but is not limited to, hardware logic, wherein computational resources are dedicated or otherwise uniquely used in conjunction with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 5B The inference and / or training logic 515 shown can be used in conjunction with an application-specific integrated circuit (ASIC), such as those from Google. Processing unit, from Graphcore TM Inference processing units (IPUs) or from Intel Corp. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 5B The inference and / or training logic 515 shown can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (e.g., field-programmable gate array (FPGA) or data processing unit (DPU) hardware). In at least one embodiment, the inference and / or training logic 515 includes, but is not limited to, code and / or data storage 501 and code and / or data storage 505, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 5B In at least one embodiment shown, each of code and / or data storage 501 and code and / or data storage 505 is associated with dedicated computing resources (e.g., computing hardware 502 and computing hardware 506). In at least one embodiment, each of computing hardware 502 and computing hardware 506 includes one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) only on the information stored in code and / or data storage 501 and code and / or data storage 505, respectively, and the results of the function execution are stored in activation storage 520.

[0101] In at least one embodiment, each of the code and / or data storage 501 and 505 and the corresponding computing hardware 502 and 506 corresponds to a different layer of the neural network, such that activation obtained from one “store / computation pair 501 / 502” of the code and / or data storage 501 and computing hardware 502 provides input as input to the next “store / computation pair 505 / 506” of the code and / or data storage 505 and computing hardware 506, in order to reflect the conceptual organization of the neural network. In at least one embodiment, each store / computation pair 501 / 502 and 505 / 506 may correspond to more than one neural network layer. In at least one embodiment, additional store / computation pairs (not shown) may be included in the inference and / or training logic 515 after or in parallel with the store / computation pairs 501 / 502 and 505 / 506.

[0102] Neural network training and deployment

[0103] Figure 6 Training and deployment of a deep neural network according to at least one embodiment are illustrated. In at least one embodiment, an untrained neural network 606 is trained using a training dataset 602. In at least one embodiment, the training framework 604 is the PyTorch framework, while in other embodiments, the training framework 604 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 604 trains the untrained neural network 606 and enables it to be trained using the processing resources described herein to generate a trained neural network 608. In at least one embodiment, the weights may be randomly selected or pre-trained using a deep belief network. In at least one embodiment, training may be performed in a supervised, partially supervised, or unsupervised manner.

[0104] In at least one embodiment, supervised learning is used to train an untrained neural network 606, wherein the training dataset 602 includes inputs paired with desired outputs for input, or wherein the training dataset 602 includes inputs with known outputs and the neural network 606 is manually graded output. In at least one embodiment, the untrained neural network 606 is trained in a supervised manner, and inputs from the training dataset 602 are processed, and the resulting output is compared with a set of expected or desired outputs. In at least one embodiment, errors are then propagated back through the untrained neural network 606. In at least one embodiment, a training framework 604 adjusts the weights controlling the untrained neural network 606. In at least one embodiment, the training framework 604 includes tools for monitoring the degree to which the untrained neural network 606 converges to a model (e.g., a trained neural network 606) adapted to generate the correct answer (e.g., result 614) based on input data (e.g., a new dataset 612). In at least one embodiment, the training framework 604 repeatedly trains the untrained neural network 606 while adjusting the weights to improve the output of the untrained neural network 606 using a loss function and tuning algorithms (e.g., stochastic gradient descent). In at least one embodiment, the training framework 604 trains an untrained neural network 606 until the untrained neural network 606 reaches the desired accuracy. In at least one embodiment, the trained neural network 608 can then be deployed to perform any number of machine learning operations.

[0105] In at least one embodiment, unsupervised learning is used to train an untrained neural network 606, wherein the untrained neural network 606 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 602 will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 606 can learn groupings within the training dataset 602 and can determine how each input relates to the untrained dataset 602. In at least one embodiment, unsupervised training can be used to generate a self-organizing graph in a trained neural network 608, which is capable of performing operations useful for reducing the dimensionality of the new dataset 612. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows the identification of data points in the new dataset 612 that deviate from the normal patterns of the new dataset 612.

[0106] In at least one embodiment, semi-supervised learning can be used, a technique in which a mixture of labeled and unlabeled data is included in the training dataset 602. In at least one embodiment, the training framework 604 can be used to perform incremental learning, for example, through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 608 to adapt to a new dataset 612 without forgetting the knowledge injected into the trained neural network 608 during initial training.

[0107] Data Center

[0108] Figure 7 An example data center 700 that can be used with at least one embodiment is shown. In at least one embodiment, the data center 700 includes a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0109] In at least one embodiment, such as Figure 7 As shown, the data center infrastructure layer 710 may include a resource coordinator 712, grouped computing resources 714, and node computing resources (“nodes CR”) 716(1)-716(N), where “N” represents a positive integer (which may be an integer “N” different from the integers used in other diagrams). In at least one embodiment, nodes CR 716(1)-716(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, data processing units, etc.), memory storage devices 718(1)-718(N) (e.g., dynamic read-only memory, solid-state drives, or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 716(1)-716(N) may be servers having one or more of the aforementioned computing resources.

[0110] In at least one embodiment, the grouped computing resources 714 may include individual groups (not shown) of node CRs housed in one or more racks, or a plurality of racks (also not shown) housed in data centers in various geographical locations. In at least one embodiment, the individual groups of node CRs within the grouped computing resources 714 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0111] In at least one embodiment, resource coordinator 712 may configure or otherwise control one or more nodes CR716(1)-716(N) and / or grouped computing resources 714. In at least one embodiment, resource coordinator 712 may include a Software Design Infrastructure (“SDI”) management entity for data center 700. In at least one embodiment, resource coordinator 712 may include hardware, software, or some combination thereof.

[0112] In at least one embodiment, such as Figure 7 As shown, framework layer 720 includes a job scheduler 722, a configuration manager 724, a resource manager 726, and a distributed file system 728. In at least one embodiment, framework layer 720 may include a framework of software 732 supporting software layer 730 and / or one or more applications 742 supporting application layer 740. In at least one embodiment, software 732 or application 742 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 720 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark, which can utilize distributed file system 728 for large-scale data processing (e.g., "big data"). TM(Hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 722 may include a Spark driver to facilitate the scheduling of workloads supported by various layers of the data center 700. In at least one embodiment, the configuration manager 724 may be able to configure different layers, such as the software layer 730 and the framework layer 720, which includes Spark and a distributed file system 728 for supporting large-scale data processing. In at least one embodiment, the resource manager 726 is able to manage cluster or group computing resources mapped to or allocated to support the distributed file system 728 and the job scheduler 722. In at least one embodiment, the cluster or group computing resources may include group computing resources 714 on the data center infrastructure layer 710. In at least one embodiment, the resource manager 726 may coordinate with the resource coordinator 712 to manage these mapped or allocated computing resources.

[0113] In at least one embodiment, the software 732 included in the software layer 730 may include software used by at least a portion of the nodes CR716(1)-716(N), the grouped computing resources 714, and / or the distributed file system 728 of the framework layer 720. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0114] In at least one embodiment, one or more applications 742 included in application layer 740 may include one or more types of applications used by at least a portion of nodes CR716(1)-716(N), grouped computing resources 714, and / or the distributed file system 728 of framework layer 720. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0115] In at least one embodiment, any of the configuration manager 724, resource manager 726, and resource coordinator 712 can implement any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 700 and can prevent underutilization and / or poor performance of the data center.

[0116] In at least one embodiment, data center 700 may include tools, services, software, or other resources to train one or more machine learning models or to use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described above with respect to data center 700. In at least one embodiment, information can be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to data center 700 by using weight parameters calculated through one or more training techniques described herein.

[0117] In at least one embodiment, the data center may use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, DPU, or other hardware to utilize the aforementioned resources to perform training and / or inference. Furthermore, one or more of the aforementioned software and / or hardware resources may be configured as a service to allow a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0118] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 5A and / or Figure 5B Details are provided regarding the inference and / or training logic 515. In at least one embodiment, the inference and / or training logic 515 can be implemented in the system. Figure 7 Used in this context for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0119] In various embodiments, the data center performs a load balancer as described above, which distributes operations (e.g., transformation of video frames) to CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, DPUs, or other hardware during the execution of video analytics pipelines or other applications.

[0120] autonomous vehicles

[0121] Figure 8AAn example of an autonomous vehicle 800 according to at least one embodiment is shown. In at least one embodiment, the autonomous vehicle 800 (which may alternatively be referred to herein as "vehicle 800") may be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle capable of accommodating one or more passengers. In at least one embodiment, vehicle 800 may be a semi-tractor-trailer for hauling goods. In at least one embodiment, vehicle 800 may be an aircraft, a robotic vehicle, or other type of vehicle.

[0122] Autonomous vehicles can be described according to the levels of automation defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation in their standard “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., standard number J3016-201806, published June 15, 2018; standard number J3016-201609, published September 30, 2016; and previous and future versions of this standard). In at least one embodiment, vehicle 800 may be able to function according to one or more of the levels of autonomous driving from Level 1 to Level 5. For example, in at least one embodiment, vehicle 800 may be able to perform conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5).

[0123] In at least one embodiment, vehicle 800 may include, but is not limited to, components such as chassis, body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 800 may include, but is not limited to, propulsion system 850, such as an internal combustion engine, a hybrid powertrain, an all-electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 850 may be connected to the drivetrain of vehicle 800, which may include, but is not limited to, a transmission, to enable propulsion of vehicle 800. In at least one embodiment, propulsion system 850 may be controlled in response to receiving a signal from throttle / accelerator 852.

[0124] In at least one embodiment, when the propulsion system 850 is operating (e.g., when the vehicle 800 is traveling), the steering system 854 (which may include, but is not limited to, a steering wheel) is used to steer the vehicle 800 (e.g., along a desired path or route). In at least one embodiment, the steering system 854 may receive signals from the steering actuator 856. In at least one embodiment, the steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, the brake sensor system 846 may be used to operate the vehicle brakes in response to signals received from the brake actuator 848 and / or brake sensors.

[0125] In at least one embodiment, the controller 836 may include, but is not limited to, one or more system-on-chips (“SoCs”). Figure 8A A controller 836 (not shown) and / or a graphics processing unit (“GPU”) provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 800. For example, in at least one embodiment, controller 836 may send signals to operate vehicle braking via brake actuator 848, to operate steering system 854 via one or more steering actuators 856, and to operate propulsion system 850 via one or more throttles / accelerators 852. In at least one embodiment, one or more controllers 836 may include one or more onboard (e.g., integrated) computing devices that process sensor signals and output operating commands (e.g., signals representing commands) to enable autonomous driving and / or assist a driver in driving vehicle 800. In at least one embodiment, one or more controllers 836 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the functions described above, and two or more controllers may handle a single function and / or any combination thereof.

[0126] In at least one embodiment, one or more controllers 836 provide signals for controlling one or more components and / or systems of vehicle 800 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from sensors, such as, but not limited to, one or more Global Navigation Satellite System (“GNSS”) sensors 858 (e.g., one or more Global Positioning System sensors), one or more RADAR sensors 860, one or more ultrasonic sensors 862, one or more LIDAR sensors 864, one or more inertial measurement unit (IMU) sensors 866 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 896, one or more stereo cameras 868, one or more wide-angle cameras (e.g., 360-degree cameras), and remote cameras (…). Figure 8A (not shown in the middle), medium-range camera ( Figure 8A (Not shown in the image) One or more speed sensors 844 (e.g., for measuring the speed of vehicle 800), one or more vibration sensors 842, one or more steering sensors 840, one or more brake sensors (e.g., as part of brake sensor system 846) and / or other sensor types are received.

[0127] In at least one embodiment, one or more controllers 836 may receive input (e.g., represented by input data) from the instrument panel 832 of the vehicle 800 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 834, a voice signaler, a speaker, and / or other components of the vehicle 800. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high-definition map). Figure 8A The HMI display 834 may display information such as (not shown in the image), location data (e.g., the location of vehicle 800, for example on a map), direction, the location of other vehicles (e.g., occupancy raster), information about objects, and the state of objects sensed by one or more controllers 836. For example, in at least one embodiment, the HMI display 834 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving operations that the vehicle has made, is making, or will make (e.g., changing lanes now, exiting exit 34B within two miles, etc.).

[0128] In at least one embodiment, vehicle 800 further includes a network interface 824 that can communicate over one or more networks using one or more wireless antennas 826 and / or one or more modems. For example, in at least one embodiment, network interface 824 may be able to communicate over Long Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multicarrier (“CDMA2000”) networks, etc. In at least one embodiment, one or more wireless antennas 826 may also enable communication between objects in the environment (e.g., vehicles, mobile devices) using one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (hereinafter “LPWAN”) (e.g., LoRaWAN, SigFox, etc. protocols).

[0129] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 5A and / or Figure 5B Details are provided regarding the inference and / or training logic 515. In at least one embodiment, the inference and / or training logic 515 can be implemented in the system. Figure 8A The operation is used to infer or predict the operation based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0130] In various embodiments, the data center performs a load balancer as described above, which distributes operations (e.g., transformation of video frames) to CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, DPUs, or other hardware during the execution of video analytics pipelines or other applications.

[0131] Figure 8B The illustration shows an embodiment according to at least one of the embodiments. Figure 8A Examples of camera positions and fields of view for an autonomous vehicle 800. In at least one embodiment, the camera and its respective field of view are exemplary embodiments and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different positions on the vehicle 800.

[0132] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera suitable for use with components and / or systems of vehicle 800. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level (“ASIL”) B and / or other ASILs. In at least one embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 120 fps, 240 fps, etc. In at least one embodiment, the camera may be able to use a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red-to-clear (“RCCC”) color filter array, a red-to-clear-blue (“RCCB”) color filter array, a red-blue-green (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensor (“RGGB”) color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, a transparent pixel camera, such as a camera with an array of RCCC, RCCB and / or RBGC color filters, may be used in an effort to improve photosensitivity.

[0133] In at least one embodiment, one or more cameras may be used to perform advanced driver assistance system (“ADAS”) functions (e.g., as part of a redundancy or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0134] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom-designed (3D-printed) assembly, to cut out stray light and reflections within the vehicle 800 (e.g., reflections from the dashboard in the windshield mirror), which may interfere with the camera's image data capture capability. Regarding the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly may be 3D-printed custom-made such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras may be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras may also be integrated within four pillars at each corner of the cabin.

[0135] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view including a portion of the environment in front of the vehicle 800 can be used for surround view and, with the assistance of one or more controllers 836 and / or control SoCs, to help identify the forward path and obstacles, thereby providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions (e.g., traffic sign recognition).

[0136] In at least one embodiment, various cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS (“complementary metal-oxide-semiconductor”) color imager. In at least one embodiment, a wide-angle camera 870 can be used to sense objects entering from the periphery (e.g., pedestrians, people crossing the street, or bicycles). Although in Figure 8B Only one wide-angle camera 870 is shown; however, in other embodiments, the vehicle 800 may have any number (including zero) of wide-angle cameras. In at least one embodiment, any number of remote cameras 898 (e.g., a pair of remote stereo cameras) can be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, the remote camera 898 can also be used for object detection and classification, as well as basic object tracking.

[0137] In at least one embodiment, any number of stereo cameras 868 may also be included in a forward configuration. In at least one embodiment, one or more stereo cameras 868 may include an integrated control unit comprising a scalable processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of the vehicle 800, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 868 may include, but are not limited to, a compact stereo vision sensor, which may include, but is not limited to, two camera lenses (one on the left and one on the right) and an image processing chip that can measure the distance from the vehicle 800 to a target object and use the generated information (e.g., metadata) to activate autonomous driving emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 868 may also be used in addition to those described herein.

[0138] In at least one embodiment, a camera (e.g., a side-view camera) having a field of view including a portion of the environment on the side of the vehicle 800 can be used for surround viewing, thereby providing information for creating and updating an occupied grid, and generating a side collision warning. For example, in at least one embodiment, a surround camera 874 (e.g., such as...) Figure 8B The four surround cameras shown can be positioned on the vehicle 800. In at least one embodiment, one or more surround cameras 874 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fisheye lenses, one or more 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye lens cameras can be located at the front, rear, and sides of the vehicle 800. In at least one embodiment, the vehicle 800 can use three surround cameras 874 (e.g., left, right, and rear) and can utilize one or more other cameras (e.g., forward-facing cameras) as a fourth surround-view camera.

[0139] In at least one embodiment, a camera having a field of view including a portion of the environment behind the vehicle 800 (e.g., a rear-view camera) can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy raster. In at least one embodiment, a wide variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 898 and / or one or more mid-range cameras 876, one or more stereo cameras 868, one or more infrared cameras 872, etc.), as described herein.

[0140] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. Figure 5A and / or Figure 5B This document provides details regarding inference and / or training logic 515. In at least one embodiment, inference and / or training logic 515 may be... Figure 8B Used in systems for reasoning or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0141] Figure 8C The illustration shows an embodiment according to at least one of the embodiments. Figure 8A A block diagram of an example system architecture for an autonomous vehicle 800. In at least one embodiment, Figure 8CEach of one or more components, one or more features, and one or more systems of vehicle 800 is shown as connected via bus 802. In at least one embodiment, bus 802 may include, but is not limited to, a CAN data interface (which may alternatively be referred to herein as “CAN bus”). In at least one embodiment, CAN may be a network within vehicle 800 used to help control various features and functions of vehicle 800, such as brake actuation, acceleration, braking, steering, windshield wipers, etc. In one embodiment, bus 802 may be configured to have dozens or even hundreds of nodes, each node having its own unique identifier (e.g., CAN ID). In at least one embodiment, bus 802 can be read to find steering wheel angle, ground speed, engine rotation speed (“RPM”), button position, and / or other vehicle status indicators. In at least one embodiment, bus 802 may be an ASIL B compliant CAN bus.

[0142] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or from CAN. In at least one embodiment, there may be any number of molded buses 802, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for a collision avoidance function, and a second bus may be used for actuation control. In at least one embodiment, each of the buses 802 may communicate with any component of the vehicle 800, and two or more buses 802 may communicate with corresponding components. In at least one embodiment, each of any number of system-on-chip (“SoC”) 804 (e.g., SoC 804(A) and SoC 804(B)), each of one or more controllers 836, and / or each computer within the vehicle may access the same input data (e.g., input from sensors of the vehicle 800) and may be connected to a common bus, such as a CAN bus.

[0143] In at least one embodiment, vehicle 800 may include one or more controllers 836, such as those described herein. Figure 8A As described above. In at least one embodiment, controller 836 can be used for a variety of functions. In at least one embodiment, controller 836 can be coupled to any of various other components and systems of vehicle 800, and can be used to control vehicle 800, artificial intelligence of vehicle 800, infotainment and / or other functions of vehicle 800.

[0144] In at least one embodiment, vehicle 800 may include any number of SoCs 804. In at least one embodiment, each of the SoCs 804 may include, but is not limited to, a central processing unit (“one or more CPUs”) 806, a graphics processing unit (“one or more GPUs”) 808, one or more processors 810, one or more caches 812, one or more accelerators 814, one or more data storage 816, and / or other components and features not shown. In at least one embodiment, one or more SoCs 804 may be used to control vehicle 800 on various platforms and systems. For example, in at least one embodiment, one or more SoCs 804 may be combined with a high-definition (“HD”) map 822 in a system (e.g., the system of vehicle 800), the high-definition map 822 being accessible from one or more servers via a network interface 824. Figure 8C (Not shown in the image) Get map refresh and / or update.

[0145] In at least one embodiment, one or more CPUs 806 may include CPU clusters or CPU complexes (which may alternatively be referred to herein as “CCPLEX”). In at least one embodiment, one or more CPUs 806 may include multiple cores and / or a secondary (“L2”) cache. For example, in at least one embodiment, one or more CPUs 806 may include eight cores in an intercoupled multiprocessor configuration. In at least one embodiment, one or more CPUs 806 may include four dual-core clusters, each cluster having a dedicated L2 cache (e.g., 2MB L2 cache). In at least one embodiment, one or more CPUs 806 (e.g., CCPLEX) may be configured to support simultaneous cluster operation, such that any combination of clusters of one or more CPUs 806 can be active at any given time.

[0146] In at least one embodiment, one or more CPUs 806 may implement power management functions, including but not limited to one or more of the following features: automatic clock gating of individual hardware modules to conserve dynamic power when idle; clock gating of each core when the core is not actively executing instructions due to executing Wait for Interrupt (“WFI”) / Event Wait (“WFE”) instructions; independent power supply for each core; clock gating of each core cluster when all cores are clock-gated or power-gated; and / or power gating of each core cluster when all cores are power-gated. In at least one embodiment, one or more CPUs 806 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power state for cores, clusters, and CCPLEX inputs. In at least one embodiment, the processing core may support a simplified power state input sequence in software, wherein the work is offloaded to the microcode.

[0147] In at least one embodiment, one or more GPUs 808 may include an integrated GPU (or “iGPU” herein). In at least one embodiment, one or more GPUs 808 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 808 may use an enhanced tensor instruction set. In one embodiment, one or more GPUs 808 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a Level 1 (“L1”) cache (e.g., an L1 cache with at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512KB of storage capacity). In at least one embodiment, one or more GPUs 808 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 808 may use a computation application programming interface (API). In at least one embodiment, one or more GPUs 808 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA’s CUDA model).

[0148] In at least one embodiment, one or more GPU 808s may be power-optimized for optimal performance in automotive and embedded use cases. For example, in one embodiment, one or more GPU 808s may be fabricated on FinFET (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores divided into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores may be divided into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor cores for deep learning matrix arithmetic, a level-zero (“L0”) instruction cache, a thread bundle scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths to provide efficient execution of workloads that mix computation and addressing operations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0149] In at least one embodiment, one or more GPUs 808 may include high-bandwidth memory (“HBM”) and / or a 16GB HBM2 memory subsystem to provide a peak storage bandwidth of approximately 900GB / s in some examples. In at least one embodiment, in addition to or instead of HBM memory, synchronous graphics random access memory (“SGRAM”) may be used, such as graphics double data rate type five synchronous random access memory (“GDDR5”).

[0150] In at least one embodiment, one or more GPUs 808 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support can be used to allow one or more GPUs 808 to directly access the page tables of one or more CPUs 806. In at least one embodiment, when a memory management unit (“MMU”) of one or more GPUs 808 experiences a miss, an address translation request can be sent to one or more CPUs 806. In response, in at least one embodiment, two CPUs of one or more CPUs 806 can look up the virtual-physical mapping of the address in their page tables and transfer the translation back to one or more GPUs 808. In at least one embodiment, unified memory technology can allow a single unified virtual address space to be used for the memory of both one or more CPUs 806 and one or more GPUs 808, thereby simplifying the programming of one or more GPUs 808 and porting applications to one or more GPUs 808.

[0151] In at least one embodiment, one or more GPUs 808 may include any number of access counters that can track the frequency with which one or more GPUs 808 access the memory of other processors. In at least one embodiment, one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the pages most frequently, thereby improving the efficiency of shared memory ranges between processors.

[0152] In at least one embodiment, one or more SoCs 804 may include any number of caches 812, including those described herein. For example, in at least one embodiment, one or more caches 812 may include a Level 3 (“L3”) cache available for one or more CPUs 806 and one or more GPUs 808 (e.g., connected to CPUs 806 and GPUs 808). In at least one embodiment, one or more caches 812 may include a write-back cache that can, for example, track the state of a line using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, although a smaller cache size may be used, according to an embodiment, the L3 cache may include 4 MB of memory or more.

[0153] In at least one embodiment, one or more SoCs 804 may include one or more accelerators 814 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 804 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) enables the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 808 and offload some tasks from one or more GPUs 808 (e.g., freeing up more cycles of one or more GPUs 808 to perform other tasks). In at least one embodiment, one or more accelerators 814 may be used for a target workload (e.g., perceptual, convolutional neural network (“CNN”), recurrent neural network (“RNN”), etc.) that is sufficiently stable to withstand acceleration testing. In at least one embodiment, the CNN may include region-based or region convolutional neural networks (“RCNN”) and fast RCNN (e.g., for object detection) or other types of CNNs.

[0154] In at least one embodiment, one or more accelerators 814 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more Tensor Processing Units (“TPUs”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized for performing image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, one or more DLAs may be further optimized for specific sets of neural network types and floating-point operations and inference. In at least one embodiment, one or more DLAs are designed to provide higher performance per millimeter than typical general-purpose GPUs and typically significantly outperform CPUs. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions supporting, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can execute neural networks, particularly CNNs, quickly and efficiently on processed or unprocessed data for any of the various functions, including, but not limited to: CNNs for object recognition and detection using data from camera sensors; CNNs for distance estimation using data from camera sensors; CNNs for emergency vehicle detection, recognition, and identification using data from microphones; CNNs for face recognition and vehicle owner recognition using data from camera sensors; and / or CNNs for safety and / or safety-related events.

[0155] In at least one embodiment, the DLA can perform any function of one or more GPUs 808, and by using inference accelerators, for example, the designer can target one or more DLAs or one or more GPUs 808 for any function. For example, in at least one embodiment, the designer can centralize the CNN processing and floating-point operations on one or more DLAs, leaving other functions to one or more GPUs 808 and / or one or more accelerators 814.

[0156] In at least one embodiment, one or more accelerators 814 may include programmable vision accelerators (“PVAs”), which may alternatively be referred to herein as computer vision accelerators. In at least one embodiment, one or more PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 838, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, one or more PVAs may strike a balance between performance and flexibility. For example, in at least one embodiment, each of one or more PVAs may include, for example, but not limited to, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0157] In at least one embodiment, the RISC core can interact with an image sensor (e.g., the image sensor of any camera described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any number of memories. In at least one embodiment, the RISC core may use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system (“RTOS”). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application-specific integrated circuits (“ASICs”), and / or storage devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0158] In at least one embodiment, DMA enables components of the PVA to access system memory independently of one or more CPU 806s. In at least one embodiment, DMA can support any number of features for providing optimization to the PVA, including but not limited to, support for multidimensional addressing and / or circular addressing. In at least one embodiment, DMA can support up to six or more addressing dimensions, which may include, but are not limited to, block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0159] In at least one embodiment, the vector processor may be a programmable processor designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may serve as the main processing engine of the PVA and may include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core may include a digital signal processor, such as a Single Instruction Multiple Data (“SIMD”) or Very Long Instruction Word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can improve throughput and speed.

[0160] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute general-purpose computer vision algorithms, except on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on a single image, or even execute different algorithms on a sequence of images or portions of images. In at least one embodiment, among others, any number of PVAs may be included in the hardware-accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error-correcting code (“ECC”) memory to enhance overall system security.

[0161] In at least one embodiment, one or more accelerators 814 may include an on-chip computer vision network and static random access memory (“SRAM”) for providing high-bandwidth, low-latency SRAM to one or more accelerators 814. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, comprising, for example, but not limited to, eight field-configurable memory blocks accessible to both the PVA and DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory via a backbone providing high-speed access to the memory for both the PVA and DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using an APB).

[0162] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as bursty communication for continuous data transmission. In at least one embodiment, although other standards and protocols may be used, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 61508 standard.

[0163] In at least one embodiment, one or more SoCs 804 may include a real-time eye-tracking hardware accelerator. In at least one embodiment, the real-time eye-tracking hardware accelerator may be used to quickly and efficiently determine the location and extent of an object (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulation, for comparison with LIDAR data for localization and / or other functions, and / or for other purposes.

[0164] In at least one embodiment, one or more accelerators 814 have broad applications for autonomous driving. In at least one embodiment, PVA can be used in critical processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of PVA with low power consumption and low latency are well-matched to algorithmic domains requiring predictable processing. In other words, PVA performs well in semi-intensive or intensive conventional computations, even on small datasets that may require predictable runtimes with low latency and low power consumption. In at least one embodiment, such as in vehicle 800, PVA may be designed to run classical computer vision algorithms, as they are efficient in object detection and integer mathematical operations.

[0165] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use dynamic estimation / stereo matching (e.g., structure recovery from motion, pedestrian recognition, lane detection, etc.) during operation. In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0166] In at least one embodiment, the PVA can be used to perform intensive optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0167] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, but not limited to, neural networks whose output is used for a confidence score for each object detection. In at least one embodiment, the confidence score can be represented or interpreted as a probability, or as providing a relative “weight” for each detection relative to other detections. In at least one embodiment, the confidence score measurement enables the system to make further decisions about which detections should be considered true positives rather than false positives. In at least one embodiment, the system can set a threshold for the confidence score and only consider detections exceeding the threshold as true positives. In embodiments using an Automatic Emergency Braking (“AEB”) system, false positives would cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence score value. In at least one embodiment, the neural network may take at least a subset of parameters as its input, such as bounding box size, obtained ground plane estimate (e.g., from another subsystem), and outputs of one or more IMU sensors 866 related to the vehicle 800 orientation, distance, and 3D position estimate of the object obtained from the neural network and / or other sensors (e.g., one or more LiDAR sensors 864 or one or more RADAR sensors 860).

[0168] In at least one embodiment, one or more SoCs 804 may include one or more data storage devices 816 (e.g., memory). In at least one embodiment, one or more data storage devices 816 may be on-chip memory of one or more SoCs 804, which may store neural networks to be executed on one or more GPUs 808 and / or DLAs. In at least one embodiment, one or more data storage devices 816 may have a sufficiently large capacity to store multiple instances of the neural network for redundancy and security. In at least one embodiment, one or more data storage devices 816 may include L2 or L3 caches.

[0169] In at least one embodiment, one or more SoCs 804 may include any number of processors 810 (e.g., embedded processors). In at least one embodiment, one or more processors 810 may include a startup and power management processor, which may be a dedicated processor and subsystem for handling startup power and management functions, as well as associated security implementations. In at least one embodiment, the startup and power management processor may be part of a startup sequence of one or more SoCs 804s and may provide runtime power management services. In at least one embodiment, the startup power and management processor may provide clock and voltage programming, assist system low-power state transitions, thermal and temperature sensor management of one or more SoCs 804s, and / or power state management of one or more SoCs 804s. In at least one embodiment, each temperature sensor may be implemented with its output frequency proportional to temperature, and one or more SoCs 804s may use the ring oscillator to detect the temperature of one or more CPUs 806s, one or more GPUs 808s, and / or one or more accelerators 814s. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the startup and power management processor may enter a temperature fault routine and place one or more SoCs 804s into a lower power state and / or place the vehicle 800 into a driver's safe stopping pattern (e.g., bring the vehicle 800 to a safe stop).

[0170] In at least one embodiment, one or more processors 810 may further include a set of embedded processors that can serve as an audio processing engine. The audio processing engine may be an audio subsystem capable of providing full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core with a digital signal processor having dedicated RAM.

[0171] In at least one embodiment, one or more processors 810 may further include an always-on processor engine that can provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the processor on the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, peripheral support devices (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0172] In at least one embodiment, one or more processors 810 may further include a secure cluster engine, which includes, but is not limited to, a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the secure cluster engine may include, but is not limited to, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In secure mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 810 may further include a real-time camera engine, which may include, but is not limited to, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 810 may further include a high dynamic range signal processor, which may include, but is not limited to, an image signal processor, which is a hardware engine as part of the camera processing pipeline.

[0173] In at least one embodiment, one or more processors 810 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by the video playback application to produce the final image for the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 870, one or more surround cameras 874, and / or one or more cabin monitoring camera sensors. In at least one embodiment, preferably, the cabin monitoring camera sensors are monitored by a neural network running on another instance of the SoC 804, the neural network being configured to recognize cabin events and respond accordingly. In at least one embodiment, the cabin system may perform, but is not limited to, lip reading to activate cellular service and make phone calls, instruct emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web browsing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous driving mode, and are otherwise disabled.

[0174] In at least one embodiment, the video image synthesizer may include enhanced temporal denoising for simultaneous spatial and temporal denoising. For example, in at least one embodiment, when motion occurs in the video, denoising appropriately weights spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, when the image or a portion of the image does not contain motion, temporal denoising performed by the video image synthesizer may use information from previous images to reduce noise in the current image.

[0175] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic correction on the input stereo lens frames. In at least one embodiment, when using an operating system desktop, the video image compositor can also be used for user interface compositing and does not require one or more GPUs 808 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 808 are powered and actively performing 3D rendering, the video image compositor can be used to offload one or more GPUs 808 to improve performance and responsiveness.

[0176] In at least one embodiment, one or more SoCs of SoC 804 may further include a Mobile Industrial Processor Interface (“MIPI”) camera serial interface, a high-speed interface, and / or a video input block that can be used for receiving video and input from a camera and associated pixel input functions. In at least one embodiment, one or more SoCs of SoC 804 may further include an input / output controller that can be software controlled and can be used to receive I / O signals not assigned to a specific role.

[0177] In at least one embodiment, one or more SoCs of SoC 804 may further include extensive peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders (“codecs”), power management and / or other devices. In at least one embodiment, one or more SoCs of SoC 804 may be used to process data from (e.g., connected via gigabit multimedia serial links and Ethernet channels) cameras, sensors (e.g., one or more LiDAR sensors 864, one or more RADAR sensors 860, etc., which may be connected via Ethernet channels), data from bus 802 (e.g., vehicle 800 speed, steering wheel position, etc.), data from one or more GNSS sensors 858 (e.g., connected via Ethernet bus or CAN bus), etc. In at least one embodiment, one or more SoCs of SoC 804 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to free one or more CPUs 806 from routine data management tasks.

[0178] In at least one embodiment, one or more SoCs 804 can be an end-to-end platform with a flexible architecture spanning automation levels 3-5, providing a comprehensive functional safety architecture that leverages and effectively utilizes computer vision and ADAS technologies to achieve diversity and redundancy. This provides a platform offering a flexible and reliable driving software stack as well as deep learning tools. In at least one embodiment, one or more SoCs 804 can be faster, more reliable, and even more energy and space efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 814, when combined with one or more CPUs 806, one or more GPUs 808, and one or more data storage devices 816, can provide a fast and efficient platform for Level 3-5 autonomous vehicles.

[0179] In at least one embodiment, the computer vision algorithm can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute multiple processing algorithms on a variety of visual data. However, in at least one embodiment, the CPU typically cannot meet the performance requirements of many computer vision applications, such as performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real time, which are used in automotive ADAS applications and practical Level 3-5 autonomous vehicles.

[0180] The embodiments described herein allow multiple neural networks to be executed simultaneously and / or sequentially, and allow the results to be combined to achieve Level 3-5 autonomous driving capabilities. For example, in at least one embodiment, a CNN executed on a DLA or discrete GPU (e.g., one or more GPU 820s) may include text and word recognition, thereby allowing a supercomputer to read and understand traffic signs, including signs for which the neural network has not yet been specifically trained. In at least one embodiment, the DLA may also include a neural network capable of recognizing, interpreting, and providing semantic understanding of symbols, and passing this semantic understanding to a path planning module running on a CPU Complex.

[0181] In at least one embodiment, for drives of levels 3, 4, or 5, multiple neural networks can run simultaneously. For example, in at least one embodiment, a warning sign consisting of a light bulb accompanied by the warning sign “Caution: flashing lights indicate icy conditions” can be interpreted independently or jointly by multiple neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text “flashing lights indicate icy conditions” can be interpreted by a second deployed neural network, which informs the vehicle’s path planning software (preferably executed on a CPU complex) that icing conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network across multiple frames, informing the vehicle’s path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within a DLA and / or on one or more GPU 808s.

[0182] In at least one embodiment, the CNN for facial recognition and vehicle owner identification can use data from camera sensors to identify the presence of an authorized driver and / or the owner of vehicle 800. In at least one embodiment, a normally open sensor processor engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in security mode, can be used to disable the vehicle when the owner leaves it. In this way, one or more SoCs 804 provide protection against theft and / or carjacking.

[0183] In at least one embodiment, the CNN for emergency vehicle detection and identification can use data from microphone 896 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 804 use the CNN to classify environmental and urban sounds, as well as visual data. In at least one embodiment, the CNN running on DLA is trained to identify the relative approach speed of emergency vehicles (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles in the area where the vehicle is operating, as identified by one or more GNSS sensors 858. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while in North America, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used, with the assistance of one or more ultrasonic sensors 862, to execute emergency vehicle safety routines, slow the vehicle, pull the vehicle to the side of the road, stop, and / or leave the vehicle idle until the emergency vehicle passes.

[0184] In at least one embodiment, vehicle 800 may include one or more CPUs 818 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to one or more SoCs 804 via high-speed interconnects (e.g., PCIe). In at least one embodiment, one or more CPUs 818 may include x86 processors. For example, one or more CPUs 818 may be used to perform any of the various functions, such as arbitrating the results of potential inconsistencies between ADAS sensors and one or more SoCs 804, and / or monitoring the status and health of one or more monitoring controllers 836 and / or on-chip information systems (“information SoCs”) 830.

[0185] In at least one embodiment, vehicle 800 may include one or more GPUs 820 (e.g., one or more discrete GPUs or one or more dGPUs) coupled to one or more SoCs 804 via high-speed interconnects (e.g., NVIDIA's NVLINK channels). In at least one embodiment, one or more GPUs 820 may provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on inputs from sensors of vehicle 800 (e.g., sensor data).

[0186] In at least one embodiment, vehicle 800 may further include a network interface 824, which may include, but is not limited to, one or more wireless antennas 826 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 824 may be used to enable wireless connectivity with other vehicles and / or computing devices (e.g., passenger client devices) via Internet cloud services (e.g., using servers and / or other network devices). In at least one embodiment, for communication with other vehicles, a direct link and / or an indirect link (e.g., via a network and the Internet) may be established between vehicle 80 and another vehicle. In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide a direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 800 with information about vehicles near vehicle 80 (e.g., vehicles in front, to the side, and / or behind vehicle 800). In at least one embodiment, the foregoing functionality may be part of a cooperative adaptive cruise control function of vehicle 800.

[0187] In at least one embodiment, network interface 824 may include a System-on-Chip (SoC) that provides modulation and demodulation functions and enables one or more controllers 836 to communicate over a wireless network. In at least one embodiment, network interface 824 may include a radio frequency (RF) front-end for up-conversion from baseband to radio frequency (RF) and down-conversion from RF to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed using known processes and / or using a superheterodyne process. In at least one embodiment, the RF front-end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functions for communication via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0188] In at least one embodiment, vehicle 800 may further include one or more data storage units 828, which may include, but are not limited to, off-chip (e.g., one or more SoC 804) storage. In at least one embodiment, one or more data storage units 828 may include, but are not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disk and / or other components and / or devices capable of storing at least one bit of data.

[0189] In at least one embodiment, the vehicle 800 may further include one or more GNSS sensors 858 (e.g., GPS and / or auxiliary GPS sensors) to assist in map creation, perception, occupancy raster generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 858 may be used, including, for example, but not limited to, GPS sensors connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

[0190] In at least one embodiment, vehicle 800 may further include one or more RADAR sensors 860. In at least one embodiment, one or more RADAR sensors 860 may be used by vehicle 800 for remote vehicle detection, even in dark and / or inclement weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, one or more RADAR sensors 860 may use a CAN bus and / or bus 802 (e.g., to transmit data generated by one or more RADAR sensors 860) for control and access to object tracking data, and in some examples may access an Ethernet channel to access raw data. In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, but not limited to, one or more of the RADAR sensors 860 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more RADAR sensors 860 are pulse Doppler RADAR sensors.

[0191] In at least one embodiment, one or more RADAR sensors 860 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a 250m range). In at least one embodiment, one or more RADAR sensors 860 can help distinguish between stationary and moving objects and can be used by the ADAS system 838 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more sensors 860 included in the long-range RADAR system may include, but are not limited to, a monostatic multimode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, having six antennas, with the four central antennas creating a focused beammap designed to record the vehicle 800's surroundings at a high speed while minimizing traffic interference from adjacent lanes. In at least one embodiment, the other two antennas can expand the field of view, thereby enabling rapid detection of vehicles 800 entering or leaving the lane.

[0192] In at least one embodiment, as an example, a mid-range RADAR system may include, for example, a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 860 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that continuously monitor the rearward direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system may be used in ADAS system 838 for blind spot detection and / or lane change assistance.

[0193] In at least one embodiment, the vehicle 800 may further include one or more ultrasonic sensors 862. In at least one embodiment, one or more ultrasonic sensors 862, which may be positioned at the front, rear, and / or sides of the vehicle 800, may be used for parking assistance and / or creating and updating occupancy detectors. In at least one embodiment, a wide variety of ultrasonic sensors 862 may be used, and different ultrasonic sensors 862 may be used for different detection ranges (e.g., 2.5m, 4m). In at least one embodiment, the ultrasonic sensors 862 may operate at the ASIL B functional safety level.

[0194] In at least one embodiment, vehicle 800 may include one or more LiDAR sensors 864. In at least one embodiment, one or more LiDAR sensors 864 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, one or more LiDAR sensors 864 may operate at functional safety level ASIL B. In at least one embodiment, vehicle 800 may include multiple (e.g., two, four, six, etc.) LiDAR sensors 864 that can use Ethernet channels (e.g., providing data to a Gigabit Ethernet switch).

[0195] In at least one embodiment, one or more LiDAR sensors 864 may be able to provide a list of objects and their distances for a 360-degree field of view. In at least one embodiment, one or more commercially available LiDAR sensors 864 may, for example, have an advertising range of approximately 100m, an accuracy of 2cm-3cm, and support a 100Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LiDAR sensors may be used. In such an embodiment, one or more LiDAR sensors 864 may include small devices that can be embedded in the front, rear, side, and / or corner locations of a vehicle 800. In at least one embodiment, one or more LiDAR sensors 864, in such an embodiment, can provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for objects with low reflectivity, and have a range of 200m. In at least one embodiment, one or more forward-facing LiDAR sensors 864 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0196] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200m around the vehicle 800. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and reflected light on each pixel, which in turn corresponds to the range from the vehicle x800 to the object. In at least one embodiment, flash LIDAR can allow the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of the vehicle 800. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use a 5-nanosecond Class I (eye-safe) laser pulse per frame and can capture reflected laser light as a 3D ranging point cloud and co-registered intensity data.

[0197] In at least one embodiment, vehicle 800 may further include one or more IMU sensors 866. In at least one embodiment, one or more IMU sensors 866 may be located at the center of the rear axle of vehicle 800. In at least one embodiment, one or more IMU sensors 866 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, a magnetic compass, multiple magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, one or more IMU sensors 866 may include, but are not limited to, accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, one or more IMU sensors 866 may include, but are not limited to, accelerometers, gyroscopes, and magnetometers.

[0198] In at least one embodiment, one or more IMU sensors 866 may be implemented as a miniature, high-performance GPS-assisted inertial navigation system (“GPS / INS”) combining a microelectromechanical system (“MEMS”) inertial sensor, a high-sensitivity GPS receiver, and an advanced Kalman filtering algorithm to provide position, velocity, and attitude estimations; in at least one embodiment, one or more IMU sensors 866 may enable vehicle 800 to estimate heading without input from a magnetic sensor obtained by directly observing and correlating velocity changes from GPS to one or more IMU sensors 866. In at least one embodiment, one or more IMU sensors 866 and one or more GNSS sensors 858 may be combined in a single integrated unit.

[0199] In at least one embodiment, vehicle 800 may include one or more microphones 896 placed inside and / or around vehicle 800. In at least one embodiment, in addition, one or more microphones 896 may be used for emergency vehicle detection and identification.

[0200] In at least one embodiment, vehicle 800 may further include any number of camera types, including one or more stereo cameras 868, one or more wide-angle cameras 870, one or more infrared cameras 872, one or more surround cameras 874, one or more long-range cameras 898, one or more mid-range cameras 876, and / or other camera types. In at least one embodiment, the cameras can be used to capture image data around the entire perimeter of vehicle 800. In at least one embodiment, the type of camera used depends on vehicle 800. In at least one embodiment, any combination of camera types can be used to provide the necessary coverage around vehicle 800. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, vehicle 800 may include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. In at least one embodiment, the cameras may be, by way of example but not limited to, supporting Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet communication. In at least one embodiment, previously referenced herein... Figure 8A and Figure 8B Each camera can be described in more detail.

[0201] In at least one embodiment, the vehicle 800 may further include one or more vibration sensors 842. In at least one embodiment, the one or more vibration sensors 842 may measure vibrations of components of the vehicle 800 (e.g., axles). For example, in at least one embodiment, changes in vibration may indicate changes in road surface conditions. In at least one embodiment, when two or more vibration sensors 842 are used, differences between vibrations may be used to determine road surface friction or slippage (e.g., when there is a vibration difference between a power drive axle and a free-rotating axle).

[0202] In at least one embodiment, vehicle 800 may include ADAS system 838. In at least one embodiment, ADAS system 838 may include, but is not limited to, SoC. In at least one embodiment, ADAS system 838 may include, but is not limited to, any number of automated driving / adaptive / automatic cruise control (“ACC”) systems, cooperative adaptive cruise control (“CACC”) systems, forward collision warning (“FCW”) systems, automatic emergency braking (“AEB”) systems, lane departure warning (“LDW”) systems, lane keeping assist (“LKA”) systems, blind spot warning (“BSW”) systems, rear cross traffic warning (“RCTW”) systems, collision warning (“CW”) systems, lane centering (“LC”) systems, and / or other systems, features, and / or functions, and combinations thereof.

[0203] In at least one embodiment, the ACC system may use one or more RADAR sensors 860, one or more LIDAR sensors 864, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle adjacent to vehicle 800 and automatically adjusts the speed of vehicle 800 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance holding and suggests that vehicle 800 change lanes when necessary. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0204] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from other vehicles via network interface 824 and / or one or more wireless antennas 826 via a wireless link or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. Typically, V2V communication provides information about the vehicle immediately preceding it (e.g., a vehicle immediately in front of vehicle 800 and in the same lane as it), while I2V communication provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about vehicles preceding vehicle 800, the CACC system can be more reliable and has the potential to improve traffic flow smoothness and reduce road congestion.

[0205] In at least one embodiment, the FCW system is designed to warn the driver of danger so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 860, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to components providing driver feedback, such as a display, speaker, and / or vibration. In at least one embodiment, the FCW system can provide warnings, for example, in the form of audible, visual warnings, vibrations, and / or rapid braking pulses.

[0206] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply brakes if the driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system may use one or more forward-facing cameras and / or one or more RADAR sensors 860 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid a collision, and if the driver does not take corrective action, the AEB system may automatically apply brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic braking to support and / or brakes for impending collisions.

[0207] In at least one embodiment, when vehicle 800 crosses lane markings, the LDW system provides visual, auditory, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver. In at least one embodiment, the LDW system is inactive when the driver indicates intentional lane departure, such as by activating turn signals. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variant of the LDW system. In at least one embodiment, if vehicle 800 begins to leave the lane, the LKA system provides steering input or braking to correct vehicle 800.

[0208] In at least one embodiment, the BSW system detects and warns the driver of a vehicle in the blind spot. In at least one embodiment, the BSW system can provide visual, auditory, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses the turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 860 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to driver feedback, such as a display, speaker, and / or vibration assembly.

[0209] In at least one embodiment, the RCTW system can provide visual, auditory, and / or tactile notifications when an object is detected outside the range of the rear camera while the vehicle 800 is reversing. In at least one embodiment, the RCTW system includes an AEB system to ensure the vehicle brakes to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear-facing RADAR sensors 860 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as displays, speakers, and / or vibration components.

[0210] In at least one embodiment, conventional ADAS systems may be prone to generating false alarms, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems warn the driver and allow the driver to determine whether a safe situation truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, the vehicle 800 itself decides whether to follow the result of the primary computer or the secondary computer (e.g., the first or second controller of controller 836). For example, in at least one embodiment, ADAS system 838 may be a backup and / or auxiliary computer for providing perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor may run redundant software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, the output from ADAS system 838 may be provided to a monitoring MCU. In at least one embodiment, if the output from the autonomous driving computer and the output from the auxiliary computer conflict, the monitoring MCU decides how to reconcile the conflict to ensure safe operation.

[0211] In at least one embodiment, the master computer may be configured to provide a confidence score to the supervisory MCU to indicate the master computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU may follow the master computer's instructions regardless of whether the auxiliary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the master computer and the auxiliary computer indicate different results (e.g., conflicting), the supervisory MCU may arbitrate between the computers to determine the appropriate result.

[0212] In at least one embodiment, the supervisory MCU may be configured to run a neural network trained and configured to determine, at least in part, the conditions under which the assistive computer provides false alarms based on the outputs from the autonomous driving computer and the assistive computer. In at least one embodiment, the neural network in the supervisory MCU may learn when the outputs of the assistive computer can be trusted and when they cannot. For example, in at least one embodiment, when the assistive computer is a RADAR-based FCW system, the neural network in the supervisory MCU may learn when the FCW system recognizes a metallic object that is not actually dangerous, such as a drain grille or manhole cover that would trigger an alarm. In at least one embodiment, when the assistive computer is a camera-based LDW system, the neural network in the supervisory MCU may learn to override the LDW when a cyclist or pedestrian is present and lane departure is actually the safest operation. In at least one embodiment, the supervisory MCU may include at least one of a DLA or GPU suitable for running a neural network with associated memory. In at least one embodiment, the supervisory MCU may include and / or be included as a component of one or more SoC 804s.

[0213] In at least one embodiment, the ADAS system 838 may include an auxiliary computer that performs ADAS functions using conventional computer vision rules. In at least one embodiment, the auxiliary computer may use classic computer vision rules (if-then), and the presence of a neural network in the supervisory MCU can improve reliability, security, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if a software vulnerability or bug exists in the software running on the host computer, and different software code running on the auxiliary computer provides consistent overall results, the supervisory MCU can more confidently assume that the overall result is correct and that the vulnerability in the software or hardware on the host computer will not lead to a significant error.

[0214] In at least one embodiment, the output of the ADAS system 838 can be input to the perception module and / or the dynamic driving task module of the host computer. For example, in at least one embodiment, if the ADAS system 838 indicates a forward collision warning due to an object directly ahead, the perception block can use this information when identifying the object. In at least one embodiment, as described herein, the assistance computer can have its own neural network trained to reduce the risk of false alarms.

[0215] In at least one embodiment, vehicle 800 may further include an infotainment SoC 830 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 830 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 830 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming media, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.) and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total coverage distance, brake fuel level, fuel level, door opening / closing, air filter information, etc.) to vehicle 800. For example, the infotainment SoC 830 may include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, automobile, in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, head-up display (“HUD”), HMI display 834, telematics device, control panel (e.g., for controlling and / or interacting with various components, features and / or systems) and / or other components. In at least one embodiment, the infotainment SoC 830 may further be used to provide information (e.g., visual and / or auditory) to users of vehicle 800, such as information from ADAS system 838, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.) and / or other information.

[0216] In at least one embodiment, the infotainment SoC 830 may include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 830 may communicate with other devices, systems, and / or components of the vehicle 800 via bus 802. In at least one embodiment, the infotainment SoC 830 may be coupled to a monitoring MCU, enabling the GPU of the infotainment system to perform some autonomous driving functions in the event of a failure of the main controller 836 (e.g., the main computer and / or backup computer of the vehicle 800). In at least one embodiment, the infotainment SoC 830 may cause the vehicle 800 to enter a driver-to-safe-stop mode, as described herein.

[0217] In at least one embodiment, vehicle 800 may further include instrument panel 832 (e.g., digital instrument panel, electronic instrument panel, digital instrument control panel, etc.). In at least one embodiment, instrument panel 832 may include, but is not limited to, controllers and / or supercomputers (e.g., discrete controllers or supercomputers). In at least one embodiment, instrument panel 832 may include, but is not limited to, any number and combination of a set of instruments, such as speedometer, fuel level, oil pressure, tachometer, odometer, turn indicator, shift position indicator, one or more seatbelt warning lights, one or more parking brake warning lights, one or more engine malfunction lights, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between infotainment SoC 830 and instrument panel 832. In at least one embodiment, instrument panel 832 may be included as part of infotainment SoC 830, or vice versa.

[0218] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 5A and / or Figure 5B Details are provided regarding the inference and / or training logic 515. In at least one embodiment, the inference and / or training logic 515 can be implemented in the system. Figure 8C The operation is used to infer or predict the operation based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0219] Figure 8D It is based on at least one embodiment in a cloud-based server and Figure 8AA diagram of a system for communication between autonomous vehicles 800. In at least one embodiment, the system may include, but is not limited to, one or more servers 878, one or more networks 890, and any number and type of vehicles, including vehicle 800. In at least one embodiment, one or more servers 878 may include, but is not limited to, multiple GPUs 884(A)-884(H) (collectively referred to herein as GPU 884), PCIe switches 882(A)-882(D) (collectively referred to herein as PCIe switch 882), and / or CPUs 880(A)-880(B) (collectively referred to herein as CPU 880). GPU 884, CPU 880, and PCIe switch 882 may be interconnected with high-speed interconnects, such as, but not limited to, NVLink interface 888 developed by NVIDIA and / or PCIe connection 886. In at least one embodiment, GPU 884 is connected via NVLink and / or NVSwitchSoC, and GPU 884 and PCIe switch 882 are connected via PCIe interconnect. Although eight GPUs 884, two CPUs 880, and four PCIe switches 882 are shown, this is not intended to be limiting. In at least one embodiment, each of one or more servers 878 may include, but is not limited to, any combination of any number of GPUs 884, CPUs 880, and / or PCIe switches 882. For example, in at least one embodiment, one or more servers 878 may each include eight, sixteen, thirty-two, and / or more GPUs 884.

[0220] In at least one embodiment, one or more servers 878 may receive image data representing images from vehicles via one or more networks 890, the images showing unexpected or changed road conditions, such as recently commenced roadworks. In at least one embodiment, one or more servers 878 may transmit updated neural network 892 and / or map information 894, including but not limited to information about traffic and road conditions, to vehicles via one or more networks 890. In at least one embodiment, updates to map information 894 may include, but are not limited to, updates to HD map 822, such as information about construction sites, potholes, sidewalks, floods, and / or other obstacles. In at least one embodiment, neural network 892 and / or map information 894 may be generated from new training and / or experience represented by data received from any number of vehicles in the environment, and / or at least based on training performed in a data center (e.g., using one or more servers 878 and / or other servers).

[0221] In at least one embodiment, one or more servers 878 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. In at least one embodiment, the training data may be generated by the vehicle, and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of training data is labeled and / or preprocessed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 890), and / or the machine learning model may be used by one or more servers 878 to remotely monitor the vehicle.

[0222] In at least one embodiment, one or more servers 878 may receive data from a vehicle and apply the data to state-of-the-art real-time neural networks for real-time intelligent inference. In at least one embodiment, one or more servers 878 may include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 884, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 878 may include a deep learning infrastructure in a data center using CPU power.

[0223] In at least one embodiment, the deep learning infrastructure of one or more servers 878 may be capable of fast, real-time inference and can use this capability to assess and verify the health of the processor, software, and / or associated hardware in vehicle 800. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 800, such as image sequences and / or objects located by vehicle 800 in the image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them with objects identified by vehicle 800, and if the results do not match and the deep learning infrastructure determines that the AI ​​in vehicle 800 is malfunctioning, one or more servers 878 may signal to vehicle 800 to instruct the fail-safe computer of vehicle 800 to take control, notify passengers, and complete a safe stopping operation.

[0224] In at least one embodiment, one or more servers 878 may include one or more GPUs 884 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT3 devices). In at least one embodiment, the combination of GPU-driven servers and inference acceleration enables real-time response. In at least one embodiment, for example, where performance is less critical, servers driven by CPUs, FPGAs, and other processors may be used for inference. In at least one embodiment, hardware architecture 515 is used to execute one or more embodiments. This document incorporates... Figure 5A and / or Figure 5B Provide details about the hardware architecture of 515.

[0225] Computer System

[0226] Figure 9 This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system of interconnected devices and components, a system-on-a-chip (SoC), or some combination thereof formed with a processor, which may include an execution unit to execute instructions. In at least one embodiment, according to this disclosure, such as the embodiments described herein, computer system 900 may include, but is not limited to, components such as processor 902, whose execution unit includes logic to execute algorithms for process data. In at least one embodiment, computer system 900 may include a processor, such as one available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM A microprocessor may be used, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors may also be used. In at least one embodiment, computer system 900 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0227] The embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0228] In at least one embodiment, the computer system 900 may include, but is not limited to, a processor 902, which may include, but is not limited to, one or more execution units 908, to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the computer system 900 is a single-processor desktop or server system, but in another embodiment, the computer system 900 may be a multiprocessor system. In at least one embodiment, the processor 902 may include, but is not limited to, a Complex Instruction Set Computer (“CISC”) microprocessor, a Reduced Instruction Set Computing (“RISC”) microprocessor, a Very Long Instruction Word (“VLIW”) microprocessor, a processor implementing instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 902 may be coupled to a processor bus 910, which can transmit data signals between the processor 902 and other components in the computer system 900.

[0229] In at least one embodiment, processor 902 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 904. In at least one embodiment, processor 902 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 902. Depending on specific implementation and requirements, other embodiments may also include a combination of internal and external caches. In at least one embodiment, register file 906 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0230] In at least one embodiment, an execution unit 908, including but not limited to logic for performing integer and floating-point operations, is also located within the processor 902. In at least one embodiment, the processor 902 may further include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode of certain macro instructions. In at least one embodiment, the execution unit 908 may include logic for processing a packaged instruction set 909. In at least one embodiment, by including the packaged instruction set 909 in the instruction set of a general-purpose processor, along with the associated circuitry for executing the instructions, the packaged data in the processor 902 can be used to perform operations used by numerous multimedia applications. In at least one embodiment, many multimedia applications can be executed more quickly and efficiently by using the full width of the processor’s data bus to perform operations on the packaged data, which may eliminate the need to transfer smaller data units on the processor’s data bus to perform one or more operations on one data element at a time.

[0231] In at least one embodiment, the execution unit 908 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, the computer system 900 may include, but is not limited to, memory 920. In at least one embodiment, memory 920 may be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or another storage device. In at least one embodiment, memory 920 may store instructions 919 and / or data 921 represented by data signals that can be executed by processor 902.

[0232] In at least one embodiment, the system logic chip may be coupled to the processor bus 910 and the memory 920. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 916, and the processor 902 may communicate with the MCH 916 via the processor bus 910. In at least one embodiment, the MCH 916 may provide a high-bandwidth memory path 918 to the memory 920 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 916 may initiate data signals between the processor 902, the memory 920, and other components in the computer system 900, and bridge data signals between the processor bus 910, the memory 920, and the system I / O interface 922. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 916 may be coupled to the memory 920 via the high-bandwidth memory path 918, and the graphics / video card 912 may be coupled to the MCH 916 via an Accelerated Graphics Port (“AGP”) interconnect 914.

[0233] In at least one embodiment, the computer system 900 may use the system I / O interface 922 as a proprietary hub interface bus to couple the MCH 916 to the I / O controller hub (“ICH”) 930. In at least one embodiment, the ICH 930 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 920, chipset, and processor 902. Examples may include, but are not limited to, an audio controller 929, a firmware hub (“Flash BIOS”) 928, a wireless transceiver 926, a data storage 924, a conventional I / O controller 923 including a user input and keyboard interface, a serial expansion port 927 (e.g., a Universal Serial Bus (USB) port), and a network controller 934. In at least one embodiment, the data storage 924 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0234] In at least one embodiment, Figure 9 A system including interconnected hardware devices or "chips" is shown, while in other embodiments, Figure 9 The SoC can be shown. In at least one embodiment, Figure 9The devices shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of the computer system 900 are interconnected using a Compute Fast Link (CXL) interconnect.

[0235] Inference and / or training logic 515 is used to perform inference and / or training operations related to one or more embodiments. This document combines... Figure 5A and / or Figure 5B Details are provided regarding the inference and / or training logic 515. In at least one embodiment, the inference and / or training logic 515 may be... Figure 9 Used in systems for reasoning or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0236] In various embodiments, the data center performs a load balancer as described above, which distributes operations (e.g., transformation of video frames) to CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, DPUs, or other hardware during the execution of video analytics pipelines or other applications.

[0237] Figure 10 This is a block diagram illustrating an electronic device 1000 for utilizing a processor 1010 according to at least one embodiment. In at least one embodiment, the electronic device 1000 may be, for example, but not limited to, a laptop computer, tower server, rack server, blade server, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0238] In at least one embodiment, the electronic device 1000 may, but is not limited to, a processor 1010 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1010 is coupled using a bus or interface, such as I... 2 C-bus, System Management Bus (“SMBus”), Low Pin Count (LPC) bus, Serial Peripheral Interface (“SPI”), High Definition Audio (“HDA”) bus, Serial Advanced Technology Accessory (“SATA”) bus, Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 10 The system shown includes interconnected hardware devices or "chips," while in other embodiments, Figure 10 An exemplary SoC can be shown. In at least one embodiment, Figure 10The device shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 10 One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0239] In at least one embodiment, Figure 10 It may include a display 1024, a touch screen 1025, a touchpad 1030, a near field communication unit (“NFC”) 1045, a sensor hub 1040, a thermal sensor 1046, a fast chipset (“EC”) 1035, a trusted platform module (“TPM”) 1038, a BIOS / firmware / flash (“BIOS, FW Flash”) 1022, a DSP 1060, a drive 1020 (e.g., a solid-state drive (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1050, a Bluetooth unit 1052, a wireless wide area network unit (“WWAN”) 1056, a global positioning system (GPS) unit 1055, a camera (“USB 3.0 camera”) 1054 (e.g., a USB 3.0 camera), and / or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1015 implemented in, for example, the LPDDR3 standard. These components can each be implemented in any suitable way.

[0240] In at least one embodiment, other components may be communicatively coupled to processor 1010 via the components described herein. In at least one embodiment, accelerometer 1041, ambient light sensor (“ALS”) 1042, compass 1043, and gyroscope 1044 may be communicatively coupled to sensor hub 1040. In at least one embodiment, thermal sensor 1039, fan 1037, keyboard 1036, and touchpad 1030 may be communicatively coupled to EC 1035. In at least one embodiment, speaker 1063, earphone 1064, and microphone (“mic”) 1065 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 1062, which in turn may be communicatively coupled to DSP 1060. In at least one embodiment, audio unit 1062 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 1057 may be communicatively coupled to WWAN unit 1056. In at least one embodiment, components such as WLAN unit 1050, Bluetooth unit 1052, and WWAN unit 1056 can be implemented as next-generation form factor (NGFF).

[0241] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 5A and / or Figure 5B Details are provided regarding the inference and / or training logic 515. In at least one embodiment, the inference and / or training logic 515 can be implemented in the system. Figure 10 It is used in the context of reasoning or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0242] Figure 11 A computer system 1100 according to at least one embodiment is shown. In at least one embodiment, the computer system 1100 is configured to implement various processes and methods described throughout this disclosure.

[0243] In at least one embodiment, the computer system 1100 includes, but is not limited to, at least one central processing unit (“CPU”) 1102 connected to a communication bus 1110 implemented using any suitable protocol, such as PCI (“Peripheral Device Interconnect”), Peripheral Component Interconnect Express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1100 includes, but is not limited to, main memory 1104 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data may be stored in main memory 1104 in the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“Network Interface”) 1122 provides an interface to other computing devices and networks for receiving data using the computer system 1100 and transferring data to other systems.

[0244] In at least one embodiment, the computer system 1100 includes, but is not limited to, an input device 1108, a parallel processing system 1112, and a display device 1106, which may be implemented using conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light-emitting diode (“LED”) display, plasma display, or other suitable display technologies. In at least one embodiment, user input is received from the input device 1108 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the modules described herein may reside on a single semiconductor platform to form the processing system.

[0245] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 5A and / or Figure 5BDetails are provided regarding the inference and / or training logic 515. In at least one embodiment, the inference and / or training logic 515 can be implemented in the system. Figure 11 It is used to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architecture or neural network use cases described herein.

[0246] Figure 12 A computer system 1200 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1200 includes, but is not limited to, a computer 1210 and a USB stick 1220. In at least one embodiment, the computer 1210 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, the computer 1210 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0247] In at least one embodiment, the USB stick 1220 includes, but is not limited to, a processing unit 1230, a USB interface 1240, and USB interface logic 1250. In at least one embodiment, the processing unit 1230 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1230 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1230 includes an application-specific integrated circuit (“ASIC”) optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1230 is a tensor processing unit (“TPC”) optimized to perform machine learning inference operations. In at least one embodiment, the processing unit 1230 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0248] In at least one embodiment, the USB interface 1240 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, the USB interface 1240 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, the USB interface 1240 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1250 may include any amount and type of logic enabling the processing unit 1230 to connect to a device (e.g., computer 1210) via the USB connector 1240.

[0249] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 5A and / or Figure 5BDetails are provided regarding the inference and / or training logic 515. In at least one embodiment, the inference and / or training logic 515 can be implemented in the system. Figure 12 In use, at least in part, the operation is based on weight parameters, neural network functions and / or architectures computed using neural network training operations, or neural network use cases described herein to infer or predict operations.

[0250] Figure 13A An exemplary architecture is illustrated in which multiple GPUs 1310(1)-1310(N) are communicatively coupled to multiple multi-core processors 1305(1)-1305(M) via high-speed links 1340(1)-1340(N) (e.g., bus / point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 1340(1)-1340(N) support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. In at least one embodiment, various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, “N” and “M” represent positive integers, the values ​​of which may vary from figure to figure.

[0251] Furthermore, in one embodiment, two or more GPUs 1310 are interconnected via high-speed links 1329(1)-1329(2), which can be implemented using a protocol / link similar to or different from that used for high-speed links 1340(1)-1340(N). Similarly, two or more multi-core processors 1305 can be connected via high-speed link 1328, which can be a symmetric multiprocessor (SMP) bus operating at speeds of 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, similar protocols / links (e.g., via a common interconnect structure) can be used. Figure 13A This shows all communication between the various system components.

[0252] In one embodiment, each multi-core processor 1305 is communicatively coupled to processor memories 1301(1)-1301(M) via memory interconnects 1326(1)-1326(M), and each GPU 1310(1)-1310(N) is communicatively coupled to GPU memories 1320(1)-1320(N) via GPU memory interconnects 1350(1)-1350(N). In at least one embodiment, memory interconnects 1326 and 1350 may utilize similar or different memory access technologies. By way of example and not limitation, processor memories 1301(1)-1301(M) and GPU memories 1320 may be volatile memories, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM. In at least one embodiment, some portions of the processor memory 1301 may be volatile memory, while other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0253] As described herein, although the various multi-core processors 1305 and GPUs 1310 can be physically coupled to specific memories 1301 and 1320 respectively, and / or can implement a unified memory architecture, in which the virtual system address space (also known as the “effective address” space) is distributed among the various physical memories. For example, processor memories 1301(1)-1301(M) can each contain 64GB of system memory address space, and GPU memories 1320(1)-1320(N) can each contain 32GB of system memory address space, resulting in a total addressable memory size of 256GB when M=2 and N=4. N and M may also be other values.

[0254] Figure 13B Additional details are shown regarding the interconnection between a multi-core processor 1307 and a graphics acceleration module 1346 according to an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1346 may include one or more GPU chips integrated on a line card coupled to the processor 1307 via a high-speed link 1340 (e.g., PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1346 may optionally be integrated on a package or chip having the processor 1307.

[0255] In at least one embodiment, the processor 1307 includes a plurality of cores 1360A-1360D, each core having a translation back cover buffer (“TLB”) 1361A-1361D and one or more caches 1362A-1362D. In at least one embodiment, the cores 1360A-1360D may include various other components (not shown) for executing instructions and processing data. In at least one embodiment, the caches 1362A-1362D may include level 1 (L1) and level 2 (L2) caches. Furthermore, one or more shared caches 1356 may be included in the caches 1362A-1362D and shared by the respective groups of cores 1360A-1360D. For example, one embodiment of the processor 1307 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1307 and the graphics acceleration module 1346 are connected to the system memory 1314, which may include... Figure 13A The processor memory 1301(1)-1301(M) is included.

[0256] In at least one embodiment, consistency of data and instructions stored in the various caches 1362A-1362D, 1356 and system memory 1314 is maintained via inter-core communication through the consistency bus 1364. In at least one embodiment, for example, each cache may have associated cache consistency logic / circuitology to communicate via the consistency bus 1364 in response to the detection of a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented via the consistency bus 1364 to snoop on cache accesses.

[0257] In at least one embodiment, proxy circuitry 1325 communicatively couples graphics acceleration module 1346 to coherence bus 1364, thereby allowing graphics acceleration module 1346 to participate in cache coherence protocols as a peer of cores 1360A-1360D. Specifically, in at least one embodiment, interface 1335 provides connectivity to proxy circuitry 1325 via high-speed link 1340, and interface 1337 connects graphics acceleration module 1346 to high-speed link 1340.

[0258] In at least one embodiment, the accelerator integrated circuit 1336 provides cache management, memory access, context management, and interrupt management services for a plurality of graphics processing engines 1331(1)-1331(N) of the graphics acceleration module. In at least one embodiment, the graphics processing engines 1331(1)-1331(N) may each include a separate graphics processing unit (GPU). In at least one embodiment, the graphics processing engines 1331(1)-1331(N) may optionally include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module 1346 may be a GPU having a plurality of graphics processing engines 1331(1)-1331(N), or the graphics processing engines 1331(1)-1331(N) may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0259] In at least one embodiment, the accelerator integrated circuit 1336 includes a memory management unit (MMU) 1339 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1314. In at least one embodiment, the MMU 1339 may also include a translation back buffer (“TLB”) (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, cache 1338 may store commands and data for efficient access by graphics processing engines 1331(1)-1331(N). In at least one embodiment, a fetch unit 1344 may be used to keep data stored in cache 1338 and graphics memory 1333(1)-1333(M) consistent with core caches 1362A-1362D, 1356 and system memory 1314. As previously mentioned, this task can be accomplished via proxy circuitry 1325 representing cache 1338 and graphics memory 1333(1)-1333(M) (e.g., sending updates related to the modification / access of cache lines on processor caches 1362A-1362D, 1356 to cache 1338 and receiving updates from cache 1338).

[0260] In at least one embodiment, a set of registers 1345 stores context data of threads executed by graphics processing engines 1331(1)-1331(N), and context management circuitry 1348 manages the thread context. For example, context management circuitry 1348 may perform save and restore operations to save and restore the context of individual threads during context switching (e.g., saving the first thread and storing the second thread so that the second thread can be executed by the graphics processing engine). For example, during context switching, context management circuitry 1348 may store the current register value in a designated area of ​​memory (e.g., identified by the context pointer). The register value can then be restored when returning to the context. In at least one embodiment, interrupt management circuitry 1347 receives and processes interrupts received from system devices.

[0261] In at least one embodiment, MMU 1339 translates virtual / effective addresses from graphics processing engine 1331 into real / physical addresses in system memory 1314. In at least one embodiment, accelerator integrated circuit 1336 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1346 and / or other accelerator devices. In at least one embodiment, graphics accelerator module 1346 may be dedicated to a single application executing on processor 1307, or may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented, wherein resources of graphics processing engines 1331(1)-1331(N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” based on processing requirements and priorities associated with VMs and / or applications, which are allocated to different VMs and / or applications.

[0262] In at least one embodiment, the accelerator integrated circuit 1336 acts as a bridge to the system of the graphics acceleration module 1346 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1336 can provide virtualization facilities for the host processor to manage the virtualization, interrupt, and memory management of the graphics processing engines 1331(1)-1331(N).

[0263] In at least one embodiment, since the hardware resources of the graphics processing engines 1331(1)-1331(N) are explicitly mapped to the real address space seen by the host processor 1307, any host processor can directly address these resources using valid address values. In at least one embodiment, a function of the accelerator integrated circuit 1336 is to physically separate the graphics processing engines 1331(1)-1331(N) so that they appear as independent units to the system.

[0264] In at least one embodiment, one or more graphics memories 1333(1)-1333(M) are coupled to each graphics processing engine 1331(1)-1331(N), and N = M. In at least one embodiment, the graphics memories 1333(1)-1333(M) store instructions and data processed by each graphics processing engine 1331(1)-1331(N). In at least one embodiment, the graphics memories 1333(1)-1333(M) may be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory, such as 3DXPoint or Nano-RAM.

[0265] In one embodiment, to reduce data traffic on the high-speed link 1340, a biasing technique can be used to ensure that the data stored in the graphics memory 1333(1)-1333(M) is the data most frequently used by the graphics processing engine 1331(1)-1331(N), and preferably data that the cores 1360A-1360D do not use (or at least do not use frequently). Similarly, in at least one embodiment, the biasing mechanism attempts to keep the data needed by the cores (and preferably not the graphics processing engine 1331(-1)-1331(N)) in the caches 1362A-1362D, 1356 and system memory 1314.

[0266] Figure 13C Another exemplary embodiment is shown, wherein the accelerator integrated circuit 1336 is integrated within the processor 1307. In this embodiment, the graphics processing engines 1331(1)-1331(N) communicate directly with the accelerator integrated circuit 1336 via a high-speed link 1340 through interfaces 1337 and 1335 (which may also be any form of bus or interface protocol). In at least one embodiment, the accelerator integrated circuit 1336 can perform operations related to... Figure 13B The described operation is similar. However, due to its close proximity to the coherence bus 1364 and caches 1362A-1362D, 1356, it may have higher throughput. In at least one embodiment, the accelerator integrated circuit supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuit 1336 and a programming model controlled by the graphics acceleration module 1346.

[0267] In at least one embodiment, graphics processing engines 1331(1)-1331(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel requests from other applications to graphics processing engines 1331(1)-1331(N), thereby providing virtualization within a VM / partition.

[0268] In at least one embodiment, graphics processing engines 1331(1)-1331(N) can be shared by multiple VM / application partitions. In at least one embodiment, the shared model can use a hypervisor to virtualize graphics processing engines 1331(1)-1331(N) to allow each operating system to access them. In at least one embodiment, for a single-partition system without a hypervisor, the operating system owns graphics processing engines 1331(1)-1331(N). In at least one embodiment, the operating system can virtualize graphics processing engines 1331(1)-1331(N) to provide access to each process or application.

[0269] In at least one embodiment, the graphics acceleration module 1346 or the individual graphics processing engine 1331(1)-1331(N) uses a process handle to select a process element. In at least one embodiment, the process element is stored in system memory 1314 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 1331(1)-1331(N) (i.e., invoking system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element in the process element linked list.

[0270] Figure 13D An exemplary accelerator integration slice 1390 is illustrated. In at least one embodiment, a "slice" includes a designated portion of the processing resources of an accelerator integrated circuit 1336. In at least one embodiment, the application is an effective address space 1382 in system memory 1314, which stores process element 1383. In at least one embodiment, process element 1383 is stored in response to a GPU call 1381 from an application 1380 executing on processor 1307. In at least one embodiment, process element 1383 contains the process state of the corresponding application 1380. In one embodiment, a job descriptor (WD) 1384 contained in process element 1383 may be a single job requested by the application, or it may contain a pointer to a job queue. In at least one embodiment, WD 1384 is a pointer to a job request queue in the effective address space 1382 of the application.

[0271] In at least one embodiment, the graphics acceleration module 1346 and / or the various graphics processing engines 1331(1)-1331(N) may be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure may be included for setting process states and sending WD 1384 to the graphics acceleration module 1346 to begin operations in a virtualized environment.

[0272] In at least one embodiment, the dedicated process programming model is implementation-specific. In at least one embodiment, in this model, a single process owns either the graphics acceleration module 1346 or an individual graphics processing engine 1331. In at least one embodiment, when the graphics acceleration module 1346 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when the graphics acceleration module 1346 is assigned, the operating system initializes the accelerator integrated circuit 1336 for the owned process.

[0273] In at least one embodiment, during operation, the WD acquisition unit 1391 in the accelerator integration slice 1390 acquires the next WD 1384, which includes instructions for work to be performed by one or more graphics processing engines of the graphics acceleration module 1346. In at least one embodiment, data from the WD 1384 may be stored in register 1345 and used by the MMU 1339, interrupt management circuitry 1347, and / or context management circuitry 1348, as shown. For example, one embodiment of the MMU 1339 includes segment / page roaming circuitry for accessing segment / page tables 1386 within the OS virtual address space 1385. In at least one embodiment, the interrupt management circuitry 1347 may process an interrupt event 1392 received from the graphics acceleration module 1346. In at least one embodiment, when performing graphics operations, a valid address 1393 generated by graphics processing engines 1331(1)-1331(N) is translated into a real address by the MMU 1339.

[0274] In at least one embodiment, register 1345 is copied for each graphics processing engine 1331(1)-1331(N) and / or graphics acceleration module 1346, and said register 1345 may be initialized by a hypervisor or operating system. In at least one embodiment, each of these copied registers may be included in accelerator integration slice 1390. Exemplary registers that may be initialized by a hypervisor are shown in Table 1.

[0275] Table 1 – Registers for Supervisor Initialization

[0276]

[0277] Table 2 shows exemplary registers that can be initialized by the operating system.

[0278] Table 2 – Operating System Initialization Registers

[0279]

[0280] In at least one embodiment, each WD 1384 is specific to a particular graphics acceleration module 1346 and / or graphics processing engine 1331(1)-1331(N). In at least one embodiment, it contains all the information required for the graphics processing engine 1331(1)-1331(N) to complete its work, or it may be a pointer to a memory location where the application has set up a command queue for the work to be completed.

[0281] Figure 13E Additional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1398, in which a list of process elements 1399 is stored. In at least one embodiment, the hypervisor real address space 1398 can be accessed via a hypervisor 1396, which virtualizes the graphics acceleration module engine for operating system 1395.

[0282] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1346. In at least one embodiment, there are two programming models in which the graphics acceleration module 1346 is shared by multiple processes and partitions, namely, time-slice sharing and graphics-oriented sharing.

[0283] In at least one embodiment, in this model, the hypervisor 1396 owns the graphics acceleration module 1346 and makes its functionality available to all operating systems 1395. In at least one embodiment, for the graphics acceleration module 1346 to support virtualization through the hypervisor 1396, the graphics acceleration module 1346 may comply with certain requirements, such as (1) the job requests of the application must be autopilot (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1346 must provide a context saving and recovery mechanism, (2) the graphics acceleration module 1346 guarantees that the job requests of the application are completed within a specified amount of time, including any conversion errors, or the graphics acceleration module 1346 provides the ability to preempt job processing, and (3) when operating in a directed shared programming model, fairness between the processes of the graphics acceleration module 1346 must be ensured.

[0284] In at least one embodiment, application 1380 needs to make system calls to operating system 1395 using the graphics acceleration module type, working descriptor (WD), permission mask register (AMR) value, and context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration function used for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is specifically formatted for graphics acceleration module 1346 and can take the form of graphics acceleration module 1346 commands, valid address pointers to user-defined structures, valid address pointers to command queues, or any other data structure describing the work to be performed by graphics acceleration module 1346.

[0285] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of the application that sets the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1336 (not shown) and the graphics acceleration module 1346 does not support the User Rights Mask Overwrite Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1396 may selectively apply the current Rights Mask Overwrite Register (AMOR) value before placing the AMR into the process element 1383. In at least one embodiment, CSRP is one of the registers 1345 that contains the effective address of a region in the effective address space 1382 of the application for the graphics acceleration module 1346 to save and restore the context state. In at least one embodiment, this pointer is optional if it is not necessary to save state between jobs or when a job is preempted. In at least one embodiment, the context save / restore region may be fixed system memory.

[0286] Upon receiving a system call, the operating system 1395 can verify that the application 1380 has been registered and granted permission to use the graphics acceleration module 1346. Then, in at least one embodiment, the operating system 1395 uses the information shown in Table 3 to invoke the hypervisor 1396.

[0287] Table 3 – Operating System to Hypervisor Call Parameters

[0288]

[0289] In at least one embodiment, upon receiving a hypervisor call, hypervisor 1396 verifies that operating system 1395 has been registered and granted permission to use graphics acceleration module 1346. Then, in at least one embodiment, hypervisor 1396 adds process element 1383 to a linked list of process elements of the corresponding graphics acceleration module 1346 type. In at least one embodiment, the process element may include the information shown in Table 4.

[0290] Table 4 – Process Element Information

[0291]

[0292]

[0293] In at least one embodiment, the hypervisor initializes multiple accelerator integration slice 1390 registers 1345.

[0294] like Figure 13F As shown, in at least one embodiment, a unified memory is used, which is addressable via a common virtual memory address space for accessing physical processor memories 1301(1)-1301(N) and GPU memories 1320(1)-1320(N). In this implementation, operations performed on GPUs 1310(1)-1310(N) utilize the same virtual / effective memory address space to access processor memories 1301(1)-1301(M) and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1301(1), a second portion to second processor memory 1301(N), a third portion to GPU memory 1320(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memory 1301 and GPU memory 1320, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0295] In at least one embodiment, the bias / coherence management circuitry 1394A-1394E within one or more MMUs 1339A-1339E ensures cache coherence between one or more host processors (e.g., 1305) and the cache of the GPU 1310, and implements biasing techniques to indicate the physical memory in which certain types of data should be stored. In at least one embodiment, although in Figure 13FSeveral instances of bias / coherence management circuits 1394A-1394E are shown, but bias / coherence circuits can be implemented within the MMU of one or more host processors 1305 and / or within the accelerator integrated circuit 1336.

[0296] One embodiment allows GPU memory 1320 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU memory 1320 as system memory without the heavy overhead of cache coherence provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows the host processor 1305 to software-set operands and access computation results without the overhead of conventional I / O DMA data copying. In at least one embodiment, such conventional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU memory 1320 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in cases with high streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1310. In at least one embodiment, the efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation can play a role in determining the effectiveness of GPU offloading.

[0297] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which may be a page-granular structure (e.g., controlled at the memory page level) comprising one or two bits of memory pages attached to each GPU. In at least one embodiment, with or without a bias cache (e.g., for caching frequently / recently used entries in the bias table) in GPU 1310, the bias table can be implemented across one or more stolen memory ranges of GPU memory 1320. Alternatively, in at least one embodiment, the entire bias table can be maintained within the GPU.

[0298] In at least one embodiment, prior to actual access to GPU memory, an access to the bias table entry associated with each access to GPU-attached memory 1320 is performed, resulting in the following operations: In at least one embodiment, a local request from GPU 1310 to find its page in the GPU bias is forwarded directly to the corresponding GPU memory 1320. In at least one embodiment, a local request from the GPU to find its page in the host bias is forwarded to processor 1305 (e.g., via the high-speed link described herein). In at least one embodiment, a request from processor 1305 to find the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, a request for a page pointing to the GPU bias can be forwarded to GPU 1310. In at least one embodiment, if the GPU is not currently using the page, the GPU may subsequently migrate the page to the host processor bias. In at least one embodiment, the page bias state can be changed through a software-based mechanism, a hardware-assisted software mechanism, or, in limited cases, a purely hardware-based mechanism.

[0299] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL), which subsequently invokes the GPU's device driver, which then sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and, in some migration, performs a cache refresh operation in the host. In at least one embodiment, the cache refresh operation is used for migration from the host processor 1305 bias to the GPU bias, but not for the reverse migration.

[0300] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that the host processor 1305 cannot cache. In at least one embodiment, to access these pages, the processor 1305 may request access from the GPU 1310, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between the processor 1305 and the GPU 1310, it is beneficial to ensure that the GPU bias pages are pages needed by the GPU rather than those needed by the host processor 1305, and vice versa.

[0301] One or more hardware structures 515 are used to execute one or more embodiments. This document may combine... Figure 5A and / or Figure 5B Provide details about one or more hardware structures 515.

[0302] Figure 14Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be manufactured using one or more IP cores. In addition to the illustrations, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0303] Figure 14 This is a block diagram illustrating an exemplary system on a chip integrated circuit 1400 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1400 includes one or more application processors 1405 (e.g., CPU), at least one graphics processor 1410, and may additionally include an image processor 1415 and / or a video processor 1420, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1400 includes peripheral or bus logic, which includes a USB controller 1425, a UART controller 1430, an SPI / SDIO controller 1435, and an I... 2 2S / I 2 2C controller 1440. In at least one embodiment, integrated circuit 1400 may include a display device 1445 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1450 and a Mobile Industrial Processor Interface (MIPI) display interface 1455. In at least one embodiment, storage may be provided by a flash memory subsystem 1460, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1465 for accessing an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits also include an embedded security engine 1470.

[0304] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 5A and / or Figure 5B Details regarding inference and / or training logic 515 are provided. In at least one embodiment, inference and / or training logic 515 may be used in integrated circuit 1400 to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0305] Figures 15A-15B Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be manufactured using one or more IP cores. In addition to the illustrations, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0306] Figures 15A-15B This is a block diagram illustrating an exemplary graphics processor used within a SoC according to embodiments described herein. Figure 15A An exemplary graphics processor 1510, which can be fabricated using one or more IP cores according to at least one embodiment, is shown. Figure 15B Further exemplary graphics processor 1540 of a system-on-a-chip integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. In at least one embodiment, Figure 15A The graphics processor 1510 is a low-power graphics processor core. In at least one embodiment, Figure 15B The graphics processor 1540 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 1510, 1540 may be... Figure 14 A variant of the graphics processor 1410.

[0307] In at least one embodiment, the graphics processor 1510 includes a vertex processor 1505 and one or more fragment processors 1515A-1515N (e.g., 1515A, 1515B, 1515C, 1515D to 1515N-1 and 1515N). In at least one embodiment, the graphics processor 1510 may execute different shader programs via separate logic, such that the vertex processor 1505 is optimized to perform operations for the vertex shader program, while one or more fragment processors 1515A-1515N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, the vertex processor 1505 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, one or more fragment processors 1515A-1515N use the primitive and vertex data generated by the vertex processor 1505 to generate framebuffers for display on a display device. In at least one embodiment, one or more fragment processors 1515A-1515N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0308] In at least one embodiment, the graphics processor 1510 additionally includes one or more memory management units (MMUs) 1520A-1520B, one or more caches 1525A-1525B, and one or more circuit interconnects 1530A-1530B. In at least one embodiment, one or more MMUs 1520A-1520B provide a virtual-to-physical address mapping for the graphics processor 1510, including for the vertex processor 1505 and / or fragment processors 1515A-1515N, which can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1525A-1525B. In at least one embodiment, one or more MMUs 1520A-1520B can be synchronized with other MMUs within the system, including with... Figure 14 One or more application processors 1405, graphics processors 1415, and / or video processors 1420 are associated with one or more MMUs, such that each processor 1405-1420 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1530A-1530B enable the graphics processor 1510 to be connected to other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0309] In at least one embodiment, the graphics processor 1540 includes one or more shader cores 1555A-1555N (e.g., 1555A, 1555B, 1555C, 1555D, 1555E, 1555F to 1555N-1 and 1555N), such as Figure 15B As shown, it provides a unified shader core architecture, where a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1540 includes an inter-core task manager 1545, which acts as a thread dispatcher to assign execution threads to one or more shader cores 1555A-1555N and a tile unit 1558 to accelerate tile-based rendering operations, where scene rendering operations are subdivided in image space, for example, to utilize local spatial consistency within the scene or optimize the use of internal caches.

[0310] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 5A and / or Figure 5BDetails regarding the inference and / or training logic 515 are provided. In at least one embodiment, the inference and / or training logic 515 may be integrated into an integrated circuit. Figure 15A and / or Figure 15B The above is used for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions or architectures, or neural network use cases described herein.

[0311] Figures 16A-16B Additional exemplary graphics processor logic according to embodiments described herein is illustrated. In at least one embodiment, Figure 16A It shows that it can be included in Figure 14 The graphics core 1600 within the graphics processor 1410, and in at least one embodiment, may be as follows: Figure 15B The unified shader cores shown are 1555A-1555N. Figure 16B A highly parallel general-purpose graphics processing unit (“GPGPU”) 1630 suitable for deployment on a multi-chip module is shown in at least one embodiment.

[0312] In at least one embodiment, the graphics core 1600 includes a shared instruction cache 1602, texture units 1618, and cache / shared memory 1620, which are common to the execution resources within the graphics core 1600. In at least one embodiment, the graphics core 1600 may include multiple slices 1601A-1601N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 1600. In at least one embodiment, slices 1601A-1601N may include supporting logic, including local instruction caches 1604A-1604N, thread schedulers 1606A-1606N, thread dispatchers 1608A-1608N, and a set of registers 1610A-1610N. In at least one embodiment, slices 1601A-1601N may include a set of additional functional units (AFU 1612A-1612N), floating-point units (FPU 1614A-1614N), integer arithmetic logic units (ALU 1616A-1616N), address calculation units (ACU 1613A-1613N), double-precision floating-point units (DPFPU1615A-1615N), and matrix processing units (MPU 1617A-1617N).

[0313] In at least one embodiment, the FPU 1614A-1614N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 1615A-1615N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 1616A-1616N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 1617A-1617N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 1617-1617N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated generalized matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 1612A-1612N can perform additional logical operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0314] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. This is combined with... Figure 5A and / or Figure 5B Details are provided regarding inference and / or training logic 515. In at least one embodiment, inference and / or training logic 515 may be used in graphics core 1600 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0315] Figure 16BA general-purpose processing unit (GPGPU) 1630 is illustrated in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by a set of graphics processing units. In at least one embodiment, the GPGPU 1630 can be directly linked to other instances of the GPGPU 1630 to create a multi-GPU cluster to improve the training speed for deep neural networks. In at least one embodiment, the GPGPU 1630 includes a host interface 1632 for connection to a host processor. In at least one embodiment, the host interface 1632 is a PCI Express interface. In at least one embodiment, the host interface 1632 may be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 1630 receives commands from the host processor and uses a global scheduler 1634 to allocate execution threads associated with those commands to a set of compute clusters 1636A-1636H. In at least one embodiment, compute clusters 1636A-1636H share a cache memory 1638. In at least one embodiment, cache memory 1638 can be used as a higher-level cache within the cache memory of computing clusters 1636A-1636H.

[0316] In at least one embodiment, the GPGPU 1630 includes memories 1644A-1644B, which are coupled to the computing cluster 1636A-1636H via a set of memory controllers 1642A-1642B. In at least one embodiment, memories 1644A-1644B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0317] In at least one embodiment, each of the computing clusters 1636A-1636H includes a set of graphics cores, for example... Figure 16A The graphics core 1600 may include various types of integer and floating-point logic units that can perform computational operations across a range of precisions, including precisions suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 1636A-1636H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0318] In at least one embodiment, multiple instances of the GPGPU 1630 can be configured as a computing cluster. In at least one embodiment, the communication used for synchronization and data exchange by the computing clusters 1636A-1636H varies between embodiments. In at least one embodiment, the multiple instances of the GPGPU 1630 communicate via a host interface 1632. In at least one embodiment, the GPGPU 1630 includes an I / O hub 1639 that couples the GPGPU 1630 to a GPU link 1640, enabling direct connection to other instances of the GPGPU 1630. In at least one embodiment, the GPU link 1640 is coupled to a dedicated GPU-to-GPU bridge, which enables communication and synchronization between the multiple instances of the GPGPU 1630. In at least one embodiment, the GPU link 1640 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, the multiple instances of the GPGPU 1630 reside in a separate data processing system and communicate via network devices accessible through the host interface 1632. In at least one embodiment, GPU link 1640 may be configured to enable connection to a host processor other than or as a replacement for host interface 1632.

[0319] In at least one embodiment, the GPGPU 1630 can be configured to train a neural network. In at least one embodiment, the GPGPU 1630 can be used within an inference platform. In at least one embodiment, when the GPGPU 1630 is used for inference, the GPGPU 1630 may include fewer compute clusters 1636A-1636H compared to when the GPGPU 1630 is used to train a neural network. In at least one embodiment, the memory technology associated with the memories 1644A-1644B can differ between inference and training configurations, wherein a higher bandwidth memory technology is dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1630 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during the inference operation of the deployed neural network.

[0320] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 5A and / or Figure 5BDetails are provided regarding the inference and / or training logic 515. In at least one embodiment, the inference and / or training logic 515 may be used in the GPGPU 1630 for inferring or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architecture, or neural network use cases described herein.

[0321] Figure 17 A block diagram of a computer system 1700 according to at least one embodiment is shown. In at least one embodiment, the computer system 1700 includes a processing subsystem 1701 having one or more processors 1702 and a system memory 1704 communicating via an interconnect path that may include a memory hub 1705. In at least one embodiment, the memory hub 1705 may be a separate component within a chipset component or may be integrated within one or more processors 1702. In at least one embodiment, the memory hub 1705 is coupled to an I / O subsystem 1711 via a communication link 1706. In one embodiment, the I / O subsystem 1711 includes an I / O hub 1707 that enables the computer system 1700 to receive input from one or more input devices 1708. In at least one embodiment, the I / O hub 1707 enables a display controller to provide output to one or more display devices 1710A, the display controller being included in one or more processors 1702. In at least one embodiment, one or more display devices 1710A coupled to the I / O hub 1707 may include local, internal, or embedded display devices.

[0322] In at least one embodiment, the processing subsystem 1701 includes one or more parallel processors 1712 coupled to the memory hub 1705 via a bus or other communication link 1713. In at least one embodiment, the communication link 1713 may use any of many standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or communication architecture. In at least one embodiment, the one or more parallel processors 1712 form a computationally concentrated parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as a multi-core integrated (MIC) processor. In at least one embodiment, the one or more parallel processors 1712 form a graphics processing subsystem that can output pixels to one or more display devices 1710A coupled via an I / O hub 1707. In at least one embodiment, the parallel processors 1712 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1710B.

[0323] In at least one embodiment, system storage unit 1714 may be connected to I / O hub 1707 to provide a storage mechanism for computer system 1700. In at least one embodiment, I / O switch 1716 may be used to provide an interface mechanism to enable connectivity between I / O hub 1707 and other components, such as network adapter 1718 and / or wireless network adapter 1717 that may be integrated into the platform, and various other devices that may be added via one or more add-on devices 1720. In at least one embodiment, network adapter 1718 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1719 may include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more wireless devices.

[0324] In at least one embodiment, the computer system 1700 may include other components not explicitly shown, such as USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 1707. In at least one embodiment, the interconnection can be implemented using any suitable protocol (e.g., PCI-based protocols such as PCI-Express or other bus or point-to-point communication interfaces and / or protocols). Figure 17 The communication paths of the various components, such as NV-Link high-speed interconnect or interconnect protocols.

[0325] In at least one embodiment, one or more parallel processors 1712 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constituting a graphics processing unit (GPU). In at least one embodiment, the parallel processor 1712 includes circuitry optimized for general-purpose processing. In at least one embodiment, components of the computer system 1700 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, the parallel processor 1712, memory hub 1705, processor 1702, and I / O hub 1707 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computer system 1700 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computer system 1700 may be integrated into a multi-chip module (MCM) that can interconnect with other MCMs to a modular computer system.

[0326] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 5A and / or Figure 5B Details are provided regarding the inference and / or training logic 515. In at least one embodiment, the inference and / or training logic 515 may be... Figure 17 The system 1700 is used for reasoning or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0327] processor

[0328] Figure 18A A parallel processor 1800 according to at least one embodiment is illustrated. In at least one embodiment, various components of the parallel processor 1800 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 1800 is according to an exemplary embodiment. Figure 17 The variants shown are of one or more parallel processors 1712.

[0329] In at least one embodiment, the parallel processor 1800 includes a parallel processing unit 1802. In at least one embodiment, the parallel processing unit 1802 includes an I / O unit 1804 that enables communication with other devices, including other instances of the parallel processing unit 1802. In at least one embodiment, the I / O unit 1804 can be directly connected to other devices. In at least one embodiment, the I / O unit 1804 is connected to other devices using a hub or switch interface (e.g., a memory hub 2105). In at least one embodiment, the connection between the memory hub 1805 and the I / O unit 1804 forms a communication link 1813. In at least one embodiment, the I / O unit 1804 is connected to a host interface 1806 and a memory crossbar switch 1816, wherein the host interface 1806 receives commands for performing processing operations, and the memory crossbar switch 1816 receives commands for performing memory operations.

[0330] In at least one embodiment, when host interface 1806 receives a command buffer via I / O unit 1804, host interface 1806 can direct work operations to execute those commands to front end 1808. In at least one embodiment, front end 1808 is coupled to scheduler 1810, which is configured to assign commands or other work items to processing cluster array 1812. In at least one embodiment, scheduler 1810 ensures that processing cluster array 1812 is correctly configured and in an active state before assigning tasks to processing cluster array 1812. In at least one embodiment, scheduler 1810 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 1810 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, thereby enabling fast preemption and context switching of threads executing on processing array 1812. In at least one embodiment, host software can demonstrate workloads for scheduling on processing array 1812 via one of multiple graphics processing paths. In at least one embodiment, the workload can then be automatically distributed on the processing array 1812 by the scheduler 1810 logic within the microcontroller, which includes the scheduler 1810.

[0331] In at least one embodiment, the processing cluster array 1812 may include up to "N" processing clusters (e.g., clusters 1814A, 1814B to 1814N), where "N" represents a positive integer (which may be an integer different from the integer "N" used in other diagrams). In at least one embodiment, each cluster 1814A-1814N of the processing cluster array 1812 can execute a large number of concurrent threads. In at least one embodiment, the scheduler 1810 may use various scheduling and / or work allocation algorithms to allocate work to the clusters 1814A-1814N of the processing cluster array 1812, which may vary depending on the workload generated by each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 1810, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 1812. In at least one embodiment, the different clusters 1814A-1814N of the processing cluster array 1812 may be assigned to process different types of programs or to perform different types of computations.

[0332] In at least one embodiment, the processing cluster array 1812 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 1812 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 1812 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0333] In at least one embodiment, the processing cluster array 1812 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 1812 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 1812 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 1802 may transfer data from system memory via I / O unit 1804 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1822) and then written back to system memory.

[0334] In at least one embodiment, when the parallel processing unit 1802 is used to perform graphics processing, the scheduler 1810 may be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations among the multiple clusters 1814A-1814N of the processing cluster array 1812. In at least one embodiment, portions of the processing cluster array 1812 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 1814A-1814N may be stored in a buffer to allow intermediate data to be transferred between the clusters 1814A-1814N for further processing.

[0335] In at least one embodiment, the processing cluster array 1812 may receive processing tasks to be executed via a scheduler 1810, which receives commands defining the processing tasks from a front end 1808. In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 1810 may be configured to acquire an index corresponding to a task, or may receive an index from the front end 1808. In at least one embodiment, the front end 1808 may be configured to ensure that the processing cluster array 1812 is configured to be active before initiating the workload specified by an incoming command buffer (e.g., a batch buffer, push buffer, etc.).

[0336] In at least one embodiment, each of one or more instances of the parallel processing unit 1802 may be coupled to the parallel processor memory 1822. In at least one embodiment, the parallel processor memory 1822 may be accessed via a memory crossbar switch 1816, which may receive memory requests from the processing cluster array 1812 and the I / O unit 1804. In at least one embodiment, the memory crossbar switch 1816 may be accessed via a memory interface 1818. In at least one embodiment, the memory interface 1818 may include a plurality of partition units (e.g., partition units 1820A, 1820B to 1820N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 1822. In at least one embodiment, the plurality of partition units 1820A-1820N are configured to be equal to the number of memory units, such that the first partition unit 1820A has a corresponding first memory unit 1824A, the second partition unit 1820B has a corresponding memory unit 1824B, and the Nth partition unit 1820N has a corresponding Nth memory unit 1824N. In at least one embodiment, the number of partition units 1820A-1820N may not be equal to the number of memory units.

[0337] In at least one embodiment, memory cells 1824A-1824N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 1824A-1824N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory cells 1824A-1824N, allowing partitioning cells 1820A-1820N to write portions of each rendering target in parallel, to efficiently utilize the available bandwidth of the parallel processor memory 1822. In at least one embodiment, local instances of the parallel processor memory 1822 may be excluded to facilitate a unified memory design that combines system memory with local cache memory.

[0338] In at least one embodiment, any of the clusters 1814A-1814N of the processing cluster array 1812 can process data to be written to any memory cell 1824A-1824N within the parallel processor memory 1822. In at least one embodiment, the memory crossbar switch 1816 can be configured to transfer the output of each cluster 1814A-1814N to any partition cell 1820A-1820N or another cluster 1814A-1814N, and the clusters 1814A-1814N can perform further processing operations on the output. In at least one embodiment, each cluster 1814A-1814N can communicate with the memory interface 1818 via the memory crossbar switch 1816 to read from or write to various external storage devices. In at least one embodiment, the memory crossbar switch 1816 has a connection to a memory interface 1818 for communication with I / O unit 1804, and a connection to a local instance of parallel processor memory 1822, thereby enabling processing units within different processing clusters 1814A-1814N to communicate with system memory or other memory not local to parallel processing unit 1802. In at least one embodiment, the memory crossbar switch 1816 may use virtual channels to separate traffic flows between clusters 1814A-1814N and partition units 1820A-1820N.

[0339] In at least one embodiment, multiple instances of the parallel processing unit 1802 may be provided on a single insert card, or multiple insert cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 1802 may be configured to interoperate, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 1802 may include higher-precision floating-point units relative to other instances. In at least one embodiment, a system combining one or more instances of the parallel processing unit 1802 or the parallel processor 1800 may be implemented in various configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0340] Figure 18B This is a block diagram of a partitioning unit 1820 according to at least one embodiment. In at least one embodiment, the partitioning unit 1820 is... Figure 18A This is an example of one of the partitioning units 1820A-1820N. In at least one embodiment, the partitioning unit 1820 includes an L2 cache 1821, a frame buffer interface 1825, and a ROP 1826 (raster operation unit). In at least one embodiment, the L2 cache 1821 is a read / write cache configured to perform load and store operations received from the memory crossbar switch 1816 and the ROP 1826. In at least one embodiment, the L2 cache 1821 outputs read misses and urgent write-back requests to the frame buffer interface 1825 for processing. In at least one embodiment, updates can also be sent to the frame buffer for processing via the frame buffer interface 1825. In at least one embodiment, the frame buffer interface 1825 communicates with memory cells in the parallel processor memory (such as...). Figure 18A It interacts with one of the memory cells 1824A-1824N (e.g., within the parallel processor memory 1822).

[0341] In at least one embodiment, ROP 1826 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 1826 then outputs processed graphics data stored in graphics memory. In at least one embodiment, ROP 1826 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic utilizing one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 1826 may vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per-tile basis.

[0342] In at least one embodiment, ROP 1826 is included within each processing cluster (e.g., Figure 18A Clusters 1814A-1814N are used instead of partition units 1820. In at least one embodiment, read and write requests for pixel data are made via memory crossbar switch 1816 instead of pixel fragment data transfer. In at least one embodiment, the processed graphics data can be displayed on a display device (such as...). Figure 17 One or more display devices 1710) display, routed by processor 1702 for further processing, or by Figure 18A One of the processing entities within the parallel processor 1800 is routed for further processing.

[0343] Figure 18C This is a block diagram of a processing cluster 1814 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is... Figure 18A An instance of one of the processing clusters 1814A-1814N. In at least one embodiment, the processing cluster 1814 can be configured to execute a number of threads in parallel, where a "thread" refers to an instance of a specific program executing on a particular set of input data. In at least one embodiment, a Single Instruction Multiple Data (SIMD) instruction issuing technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, a Single Instruction Multiple Threading (SIMT) technique is used to support the parallel execution of a large number of generally synchronous threads, which uses a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0344] In at least one embodiment, the operation of the processing cluster 1814 can be controlled by a pipeline manager 1832 that assigns processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 1832 receives... Figure 18AThe scheduler 1810 receives instructions and manages the execution of these instructions via the graphics multiprocessor 1834 and / or texture unit 1836. In at least one embodiment, the graphics multiprocessor 1834 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 1814 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, the processing cluster 1814 may include one or more instances of the graphics multiprocessor 1834. In at least one embodiment, the graphics multiprocessor 1834 can process data, and the data cross switch 1840 can be used to distribute the processed data to one of a number of possible destinations, including other shader units. In at least one embodiment, the pipeline manager 1832 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data cross switch 1840.

[0345] In at least one embodiment, each graphics multiprocessor 1834 within the processing cluster 1814 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, wherein new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shift operations, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0346] In at least one embodiment, instructions sent to the processing cluster 1814 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes a general program on different input data. In at least one embodiment, each thread within the thread group may be assigned to a different processing engine within the graphics multiprocessor 1834. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 1834. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during a loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 1834. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 1834, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 1834.

[0347] In at least one embodiment, the graphics multiprocessor 1834 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 1834 may forgo the internal cache and use a cache memory within the processing cluster 1814 (e.g., L1 cache 1848). In at least one embodiment, each graphics multiprocessor 1834 may also access partition units (e.g., Figure 18A The L2 cache is located within partition units 1820A-1820N, which are shared among all processing clusters 1814 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 1834 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 1802 can be used as global memory. In at least one embodiment, the processing cluster 1814 includes multiple instances of the graphics multiprocessor 1834, which can share common instructions and data that can be stored in the L1 cache 1848.

[0348] In at least one embodiment, each processing cluster 1814 may include a memory management unit (“MMU”) 1845 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 1845 may reside in Figure 18A The memory interface 1818 is located within the MMU 1845. In at least one embodiment, the MMU 1845 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 1845 may include an address translation lookup buffer (TLB) or a cache that may reside within the graphics multiprocessor 1834, the L1 cache 1848, or the processing cluster 1814. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, cache line indices may be used to determine whether a request for a cache line is a hit or a miss.

[0349] In at least one embodiment, the processing cluster 1814 can be configured such that each graphics multiprocessor 1834 is coupled to a texture unit 1836 to perform texture mapping operations that determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read as needed from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 1834, and texture data is also retrieved from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 1834 outputs a processed task to a data crossbar switch 1840 to provide the processed task to another processing cluster 1814 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via a memory crossbar switch 1816. In at least one embodiment, a preROP 1842 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 1834 and direct the data to a ROP unit, which can be associated with a partitioning unit (e.g., [missing information]). Figure 18A The PreROP 1842 unit is located together with the partitioning units 1820A-1820N. In at least one embodiment, the PreROP 1842 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0350] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 5A and / or Figure 5B Details are provided regarding inference and / or training logic 515. In at least one embodiment, inference and / or training logic 515 may be used in a graphics processing cluster 1814 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0351] Figure 18D A graphics multiprocessor 1834 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 1834 is coupled to a pipeline manager 1832 of a processing cluster 1814. In at least one embodiment, the graphics multiprocessor 1834 has an execution pipeline including, but not limited to, an instruction cache 1852, an instruction unit 1854, an address mapping unit 1856, a register file 1858, one or more general-purpose graphics processing unit (GPGPU) cores 1862, and one or more load / store units 1866. In at least one embodiment, the GPGPU cores 1862 and the load / store units 1866 are coupled to a cache memory 1872 and a shared memory 1870 via a memory and cache interconnect 1868.

[0352] In at least one embodiment, instruction cache 1852 receives a stream of instructions to be executed from pipeline manager 1832. In at least one embodiment, instructions are cached in instruction cache 1852 and dispatched to instruction unit 1854 for execution. In one embodiment, instruction unit 1854 may dispatch instructions as thread groups (e.g., thread bundles), assigning each thread of the thread group to a different execution unit within GPGPU core 1862. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 1856 may be used to translate addresses in the unified address space into different memory addresses that can be accessed by load / store unit 1866.

[0353] In at least one embodiment, register file 1858 provides a set of registers for functional units of graphics multiprocessor 1834. In at least one embodiment, register file 1858 provides temporary storage for operands of data paths connected to functional units of graphics multiprocessor 1834 (e.g., GPGPU core 1862, load / store unit 1866). In at least one embodiment, register file 1858 is partitioned among each functional unit, such that a dedicated portion of register file 1858 is allocated to each functional unit. In at least one embodiment, register file 1858 is partitioned among different thread bundles being executed by graphics multiprocessor 1834.

[0354] In at least one embodiment, each of the GPGPU cores 1862 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 1834. In at least one embodiment, the GPGPU cores 1862 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 1862 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point algorithms or enable variable-precision floating-point algorithms. In at least one embodiment, the graphics multiprocessor 1834 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 1862 may also include fixed-function or special-function logic.

[0355] In at least one embodiment, the GPGPU core 1862 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 1862 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed using a single SIMD instruction. For example, in at least one embodiment, eight SIMD threads performing the same or similar operations can be executed in parallel using a single SIMD8 logic unit.

[0356] In at least one embodiment, the memory and cache interconnect 1868 is an interconnect network connecting each functional unit of the graphics multiprocessor 1834 to the register file 1858 and the shared memory 1870. In at least one embodiment, the memory and cache interconnect 1868 is a cross-switch interconnect that allows the load / store unit 1866 to perform load and store operations between the shared memory 1870 and the register file 1858. In at least one embodiment, the register file 1858 can operate at the same frequency as the GPGPU core 1862, resulting in very low latency for data transfer between the GPGPU core 1862 and the register file 1858. In at least one embodiment, the shared memory 1870 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 1834. In at least one embodiment, the cache memory 1872 can be used, for example, as a data cache to cache texture data communicated between functional units and texture units 1836. In at least one embodiment, the shared memory 1870 can also be used as a program-managed cache. In at least one embodiment, in addition to the data automatically cached in cache memory 1872, the thread executing on GPGPU core 1862 can also programmatically store data in shared memory.

[0357] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated with the core on a package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). In at least one embodiment, regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0358] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 5A and / or Figure 5B Details regarding inference and / or training logic 515 are provided. In at least one embodiment, inference and / or training logic 515 may be used in a graphics multiprocessor 1834 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0359] Figure 19A multi-GPU computing system 1900 according to at least one embodiment is illustrated. In at least one embodiment, the multi-GPU computing system 1900 may include a processor 1902 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 1906A-D via a host interface switch 1904. In at least one embodiment, the host interface switch 1904 is a PCI Express switch device that couples the processor 1902 to a PCI Express bus, through which the processor 1902 can communicate with the GPGPUs 1906A-D. In at least one embodiment, the GPGPUs 1906A-D may be interconnected via a set of high-speed P2P GPU-to-GPU links 1916. In at least one embodiment, the GPU-to-GPU links 1916 are connected to each of the GPGPUs 1906A-D via dedicated GPU links. In at least one embodiment, the P2P GPU links 1916 enable direct communication between each GPGPU 1906A-D without communication via the host interface bus 1904 to which the processor 1902 is connected. In at least one embodiment, when GPU-to-GPU traffic is directed to the P2P GPU link 1916, the host interface bus 1904 remains available for system memory access or, for example, communication with other instances of the multi-GPU computing system 1900 via one or more network devices. While in at least one embodiment, the GPGPUs 1906A-D are connected to the processor 1902 via the host interface switch 1904, in at least one embodiment, the processor 1902 includes direct support for the P2P GPU link 1916 and can be directly connected to the GPGPUs 1906A-D.

[0360] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 5A and / or Figure 5B Details are provided regarding inference and / or training logic 515. In at least one embodiment, inference and / or training logic 515 may be used in a multi-GPU computing system 1900 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0361] Figure 20This is a block diagram of a graphics processor 2000 according to at least one embodiment. In at least one embodiment, the graphics processor 2000 includes a ring interconnect 2002, a pipeline front end 2004, a media engine 2037, and graphics cores 2080A-2080N. In at least one embodiment, the ring interconnect 2002 couples the graphics processor 2000 to other processing units, said processing units including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2000 is one of many processors integrated within a multi-core processing system.

[0362] In at least one embodiment, the graphics processor 2000 receives multiple batches of commands via a ring interconnect 2002. In at least one embodiment, the input commands are interpreted by a command streamer 2003 in a pipeline front-end 2004. In at least one embodiment, the graphics processor 2000 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2080A-2080N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2003 provides the commands to the geometry pipeline 2036. In at least one embodiment, for at least some media processing commands, the command streamer 2003 provides the commands to a video front-end 2034, which is coupled to a media engine 2037. In at least one embodiment, the media engine 2037 includes a video quality engine (VQE) 2030 for video and image post-processing, and a multi-format encoding / decoding (MFX) engine 2033 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2036 and the media engine 2037 each generate an execution thread for thread execution resources provided by at least one graphics core 2080.

[0363] In at least one embodiment, the graphics processor 2000 includes scalable thread execution resources featuring graphics cores 2080A-2080N (which may be modular and sometimes referred to as core slices), each graphics core having multiple sub-cores 2050A-2050N, 2060A-2060N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2000 may have any number of graphics cores 2080A. In at least one embodiment, the graphics processor 2000 includes graphics cores 2080A having at least a first sub-core 2050A and a second sub-core 2060A. In at least one embodiment, the graphics processor 2000 is a low-power processor having a single sub-core (e.g., 2050A). In at least one embodiment, the graphics processor 2000 includes multiple graphics cores 2080A-2080N, each graphics core including a set of first sub-cores 2050A-2050N and a set of second sub-cores 2060A-2060N. In at least one embodiment, each of the first sub-cores 2050A-2050N includes at least a first set of execution units 2052A-2052N and media / texture samplers 2054A-2054N. In at least one embodiment, each of the second sub-cores 2060A-2060N includes at least a second set of execution units 2062A-2062N and samplers 2064A-2064N. In at least one embodiment, each of the sub-cores 2050A-2050N and 2060A-2060N shares a set of shared resources 2070A-2070N. In at least one embodiment, the shared resources include a shared cache memory and pixel operation logic.

[0364] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 5A and / or Figure 5B Details regarding inference and / or training logic 515 are provided. In at least one embodiment, inference and / or training logic 515 may be used in graphics processor 2000 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0365] Figure 21This is a block diagram illustrating a microarchitecture for a processor 2100 according to at least one embodiment, the processor 2100 including logic circuitry for executing instructions. In at least one embodiment, the processor 2100 can execute instructions, including x86 instructions, ARM instructions, and special-purpose instructions for application-specific integrated circuits (ASICs). In at least one embodiment, the processor 2100 may include registers for storing packaged data, such as the 64-bit wide MMX registers used in Intel Corporation's Santa Clara, California-enabled MMX technology microprocessors. TM Registers. In at least one embodiment, MMX registers available in integer and floating-point forms can operate alongside packaged data elements accompanied by Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, a 128-bit wide XMM register associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as “SSEx”) technologies can hold such packaged data operands. In at least one embodiment, processor 2100 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0366] In at least one embodiment, processor 2100 includes an ordered front end (“front end”) 2101 to fetch instructions to be executed and prepare instructions for later use in the processor pipeline. In at least one embodiment, front end 2101 may include several units. In at least one embodiment, instruction prefetcher 2126 fetches instructions from memory and provides the instructions to instruction decoder 2128, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2128 decodes the received instructions into one or more machine-executable so-called “micro-instructions” or “micro-operations” (also referred to as “micro-operations” or “micro-instructions”). In at least one embodiment, instruction decoder 2128 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, trace cache 2130 may assemble the decoded micro-instructions into a program-ordered sequence or trace in micro-instruction queue 2134 for execution. In at least one embodiment, when the trace cache 2130 encounters complex instructions, the microcode ROM 2132 provides the microinstructions required to complete the operation.

[0367] In at least one embodiment, some instructions may be converted into a single micro-operation, while others require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-instructions are required to complete an instruction, the instruction decoder 2128 may access the microcode ROM 2132 to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-instructions for processing at the instruction decoder 2128. In at least one embodiment, if multiple micro-instructions are required to complete the operation, the instructions may be stored in the microcode ROM 2132. In at least one embodiment, the trace cache 2130 references an entry point programmable logic array (“PLA”) to determine the correct micro-instruction pointer for reading a microcode sequence from the microcode ROM 2132 to complete one or more instructions, according to at least one embodiment. In at least one embodiment, after the microcode ROM 2132 has completed the micro-operation ordering of the instructions, the machine front end 2101 may resume fetching micro-operations from the trace cache 2130.

[0368] In at least one embodiment, the out-of-order execution engine (“out-of-order engine”) 2103 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions descend the pipeline and are scheduled for execution. In at least one embodiment, the out-of-order execution engine 2103 includes, but is not limited to, an allocator / register renamer 2140, a memory microinstruction queue 2142, an integer / floating-point microinstruction queue 2144, a memory scheduler 2146, a fast scheduler 2102, a slow / general-purpose floating-point scheduler (“slow / general-purpose FP scheduler”) 2104, and a simple floating-point scheduler (“simple FP scheduler”) 2106. In at least one embodiment, the fast scheduler 2102, the slow / general-purpose floating-point scheduler 2104, and the simple floating-point scheduler 2106 are also collectively referred to as “microinstruction schedulers 2102, 2104, 2106”. In at least one embodiment, allocator / register renamer 2140 allocates the machine buffers and resources required for the sequential execution of each microinstruction. In at least one embodiment, allocator / register renamer 2140 renames logical registers to entries in a register file. In at least one embodiment, allocator / register renamer 2140 also allocates entries for each microinstruction in one of two microinstruction queues, memory microinstruction queue 2142 for memory operations and integer / floating-point microinstruction queue 2144 for non-memory operations, preceding memory scheduler 2146 and microinstruction schedulers 2102, 2104, 2106. In at least one embodiment, microinstruction schedulers 2102, 2104, 2106 determine when they are ready to execute a microinstruction based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, fast scheduler 2102 can schedule on each half of the master clock cycle, while slow / general-purpose floating-point scheduler 2104 and simple floating-point scheduler 2106 can schedule once per master processor clock cycle. In at least one embodiment, microinstruction schedulers 2102, 2104, and 2106 arbitrate the scheduling ports to schedule microinstructions for execution.

[0369] In at least one embodiment, execution block 2111 includes, but is not limited to, integer register file / branch network 2108, floating-point register file / branch network (“FP register file / branch network”) 2110, address generation units (“AGU”) 2112 and 2114, fast arithmetic logic units (“fast ALU”) 2116 and 2118, slow arithmetic logic unit (“slow ALU”) 2120, floating-point ALU (“FP”) 2122, and floating-point move unit (“FP move”) 2124. In at least one embodiment, integer register file / branch network 2108 and floating-point register file / bypass network 2110 are also referred to herein as “register files 2108, 2110”. In at least one embodiment, AGUs 2112 and 2114, fast ALUs 2116 and 2118, slow ALU 2120, floating-point ALU 2122, and floating-point movement unit 2124 are also referred to herein as "execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124". In at least one embodiment, execution block 2111 may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0370] In at least one embodiment, register networks 2108, 2110 may be arranged between microinstruction schedulers 2102, 2104, 2106 and execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124. In at least one embodiment, integer register file / branch network 2108 performs integer operations. In at least one embodiment, floating-point register file / branch network 2110 performs floating-point operations. In at least one embodiment, each of register networks 2108, 2110 may include, but is not limited to, a branch network that can bypass or forward recently completed results not yet written to a register file to a new dependent object. In at least one embodiment, register networks 2108, 2110 may communicate data with each other. In at least one embodiment, integer register file / branch network 2108 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, the floating-point register file / branch network 2110 may include, but is not limited to, entries with a width of 128 bits, since floating-point instructions typically have operands with a width of 64 to 128 bits.

[0371] In at least one embodiment, execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124 can execute instructions. In at least one embodiment, register networks 2108 and 2110 store integer and floating-point data operation values ​​that the microinstructions need to execute. In at least one embodiment, processor 2100 may include, but is not limited to, any number of execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124, and combinations thereof. In at least one embodiment, floating-point ALU 2122 and floating-point movement unit 2124 can perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2122 may include, but is not limited to, a 64-bit multiplication-64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2116 and 2118. In at least one embodiment, fast ALUs 2116 and 2118 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations are routed to slow ALU 2120, because slow ALU 2120 can include, but is not limited to, integer execution hardware for long-latency type operations, such as multipliers, shifters, flag logic, and branching. In at least one embodiment, memory load / store operations can be performed by ALUs 2112 and 2114. In at least one embodiment, fast ALU 2116, fast ALU 2118, and slow ALU 2120 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2116, fast ALU 2118, and slow ALU 2120 can be implemented to support various data bit sizes, including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, the floating-point ALU 2122 and the floating-point moving unit 2124 can be implemented to support a range of operands with various bit widths, for example, they can be combined with SIMD and multimedia instructions to operate on 128-bit wide packaged data operands.

[0372] In at least one embodiment, microinstruction schedulers 2102, 2104, and 2106 schedule dependent operations before the parent load completes execution. In at least one embodiment, since microinstructions can be speculatively scheduled and executed within processor 2100, processor 2100 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be a dependent operation running in the pipeline that temporarily deprives the scheduler of the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and may allow independent operations to be completed. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0373] In at least one embodiment, "register" can refer to an onboard processor storage location that can be used as part of an instruction that identifies an operand. In at least one embodiment, a register can be one that can be used externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented using a variety of different techniques via circuitry within the processor, such as dedicated physical registers, dynamically allocated physical registers renamed using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for encapsulating data.

[0374] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 5A and / or Figure 5B Details regarding inference and / or training logic 515 are provided. In at least one embodiment, some or all of the inference and / or training logic 515 may be incorporated into execution block 2111 and other memories or registers shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs shown in execution block 2111. Furthermore, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of execution block 2111 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0375] Figure 22A deep learning application processor 2200 according to at least one embodiment is illustrated. In at least one embodiment, the deep learning application processor 2200 uses instructions, which, if executed by the deep learning application processor 2200, cause the deep learning application processor 2200 to perform some or all of the processes and techniques described herein. In at least one embodiment, the deep learning application processor 2200 is an application-specific integrated circuit (ASIC). In at least one embodiment, the application processor 2200 performs matrix multiplication operations or is "hardwired" into hardware as a result of executing one or more instructions or both. In at least one embodiment, the deep learning application processor 2200 includes, but is not limited to, a processing cluster 2210(1)-2210(12), an inter-chip link (“ICL”) 2220(1)-18@20(12), an inter-chip controller (“ICC”) 2230(1)-2230(2), a second-generation high-bandwidth memory (“HBM2”) 2240(1)-2240(4), a memory controller (“MemCtrlr”) 2242(1)-2242(4), a high-bandwidth memory physical layer (“HBM PHY”) 2244(1)-2244(4), a management controller central processing unit (“management controller CPU”) 2250, a serial peripheral interface, internal integrated circuits and general purpose input / output blocks (“SPI, I2C, GPIO”) 2260, a peripheral component interconnect fast controller and direct memory access block (“PCIe controller and DMA”) 2270, and a sixteen-channel peripheral component interconnect fast port (“PCI Express”). x 16”)2280.

[0376] In at least one embodiment, processing cluster 2210 can perform deep learning operations, including inference or prediction operations based on weight parameters computed using one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2210 can include, but is not limited to, any number and type of processors. In at least one embodiment, deep learning application processor 2200 can include any number and type of processing cluster 2200. In at least one embodiment, the inter-chip link 2220 is bidirectional. In at least one embodiment, the inter-chip link 2220 and the inter-chip controller 2230 enable multiple deep learning application processors 2200 to exchange information, including activation information generated from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, deep learning application processor 2200 can include any number (including zero) and type of ICL 2220 and ICC 2230.

[0377] In at least one embodiment, the HBM2 2240 provides a total of 32GB of memory. In at least one embodiment, the HBM2 2240(i) is associated with both the memory controller 2242(i) and the HBM PHY 2244(i), where “i” is any integer. In at least one embodiment, any number of HBM2 2240s can provide any type and total amount of high-bandwidth memory and can be associated with any number (including zero) and type of memory controller 2242 and HBM PHY 2244. In at least one embodiment, any number and type of blocks can replace SPI, I2C, GPIO 3360, PCIe controller 2260 and DMA2270 and / or PCIe 2280 to implement any number and type of communication standards in any technically feasible manner.

[0378] Inference and / or training logic 515 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 5A and / or Figure 5B Details regarding the inference and / or training logic 515 are provided. In at least one embodiment, the deep learning application processor is used to train a machine learning model (e.g., a neural network) to predict or infer information provided to the deep learning application processor 2200. In at least one embodiment, the deep learning application processor 2200 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2200. In at least one embodiment, the processor 2200 may be used to perform one or more neural network use cases described herein.

[0379] Figure 23This is a block diagram of a neuromorphic processor 2300 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2300 may receive one or more inputs from a source external to the neuromorphic processor 2300. In at least one embodiment, these inputs may be transmitted to one or more neurons 2302 within the neuromorphic processor 2300. In at least one embodiment, the neurons 2302 and their components may be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2300 may include, but is not limited to, thousands upon thousands of instances of neurons 2302, but any suitable number of neurons 2302 may be used. In at least one embodiment, each instance of a neuron 2302 may include a neuron input 2304 and a neuron output 2306. In at least one embodiment, a neuron 2302 may generate an output that can be transmitted to the inputs of other instances of the neuron 2302. In at least one embodiment, the neuron input 2304 and the neuron output 2306 may be interconnected via synapses 2308.

[0380] In at least one embodiment, neuron 2302 and synapse 2308 may be interconnected, causing neuromorphic processor 2300 to operate to process or analyze information received by neuromorphic processor 2300. In at least one embodiment, neuron 2302 may send an output pulse (or “trigger” or “peak”) when the input received through neuron input 2304 exceeds a threshold. In at least one embodiment, neuron 2302 may sum or integrate the signal received at neuron input 2304. For example, in at least one embodiment, neuron 2302 may be implemented as a leaky integral-triggered neuron, wherein if the summation (referred to as “membrane potential”) exceeds a threshold, neuron 2302 may use a transfer function such as a sigmoid or threshold function to generate an output (or “trigger”). In at least one embodiment, the leaky integral-triggered neuron may sum the signal received at neuron input 2304 to a membrane potential and may apply an attenuation factor (or leak) to reduce the membrane potential. In at least one embodiment, a leaking integral-triggered neuron may trigger if multiple input signals are received at neuron input 2304 quickly enough to exceed a threshold (i.e., before the membrane potential decays too low to trigger). In at least one embodiment, neuron 2302 may be implemented using circuitry or logic that receives input, integrates the input to the membrane potential, and decays the membrane potential. In at least one embodiment, the input may be averaged, or any other suitable transfer function may be used. Furthermore, in at least one embodiment, neuron 2302 may include, but is not limited to, comparator circuitry or logic that generates an output spike at neuron output 2306 when the result of applying the transfer function to neuron input 2304 exceeds a threshold. In at least one embodiment, once neuron 2302 is triggered, it can ignore previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, neuron 2302 may resume normal operation after a suitable period of time (or recovery period).

[0381] In at least one embodiment, neurons 2302 can be interconnected via synapses 2308. In at least one embodiment, synapses 2308 can be operated to transmit signals from the output of a first neuron 2302 to the input of a second neuron 2302. In at least one embodiment, neurons 2302 can transmit information on more than one instance of synapses 2308. In at least one embodiment, one or more instances of neuron outputs 2306 can be connected via instances of synapses 2308 to instances of neuron inputs 2304 within the same neuron 2302. In at least one embodiment, an instance of neuron 2302 that produces an output to be transmitted on the instance of synapse 2308 may be referred to as a "presynaptic neuron". In at least one embodiment, an instance of neuron 2302 that receives input transmitted via an instance of synapse 2308 may be referred to as a "postsynaptic neuron". In at least one embodiment, regarding various instances of synapse 2308, since instances of neuron 2302 can receive input from one or more instances of synapse 2308 and can also transmit output through one or more instances of synapse 2308, a single instance of neuron 2302 can be both a "presynaptic neuron" and a "postsynaptic neuron".

[0382] In at least one embodiment, neurons 2302 may be organized into one or more layers. In at least one embodiment, each instance of neuron 2302 may have a neuron output 2306 that fans out to one or more neuron inputs 2304 via one or more synapses 2308. In at least one embodiment, the neuron output 2306 of neuron 2302 in the first layer 2310 may be connected to the neuron input 2304 of neuron 2302 in the second layer 2312. In at least one embodiment, layer 2310 may be referred to as a “feedforward layer.” In at least one embodiment, each instance of neuron 2302 in an instance of the first layer 2310 may fan out to each instance of neuron 2302 in the second layer 2312. In at least one embodiment, the first layer 2310 may be referred to as a “fully connected feedforward layer.” In at least one embodiment, each instance of neuron 2302 in an instance of the second layer 2312 fans out to fewer than all instances of neuron 2302 in the third layer 2314. In at least one embodiment, the second layer 2312 may be referred to as a “sparsely connected feedforward layer.” In at least one embodiment, neurons 2302 in the second layer 2312 may fan out to neurons 2302 in multiple other layers, including neurons 2302 fan out to the second layer 2312. In at least one embodiment, the second layer 2312 may be referred to as a "recurrent layer". In at least one embodiment, the neuromorphic processor 2300 may be any suitable combination of recurrent layers and feedforward layers, including but not limited to sparsely connected feedforward layers and fully connected feedforward layers.

[0383] In at least one embodiment, the neuromorphic processor 2300 may include, but is not limited to, a reconfigurable interconnect architecture or dedicated hardwired interconnects to connect synapses 2308 to neurons 2302. In at least one embodiment, the neuromorphic processor 2300 may include, but is not limited to, circuitry or logic that allows synapses to be assigned to different neurons 2302 as needed, depending on the neural network topology and neuron fan-in / fan-out. For example, in at least one embodiment, synapses 2308 may be connected to neurons 2302 using interconnect structures (such as on-chip networks) or via dedicated connections. In at least one embodiment, synaptic interconnects and their components may be implemented using circuitry or logic.

[0384] Figure 24A processing system according to at least one embodiment is illustrated. In at least one embodiment, system 2400 includes one or more processors 2402 and one or more graphics processors 2408, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 2402 or processor cores 2407. In at least one embodiment, system 2400 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0385] In at least one embodiment, system 2400 may include or be integrated into a server-based gaming platform, including a game console, mobile game console, handheld game console, or online game console, which are game and media consoles. In at least one embodiment, system 2400 is a mobile phone, smartphone, tablet computing device, or mobile internet device. In at least one embodiment, processing system 2400 may also include components coupled to or integrated into a wearable device, such as a smartwatch, smart glasses, augmented reality, or virtual reality device. In at least one embodiment, processing system 2400 is a television or set-top box device having one or more processors 2402 and a graphical interface generated by one or more graphics processors 2408.

[0386] In at least one embodiment, each of the one or more processors 2402 includes one or more processor cores 2407 for processing instructions that, when executed, perform operations against the system and user software. In at least one embodiment, each of the one or more processor cores 2407 is configured to process a specific instruction sequence 2409. In at least one embodiment, the instruction sequence 2409 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). In at least one embodiment, each processor core 2407 may process a different instruction sequence 2409, which may include instructions that facilitate the emulation of other instruction sequences. In at least one embodiment, the processor core 2407 may also include other processing devices, such as a digital signal processor (DSP).

[0387] In at least one embodiment, processor 2402 includes cache memory 2404. In at least one embodiment, processor 2402 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory is shared among various components of processor 2402. In at least one embodiment, processor 2402 also uses an external cache (e.g., a Level 3 (L3) cache or a last-level cache (LLC)) (not shown), which can be shared among processor cores 2407 using known cache coherence techniques. In at least one embodiment, processor 2402 further includes a register file 2406, which may include different types of registers for storing different types of data (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers). In at least one embodiment, register file 2406 may include general-purpose registers or other registers.

[0388] In at least one embodiment, one or more processors 2402 are coupled to one or more interface buses 2410 to transmit communication signals, such as address, data, or control signals, between the processors 2402 and other components in the system 2400. In at least one embodiment, the interface bus 2410 may be a processor bus, such as a version of the Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 2410 is not limited to the DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 2402 includes an integrated memory controller 2416 and a platform controller hub 2430. In at least one embodiment, the memory controller 2416 facilitates communication between memory devices and other components of the processing system 2400, while the platform controller hub (PCH) 2430 provides connectivity to input / output (I / O) devices via a local I / O bus.

[0389] In at least one embodiment, memory device 2420 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or a device with suitable performance for use as processor memory. In at least one embodiment, memory device 2420 may be used as system memory of processing system 2400 to store data 2422 and instructions 2421 for use when one or more processors 2402 execute an application or process. In at least one embodiment, memory controller 2416 is also coupled to an optional external graphics processor 2412, which may communicate with one or more graphics ...

Claims

1. A system comprising: One or more processors; as well as A memory that stores instructions, which, due to execution by the one or more processors, enable the system to: Identify the first hardware accelerator as a pre-selected hardware accelerator to execute the client set based on configuration information, wherein the configuration information indicates the type of the client set; The client set is assigned to the first hardware accelerator to process a batch of frames; A first determination is made that the metric associated with each of the client sets exceeds a threshold; In response to the first determination, a subset of clients from the client set is assigned to a second hardware accelerator set such that the metric associated with each of the client sets is below the threshold. As a result of allocating the client subset, a second determination is generated regarding whether to reassign at least one client from the client subset to the first hardware accelerator so that the metric associated with each of the client subset remains below the threshold. as well as Based at least in part on the second determination, at least one client in the client subset is reassigned to the first hardware accelerator.

2. The system of claim 1, wherein the threshold is determined at least in part based on the frame rate associated with the batch of frames.

3. The system of claim 1, wherein the metric further includes a value indicating the percentage of activity of the first hardware accelerator.

4. The system as claimed in claim 1, wherein: The first hardware accelerator also includes a video image synthesizer (VIC); and The second set of hardware accelerators also includes a graphics processing unit (GPU).

5. The system of claim 1, wherein the metric associated with each of the client set is measured at least in part based on information obtained from one or more application programming interface (API) calls submitted by the client set for performing one or more transformations of the batch frame.

6. The system of claim 1, wherein the metric further includes the amount of time taken by the at least one client in the client subset to perform processing of the batch frame using the first hardware accelerator.

7. The system of claim 1, wherein the metric further comprises a percentage of the processing power of the first hardware accelerator representing the processing power of the at least one client in the subset of clients for processing the batch of frames.

8. The system of claim 1, wherein the metric further includes an average load generated by processing at least the batch of frames provided by the at least one client in the subset of clients.

9. The system of claim 1, wherein the first determination is generated during a time interval.

10. The system of claim 1, wherein the first determination is generated at least in part based on historical data.

11. The system of claim 1, wherein the configuration information is generated at least in part based on user input.

12. The system of claim 1, wherein the threshold is specified by the user.

13. The system of claim 1, wherein the type includes: Modify the resolution of this batch of frames, convert the format of this batch of frames, or modify the color of this batch of frames.

14. The system of claim 1, wherein the metric is obtained from a hardware performance counter included in the first hardware accelerator.

15. The system of claim 1, wherein the first hardware accelerator further comprises a field-programmable gate array (FPGA).

16. The system of claim 1, wherein the memory further stores instructions that, upon execution by the one or more processors, cause the system to obtain the metric via a system call.

17. The system of claim 1, wherein the client set further includes a set of components in the artificial intelligence pipeline.

18. The system of claim 17, wherein the artificial intelligence pipeline comprises one or more neural networks.

19. The system of claim 1, wherein the memory further stores instructions that, when executed by the one or more processors, cause the system to cause the first hardware accelerator to process the batch of frames by at least converting the batch of frames from a first format to a second format.

20. The system of claim 1, wherein the memory further stores instructions that, when executed by the one or more processors, cause the system to cause the first hardware accelerator to process the batch of frames by at least scaling the batch of frames.

21. The system of claim 1, wherein the memory further stores instructions that, when executed by the one or more processors, cause the system to cause the first hardware accelerator to process the batch of frames by at least modifying one or more color values ​​associated with at least one frame in the batch.

22. A method comprising: The application client set is assigned to the VIC engine of the video image synthesizer, which is instructed to be a pre-selected hardware accelerator, to execute the application client set at least in part based on configuration information, including the type of the application client set; It was determined that the average time taken by the VIC engine to perform processing for the application client set exceeded the frame processing threshold; A subset of application clients in the application client set is assigned to a processing unit set that is different from the VIC engine, so that the average time used by the processing unit set is lower than the frame processing threshold. Determine whether reallocating the application client subset keeps the average time used by the VIC below the frame processing threshold; and Move the subset of application clients back to the VIC engine.

23. The method of claim 22, wherein the average time used to determine the VIC engine and the movement are repeated once or more.

24. The method of claim 22, wherein the frame processing threshold is determined at least in part based on the frame rate of the video processing.

25. The method of claim 22, wherein the reallocation of the application client subset is performed using a load balancer.

26. The method of claim 25, wherein the load balancer allocating the subset of application clients includes processing threads.

27. The method of claim 25, wherein the load balancer allocating the subset of application clients maintains a table of the set of application clients.

28. The method of claim 27, wherein the table of the application client set includes a processing engine assigned to each client and the average time spent by the client to compute the transformation of each processing engine.

29. The method of claim 22, wherein the set of processing units includes an image processing unit (GPU).

30. A non-transitory computer-readable storage medium storing executable instructions thereon, the instructions causing the computer system to: First performance data is obtained associated with a video image synthesizer (VIC) that is indicated as a pre-selected hardware accelerator, the first performance data being associated with a set of application clients assigned to the VIC, the VIC being used to execute the set of application clients at least in part based on the type of the set of application clients; It is determined that the first performance data exceeds the threshold; As a result of determining that the first performance data exceeds the threshold, the subset of application clients in the application client set is assigned to the processor set so that the second performance data associated with the application client set is lower than the threshold; The processor set is then configured to execute a subset of the application clients to reduce the load on the VIC. as well as By determining at least that the second performance data remains below the threshold, at least one client in the subset of application clients is reassigned to the VIC.

31. The non-transitory computer-readable storage medium of claim 30, wherein the threshold is determined at least in part based on one or more frame rates associated with the set of application clients.

32. The non-transitory computer-readable storage medium of claim 30, wherein the processor set includes a field-programmable gate array (FPGA).

33. The non-transitory computer-readable storage medium of claim 30, wherein the instructions further include instructions that, upon execution by the one or more processors, cause the computer system to maintain a table of the set of application clients, each application client being a member of the table.

34. The non-transitory computer-readable storage medium of claim 33, wherein the table of the application client set comprises: Information indicating the subset of the application client to which the processor set is assigned, and the average time spent by the processor set in calculating the transformation of the application client subset.

Images