Shift register unit, driving method, driving circuit and display device

Abstract

A shift register unit, a driving method, a driving circuit and a display device, wherein the shift register unit comprises: a control circuit (10) configured to adjust the signals of a first node (N1) and a second node (N2) according to an input signal terminal (INP), a first control signal terminal (CN1), a second control signal terminal (CN2) and a first reference signal terminal (VREF1); a cascade circuit (20) configured to provide a signal of a first cascade clock signal terminal (GCK1) to a cascade output terminal (GO) according to the signal of the first node (N1); and an output circuit (30) configured to provide a signal of a control clock signal terminal (CCK) to a driving output terminal (SO) according to the signal of the first node (N1), and to provide a signal of a second reference signal terminal (VREF2) to the driving output terminal (SO) according to the signal of the second node (N2).

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register unit, a driving method, a driving circuit and a display device. Background Art

[0002] With the rapid development of display technology, display devices are increasingly developing towards high integration and low cost. Among them, GOA (Gate Driver on Array) technology integrates TFT (Thin Film Transistor) drive circuits on the array substrate of the display device to form a scan drive for the display device. Among them, the drive circuit is usually composed of multiple cascaded shift registers. However, the output of the shift register is unstable, which will cause display abnormality. Summary of the invention

[0003] The shift register unit provided by the embodiment of the present disclosure includes:

[0004] A control circuit is electrically connected to an input signal terminal, a reset signal terminal, a first control signal terminal, a second control signal terminal, a first reference signal terminal, a first node, and a second node, respectively; and the control circuit is configured to adjust signals of the first node and the second node according to the input signal terminal, the first control signal terminal, the second control signal terminal, and the first reference signal terminal;

[0005] a cascade circuit, electrically connected to the first cascade clock signal terminal, the first node and the cascade output terminal respectively; and the cascade circuit is configured to provide the signal of the first cascade clock signal terminal to the cascade output terminal according to the signal of the first node;

[0006] The output circuit is electrically connected to the control clock signal terminal, the first node, the second node, the second reference signal terminal and the driving output terminal respectively; and the output circuit is configured to provide the signal of the control clock signal terminal to the driving output terminal according to the signal of the first node, and to provide the signal of the second reference signal terminal to the driving output terminal according to the signal of the second node.

[0007] In some examples the output circuit includes: a first transistor and a second transistor;

[0008] The gate of the first transistor is electrically connected to the first node, the first terminal of the first transistor is electrically connected to the control clock signal terminal, and the second terminal of the first transistor is electrically connected to the driving output terminal;

[0009] A gate of the second transistor is electrically connected to the second node, a first terminal of the second transistor is electrically connected to the second reference signal terminal, and a second terminal of the second transistor is electrically connected to the driving output terminal.

[0010] In some examples, the output circuit further includes: a third transistor and a fourth transistor;

[0011] The gate of the third transistor is electrically connected to the control signal terminal, the first terminal of the third transistor is electrically connected to the second terminal of the first transistor, and the second terminal of the third transistor is electrically connected to the driving output terminal;

[0012] The gate of the fourth transistor is electrically connected to the control signal terminal, the first terminal of the fourth transistor is electrically connected to the second terminal of the second transistor, and the second terminal of the fourth transistor is electrically connected to the driving output terminal.

[0013] In some examples, the cascade circuit includes: a fifth transistor and a storage capacitor;

[0014] The gate of the fifth transistor is electrically connected to the first node, the first terminal of the fifth transistor is electrically connected to the first cascade clock signal terminal, and the second terminal of the fifth transistor is electrically connected to the cascade output terminal;

[0015] The first end of the storage capacitor is electrically connected to the first node, and the storage capacitor is electrically connected to the cascade output end.

[0016] In some examples, the shift register unit further includes: a sixth transistor;

[0017] A gate of the sixth transistor is electrically connected to the driving output terminal, a first terminal of the sixth transistor is electrically connected to the first reference signal terminal, and a second terminal of the sixth transistor is electrically connected to the second node.

[0018] In some examples, the control circuit includes:

[0019] An input circuit is electrically connected to the input signal terminal, the first control signal terminal and the intermediate node respectively; and the input circuit is configured to provide the signal of the first control signal terminal to the intermediate node under the control of the signal of the input signal terminal;

[0020] a reset circuit, electrically connected to the reset signal terminal, the second control signal terminal and the intermediate node respectively; and the reset circuit is configured to provide the signal of the second control signal terminal to the intermediate node under the control of the signal of the reset signal terminal;

[0021] a node adjustment circuit, electrically connected to the first reference signal terminal, the second cascade clock signal terminal, the second node and the intermediate node respectively; and the node adjustment circuit is configured to provide the signal of the first reference signal terminal to the second node under the control of the signal of the intermediate node; and provide the signal of the first reference signal terminal to the intermediate node under the control of the second cascade clock signal terminal and the signal of the second node;

[0022] A stabilization circuit is electrically connected to the intermediate node, the first node and the control signal end respectively; and the stabilization circuit is configured to conduct the intermediate node and the first node under the control of the signal of the control signal end.

[0023] In some examples, the input circuit includes: a seventh transistor;

[0024] A gate of the seventh transistor is electrically connected to the input signal terminal, a first terminal of the seventh transistor is electrically connected to the first control signal terminal, and a second terminal of the seventh transistor is electrically connected to the intermediate node.

[0025] In some examples, the reset circuit includes: an eighth transistor;

[0026] A gate of the eighth transistor is electrically connected to the reset signal terminal, a first terminal of the eighth transistor is electrically connected to the second control signal terminal, and a second terminal of the eighth transistor is electrically connected to the intermediate node.

[0027] In some examples, the node adjustment circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, and a stabilizing capacitor;

[0028] The gate of the ninth transistor is electrically connected to the intermediate node, the first terminal of the ninth transistor is electrically connected to the first reference signal terminal, and the second terminal of the ninth transistor is electrically connected to the second node;

[0029] The gate and the first terminal of the tenth transistor are both electrically connected to the second cascade clock signal terminal, and the second terminal of the tenth transistor is electrically connected to the second node;

[0030] The gate of the eleventh transistor is electrically connected to the second node, the first terminal of the eleventh transistor is electrically connected to the first reference signal terminal, and the second terminal of the eleventh transistor is electrically connected to the intermediate node;

[0031] A first end of the stabilizing capacitor is electrically connected to the second node, and a second end of the stabilizing capacitor is electrically connected to the first reference signal end.

[0032] In some examples, the stabilization circuit includes: a twelfth transistor;

[0033] The gate of the twelfth transistor is electrically connected to the control signal terminal, the first terminal of the twelfth transistor is electrically connected to the intermediate node, and the second terminal of the twelfth transistor is electrically connected to the first node.

[0034] In some examples, the shift register unit further includes: a thirteenth transistor and a fourteenth transistor;

[0035] The gate of the thirteenth transistor is electrically connected to the frame reset signal terminal, the first terminal of the thirteenth transistor is electrically connected to the first reference signal terminal, and the second terminal of the thirteenth transistor is electrically connected to the intermediate node;

[0036] The gate of the fourteenth transistor is electrically connected to the touch control terminal, the first terminal of the fourteenth transistor is electrically connected to the second reference signal terminal, and the second terminal of the fourteenth transistor is electrically connected to the driving output terminal.

[0037] The driving circuit provided by the embodiment of the present disclosure includes: a plurality of the above-mentioned shift register units connected in cascade;

[0038] The input signal terminal of the first-stage shift register unit is electrically connected to the frame trigger signal terminal;

[0039] In each of two adjacent shift register units, the input signal end of the next shift register unit is electrically connected to the cascade output end of the previous shift register unit, and the reset signal end of the previous shift register unit is electrically connected to the cascade output end of the next shift register unit.

[0040] The display device provided by the embodiment of the present disclosure includes the above-mentioned driving circuit.

[0041] In some examples, the display device further includes: a plurality of gate lines; one of the gate lines is electrically connected to a driving output terminal of one of the shift register units in the driving circuit.

[0042] In some examples, the display device further includes: a plurality of gate lines and a gate scanning circuit;

[0043] The driving circuit is electrically connected to the gate lines that are spaced apart by one gate line, and the gate scanning circuit is electrically connected to the remaining gate lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 Some structural schematic diagrams of shift registers provided in the embodiments of the present disclosure;

[0045] Figure 2 Some further structural schematic diagrams of shift registers provided in the embodiments of the present disclosure;

[0046] Figure 3 Some specific structural schematic diagrams of the shift register provided in the embodiments of the present disclosure;

[0047] Figure 4 Some signal timing diagrams provided for embodiments of the present disclosure;

[0048] Figure 5 Some further specific structural schematic diagrams of the shift register provided by the embodiments of the present disclosure;

[0049] Figure 6 A schematic diagram of the structure of a driving circuit provided in an embodiment of the present disclosure;

[0050] Figure 7 Some structural schematic diagrams of display devices provided by embodiments of the present disclosure;

[0051] Figure 8 Some other structural schematic diagrams of display devices provided by embodiments of the present disclosure;

[0052] Fig. 9 Some further structural schematic diagrams of display devices provided by embodiments of the present disclosure;

[0053] Fig.10 Some further structural schematic diagrams of the display device provided in the embodiments of the present disclosure. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present disclosure.

[0055] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0056] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, but are only intended to illustrate the content of the present invention. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0057] The shift register unit provided by the embodiment of the present invention is as follows: Figure 1 As shown, it may include:

[0058] The control circuit 10 is electrically connected to the input signal terminal INP, the reset signal terminal RST, the first control signal terminal CN1, the second control signal terminal CN2, the first reference signal terminal VREF1, the first node N1 and the second node N2 respectively; and the control circuit 10 is configured to adjust the signals of the first node N1 and the second node N2 according to the input signal terminal INP, the first control signal terminal CN1, the second control signal terminal CN2, and the first reference signal terminal VREF1;

[0059] The cascade circuit 20 is electrically connected to the first cascade clock signal terminal GCK1, the first node N1 and the cascade output terminal GO respectively; and the cascade circuit 20 is configured to provide the signal of the first cascade clock signal terminal GCK1 to the cascade output terminal GO according to the signal of the first node N1;

[0060] The output circuit 30 is electrically connected to the control clock signal terminal CCK, the first node N1, the second node N2, the second reference signal terminal VREF2 and the driving output terminal SO, respectively; and the output circuit 30 is configured to provide the signal of the control clock signal terminal CCK to the driving output terminal SO according to the signal of the first node N1, and to provide the signal of the second reference signal terminal VREF2 to the driving output terminal SO according to the signal of the second node N2.

[0061] In some examples, when implementing, Figure 2 As shown, the control circuit 10 may include:

[0062] The input circuit 11 is electrically connected to the input signal terminal INP, the first control signal terminal CN1 and the intermediate node N0 respectively; and the input circuit 11 is configured to provide the signal of the first control signal terminal CN1 to the intermediate node N0 under the control of the signal of the input signal terminal INP;

[0063] The reset circuit 12 is electrically connected to the reset signal terminal RST, the second control signal terminal CN2 and the intermediate node N0 respectively; and the reset circuit 12 is configured to provide the signal of the second control signal terminal CN2 to the intermediate node N0 under the control of the signal of the reset signal terminal RST;

[0064] The node adjustment circuit 13 is electrically connected to the first reference signal terminal VREF1, the second cascade clock signal terminal, the second node N2 and the intermediate node N0 respectively; and the node adjustment circuit 13 is configured to provide the signal of the first reference signal terminal VREF1 to the second node N2 under the control of the signal of the intermediate node N0; and provide the signal of the first reference signal terminal VREF1 to the intermediate node N0 under the control of the signal of the second cascade clock signal terminal and the second node N2;

[0065] The stabilization circuit 14 is electrically connected to the middle node N0, the first node N1 and the control signal terminal VC respectively; and the stabilization circuit 14 is configured to conduct the middle node N0 and the first node N1 under the control of the signal of the control signal terminal VC.

[0066] In some examples, when implementing, Figure 3 As shown, the input circuit 11 may include: a seventh transistor M7;

[0067] A gate of the seventh transistor M7 is electrically connected to the input signal terminal INP, a first terminal of the seventh transistor M7 is electrically connected to the first control signal terminal CN1, and a second terminal of the seventh transistor M7 is electrically connected to the middle node N0.

[0068] In some examples, when implementing, Figure 3 As shown, the reset circuit 12 may include: an eighth transistor M8;

[0069] A gate of the eighth transistor M8 is electrically connected to the reset signal terminal RST, a first terminal of the eighth transistor M8 is electrically connected to the second control signal terminal CN2, and a second terminal of the eighth transistor M8 is electrically connected to the middle node N0.

[0070] In some examples, when implementing, Figure 3 As shown, the node adjustment circuit 13 may include: a ninth transistor M9 and a tenth transistor M10;

[0071] A gate of the ninth transistor M9 is electrically connected to the middle node N0, a first terminal of the ninth transistor M9 is electrically connected to the first reference signal terminal VREF1, and a second terminal of the ninth transistor M9 is electrically connected to the second node N2;

[0072] The gate and the first end of the tenth transistor M10 are both electrically connected to the second cascade clock signal end, and the second end of the tenth transistor M10 is electrically connected to the second node N2;

[0073] A gate of the eleventh transistor M11 is electrically connected to the second node N2 , a first terminal of the eleventh transistor M11 is electrically connected to the first reference signal terminal VREF1 , and a second terminal of the eleventh transistor M11 is electrically connected to the middle node N0 .

[0074] In some examples, when implementing, Figure 3 As shown, the stabilization circuit 14 may include: a twelfth transistor M12;

[0075] A gate of the twelfth transistor M12 is electrically connected to the control signal terminal VC, a first end of the twelfth transistor M12 is electrically connected to the middle node N0, and a second end of the twelfth transistor M12 is electrically connected to the first node N1.

[0076] In some examples, when implementing, Figure 3 As shown, the output circuit 30 may include: a first transistor M1 and a second transistor M2;

[0077] The gate of the first transistor M1 is electrically connected to the first node N1, the first end of the first transistor M1 is electrically connected to the control clock signal end CCK, and the second end of the first transistor M1 is electrically connected to the driving output end SO;

[0078] A gate of the second transistor M2 is electrically connected to the second node N2, a first terminal of the second transistor M2 is electrically connected to the second reference signal terminal VREF2, and a second terminal of the second transistor M2 is electrically connected to the driving output terminal SO.

[0079] In some examples, when implementing, Figure 3 As shown, the cascade circuit 20 includes: a fifth transistor M5 and a storage capacitor;

[0080] A gate of the fifth transistor M5 is electrically connected to the first node N1, a first end of the fifth transistor M5 is electrically connected to the first cascade clock signal end GCK1, and a second end of the fifth transistor M5 is electrically connected to the cascade output end GO;

[0081] A first terminal of the storage capacitor is electrically connected to the first node N1, and the storage capacitor is electrically connected to the cascade output terminal GO.

[0082] In a specific implementation, according to the flow direction of the signal, the first end of the transistor can be used as its source and the second end can be used as its drain; or, the first end can be used as its drain and the second end can be used as its source, without making a specific distinction here.

[0083] It should be noted that the transistors mentioned in the above embodiments of the present disclosure may be TFTs or metal oxide semiconductor field effect transistors (MOS), which are not limited here.

[0084] In order to simplify the preparation process, in the specific implementation, in the embodiment of the present disclosure, as Figure 3 As shown, all transistors can be N-type transistors. Among them, the voltage difference V between the gate and the source of the N-type transistor gsWith its threshold voltage V th Satisfy the relationship V gs >V th For example, the twelfth transistor M12 may be an N-type transistor, and the voltage difference V between the gate and the source of the twelfth transistor M12 is gs1 With its threshold voltage V th1 The relationship between satisfies the formula: V gs1 >V th1 Of course, in the embodiment of the present disclosure, the transistor is an N-type transistor for example. For the case where the transistor is a P-type transistor, the design principle is the same as that of the present disclosure and also falls within the scope of protection of the present disclosure. In addition, the voltage difference V between the gate and the source of the P-type transistor is gs With its threshold voltage V th Satisfy the relationship V gs <V th For example, the twelfth transistor M12 may be a P-type transistor, and the voltage difference V between the gate and the source of the twelfth transistor M12 is gs1 With its threshold voltage V th1 The relationship between satisfies the formula: V gs1 <V th1 When turned on.

[0085] Furthermore, in a specific implementation, the P-type transistor is turned off under the action of a high-level signal and turned on under the action of a low-level signal, and the N-type transistor is turned on under the action of a high-level signal and turned off under the action of a low-level signal.

[0086] The above is only an example to illustrate the specific structure of the shift register unit provided in the embodiment of the present disclosure. In specific implementation, the specific structure of the above circuits is not limited to the above structure provided in the embodiment of the present disclosure, and can also be other structures known to those skilled in the art, which is not limited here.

[0087] Below Figure 3 Take the shift register unit shown in the figure as an example, combined with Figure 4 The signal timing diagram shown describes the working process of the above-mentioned shift register unit provided by the embodiment of the present disclosure. In the following description, 1 represents a high-level signal and 0 represents a low-level signal. It should be noted that 1 and 0 are logic levels, which are only for better explanation of the specific working process of the embodiment of the present disclosure, rather than the voltage applied to the gate of each transistor during specific implementation.

[0088] Specifically, select Figure 4 The signal timing diagram shown in the figure has six stages: T1, T2, T3, T4, T5, and T6. It should be noted that: Figure 4The signal timing diagram shown is only the working process of a certain shift register unit in a display frame. The working process of the shift register unit in other display frames is basically the same as the working process in this display frame, and will not be repeated here. Among them, the signal of the first reference signal terminal VREF1 is a low-level signal, the signal of the second reference signal terminal VREF2 is a high-level signal, and the control signal terminal VC is a high-level signal. The signal of the first control signal terminal CN1 is a high-level signal, and the signal of the second control signal terminal CN2 is a low-level signal.

[0089] In the T1 phase, GCK2=0, GCK1=0, INP=1, CCK=1, RST=0.

[0090] Since INP=1, the seventh transistor M7 is turned on to provide the signal of the first control signal terminal CN1 to the middle node N0, so that the middle node N0 is a high level signal, so that the ninth transistor M9 can be controlled to be turned on. The turned-on ninth transistor M9 provides the signal of the first reference signal terminal VREF1 to the second node N2, so that the signal of the second node N2 is a low level signal, so that the eleventh transistor M11 and the second transistor M2 can be controlled to be turned off. The twelfth transistor M12 is turned on under the control of the high level signal of the control signal terminal VC to conduct the middle node N0 and the first node N1, so that the signal of the first node N1 is a high level signal, thereby controlling the first transistor M1 and the fifth transistor M5 to be turned on. The turned-on first transistor M1 provides the high level signal of the control clock signal terminal CCK to the driving output terminal SO, so that the driving output terminal SO outputs a high level signal. The turned-on fifth transistor M5 provides the low level signal of the first cascade clock signal terminal GCK1 to the cascade output terminal GO, so that the cascade output terminal GO outputs a low level signal.

[0091] In the T2 phase, GCK2=1, GCK1=0, INP=0, CCK=1, RST=0.

[0092] Since INP=0, the seventh transistor M7 is turned off. Due to the effect of the storage capacitor, the signal of the first node N1 can be kept at a high level, thereby controlling the first transistor M1 and the fifth transistor M5 to be turned on. The turned-on first transistor M1 provides the high-level signal of the control clock signal terminal CCK to the driving output terminal SO, so that the driving output terminal SO outputs a high-level signal. The turned-on fifth transistor M5 provides the low-level signal of the first cascade clock signal terminal GCK1 to the cascade output terminal GO, so that the cascade output terminal GO outputs a low-level signal. In addition, the intermediate node N0 is a high-level signal, so that the ninth transistor M9 can be controlled to be turned on. The turned-on ninth transistor M9 provides the signal of the first reference signal terminal VREF1 to the second node N2, so that the signal of the second node N2 is a low-level signal, so that the eleventh transistor M11 and the second transistor M2 can be controlled to be turned off.

[0093] In the T3 stage, GCK2=0, GCK1=1, INP=0, CCK=0, RST=0.

[0094] Since INP=0, the seventh transistor M7 is turned off. Due to the effect of the storage capacitor, the signal of the first node N1 can be kept at a high level, thereby controlling the first transistor M1 and the fifth transistor M5 to be turned on. The turned-on fifth transistor M5 provides the high-level signal of the first cascade clock signal terminal GCK1 to the cascade output terminal GO, so that the cascade output terminal GO outputs a high-level signal. Due to the effect of the storage capacitor, the level of the first node N1 can be further pulled up, so that the first transistor M1 and the fifth transistor M5 can be turned on as completely as possible. Then the turned-on first transistor M1 provides the low-level signal of the control clock signal terminal CCK to the drive output terminal SO, so that the drive output terminal SO outputs a low-level signal. The turned-on fifth transistor M5 provides the high-level signal of the first cascade clock signal terminal GCK1 to the cascade output terminal GO, so that the cascade output terminal GO outputs a high-level signal. Since the signal of the first node N1 is further pulled up, the twelfth transistor M12 is turned off. In addition, the intermediate node N0 is a high-level signal, so that the ninth transistor M9 can be controlled to be turned on. The turned-on ninth transistor M9 provides the signal of the first reference signal terminal VREF1 to the second node N2, so that the signal of the second node N2 is a low level signal, thereby controlling the eleventh transistor M11 and the second transistor M2 to be turned off.

[0095] In the T4 stage, GCK2=0, GCK1=0, INP=0, CCK=1, RST=0.

[0096] Since INP=0, the seventh transistor M7 is turned off. Due to the effect of the storage capacitor, the signal of the first node N1 can be kept at a high level, thereby controlling the first transistor M1 and the fifth transistor M5 to be turned on. The turned-on fifth transistor M5 provides the low-level signal of the first cascade clock signal terminal GCK1 to the cascade output terminal GO, so that the cascade output terminal GO outputs a low-level signal. The turned-on first transistor M1 provides the high-level signal of the control clock signal terminal CCK to the drive output terminal SO, so that the drive output terminal SO outputs a high-level signal. In addition, the intermediate node N0 is a high-level signal, so that the ninth transistor M9 can be controlled to be turned on. The turned-on ninth transistor M9 provides the signal of the first reference signal terminal VREF1 to the second node N2, so that the signal of the second node N2 is a low-level signal, so that the eleventh transistor M11 and the second transistor M2 can be controlled to be turned off.

[0097] In the T5 stage, GCK2=0, GCK1=0, INP=0, CCK=1, RST=1.

[0098] Since INP=0, the seventh transistor M7 is turned off. Since RST=1, the eighth transistor M8 is turned on to provide the low-level signal of the second control signal terminal CN2 to the intermediate node N0, and the twelfth transistor M12 is turned on under the control of the high-level signal of the control signal terminal VC to connect the intermediate node N0 and the first node N1, so that the signal of the first node N1 is a low-level signal, thereby controlling the first transistor M1 and the fifth transistor M5 to be turned off. The driving output terminal SO maintains a high-level signal output, and the cascade output terminal GO maintains a low-level signal output.

[0099] In the T6 stage, GCK2=1, GCK1=0, INP=0, CCK=1, RST=0.

[0100] Since INP=0, the seventh transistor M7 is turned off. Since RST=0, the eighth transistor M8 is turned off. Since GCK2=1, the tenth transistor M10 is turned on to provide the high-level signal of the second cascade clock signal terminal to the second node N2, so that the signal of the second node N2 is high level, so as to control the eleventh transistor M11 and the second transistor M2 to be turned on. The turned-on eleventh transistor M11 provides the low-level signal of the first reference signal terminal VREF1 to the middle node N0, so that the signal of the middle node N0 is a low-level signal, and the first transistor M1 and the fifth transistor M5 are turned off. The turned-on second transistor M2 provides the high-level signal of the second reference signal terminal VREF2 to the driving output terminal SO, so that the driving output terminal SO outputs a high-level signal. And, the cascade output terminal GO maintains a low-level signal output.

[0101] The present disclosure also provides some shift register units, the structural diagram of which is shown in FIG. Figure 5 As shown, the implementation method in the above embodiment is modified. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0102] In some examples, when implementing, Figure 5 As shown, the output circuit 30 may further include: a third transistor M3 and a fourth transistor M4; wherein, the gate of the third transistor M3 is electrically connected to the control signal terminal VC, the first end of the third transistor M3 is electrically connected to the second end of the first transistor M1, and the second end of the third transistor M3 is electrically connected to the drive output terminal SO; the gate of the fourth transistor M4 is electrically connected to the control signal terminal VC, the first end of the fourth transistor M4 is electrically connected to the second end of the second transistor M2, and the second end of the fourth transistor M4 is electrically connected to the drive output terminal SO.

[0103] In application, when the driving output terminal SO is outputting, the first transistor M1 may couple out a noise voltage through the first node N1, and the noise voltage is superimposed on the driving output terminal SO, which may affect the driving output terminal SO. The shift register unit provided by the embodiment of the present invention can eliminate the noise voltage coupled out by the first transistor M1 due to the first node N1 by setting the third transistor M3, thereby improving the output stability of the driving output terminal SO.

[0104] In application, when the driving output terminal SO is outputting, the second transistor M2 may couple out a noise voltage through the second node N2, and the noise voltage is superimposed on the driving output terminal SO, which may affect the driving output terminal SO. The shift register unit provided by the embodiment of the present invention can eliminate the noise voltage coupled out by the second transistor M2 due to the second node N2 by setting the fourth transistor M4, thereby improving the output stability of the driving output terminal SO.

[0105] In some examples, when implementing, Figure 5 As shown, the shift register unit may further include: a sixth transistor M6; wherein the gate of the sixth transistor M6 is electrically connected to the driving output terminal SO, the first end of the sixth transistor M6 is electrically connected to the first reference signal terminal VREF1, and the second end of the sixth transistor M6 is electrically connected to the second node N2. Exemplarily, the sixth transistor M6 may be a P-type transistor. Furthermore, by setting the sixth transistor M6 to be turned on when the signal at the driving output terminal SO is a low-level signal, the low-level signal of the first reference signal terminal VREF1 is provided to the second node N2, and the signal at the second node N2 is further stabilized as a low-level signal.

[0106] In some examples, when implementing, Figure 5As shown, the shift register unit may further include: a thirteenth transistor M13 and a fourteenth transistor M14; wherein, the gate of the thirteenth transistor M13 is electrically connected to the frame reset signal terminal RST, the first end of the thirteenth transistor M13 is electrically connected to the first reference signal terminal VREF1, and the second end of the thirteenth transistor M13 is electrically connected to the intermediate node N0; the gate of the fourteenth transistor M14 is electrically connected to the touch control terminal, the first end of the fourteenth transistor M14 is electrically connected to the second reference signal terminal VREF2, and the second end of the fourteenth transistor M14 is electrically connected to the drive output terminal SO.

[0107] In practical applications, a blanking time is set between two adjacent display frames. During the blanking time, the thirteenth transistor M13 can be turned on by the frame reset signal terminal RST to stabilize the signal at the middle node N0 to a low level signal, thereby improving the output stability of the shift register unit.

[0108] In practical applications, the display device can realize not only the display function but also the touch function. In specific implementation, the display function and the touch function can be performed in time-sharing mode. Therefore, when the display device realizes the display function, the fourteenth transistor M14 can be controlled to be turned off through the touch control terminal. When the display device realizes the touch function, the fourteenth transistor M14 can be controlled to be turned on through the touch control terminal to provide the high-level signal of the second reference signal terminal VREF2 to the driving output terminal SO, so that the driving output terminal SO outputs a high-level signal.

[0109] It should be noted that, in the above embodiment, the sixth transistor M6 may be a P-type transistor, and the remaining transistors may be N-type transistors, which is not limited here.

[0110] The driving circuit provided by the embodiment of the present invention is as follows: Figure 6 As shown, it may include: a plurality of cascaded shift register units: for example, shift register units SR(1), SR(2) ... SR(n-1), SR(n) ... SR(N-1), SR(N) (a total of N shift register units, 1≤n≤N, n is an integer);

[0111] The input signal terminal INP of the first stage shift register unit SR (1) is electrically connected to the frame trigger signal terminal;

[0112] In each two adjacent shift register units, the input signal terminal INP of the next shift register unit SR(n) is electrically connected to the cascade output terminal GO of the previous shift register unit SR(n-1), and the reset signal terminal RST of the previous shift register unit SR(n-1) is electrically connected to the cascade output terminal GO of the next shift register unit SR(n).

[0113] Specifically, the specific structure of each shift register unit in the above-mentioned driving circuit is the same as the above-mentioned shift register unit in the present disclosure in terms of function and structure, and the repeated parts are not repeated. The driving circuit can be configured in a liquid crystal display device or in an electroluminescent display device, which is not limited here.

[0114] Specifically, in the above-mentioned driving circuit provided in the embodiment of the present disclosure, the first reference signal terminal VREF1VREF1 of each level of shift register unit SR(n) is coupled to the same DC signal terminal vss, and the second reference signal terminal VREF2VREF2 of each level of shift register unit SR(n) is coupled to the same DC signal terminal vdd.

[0115] Specifically, in the above-mentioned driving circuit provided in the embodiment of the present disclosure, if Figure 6 As shown, the first cascade clock signal terminal GCK1GCK1 of the 2k-1th stage shift register unit is coupled to the same clock terminal, i.e., the first clock terminal gck1. The second cascade clock signal terminal GCK2 of the 2k-1th stage shift register unit is coupled to the same clock terminal, i.e., the second clock terminal gck2. The first cascade clock signal terminal GCK1GCK1 of the 2kth stage shift register is coupled to the same clock terminal, i.e., the fourth clock terminal gck4. The second cascade clock signal terminal GCK2 of the 2kth stage shift register is coupled to the same clock terminal, i.e., the third clock terminal gck3. Wherein, k is a positive integer.

[0116] Specifically, in the above-mentioned driving circuit provided in the embodiment of the present disclosure, if Figure 6 As shown, the control clock signal terminal CCK of the 2k-1th stage shift register unit is electrically connected to the cck1 terminal, and the control clock signal terminal CCK of the 2kth stage shift register unit is electrically connected to the cck2 terminal.

[0117] The embodiment of the present disclosure also provides a display device, including the above-mentioned driving circuit. The principle of solving the problem of the display device is similar to that of the above-mentioned shift register unit, so the implementation of the display device can refer to the implementation of the above-mentioned shift register unit, and the repeated parts are not repeated here.

[0118] In a specific implementation, the display device may include multiple pixel units, multiple gate lines and data lines, and each pixel unit may include multiple sub-pixels, such as red sub-pixels, green sub-pixels, and blue sub-pixels. The above-mentioned display device provided in the embodiment of the present disclosure may be an organic light-emitting display device, or may also be a liquid crystal display device, which is not limited here.

[0119] In a display device, such as Figure 7As shown, a row of sub-pixels spx is electrically connected to a gate line GA, and a column of sub-pixels spx is electrically connected to a data line DA. The sub-pixels spx may include a scanning transistor N00 and a pixel electrode 200. Among them, the gate of the scanning transistor N00 may be electrically connected to the gate line GA, the source of the scanning transistor N00 is electrically connected to the data line DA, and the drain of the scanning transistor N00 is electrically connected to the pixel electrode 200. In addition, a gate line GA is electrically connected to a driving output terminal SOSO of a shift register unit in the driving circuit. In this way, the driving output terminal SOSO of the shift register unit can provide a signal to the gate of the scanning transistor N00 in the sub-pixel, and the cascade output terminal GOGO of the shift register unit is used to transmit a start signal to the next-level shift register unit. In this way, when the above-mentioned display device provided in the embodiment of the present disclosure is a liquid crystal display device, the above-mentioned driving circuit can be used as a gate driving circuit, which is applied to provide a gate scanning signal for the scanning transistor N00. It should be noted that the scanning transistor N00 may be a P-type transistor, which is turned on under the control of a low-level signal transmitted by the scanning transistor N00 on the gate line, and is cut off under the control of a high-level signal transmitted on the gate line. Alternatively, the scanning transistor N00 may also be an N-type transistor, which is turned on under the control of a high-level signal transmitted by the scanning transistor N00 on the gate line, and is cut off under the control of a low-level signal transmitted on the gate line.

[0120] Furthermore, two different types of transistors may be provided in different sub-pixels. Figure 8 and Fig. 9 As shown, the display device may further include a gate scanning circuit, wherein the driving circuit is electrically connected to the gate lines that are separated by one gate line, and the gate scanning circuit is electrically connected to the remaining gate lines. Figure 8As shown, the display device may include a plurality of gate lines GA-1, GA-2, GA-3, GA-4 ... GA-2m, ... GA-2M, and a row of sub-pixels is electrically connected to a gate line. Wherein, m and M are integers, 1≤m≤M). The transistor N01 in the sub-pixel electrically connected to the odd-numbered gate lines (such as: GA-1, GA-3, ... GA-2m-1, ... GA-2M-11) is a P-type transistor, and the transistor N02 in the sub-pixel electrically connected to the even-numbered gate lines (such as: GA-2, GA-3, ... GA-2m, ... GA-2M) is an N-type transistor. The odd-numbered gate lines (such as: GA-1, GA-3, ... GA-2m-1, ... GA-2M-11) can be electrically connected to the driving circuit, and the driving output terminal SO of a shift register unit in the driving circuit is electrically connected to a gate line in the odd-numbered gate lines (such as: GA-1, GA-3, ... GA-2m-1, ... GA-2M-11). The even-numbered rows of gate lines (such as GA-2, GA-3, ... GA-2m, ... GA-2M) can be electrically connected to the gate scanning circuit, and the gate scanning circuit can include multiple cascaded shift registers, and the output end of a shift register in the gate scanning circuit can be electrically connected to one of the even-numbered rows of gate lines (such as GA-2, GA-3, ... GA-2m, ... GA-2M).

[0121] Or, if Fig. 9 As shown, the transistor N02 in the sub-pixel electrically connected to the odd-numbered gate lines (such as GA-1, GA-3, ... GA-2m-1, ... GA-2M-11) is an N-type transistor, and the transistor N02 in the sub-pixel electrically connected to the even-numbered gate lines (such as GA-2, GA-3, ... GA-2m, ... GA-2M) is a P-type transistor. The odd-numbered gate lines (such as GA-1, GA-3, ... GA-2m-1, ... GA-2M-11) can be electrically connected to the gate scanning circuit, and the output end of a shift register in the gate scanning circuit is electrically connected to one of the odd-numbered gate lines (such as GA-1, GA-3, ... GA-2m-1, ... GA-2M-11). The even-numbered rows of gate lines (such as GA-2, GA-3, ... GA-2m, ... GA-2M) can be electrically connected to the driving circuit, and the driving output terminal SO of a shift register unit in the driving circuit can be electrically connected to one of the even-numbered rows of gate lines (such as GA-2, GA-3, ... GA-2m, ... GA-2M).

[0122] In a specific implementation, the display device provided in the embodiment of the present disclosure may be as follows: Fig.10Of course, the display device provided in the embodiment of the present disclosure may also be any product or component with a display function, such as a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device should be understood by ordinary technicians in the field, and will not be described here, nor should they be used as a limitation to the present disclosure.

[0123] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0124] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A shift register unit, wherein: include: A control circuit is electrically connected to an input signal terminal, a reset signal terminal, a first control signal terminal, a second control signal terminal, a first reference signal terminal, a first node, and a second node, respectively; and the control circuit is configured to adjust signals of the first node and the second node according to the input signal terminal, the first control signal terminal, the second control signal terminal, and the first reference signal terminal; a cascade circuit, electrically connected to the first cascade clock signal terminal, the first node and the cascade output terminal respectively; And the cascade circuit is configured to provide the signal of the first cascade clock signal terminal to the cascade output terminal according to the signal of the first node; An output circuit is electrically connected to the control clock signal terminal, the first node, the second node, the second reference signal terminal and the driving output terminal respectively; The output circuit is configured to provide the signal of the control clock signal terminal to the driving output terminal according to the signal of the first node, and to provide the signal of the second reference signal terminal to the driving output terminal according to the signal of the second node; The output circuit includes: a first transistor and a second transistor; the gate of the first transistor is electrically connected to the first node, the first end of the first transistor is electrically connected to the control clock signal end, and the second end of the first transistor is electrically connected to the drive output end; the gate of the second transistor is electrically connected to the second node, the first end of the second transistor is electrically connected to the second reference signal end, and the second end of the second transistor is electrically connected to the drive output end; The output circuit also includes: a third transistor and a fourth transistor; the gate of the third transistor is electrically connected to the control signal terminal, the first end of the third transistor is electrically connected to the second end of the first transistor, and the second end of the third transistor is electrically connected to the drive output terminal; the gate of the fourth transistor is electrically connected to the control signal terminal, the first end of the fourth transistor is electrically connected to the second end of the second transistor, and the second end of the fourth transistor is electrically connected to the drive output terminal.

2. The shift register unit according to claim 1, wherein: The cascade circuit comprises: a fifth transistor and a storage capacitor; The gate of the fifth transistor is electrically connected to the first node, the first terminal of the fifth transistor is electrically connected to the first cascade clock signal terminal, and the second terminal of the fifth transistor is electrically connected to the cascade output terminal; The first end of the storage capacitor is electrically connected to the first node, and the storage capacitor is electrically connected to the cascade output end.

3. The shift register unit according to claim 1 or 2, wherein: The shift register unit further includes: a sixth transistor; A gate of the sixth transistor is electrically connected to the driving output terminal, a first terminal of the sixth transistor is electrically connected to the first reference signal terminal, and a second terminal of the sixth transistor is electrically connected to the second node.

4. The shift register unit according to claim 1 or 2, wherein: The control circuit comprises: An input circuit is electrically connected to the input signal terminal, the first control signal terminal and the intermediate node respectively; and the input circuit is configured to provide the signal of the first control signal terminal to the intermediate node under the control of the signal of the input signal terminal; a reset circuit, electrically connected to the reset signal terminal, the second control signal terminal and the intermediate node respectively; and the reset circuit is configured to provide the signal of the second control signal terminal to the intermediate node under the control of the signal of the reset signal terminal; a node adjustment circuit, electrically connected to the first reference signal terminal, the second cascade clock signal terminal, the second node and the intermediate node respectively; and the node adjustment circuit is configured to provide the signal of the first reference signal terminal to the second node under the control of the signal of the intermediate node; and provide the signal of the first reference signal terminal to the intermediate node under the control of the second cascade clock signal terminal and the signal of the second node; A stabilization circuit is electrically connected to the intermediate node, the first node and the control signal end respectively; and the stabilization circuit is configured to conduct the intermediate node and the first node under the control of the signal of the control signal end.

5. The shift register unit according to claim 4, wherein: The input circuit comprises: a seventh transistor; A gate of the seventh transistor is electrically connected to the input signal terminal, a first terminal of the seventh transistor is electrically connected to the first control signal terminal, and a second terminal of the seventh transistor is electrically connected to the intermediate node.

6. The shift register unit according to claim 4, wherein: The reset circuit comprises: an eighth transistor; A gate of the eighth transistor is electrically connected to the reset signal terminal, a first terminal of the eighth transistor is electrically connected to the second control signal terminal, and a second terminal of the eighth transistor is electrically connected to the intermediate node.

7. The shift register unit according to claim 4, wherein: The node adjustment circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor and a stabilizing capacitor; The gate of the ninth transistor is electrically connected to the intermediate node, the first terminal of the ninth transistor is electrically connected to the first reference signal terminal, and the second terminal of the ninth transistor is electrically connected to the second node; The gate and the first terminal of the tenth transistor are both electrically connected to the second cascade clock signal terminal, and the second terminal of the tenth transistor is electrically connected to the second node; The gate of the eleventh transistor is electrically connected to the second node, the first terminal of the eleventh transistor is electrically connected to the first reference signal terminal, and the second terminal of the eleventh transistor is electrically connected to the intermediate node; A first end of the stabilizing capacitor is electrically connected to the second node, and a second end of the stabilizing capacitor is electrically connected to the first reference signal end.

8. The shift register unit according to claim 4, wherein: The stabilization circuit comprises: a twelfth transistor; The gate of the twelfth transistor is electrically connected to the control signal terminal, the first terminal of the twelfth transistor is electrically connected to the intermediate node, and the second terminal of the twelfth transistor is electrically connected to the first node.

9. The shift register unit according to claim 1 or 2, wherein: The shift register unit further includes: a thirteenth transistor and a fourteenth transistor; The gate of the thirteenth transistor is electrically connected to the frame reset signal terminal, the first terminal of the thirteenth transistor is electrically connected to the first reference signal terminal, and the second terminal of the thirteenth transistor is electrically connected to the intermediate node; The gate of the fourteenth transistor is electrically connected to the touch control terminal, the first terminal of the fourteenth transistor is electrically connected to the second reference signal terminal, and the second terminal of the fourteenth transistor is electrically connected to the driving output terminal.

10. A driving circuit, wherein: include: A plurality of cascaded shift register units according to any one of claims 1 to 9; The input signal terminal of the first-stage shift register unit is electrically connected to the frame trigger signal terminal; In each two adjacent shift register units, the input signal end of the next shift register unit is electrically connected to the cascade output end of the previous shift register unit, and the reset signal end of the previous shift register unit is electrically connected to the cascade output end of the next shift register unit.

11. A display device, wherein: Comprising the driving circuit as claimed in claim 10.

12. The display device according to claim 11, wherein: The display device further comprises: a plurality of gate lines; One of the gate lines is electrically connected to a driving output terminal of one of the shift register units in the driving circuit.

13. The display device according to claim 12, wherein: The display device further comprises: a plurality of gate lines and a gate scanning circuit; The driving circuit is electrically connected to the gate lines that are spaced apart by one gate line, and the gate scanning circuit is electrically connected to the remaining gate lines.

Images