Methods of forming microelectronic devices, and related microelectronic devices and electronic systems

Abstract

A microelectronic device includes a memory array region, a control logic region, and an additional control logic region. The memory array region includes a stack structure including vertically alternating conductive structures and insulative structures, and vertically-extending strings of memory cells located within the stack structure. The control logic region underlies the stack structure and includes control logic devices configured to implement a portion of a control operation of the vertically-extending strings of memory cells. The additional control logic region overlies the stack structure and includes additional control logic devices configured to implement an additional portion of the control operation of the vertically-extending strings of memory cells. Methods of forming microelectronic devices, as well as additional microelectronic devices and electronic systems, are also described.

Description

[0001] CLAIM OF PRIORITY

[0002] This application claims the benefit of the filing date of January 14, 2020 of U.S. Patent Application No. 16 / 742,485, entitled “METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS,” which is hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0003] In various embodiments, the present disclosure relates generally to the field of microelectronic device design and fabrication. More particularly, the present disclosure relates to methods of forming microelectronic devices, and to related microelectronic devices and electronic systems. BACKGROUND

[0004] Microelectronic device designers often need to increase the level of integration or density of features within a microelectronic device by reducing the size of individual features and by reducing the separation distance between adjacent features. In addition, microelectronic device designers often need to design architectures that are not only compact, but also provide performance advantages and simplify design.

[0005] One example of a microelectronic device is a memory device. Memory devices are typically provided as internal integrated circuits in computers or electronic devices. There are many types of memory devices, including but not limited to non-volatile memory devices (e.g., NAND gate flash memory devices). One way to increase memory density in non-volatile memory devices is to utilize a vertical memory array (also referred to as a “three-dimensional (3D) memory array”) architecture. Conventional vertical memory arrays include vertical memory strings that extend through openings in one or more stacks (e.g., stacked structures) that include a stack of conductive structures and dielectric materials. Each vertical memory string can include at least one select device that is coupled in series to a series combination of vertically stacked memory cells. This configuration permits a larger number of switching devices (e.g., transistors) to be positioned in a unit of die area (i.e., the length and width of the active surface consumed) by building the array upward (e.g., vertically) on a die, as compared to structures that employ conventional planar (e.g., two-dimensional) transistor arrangements.

[0006] Control logic devices within a base control logic structure underlying a memory array of a memory device (e.g., a non-volatile memory device) have been used to control operations (e.g., access operations, read operations, write operations) on memory cells of the memory device. Assemblies of control logic devices can be provided in electrical communication with memory cells of a memory array by way of wiring and interconnect structures. However, processing conditions (e.g., temperature, pressure, materials) used to form a memory array over a base control logic structure can limit the configuration and performance of control logic devices within the base control logic structure. Additionally, the number, size, and arrangement of different control logic devices within a base control logic structure can also undesirably impede a reduction in size (e.g., horizontal footprint) of a memory device and / or an improvement in performance (e.g., faster memory cell turn-on / off speed, lower threshold voltage switching requirements, faster data transfer rates, lower power consumption) of a memory device.

[0007] Accordingly, there is a need for new methods of forming microelectronic devices (e.g., memory devices, such as NAND gate flash memory devices), as well as new microelectronic devices and electronic systems. SUMMARY

[0008] In some embodiments, a microelectronic device includes a memory array region, a control logic region, and an additional control logic region. The memory array region includes a stack structure including vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells located within the stack structure. The control logic region underlies the stack structure and includes control logic devices configured to implement a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and includes additional control logic devices configured to implement an additional portion of the control operations for the vertically extending strings of memory cells.

[0009] In additional embodiments, a method of forming a microelectronic device includes forming a first microelectronic device structure including a control logic region and a memory array region located over the control logic region. The control logic region includes the control logic devices. The memory array region includes a stack structure including vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells located within the stack structure. A second microelectronic device structure is formed to include an additional control logic region including additional control logic devices. The first microelectronic device structure is attached to the second microelectronic device structure such that the stack structure is vertically interposed between the control logic region and the additional control logic region.

[0010] In yet other embodiments, a microelectronic device includes a memory array region, a first conductive pad structure, a second conductive pad structure, and a control logic region. The memory array region includes a stack structure including a vertically-alternating sequence of conductive structures and insulative structures, and vertically-extending strings of memory cells located within the stack structure. The first conductive pad structure underlies the stack structure of the memory array region. The second conductive pad structure underlies the first conductive pad structure. The control logic region underlies the second conductive pad structure and includes control logic devices including CMOS circuitry.

[0011] In yet other embodiments, a method of forming a microelectronic device includes forming a first microelectronic device structure including a control logic region including control logic devices. A second microelectronic device structure is formed to include a base structure, and a memory array region located on the base structure. The memory array region includes a stack structure including vertically-alternating conductive structures and insulative structures, and vertically-extending strings of memory cells located within the stack structure. The base structure is removed from the second microelectronic device structure. A remaining portion of the second microelectronic device structure is attached to the first microelectronic device structure such that the control logic region of the first microelectronic device structure underlies the memory array region of the second microelectronic device structure.

[0012] In yet other embodiments, an electronic system includes an input device, an output device, a processor device operably coupled to the input device and the output device, and a memory device operably coupled to the processor device. The memory device includes a stack structure, vertically-extending strings of memory cells located within the stack structure, control logic devices including CMOS circuitry underlying the stack structure, and additional control logic devices including additional CMOS circuitry overlying the stack structure. The stack structure includes laminates each including a conductive structure and an insulative structure vertically-adjacent the conductive structure. The control logic devices are configured to implement a portion of control operations for the vertically-extending strings of memory cells. The additional control logic devices have relatively lower operating voltage requirements than the control logic devices, and are configured to implement additional portions of the control operations for the vertically-extending strings of memory cells. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figures 1A to 1D A simplified partial cross-sectional view is shown for a method of forming a microelectronic device according to an embodiment of the present disclosure.

[0014] Figures 2A to 2D A simplified partial cross-sectional view is shown for a method of forming a microelectronic device according to an additional embodiment of the present disclosure.

[0015] Figures 3A to 3D A simplified partial cross-sectional view illustrating a method of forming a microelectronic device is shown for another additional embodiment in accordance with the present disclosure.

[0016] Figures 4A to 4D A simplified partial cross-sectional view illustrating a method of forming a microelectronic device is shown for another additional embodiment in accordance with the present disclosure.

[0017] Figure 5 A schematic block diagram of an electronic system in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] The following description provides specific details, such as material compositions and processing conditions (e.g., temperatures, pressures, flow rates, etc.), in order to provide a thorough description of embodiments of the present disclosure. However, a person of ordinary skill in the art will understand that the present embodiments can be practiced without employing these specific details. Indeed, the present embodiments can be practiced in conjunction with conventional systems and methods in the industry. Additionally, only those processing components and acts strictly necessary to understand the embodiments of the present disclosure are described in great detail below. A person of ordinary skill in the art will understand some processing components (e.g., lines, line filters, valves, temperature detectors, flow detectors, pressure detectors, and the like) are inherently disclosed herein, and adding various conventional processing components and acts would be in accordance with the present disclosure. Moreover, the description provided below does not form a complete process flow for fabricating a microelectronic device. The structures described below do not form a complete microelectronic device. Additional acts can be performed to form a complete microelectronic device from the structures by conventional fabrication techniques.

[0019] The drawings presented herein are for purposes of illustration only and are not intended to be a precise view of any particular material, component, structure, device, or system. Variations in the depicted shapes are expected due to, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein are not to be interpreted as being limited to the particular shape as shown, but include variations as a result of, for example, manufacturing. For example, a region shown or described as a box can have rough and / or nonlinear features, and a region shown or described as circular can include some rough and / or linear features. Further, sharp corners shown can be rounded, and vice versa. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to show the precise shape of the regions, and are not limiting to the scope of the present claims. The drawings are not necessarily to scale. Additionally, elements common between figures can retain the same numerical designation.

[0020] As used herein, "memory device" means and includes microelectronic devices that exhibit, but are not limited to, memory functionality.

[0021] As used herein, the term “configured” refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device in a predetermined manner to facilitate the operation of one or more of the structure and device.

[0022] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” refer to the principal plane of the structure and are not necessarily defined by the Earth’s gravitational field. A “horizontal” or “lateral” direction is a direction substantially parallel to the principal plane of the structure, while a “vertical” or “longitudinal” direction is a direction substantially perpendicular to the principal plane of the structure. The principal plane of the structure is defined by the surface of the structure that has a relatively large area compared to the other surfaces of the structure.

[0023] As used herein, a feature described as “adjacent” to each other (e.g., area, structure, device) means and includes the feature of the disclosed identifier (or identifiers) located closest to each other (e.g., closest to each other). Additional features (e.g., additional areas, additional structures, additional devices) of the disclosed identifier (or identifiers) that do not match “adjacent” features may be positioned between “adjacent” features. In other words, “adjacent” features may be directly positioned to be adjacent to each other such that no other features are inserted between “adjacent” features; or “adjacent” features may be indirectly positioned to be adjacent to each other such that at least one feature having an identifier other than the one associated with at least one “adjacent” feature is positioned between “adjacent” features. Thus, a feature described as “vertically adjacent” to each other means and includes the feature of the disclosed identifier (or identifiers) located closest to each other vertically (e.g., closest to each other vertically). Furthermore, a feature described as “horizontally adjacent” to each other means and includes the feature of the disclosed identifier (or identifiers) located closest to each other horizontally (e.g., closest to each other horizontally).

[0024] As used herein, spatially relative terms (e.g., "below," "under," "lower," "bottom," "above," "upper," "top," "front," "back," "left," "right," and the like) are readily descriptive terms used to describe the relationship of one element or feature to another element(s) shown in the diagrams. Unless otherwise stated, spatially relative terms are intended to cover different orientations of material, in addition to those depicted in the diagrams. For example, if material in the diagrams is reversed, then an element described as "below other elements or features," "below other elements or features," or "below other elements or features," or "at the bottom of other elements or features," would then be oriented "above other elements or features" or "on top of other elements or features." Thus, the term "below" can encompass both above and below orientations, depending on the context in which the term is used, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, reversed, flipped), and the spatially relative descriptive terms used herein are interpreted accordingly.

[0025] As used herein, the singular forms “a” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0026] As used in this document, “and / or” includes any and all combinations of one or more of the associated listed items.

[0027] As used herein, the term “substantially” refers to a given parameter, property, or condition and means, and includes, a degree of conformity (e.g., within acceptable manufacturing tolerances) that would be understood by one of ordinary skill in the art to be understood. By way of example, depending on the specific parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be satisfied at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0028] As used herein, the term "about" or "approximately" to refer to a particular parameter includes the value such that a variation of the value would be understood by one of ordinary skill in the art to be within acceptable tolerances for the particular parameter. For example, "about" or "approximately" to refer to a value may include additional values ​​within the range of 90.0% to 110.0% of the value, such as within the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0029] As used herein, “conductive material” means and includes conductive materials such as metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), and aluminum (Al), alloys (e.g., Co-based alloys, Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, Co and N). Materials containing conductive metals (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped germanium (Ge), conductive doped silicon germanium (SiGe)) are selected from one or more of the following: i-based alloys, Fe and Co-based alloys, Co and Ni and Fe-based alloys, Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steel, low-carbon steel, stainless steel), and materials containing conductive metals (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), and conductive doped semiconductor materials (e.g., conductive doped polycrystalline silicon, conductive doped germanium (Ge), conductive doped silicon germanium (SiGe)). Furthermore, "conductive structure" means and includes structures formed of conductive materials and containing conductive materials.

[0030] As used herein, “insulating material” means and includes electrically insulating materials, such as at least one dielectric oxide material (e.g., silicon oxide (SiO2)). x Phossilicate glass, borosilicate glass, borosilicate-phosphorus glass, fluorosilicate glass, alumina (AlO) x ), hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium trioxide (TiO) x ), zirconium oxide (ZrO x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x One or more of the following), at least one dielectric nitride material (e.g., silicon nitride (SiN)y ()), at least one dielectric oxide nitride material (e.g., silicon oxynitride (SiO) x N y And at least one dielectric carboxyl nitride material (e.g., silicon carboxyl nitride (SiO2)). x C z N y One or more of the following. This text includes chemical formulas of one or more of "x", "y", and "z" (e.g., SiO2). x AlO x HfO x NbO x TiO x SiN y SiO x N y SiO x C z N y An insulating material (e.g., Si, Al, Hf, Nb, Ti) represents a material containing an average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if present) for each atom of the other element. Since a chemical formula represents relative atomic ratios and is not a strict chemical structure, an insulating material may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if present) may be integers or non-integers. As used herein, the term "non-stoichiometric compound" means and includes compounds having elemental compositions that cannot be expressed as well-defined natural numbers and violate the law of definite proportions. Additionally, "insulating structure" means and includes structures formed from and containing insulating materials.

[0031] Figures 1A to 1D This is a simplified partial cross-sectional view illustrating an embodiment of a method for forming a microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device). It will be readily apparent to those skilled in the art using the description provided below, with reference to which references are made herein. Figures 1A to 1D The described methods and structures can be used in various devices and electronic systems.

[0032] See Figure 1AThe first microelectronic device structure 100 (e.g., a first die) may be formed to include a first control logic region 102, a memory array region 104 vertically located above (e.g., in the Z direction) and electrically connected to the first control logic region 102, and a first interconnect region 106 vertically located above and electrically connected to the memory array region 104. In other words, the memory array region 104 may be vertically inserted between the first control logic region 102 and the first interconnect region 106, and electrically connected to both the first control logic region and the first interconnect region. The first control logic region 102 and the first interconnect region 106 may be at least partially (e.g., substantially) horizontally positioned within the horizontal boundaries of the memory array region 104 of the first microelectronic device structure 100 (e.g., in the X direction and another horizontal direction orthogonal to the X direction).

[0033] The first control logic region 102 of the first microelectronic device structure 100 includes a first semiconducting substrate structure 108, a first gate structure 111, a first wiring structure 110, and a first interconnect structure 112. A portion of the first semiconducting substrate structure 108, the first gate structure 111, the first wiring structure 110, and the first interconnect structure 112 form various first control logic devices 113 of the first control logic region 102, as described in more detail below.

[0034] The first semiconducting substrate structure 108 (e.g., a first semiconducting wafer) of the first control logic region 102 includes a substrate material or structure on which additional materials and structures of the first microelectronic device structure 100 are formed. The first semiconducting substrate structure 108 may include a semiconducting structure (e.g., a semiconducting wafer) or a substrate semiconducting material located on a support structure. For example, the first semiconducting substrate structure 108 may include a conventional silicon substrate (e.g., a conventional silicon wafer) or another bulk substrate including a semiconducting material. As used herein, the term "bulk substrate" means and includes not only a silicon substrate, but also silicon-on-insulator (SOI) substrates (e.g., silicon-on-sapphire (SOS) substrates and silicon-on-glass (SOG) substrates), silicon epitaxial layers on a substrate semiconducting pedestal, and other substrates formed of one or more semiconducting materials and including said one or more semiconducting materials (e.g., one or more of silicon materials, such as monocrystalline silicon or polycrystalline silicon; silicon-germanium; germanium; gallium arsenide; gallium nitride; and indium phosphide). In some embodiments, the first semiconducting substrate structure 108 includes a silicon wafer. Additionally, the first semiconducting substrate structure 108 may include different layers, structures, and / or regions formed therein and / or on it. For example, the first semiconducting substrate structure 108 may include conductive doped regions and undoped regions. The conductive doped regions may, for example, serve as the source and drain regions of the transistors of the first control logic device 113 of the first control logic region 102; and the undoped regions may, for example, serve as the channel regions of the transistors of the first control logic device 113.

[0035] like Figure 1A As shown, the first semiconducting substrate structure 108 may optionally further include one or more filled vias 109 (e.g., filled through-silicon vias (TSVs)) that extend at least partially (e.g., partially, fully) vertically through the first semiconducting substrate structure. If present, the filled vias 109 may be at least partially (e.g., substantially) filled with a conductive material. The filled vias 109 may be used to facilitate electrical connections between one or more components of the first microelectronic device structure 100 located on a first side (e.g., front side, top side) of the first semiconducting substrate structure 108 and additional components (e.g., one or more structures and / or devices) to be provided on a second opposite side (e.g., back side, bottom side) of the first semiconducting substrate structure 108, as described in more detail below. In additional embodiments, the filled vias 109 may be omitted from the first semiconducting substrate structure 108 (e.g., they may not exist).

[0036] Continue to refer to Figure 1A The first gate structure 111 of the first control logic region 102 of the first microelectronic device structure 100 may be vertically superimposed on a portion of the first semiconducting substrate structure 108. The first gate structure 111 may extend horizontally between transistors of the first control logic device 113 within the first control logic region 102 of the first microelectronic device structure 100, and be used through said transistors. The first gate structure 111 may be formed of and contain a conductive material. A gate dielectric material (e.g., dielectric oxide) may be vertically inserted (e.g., in the Z direction) between the first gate structure 111 and the channel region of the transistor (e.g., within the first semiconducting substrate structure 108).

[0037] like Figure 1A As shown, a first wiring structure 110 may be vertically (e.g., in the Z direction) overlying a first semiconducting substrate structure 108. The first wiring structure 110 may be electrically connected to the first semiconducting substrate structure 108 via a first interconnect structure 112. A portion of the first interconnect structure 112 may extend vertically between portions of the first wiring structure 110 and be electrically coupled to said portions, and other portions of the first interconnect structure 112 may extend vertically between regions of the first semiconducting substrate structure 108 (e.g., conductive doped regions, such as source and drain regions) and one or more of the first wiring structures 110, and electrically couple said regions to said one or more. The first wiring structure 110 and the first interconnect structure 112 may each be individually formed of and contain conductive material.

[0038] As previously mentioned, portions of the first semiconducting substrate structure 108 (e.g., conductive doped regions acting as source and drain regions, and undoped regions acting as channel regions), the first gate structure 111, the first wiring structure 110, and the first interconnect structure 112 form various first control logic devices 113 of the first control logic region 102. The first control logic devices 113 can be configured to control various operations of other components of the first microelectronic device structure 100, such as components within the memory array region 104 of the first microelectronic device structure 100. The first control logic devices 113, optionally included in the first control logic region 102, may be incorporated into an assembly comprising the first microelectronic device structure 100 and one or more additional microelectronic device structures, as described in more detail below, relative to additional control logic devices (e.g., second control logic devices) included in one or more additional control logic regions. The configuration of the first control logic devices 113 included in the first control logic region 102 may differ from the configuration of additional control logic devices included in additional control logic regions. In some embodiments, the additional control logic device included in the additional control logic region includes a relatively high-performance control logic device employing a relatively high-performance control logic circuit system (e.g., a relatively high-performance complementary metal-oxide-semiconductor (CMOS) circuit system); and the first control logic device 113 included in the first control logic region 102 employs a relatively low-performance control logic circuit system (e.g., an additional CMOS circuit system). The additional control logic device within the additional control logic region may be configured, for example, to operate at an applied voltage less than or equal to (e.g., less than) about 1.4 volts (V), such as in the range of about 0.7V to about 1.4V (e.g., about 0.7V to about 1.3V, about 0.7V to about 1.2V, about 0.9V to about 1.2V, about 0.95V to about 1.15V, or about 1.1V); and the first control logic device 113 within the first control logic region 102 may be configured to operate at an applied voltage higher than the higher operating voltage of the additional control logic device within the additional control logic region, such as at an applied voltage greater than about 1.2V (e.g., greater than or equal to about 1.3V, greater than or equal to about 1.4V).

[0039] As a non-limiting example, the first control logic device 113 included in the first control logic region 102 of the first microelectronic device structure 100 may include a charge pump (e.g., V0). CCP Charge pump, V NEGWL Charge pumps, DVC2 charge pumps), delayed-locked loop (DLL) circuit systems (e.g., ring oscillators), drain supply voltage (V) ddThe first control logic device 113 may include one or more of the following (e.g., each): regulator, string driver, page buffer, and various chip / stack control circuitry. As another non-limiting example, the first control logic device 113 may include means configured to control column operations of an array (e.g., memory element array, access device array) within the memory array region 104 of the first microelectronic device structure 100: such as decoders (e.g., local stack decoders, column decoders), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSA), PMOS sense amplifiers (PSA)), maintenance circuitry (e.g., column maintenance circuitry), I / O devices (e.g., local I / O devices), memory test devices, array multiplexers (MUX), and error checking and correction (ECC) devices (e.g., each). As another non-limiting example, the first control logic device 113 may include means configured to control row operations of an array (e.g., a memory element array, an access device array) within the memory array region 104 of the first microelectronic device structure 100, such as a decoder (e.g., a local overlay decoder, a row decoder), a driver (e.g., a word line (WL) driver), a maintenance circuit system (e.g., a row maintenance circuit system), a memory test device, a MUX, an ECC device, and a self-refresh / wear-out equalization device (e.g., each of these).

[0040] The memory array region 104 of the first microelectronic device structure 100 may include a stacked structure 116, a line structure 124 (e.g., a digital line structure, a bit line structure), and a line contact structure 126. For example... Figure 1A As shown, the wire structure 124 may be vertically (e.g., in the Z direction) overlying the stacked structure 116 and may be electrically connected to structures within the stacked structure 116 (e.g., pillar structures, such as unit pillar structures; filled vias, such as through-holes filled with conductive material) via the wire contact structure 126. The wire contact structure 126 may extend vertically between individual wire structures 124 and individual structures within the stacked structure 116 and be electrically coupled to said structures. The wire structure 124 and the wire contact structure 126 may each be individually formed of and contain conductive material.

[0041] The stacked structure 116 of the memory array region 104 includes a vertically alternating (e.g., in the Z direction) sequence of conductive structures 120 and insulating structures 122 arranged in a stack 118. Each of the stacks 118 of the stacked structure 116 may include at least one of the conductive structures 120 vertically adjacent to at least one of the insulating structures 122. In some embodiments, the conductive structure 120 is formed of and contains tungsten (W), and the insulating structure 122 is formed of and contains silicon dioxide (SiO2). The conductive structures 120 and insulating structures 122 of the stacks 118 of the stacked structure 116 may each be substantially planar and may each exhibit a desired thickness.

[0042] like Figure 1A As shown, at least one deep contact structure 128 may extend vertically through the stacked structure 116. The deep contact structure 128 may be configured and positioned to electrically connect one or more components of the first microelectronic device structure 100 vertically overlying the stacked structure 116 to one or more components of the first microelectronic device structure 100 vertically lying on the stacked structure 116. The deep contact structure 128 may be formed of and contain conductive material.

[0043] The memory array region 104 further includes additional structures and / or devices located on, above, and / or within the stacked structure 116. As a non-limiting example, the memory array region 104 includes cell pillar structures extending vertically through the stacked structure 116. Each cell pillar structure may individually include a semiconducting pillar (e.g., a polysilicon pillar, a silicon-germanium pillar) at least partially surrounded by one or more charge storage structures (e.g., charge collection structures, such as charge collection structures comprising oxide-nitride-oxide (“ONO”) materials; floating gate structures). The intersection of the cell pillar structure with the conductive structure 120 of the stack 118 of the stacked structure 116 defines a vertically extending string of memory cells coupled in series within the memory array region 104 of the first microelectronic device structure 100. In some embodiments, the memory cells formed within each stack 118 of the stacked structure 116 at the intersection of the conductive structure 120 and the cell pillar structure include so-called “MONOS” (metal-oxide-nitride-oxide-semiconductor) memory cells. In an additional embodiment, the memory cell includes a so-called "TANOS" (tantalum nitride-aluminum oxide-nitride-oxide-semiconductor) memory cell or a so-called "BETANOS" (bandwidth / barrier-engineered TANOS) memory cell, each of which is a subset of the MONOS memory cell. In another embodiment, the memory cell includes a so-called "floating gate" memory cell, which includes a floating gate (e.g., a metallic floating gate) as a charge storage structure. The floating gate may be horizontally inserted between the central structure of the cell pillar structure and the conductive structures 120 of the different layers 118 of the stacked structure 116.

[0044] like Figure 1A As shown, components of the memory array region 104 of the first microelectronic device structure 100 can be electrically connected to components of the first control logic region 102 of the first microelectronic device structure 100 (e.g., the structure of the first wiring structure 110; e.g., the device of the first control logic device 113) via a first pad structure 114 and a second interconnect structure 130. For example, components (e.g., structures, devices) of the memory array region 104 can rest on the first pad structure 114, and the second interconnect structure 130 can extend vertically between the first pad structure 114 and the various components of the first control logic region 102 and electrically connect them. The first pad structure 114 and the second interconnect structure 130 can each be individually formed of and contain conductive material.

[0045] Continue to refer to Figure 1AThe first interconnect region 106 of the first microelectronic device structure 100 may include a second wiring structure 132 and a first bonding pad structure 136. The second wiring structure 132 may vertically overlay and be electrically connected to the line structure 124 of the memory array region 104, and the first bonding pad structure 136 may vertically overlay and be electrically connected to the second wiring structure 132. For example... Figure 1A As shown, a third interconnect structure 134 extends vertically between and electrically connects the second wiring structure 132 and the wire structure 124, and a fourth interconnect structure 138 extends vertically between and electrically connects the second wiring structure 132 and the first bonding pad structure 136. The second wiring structure 132, the third interconnect structure 134, the first bonding pad structure 136, and the fourth interconnect structure 138 may each be individually formed of and contain a conductive material. In some embodiments, the second wiring structure 132 is formed of and contains Al, and the first bonding pad structure 136 is formed of and contains Cu.

[0046] Next reference Figure 1B The second microelectronic device structure 150 (e.g., a chiplet) may be formed to include a second control logic region 152 and a second interconnect region 154 that is vertically located above and electrically connected to the second control logic region 152. The second microelectronic device structure 150 may be configured to couple to the first microelectronic device structure 100, as described in more detail below.

[0047] The second control logic region 152 of the second microelectronic device structure 150 may include a second semiconducting substrate structure 156, a second gate structure 157, a third wiring structure 162, and a fifth interconnect structure 160. A portion of the second semiconducting substrate structure 156, the second gate structure 157, the third wiring structure 162, and the fifth interconnect structure 160 form various second control logic devices 163 of the second control logic region 152, as described in more detail below.

[0048] The second semiconducting substrate structure 156 (e.g., a second semiconducting wafer) of the second control logic region 152 includes a substrate material or structure on which additional materials and structures of the second microelectronic device structure 150 are formed. The second semiconducting substrate structure 156 may include a semiconducting structure (e.g., a semiconducting wafer) or a substrate semiconducting material located on a support structure. For example, the second semiconducting substrate structure 156 may include a conventional silicon substrate (e.g., a conventional silicon wafer) or another bulk substrate including a semiconducting material. In some embodiments, the second semiconducting substrate structure 156 includes a silicon wafer. Additionally, the second semiconducting substrate structure 156 may include one or more layers, structures, and / or regions formed therein and / or on it. For example, the second semiconducting substrate structure 156 may include conductive doped regions and undoped regions. The conductive doped regions may, for example, serve as the source and drain regions of the transistors of the second control logic device 163 of the second control logic region 152; and the undoped regions may, for example, serve as the channel regions of the transistors of the second control logic device 163.

[0049] like Figure 1B As shown, the second semiconducting substrate structure 156 may further include at least partially (e.g., incompletely, completely) vertically extending one or more additional filled vias 158 (e.g., additional filled TSVs) therethrough. The additional filled vias 158 may be at least partially (e.g., substantially) filled with a conductive material. The additional filled vias 158 may be used to facilitate electrical connections between one or more components of the second microelectronic device structure 150 located on a first side (e.g., front side, top side) of the second semiconducting substrate structure 156 and additional components (e.g., one or more structures and / or devices) to be provided on a second opposite side (e.g., back side, bottom side) of the second semiconducting substrate structure 156, as described in more detail below.

[0050] Continue to refer to Figure 1B The second gate structure 157 of the second control logic region 152 of the second microelectronic device structure 150 may be vertically superimposed on a portion of the second semiconducting substrate structure 156. The second gate structure 157 may extend horizontally, individually, within the second control logic region 152 of the second microelectronic device structure 150, between and through the transistors of the second control logic device 163. The second gate structure 157 may be formed of and contain a conductive material. A gate dielectric material (e.g., dielectric oxide) may be vertically inserted (e.g., in the Z direction) between the second gate structure 157 and the channel region of the transistor (e.g., within the second semiconducting substrate structure 156).

[0051] like Figure 1BAs shown, a third wiring structure 162 may be vertically (e.g., in the Z direction) overlying a second semiconducting substrate structure 156. The third wiring structure 162 may be electrically connected to the second semiconducting substrate structure 156 via a fifth interconnect structure 160. A portion of the fifth interconnect structure 160 may extend vertically between portions of the third wiring structure 162 and electrically couple them, and other portions of the fifth interconnect structure 160 may extend vertically between regions of the second semiconducting substrate structure 156 (e.g., conductive doped regions, such as source and drain regions) and one or more of the third wiring structures 162 and electrically couple them. The third wiring structure 162 and the fifth interconnect structure 160 may each be individually formed of and contain conductive material.

[0052] As previously mentioned, portions of the second semiconducting substrate structure 156 (e.g., conductive doped regions serving as source and drain regions, and undoped regions serving as channel regions), the second gate structure 157, the third wiring structure 162, and the fifth interconnect structure 160 form various second control logic devices 163 of the second control logic region 152. The second control logic devices 163 can be configured to control at least the first microelectronic device structure 100 (…). Figure 1A The various operations of other components, such as the first microelectronic device structure 100 ( Figure 1A ) memory array area 104 ( Figure 1A Components contained within the first microelectronic device structure 100. Figure 1A At least the first control logic region 102 () Figure 1A The first control logic device 113 in ) Figure 1A The second control logic device 163, which may be included in the second control logic area 152, can be selected. The second control logic device 163 may be different from the first control logic device 113. Figure 1A In some embodiments, the second control logic device 163 includes a relatively high-performance control logic device employing a relatively high-performance control logic circuit system (e.g., a relatively high-performance CMOS circuit system). The second control logic device 163 may, for example, be configured to operate at an applied voltage less than or equal to (e.g., less than) about 1.4 volts (V), such as in the range of about 0.7V to about 1.4V (e.g., about 0.9V to about 1.2V, about 0.95V to about 1.15V, or about 1.1V).

[0053] As a non-limiting example, the second control logic device 163 included in the second control logic region 152 of the second microelectronic device structure 150 may include a configuration for controlling the first microelectronic device structure 100. Figure 1A ) memory array area 104 ( Figure 1AThe means of column operation of an array (e.g., a memory element array, an access device array) within the first microelectronic device structure 100, such as decoders (e.g., local overlay decoders, column decoders), sense amplifiers (e.g., EQ amplifiers, ISO amplifiers, NSA, PSA), maintenance circuitry (e.g., column maintenance circuitry), I / O devices (e.g., local I / O devices), memory test devices, MUX, and ECC devices (e.g., each one). As another non-limiting example, the second control logic device 163 may include a configuration for controlling the first microelectronic device structure 100. Figure 1A ) memory array area 104 ( Figure 1A The second control logic device 163 may include one or more of the following: a decoder (e.g., a local overlay decoder, a row decoder), a driver (e.g., a WL driver), a maintenance circuitry (e.g., a row maintenance circuitry), a memory test device, a MUX, an ECC device, and a self-refresh / wear-out equalization device (e.g., each of these). As another non-limiting example, the second control logic device 163 may include one or more of a string driver and a page buffer.

[0054] Continue to refer to Figure 1B The second interconnect region 154 of the second microelectronic device structure 150 may include a second pad structure 164 and a second bonding pad structure 168. The second pad structure 164 may vertically overlay and be electrically connected to the third wiring structure 162 of the second control logic region 152, and the second bonding pad structure 168 may vertically overlay and be electrically connected to the second pad structure 164. For example... Figure 1B As shown, a sixth interconnect structure 166 extends vertically between and electrically connects the second pad structure 164 and the third wiring structure 162, and a seventh interconnect structure 169 extends vertically between and electrically connects the second pad structure 164 and the second bonding pad structure 168. The second pad structure 164, the sixth interconnect structure 166, the second bonding pad structure 168, and the seventh interconnect structure 169 may each be individually formed of and contain a conductive material. In some embodiments, the second bonding pad structure 168 is formed of and contains Cu.

[0055] Next reference Figure 1C The second microelectronic device structure 150 may be inverted (e.g., in the Z direction) and attached (e.g., joined) to the first microelectronic device structure 100 to form a microelectronic device structure assembly 170. Alternatively, the first microelectronic device structure 100 may be inverted and attached to the second microelectronic device structure 150 to form a microelectronic device structure assembly 170.

[0056] like Figure 1CAs shown, the microelectronic device structure assembly 170 can be formed to include an eighth interconnect structure 172, which is vertically inserted between the second wiring structure 132 of the first microelectronic device structure 100 and the second pad structure 164 of the second microelectronic device structure 150 and electrically connects them. Additionally, a dielectric material (e.g., a dielectric oxide material) (for clarity and ease of understanding of the illustrations and related descriptions, from...) Figure 1C (omitted) may cover and surround the eighth interconnect structure 172, and may physically couple a portion of the first microelectronic device structure 100 to the second microelectronic device structure 150. The second microelectronic device structure 150 may be attached to the first microelectronic device structure 100 without bonding wires.

[0057] The eighth interconnect structure 172 of the microelectronic device structure assembly 170 may be derived from the first bonding pad structure 136 of the first microelectronic device structure 100. Figure 1A ) and the second bonding pad structure 168 of the second microelectronic device structure 150. Figure 1B ) is formed. For example, after flipping the second microelectronic device structure 150, its second bonding pad structure 168 ( Figure 1B ) can be connected to the first bonding pad structure 136 of the first microelectronic device structure 100. Figure 1A The first bonding pad structure 136 is then horizontally aligned and brought into physical contact with it. At least one thermocompression process can then be used to transfer (e.g., diffusion) the first bonding pad structure 136. Figure 1A ) and the second bonding pad structure 168 ( Figure 1B The materials (e.g., Cu) interact with each other and form an eighth interconnect structure 172.

[0058] Still referencing Figure 1C The microelectronic device structure assembly 170 may further include one or more wiring pad structures 174 (e.g., wire bonding pad structures) coupled (e.g., physically coupled, electrically coupled) to additional filled vias 158 extending vertically through the second semiconducting substrate structure 156 of the second microelectronic device structure 150. The wiring pad structures 174 can be used to electrically connect the microelectronic device structure assembly 170 to a package of the microelectronic device including the microelectronic device structure assembly 170. The wiring pad structures 174 may be coupled to the conductive material of the additional filled vias 158, for example, after thinning (e.g., in the Z direction) the second semiconducting substrate structure 156 from its back surface, to expose the additional filled vias 158 after the second microelectronic device structure 150 is attached to the first microelectronic device structure 100. In an additional embodiment, the additional fill via 158 is formed in the second semiconducting substrate structure 156 after the second microelectronic device structure 150 is attached to the first microelectronic device structure 100, and then the wiring pad structure 174 is coupled to the additional fill via 158.

[0059] Compared to conventional assembly configurations, the microelectronic device structure assembly 170 (including its second microelectronic device structure 150) facilitates improved microelectronic device performance, increased miniaturization of components, and greater package density. For example, a second control logic region 152 (including its second control logic device 163) vertically overlying the memory array region 104 (including a vertically extending string of its memory cells) can reduce the amount of time required to switch memory cells of the memory array region 104 between on and off states (e.g., increasing the speed of switching memory cells between relatively low resistivity states (on state) and relatively high resistivity states (off state), and / or can reduce the applied critical switching voltage (V0) compared to a conventional assembly configuration without the second control logic region 152. cc The requirements are as follows: Compared to the conventional configuration where these control logic devices are contained within a conventional substrate control logic region vertically embedded in the memory array region 104, providing a second control logic region 152 vertically positioned above the memory array region 104 can, for example, reduce the distance between the vertical extension string of memory cells of the memory array region 104 and the second control logic devices 163 (e.g., high-performance I / O devices) of the microelectronic device architecture assembly 170. Furthermore, employing the second control logic devices 163 within the second control logic region 152 instead of the first control logic region 102, compared to a conventional substrate control logic region configuration, can reduce the horizontal dimension of the first control logic region 102, thereby promoting a relatively smaller horizontal coverage area and improved efficiency of the memory array, die, and / or socket areas compared to a conventional configuration.

[0060] Next reference Figure 1D After attaching the first microelectronic device structure 100 and the second microelectronic device structure 150 to form the microelectronic device structure assembly 170, the microelectronic device structure assembly 170 may undergo additional processing. By way of non-limiting example, optionally, another microelectronic device structure 100' (e.g., an additional die) substantially similar to the first microelectronic device structure 100 may be attached to the first microelectronic device structure 100 to form a relatively large microelectronic device structure assembly 180.

[0061] A relatively large microelectronic device structure assembly 180 may be formed, for example, by the following steps: thinning (e.g., in the Z direction) a first semiconductive substrate structure 108 to expose a filled via 109; coupling a bonding pad structure to a conductive material of the filled via 109; and connecting the bonding pad structure to an additional bonding pad structure (e.g., to the first bonding pad structure 136 of the first microelectronic device structure 100). Figure 1AA substantially similar additional bonding pad structure is horizontally aligned and physically contacted; and subsequently, at least one thermoforming process is performed to form one or more ninth interconnect structures 176 (e.g., interconnect structures substantially similar to the eighth interconnect structure 172) vertically inserted between the first microelectronic device structure 100 and another microelectronic device structure 100' and electrically connecting them. Any desired number of additional microelectronic device structures can be attached to a relatively large microelectronic device structure assembly 180 by substantially similar processing.

[0062] Therefore, according to embodiments of this disclosure, a microelectronic device includes a memory array region, a control logic region, and an additional control logic region. The memory array region includes: a stacked structure comprising vertically alternating conductive and insulating structures; and a vertically extending string of memory cells located within the stacked structure. The control logic region lies beneath the stacked structure and includes control logic means configured to implement a portion of control operations on the vertically extending string of memory cells. The additional control logic region overlies the stacked structure and includes additional control logic means configured to implement additional portions of control operations on the vertically extending string of memory cells.

[0063] Furthermore, according to embodiments of this disclosure, a method of forming a microelectronic device includes forming a first microelectronic device structure comprising a control logic region and a memory array region located above the control logic region. The control logic region includes the control logic devices. The memory array region includes: a stacked structure comprising vertically alternating conductive and insulating structures; and a vertically extending string of memory cells located within the stacked structure. A second microelectronic device structure is formed to include an additional control logic region comprising additional control logic devices. The first microelectronic device structure is attached to the second microelectronic device structure such that the stacked structure is vertically inserted between the control logic region and the additional control logic region.

[0064] Figures 2A to 2D This is a simplified partial cross-sectional view illustrating an embodiment of another method for forming a microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device). It will be readily apparent to those skilled in the art, using the description provided below, which references... Figures 2A to 2D The described methods and structures can be used in various devices and electronic systems.

[0065] See Figure 2AA first microelectronic device structure 200 (e.g., a first die) may be formed to include a control logic region 202. The control logic region 202 includes a semiconducting substrate structure 204, a gate structure 205, a first wiring structure 206, and a first interconnect structure 208. A portion of the semiconducting substrate structure 204, the gate structure 205, the first wiring structure 206, and the first interconnect structure 208 form various control logic devices 209 of the control logic region 202, as described in more detail below.

[0066] The semiconductive substrate structure 204 (e.g., a semiconductive wafer) of the control logic region 202 includes a substrate material or structure on which additional materials and structures of the first microelectronic device structure 200 are formed. The semiconductive substrate structure 204 may include a semiconductive structure (e.g., a semiconductive wafer) or a substrate semiconductive material located on a support structure. For example, the semiconductive substrate structure 204 may include a conventional silicon substrate (e.g., a conventional silicon wafer) or another bulk substrate comprising a semiconductive material. In some embodiments, the semiconductive substrate structure 204 includes a silicon wafer. Additionally, the semiconductive substrate structure 204 may include one or more layers, structures, and / or regions formed therein and / or on it. For example, the semiconductive substrate structure 204 may include conductive doped regions and undoped regions. The conductive doped regions may, for example, serve as the source and drain regions of the transistors of the control logic device 209 of the control logic region 202; and the undoped regions may, for example, serve as the channel regions of the transistors of the control logic device 209.

[0067] like Figure 2A As shown, the gate structure 205 of the control logic region 202 of the first microelectronic device structure 200 may be vertically superimposed on a portion of the semiconductive substrate structure 204. The gate structure 205 may extend horizontally individually within the control logic region 202 of the first microelectronic device structure 200 between and through the transistors of the control logic device 209. The gate structure 205 may be formed of and contain a conductive material. A gate dielectric material (e.g., dielectric oxide) may be vertically inserted (e.g., in the Z direction) between the gate structure 205 and the channel region of the transistor (e.g., within the semiconductive substrate structure 204).

[0068] like Figure 2AAs shown, a first wiring structure 206 may be vertically (e.g., in the Z direction) overlying a semiconductive substrate structure 204 and electrically connected to the semiconductive substrate structure 204 via a first interconnect structure 208. A portion of the first interconnect structure 208 may extend vertically between portions of the first wiring structure 206 and be electrically coupled to said portions, and other portions of the first interconnect structure 208 may extend vertically between regions of the first semiconductive substrate structure 204 (e.g., conductive doped regions, such as source and drain regions) and one or more of the first wiring structures 206, and electrically couple said regions to said one or more. The first wiring structure 206 and the first interconnect structure 208 may each be individually formed of and contain conductive material.

[0069] As previously mentioned, portions of the semiconducting substrate structure 204 (e.g., conductive doped regions acting as source and drain regions, and undoped regions acting as channel regions), gate structure 205, first wiring structure 206, and first interconnect structure 208 form various control logic devices 209 of the control logic region 202. The control logic devices 209 can be configured to control various operations of other components of a relatively large assembly (e.g., memory cells of a memory cell array) to include the first microelectronic device structure 200, as described in more detail below. As a non-limiting example, the control logic device 209 may include a charge pump (e.g., V0). CCP Charge pump, V NEGWL Charge pumps, DVC2 charge pumps), DLL circuit systems (e.g., ring oscillators), V ddOne or more of the following (e.g., each): regulator, string driver, page buffer, and various chip / stack control circuitry. As another non-limiting example, control logic device 209 may include means configured to control column operations of an array (e.g., memory element array, access device array) within a memory array region of another (e.g., second) microelectronic device structure to be coupled to the first microelectronic device structure 200: such as decoders (e.g., local stack decoders, column decoders), sense amplifiers (e.g., EQ amplifiers, ISO amplifiers, NSA, PSA), maintenance circuitry (e.g., column maintenance circuitry), I / O devices (e.g., local I / O devices), memory test devices, MUX, and ECC devices (e.g., each). As another non-limiting example, the control logic device 209 may include means configured to control row operations of an array (e.g., memory element array, access device array) within a memory array region of another microelectronic device structure to be coupled to the first microelectronic device structure 200, such as a decoder (e.g., local overlay decoder, row decoder), a driver (e.g., WL driver), a maintenance circuit system (e.g., row maintenance circuit system), a memory test device, a MUX, an ECC device, and a self-refresh / wear-out equalization device (e.g., each of these).

[0070] Continue to refer to Figure 2A The first microelectronic device structure 200 may further include a first pad structure 210 and a second interconnect structure 212 that is vertically overlaid on and electrically connected to a first wiring structure 206 of the control logic area 202. For example... Figure 2A As shown, a first pad structure 210 may be vertically overlaid on a first wiring structure 206, and a second interconnect structure 212 may extend vertically between and electrically connect to the first pad structure 210 and the first wiring structure 206. The first pad structure 210 and the second interconnect structure 212 may each be individually formed of and contain conductive material.

[0071] Next reference Figure 2B The second microelectronic device structure 250 (e.g., a second die) may be formed as including a substrate structure 214 (e.g., a substrate wafer, a support wafer), a memory array region 216 vertically located above the substrate structure 214 (e.g., in the Z direction), and an interconnect region 218 vertically located above and electrically connected to the memory array region 216. The memory array region 216 may be vertically inserted between the substrate structure 214 and the interconnect region 218.

[0072] The substrate structure 214 may include a substrate material or construction on which additional materials and structures for forming the second microelectronic device structure 250 are formed. The substrate structure 214 may be a conventional silicon substrate (e.g., a conventional silicon wafer) or another bulk substrate. As a non-limiting example, the substrate structure 214 may include one or more of the following: silicon, silicon dioxide, silicon having a native oxide, silicon nitride, silicon carbonitride, glass, semiconductor, metal oxide, metal, titanium nitride, titanium carbonitride, Ta, tantalum nitride, tantalum carbonitride, niobium, niobium nitride, niobium carbonitride, molybdenum, molybdenum nitride, molybdenum carbonitride, tungsten, tungsten nitride, tungsten carbonitride, Cu, Co, Ni, Fe, Al, and noble metals. In some embodiments, the substrate structure 214 includes a silicon wafer.

[0073] The memory array region 216 of the second microelectronic device structure 250 may include a stacked structure 222, a line structure 230 (e.g., a digital line structure, a bit line structure), and a line contact structure 232. For example... Figure 2B As shown, the wire structure 230 may be vertically (e.g., in the Z direction) overlying the stacked structure 222 and may be electrically connected to structures within the stacked structure 222 (e.g., pillar structures, filled vias) via the wire contact structure 232. The wire contact structure 232 may extend vertically between individual wire structures 230 and individual structures within the stacked structure 222 and be electrically coupled to said structures. The wire structure 230 and the wire contact structure 232 may each be individually formed of and contain conductive material.

[0074] The stacked structure 222 of the memory array region 216 includes a vertically alternating (e.g., in the Z direction) sequence of conductive structures 226 and insulating structures 228 arranged in a stack 224. The stacked structure 222 (including the stack 224 having conductive structures 226 and insulating structures 228) is comparable to the previously referenced... Figure 1A The described stacked structure 116 (including a stack 118 having a conductive structure 120 and an insulating structure 122) is substantially similar. Additionally, at least one deep contact structure 236 may extend vertically through the stacked structure 222. The deep contact structure 236 may be configured and positioned to electrically connect one or more components of the second microelectronic device structure 250 vertically overlying the stacked structure 222 to one or more components of the second microelectronic device structure 250 vertically lying beneath the stacked structure 222. The deep contact structure 236 may be formed of and contain a conductive material.

[0075] The memory array region 216 further includes additional structures and / or devices located on, above, and / or within the stacked structure 222. As a non-limiting example, the memory array region 216 includes cell pillar structures extending vertically through the stacked structure 222. The intersection of the cell pillar structures with the conductive structures 226 of the stack 224 of the stacked structure 222 defines a vertically extending string of memory cells coupled in series within the memory array region 216 of the second microelectronic device structure 250. The cell pillar structures and the vertically extending strings of memory cells can be correspondingly compared with previously referenced... Figure 1A The described cell column structure and the vertical extension string of memory cells are basically similar.

[0076] Continue to refer to Figure 2B The second microelectronic device structure 250 may further include a second pad structure 220 and a third interconnect structure 219 vertically inserted between the memory array region 216 and the substrate structure 214. The second pad structure 220 may lie vertically on the stack structure 222, and the third interconnect structure 219 may extend vertically between the second pad structure 220 and the substrate structure 214. Components (e.g., structures, devices) of the memory array region 216 may rest on the second pad structure 220, and the third interconnect structure 219 may physically contact the second pad structure 220 and the substrate structure 214. The second pad structure 220 and the third interconnect structure 219 may each be individually formed of and contain conductive material.

[0077] Continue to refer to Figure 2B The interconnect region 218 of the second microelectronic device structure 250 may include a second wiring structure 238 and a bonding pad structure 242. The second wiring structure 238 may vertically overlay and be electrically connected to the wiring structure 230 of the memory array region 216, and the bonding pad structure 242 may vertically overlay and be electrically connected to the second wiring structure 238. For example... Figure 2B As shown, a fourth interconnect structure 240 extends vertically between and electrically connects the second wiring structure 238 and the wire structure 230, and a fifth interconnect structure 244 extends vertically between and electrically connects the second wiring structure 238 and the bonding pad structure 242. The second wiring structure 238, the fourth interconnect structure 240, the bonding pad structure 242, and the fifth interconnect structure 244 may each be individually formed of and contain a conductive material. In some embodiments, the second wiring structure 238 is formed of and contains Al, and the bonding pad structure 242 is formed of and contains Cu.

[0078] Next reference Figure 2C , base structure 214 ( Figure 2BThe carrier structure 246 (e.g., carrier wafer) can be removed (e.g., peeled off) from the second microelectronic device structure 250, and the carrier structure 246 can be attached (e.g., bonded) to the bonding pad structure 242 by means of the adhesive material 248. The carrier structure 246 and the adhesive material 248 can be configured to facilitate the safe disposal of the second microelectronic device structure 250 for further processing (e.g., attachment to the first microelectronic device structure 200). Figure 2A As described in more detail below. The carrier structure 246 and adhesive material 248 may correspond to conventional carrier structures (e.g., conventional carrier wafers) and conventional adhesive materials, and are therefore not described in detail herein. Additionally, the substrate structure 214 ( Figure 2B The device can be removed from the second microelectronic device structure 250 using conventional removal processes (e.g., conventional stripping processes, conventional grinding processes) and conventional equipment, which are not described in detail herein.

[0079] Next, refer to Figure 2D The second microelectronic device structure 250 may be attached (e.g., bonded) to the first microelectronic device structure 200 to form a microelectronic device structure assembly 260, and the carrier structure 246 ( Figure 2C ) and adhesive material 248 ( Figure 2C (Can be removed.) Figure 2D As shown, the third interconnect structure 219 of the second microelectronic device structure 250 can be positioned on the first pad structure 210 of the first microelectronic device structure 200. Additionally, the dielectric material (e.g., dielectric oxide material) (for clarity and ease of understanding of the illustrations and related descriptions, see below) Figure 2D (omitted) may encompass and surround the first pad structure 210, the second interconnect structure 212, the third interconnect structure 219, and the second pad structure 220, and may at least partially physically couple the second microelectronic device structure 250 to the first microelectronic device structure 200. The second microelectronic device structure 250 may be attached to the first microelectronic device structure 200 without bonding wires.

[0080] After attaching the second microelectronic device structure 250 to the first microelectronic device structure 200, the carrier structure 246 ( Figure 2C ) and adhesive material 248 ( Figure 2C The microelectronic device structural assembly 260 can be removed using conventional removal processes (e.g., conventional stripping processes, conventional grinding processes) and conventional equipment, which are not described in detail herein.

[0081] The above references Figures 2A to 2DThe described method addresses limitations on the configuration of control logic devices and associated microelectronic device performance (e.g., speed, data transfer rate, power consumption), limitations that may otherwise arise from thermal budget constraints imposed by the formation and / or processing of the array of microelectronic devices (e.g., memory cell array, memory element array, access device array). For example, by forming a first microelectronic device structure 200 separated from the second microelectronic device structure 250, the configuration of control logic devices 209 within the control logic region 202 of the first microelectronic device structure 200 is not limited by the processing conditions (e.g., temperature, pressure, materials) required for the components (e.g., memory cells, memory elements, access devices) of the memory array region 216 of the second microelectronic device structure 250, and vice versa. Additionally, in the substrate structure 214 ( Figure 2B Features (e.g., structure, material, openings) that form the memory array region 216 above may prevent undesired out-of-plane deformation (e.g., bending, warping, folding, denting) of the components (e.g., the stack 224 of the stacked structure 222), which may otherwise occur during various deposition, patterning, doping, etching, and annealing processes used to form at least the memory array region 216.

[0082] Therefore, according to embodiments of this disclosure, a microelectronic device includes a memory array region, a first conductive pad structure, a second conductive pad structure, and a control logic region. The memory array region includes: a stacked structure comprising a vertically alternating sequence of conductive and insulating structures; and a vertically extending string of memory cells located within the stacked structure. The first conductive pad structure lies beneath the stacked structure of the memory array region. The second conductive pad structure lies beneath the first conductive pad structure. The control logic region lies beneath the second conductive pad structure and includes control logic devices, including a CMOS circuit system.

[0083] Furthermore, according to embodiments of this disclosure, a method of forming a microelectronic device includes forming a first microelectronic device structure including a control logic region, the control logic region including control logic devices. A second microelectronic device structure is formed including a substrate structure and a memory array region located on the substrate structure. The memory array region includes: a stacked structure including vertically alternating conductive and insulating structures; and a vertically extending string of memory cells located within the stacked structure. The substrate structure is removed from the second microelectronic device structure. The remaining portion of the second microelectronic device structure is attached to the first microelectronic device structure such that the control logic region of the first microelectronic device structure lies beneath the memory array region of the second microelectronic device structure.

[0084] Figures 3A to 3DThis is a simplified partial cross-sectional view illustrating an embodiment of another method for forming a microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device). It will be readily apparent to those skilled in the art, using the description provided below, which references... Figures 3A to 3D The described methods and structures can be used in various devices and electronic systems.

[0085] See Figure 3A A first microelectronic device structure 300 (e.g., a first die) may be formed to include a control logic region 302, including a semiconductive substrate structure 304, a gate structure 305, a first wiring structure 306, and a first interconnect structure 308. A portion of the semiconductive substrate structure 304, the gate structure 305, the first wiring structure 306, and the first interconnect structure 308 form various control logic devices 309 within the control logic region 302. The semiconductive substrate structure 304, the gate structure 305, the first wiring structure 306, the first interconnect structure 308, and the control logic devices 309 within the control logic region 302 may correspond to previously referenced... Figure 2A The described semiconducting substrate structure 204, gate structure 205, first wiring structure 206, first interconnect structure 208, and control logic device 209 are substantially similar. Additionally, the first microelectronic device structure 300 may further include a pad structure 310 and a second interconnect structure 312 that are vertically overlaid on and electrically connected to the first wiring structure 306 of the control logic region 302. The pad structure 310 and the second interconnect structure 312 may correspond to those previously referenced. Figure 2A The first pad structure 210 and the second interconnect structure 212 described are substantially similar.

[0086] Still referencing Figure 3A The first microelectronic device structure 300 is further configured to include an additional semiconductive structure 314 vertically (e.g., in the Z direction) over the control logic region 302 (e.g., vertically over the first pad structure 210, and vertically over the first wiring structure 306 of the control logic region 302); and one or more semiconductive pillar structures 318 extending vertically (e.g., in the Z direction) from and between the semiconductive substrate structure 304 and the additional semiconductive structure 314. Figure 3A As shown, the semiconducting pillar structure 318 can extend vertically from the additional semiconducting structure 314 through the first wiring structure 306 of the control logic area 302 and extend to the semiconducting substrate structure 304.

[0087] The additional semiconducting structure 314 and the semiconducting pillar structure 318 may each be individually formed of and comprise a semiconducting material (e.g., silicon material such as monocrystalline or polycrystalline silicon; silicon-germanium material; germanium material; gallium arsenide material; gallium nitride material; indium phosphide material; or combinations thereof). In some embodiments, the additional semiconducting structure 314 and the semiconducting pillar structure 318 are each formed of and comprise monocrystalline silicon. Additionally, the additional semiconducting structure 314 may be formed to include at least one conductive doped region 316. The conductive doped region 316 of the additional semiconducting structure 314 may be doped with one or more conductive dopants (e.g., one or more N-type dopants, such as one or more of phosphorus, arsenic, antimony, and bismuth; one or more P-type dopants, such as one or more of boron, aluminum, and gallium), and may serve as the source region for a vertically extended string of memory cells to be coupled, as described in more detail below.

[0088] In some embodiments, the additional semiconducting structure 314 is formed by epitaxial growth, followed by doping implantation to form its conductive doped region 316. In an additional embodiment, the additional semiconducting structure 314 is formed (e.g., diced) from an additional semiconducting structure (e.g., separately relative to the semiconducting structure, such as a separate silicon wafer) and subsequently vertically provided (e.g., placed) over the control logic region 302. For example, hydrogen ions can be implanted into the additional semiconducting structure to a desired vertical depth, the additional semiconducting structure can be heated to form voids (e.g., recesses, bubbles) to a desired vertical depth in the additional semiconducting structure, and the additional semiconducting structure 314 can be effectively diced from the additional semiconducting structure, and then the additional semiconducting structure 314 can be provided over the control logic region 302. The conductive doped region 316 of the additional semiconducting structure 314 can be formed before or after providing the additional semiconducting structure 314 over the control logic region 302.

[0089] Next reference Figure 3B The second microelectronic device structure 350 (e.g., another die) may be formed as including a substrate structure 320 (e.g., a substrate wafer), a memory array region 322 located vertically above (e.g., in the Z direction) of the substrate structure 320, and an interconnect region 324 located vertically above and electrically connected to the memory array region 322. The memory array region 322 may be vertically inserted between the substrate structure 320 and the interconnect region 324. The substrate structure 320 may be compared with the previously referenced Figure 2B The described substrate structure 214 is basically similar.

[0090] The memory array region 322 of the second microelectronic device structure 350 may include a stacked structure 326, a line structure 338 (e.g., a digital line structure, a bit line structure), and a line contact structure 340. For example... Figure 3BAs shown, the wire structure 338 may be vertically (e.g., in the Z direction) overlying the stacked structure 326 and may be electrically connected to structures within the stacked structure 326 (e.g., pillar structures, filled vias) via the wire contact structure 340. The wire contact structure 340 may extend vertically between the individual wire structure 338 and the individual structures within the stacked structure 326 and be electrically coupled to said structures. The wire structure 338 and the wire contact structure 340 may each be individually formed of and contain a conductive material.

[0091] The stacked structure 326 of the memory array region 322 includes a vertically alternating (e.g., in the Z direction) sequence of conductive structures 330 and insulating structures 332 arranged in a stack 328. The stacked structure 326 (including the stack 328 having conductive structures 330 and insulating structures 332) is comparable to the previously referenced... Figure 1A The described stacked structure 116 (including a stack 118 having a conductive structure 120 and an insulating structure 122) is substantially similar. Additionally, at least one deep contact structure 337 may extend vertically through the stacked structure 326. For example, as... Figure 3B As shown, the deep contact structure 337 may extend vertically from the higher vertical boundary of the stacked structure 326, through the stacked structure 326, and extend to the higher vertical boundary of the substrate structure 320 or the closest location (e.g., within the dielectric material on the substrate structure 320). The deep contact structure 337 may be formed of and contain conductive material.

[0092] like Figure 3B As shown, the memory array region 322 further includes a cell pillar structure 336 extending vertically through the stack structure 326. The intersection of the cell pillar structure 336 and the conductive structure 330 of the stack 328 of the stack structure 326 defines a vertically extending string of memory cells 335 coupled in series within the memory array region 322 of the second microelectronic device structure 350. The cell pillar structure 336 and the vertically extending string of memory cells 335 are correspondingly related to the previously referenced... Figure 1A The described cell pillar structure and the vertically extending string of memory cells are substantially similar. The cell pillar structure 336 may extend vertically from the higher vertical boundary of the stack structure 326, through the stack structure 326, and to the higher vertical boundary of the substrate structure 320 or the closest location (e.g., within the dielectric material on the substrate structure 320).

[0093] Still referencing Figure 3BThe memory array region 322 also includes a conductive contact structure 334 (e.g., a source contact structure) extending vertically through the stack structure 326. The conductive contact structure 334 may be horizontally positioned within a fill slot extending vertically through the stack structure 326. The fill slot may divide the stack structure 326 into multiple (e.g., a plurality of) blocks spaced apart from each other by the fill slot. The conductive contact structure 334 may extend vertically from a higher vertical boundary of the stack structure 326, through the stack structure 326, and to the higher vertical boundary of the substrate structure 320 or its closest location (e.g., within the dielectric material on the substrate structure 320). Further processing of the second microelectronic device structure 350 and the first microelectronic device structure 300 ( Figure 3A When the conductive contact structure 334 is sized, shaped, and positioned to contact the first microelectronic device structure 300, the conductive contact structure 334 can be configured to do so. Figure 3A Additional semiconducting structure 314 () Figure 3A The conductive doped region 316 ( Figure 3A ), as described in more detail below.

[0094] Continue to refer to Figure 3B The interconnect region 324 of the second microelectronic device structure 350 may include a second wiring structure 342 and a bonding pad structure 346. The second wiring structure 342 may vertically overlay and be electrically connected to the line structure 338 of the memory array region 322, and the bonding pad structure 346 may vertically overlay and be electrically connected to the second wiring structure 342. Figure 3B As shown, a third interconnect structure 344 extends vertically between and electrically connects the second wiring structure 342 and the wire structure 338, and a fourth interconnect structure 348 extends vertically between and electrically connects the second wiring structure 342 and the bonding pad structure 346. The second wiring structure 342, the third interconnect structure 344, the bonding pad structure 346, and the fourth interconnect structure 348 may each be individually formed of and contain a conductive material. In some embodiments, the second wiring structure 342 is formed of and contains Al, and the bonding pad structure 346 is formed of and contains Cu.

[0095] Next reference Figure 3C , base structure 320 ( Figure 3B The carrier structure 352 (e.g., carrier wafer) can be removed (e.g., peeled off) from the second microelectronic device structure 350, and the carrier structure 352 can be attached (e.g., bonded) to the bonding pad structure 346 by means of the adhesive material 354. The carrier structure 352 and the adhesive material 354 can be configured to facilitate the safe disposal of the second microelectronic device structure 350 for further processing (e.g., attachment to the first microelectronic device structure 300). Figure 3AAs described in more detail below. The carrier structure 352 and adhesive material 354 may correspond to conventional carrier structures (e.g., conventional carrier wafers) and conventional adhesive materials, and are therefore not described in detail herein. Additionally, the substrate structure 320 ( Figure 3B The device can be removed from the second microelectronic device structure 350 using conventional removal processes (e.g., conventional stripping processes, conventional grinding processes) and conventional equipment, which are not described in detail herein.

[0096] Next, refer to Figure 3D The second microelectronic device structure 350 may be attached (e.g., bonded) to the first microelectronic device structure 300 to form a microelectronic device structure assembly 360, and the carrier structure 352 ( Figure 3C ) and adhesive material 354 ( Figure 3C It is removable. The second microelectronic device structure 350 can be attached to the first microelectronic device structure 300 without bonding wires. For example... Figure 3D As shown, the conductive contact structure 334, unit pillar structure 336, and deep contact structure 337 of the second microelectronic device structure 350 can be positioned on the additional semiconducting structure 314 of the first microelectronic device structure 300. The conductive contact structure 334 and unit pillar structure 336 of the second microelectronic device structure 350 can contact (e.g., physically or electrically) the conductive doped region 316 (e.g., the source region) of the additional semiconducting structure 314.

[0097] After attaching the second microelectronic device structure 350 to the first microelectronic device structure 300, the carrier structure 352 ( Figure 3C ) and adhesive material 354 ( Figure 3C The microelectronic device structural assembly 360 can be removed using conventional removal processes (e.g., conventional stripping processes, conventional grinding processes) and conventional equipment, which are not described in detail herein.

[0098] The above references Figures 3A to 3D The described method advantageously allows the unit pillar structure 336 and conductive contact structure 334 (and associated filling slots) to be formed within the stacked structure 326 without the difficulties and problems typically associated with forming unit pillar structures and conductive contact structures within conventional stacked structures vertically superimposed on the source structure or source region. For example, if the conductive doped region 316 is vertically positioned below the stacked structure 326 during the process of forming the unit pillar structure 336 and conductive contact structure 334, then the stacked structure 326 vertically superimposed on the substrate structure 320 ( Figure 3B(Instead of vertically covering the conductive doped region 316 of the additional semiconductive structure 314 onto the stacked structure 326) while forming the unit pillar structure 336 and conductive contact structure 334 within the stacked structure 326, this mitigates processing complexity and / or undesirable damage to the conductive doped region 316 (e.g., corrosion damage) that could otherwise occur (e.g., during an etching process that forms openings in the initial stacked structure to fill the unit pillar structure 336 and conductive contact structure 334). Additionally, the above references... Figures 3A to 3D The described method also benefits from the references in this paper. Figures 2A to 2D The advantages discussed in relation to the described method.

[0099] Figures 4A to 4D This is a simplified partial cross-sectional view illustrating an embodiment of another method for forming a microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device). It will be readily apparent to those skilled in the art, using the description provided below, which references... Figures 4A to 4D The described methods and structures can be used in various devices and electronic systems.

[0100] See Figure 4A A first microelectronic device structure 400 (e.g., a first die) may be formed to include a control logic region 402, which includes a semiconducting substrate structure 404, a gate structure 405, a first wiring structure 406, and a first interconnect structure 408. A portion of the semiconducting substrate structure 404, the gate structure 405, the first wiring structure 406, and the first interconnect structure 408 form various control logic devices 409 of the control logic region 402. The semiconducting substrate structure 404, the gate structure 405, the first wiring structure 406, the first interconnect structure 408, and the control logic devices 409 of the control logic region 402 may correspond to those described above. Figure 2A The described semiconducting substrate structure 204, gate structure 205, first wiring structure 206, first interconnect structure 208, and control logic device 209 are substantially similar. Optionally, the semiconducting substrate structure 404 may also include at least partially (e.g., incompletely, completely) vertically extending one or more filled vias 407 (e.g., filled TSVs). If present, the filled vias 407 may be at least partially (e.g., substantially) filled with a conductive material. The filled vias 407 can be used to facilitate electrical connections between one or more components of a first microelectronic device structure 400 located on a first side (e.g., front side, top side) of the first semiconducting substrate structure 404 and additional components (e.g., one or more structures and / or devices) to be provided on a second opposite side (e.g., back side, bottom side) of the first semiconducting substrate structure 404, as described in more detail below. In an additional embodiment, the filled vias 407 are omitted from the semiconducting substrate structure 404 (e.g., they are not present).

[0101] like Figure 4A As shown, the first microelectronic device structure 400 can also be configured as including a first wiring structure 406 vertically overlying and electrically communicating with the control logic area 402, and a first pad structure 410 and a second interconnect structure 412. The first pad structure 410 and the second interconnect structure 412 can be correspondingly described in the foregoing reference. Figure 2A The first pad structure 210 and the second interconnect structure 212 described are substantially similar.

[0102] Next reference Figure 4B The second microelectronic device structure 450 (e.g., another die) may be formed as including a substrate structure 414 (e.g., a substrate wafer), a memory array region 416 located vertically above (e.g., in the Z direction) of the substrate structure 414, and an interconnect region 418 located vertically above and electrically connected to the memory array region 416. The memory array region 416 may be vertically inserted between the substrate structure 414 and the interconnect region 418. The substrate structure 414 may be compared with the previously referenced Figure 2B The described substrate structure 214 is basically similar.

[0103] The memory array region 416 of the second microelectronic device structure 250 may include: a stack structure 422 comprising a vertically alternating (e.g., in the Z direction) sequence of conductive structures 426 and insulating structures 428 arranged in a stack 424; a line structure 430 (e.g., a digital line structure, a bit line structure); a line contact structure 432; and a deep contact structure 436. The stack structure 422 (including the stack 424 having conductive structures 426 and insulating structures 428), the line structure 430, the line contact structure 432, and the deep contact structure 436 may correspond to the previously referenced Figure 2B The described stacked structure 222 (including a stack 224 having a conductive structure 226 and an insulating structure 228), wire structure 230, wire contact structure 232 and deep contact structure 236 are substantially similar.

[0104] The memory array region 416 of the second microelectronic device structure 450 further includes additional structures and / or devices located on, above, and / or within the stacked structure 422. As a non-limiting example, the memory array region 416 includes cell pillar structures extending vertically through the stacked structure 422. The intersection of the cell pillar structures with the conductive structures 426 of the stack 424 of the stacked structure 422 defines a vertically extending string of memory cells coupled in series within the memory array region 416 of the second microelectronic device structure 450. The cell pillar structures and the vertically extending strings of memory cells can be correspondingly compared with previously referenced... Figure 1A The described cell column structure and the vertical extension string of memory cells are basically similar.

[0105] The second microelectronic device structure 450 may further include a second pad structure 420 and a third interconnect structure 419 vertically inserted between the memory array region 416 and the substrate structure 414. The second pad structure 420 and the third interconnect structure 419 may correspond to those previously referenced. Figure 2B The second pad structure 220 and the third interconnect structure 219 described are substantially similar.

[0106] Still referencing Figure 4B The interconnect region 418 of the second microelectronic device structure 450 may include a second wiring structure 438, a fourth interconnect structure 440, a bonding pad structure 442, and a fifth interconnect structure 444. The second wiring structure 438, the fourth interconnect structure 440, the bonding pad structure 442, and the fifth interconnect structure 444 may correspond to those previously referenced. Figure 2B The second wiring structure 238, the fourth interconnect structure 240, the bonding pad structure 242, and the fifth interconnect structure 244 described are substantially similar.

[0107] Next reference Figure 4C , base structure 414 ( Figure 4B The carrier structure 446 (e.g., carrier wafer) can be removed (e.g., peeled off) from the second microelectronic device structure 450, and the carrier structure 446 can be attached (e.g., bonded) to the bonding pad structure 442 by means of an adhesive material 448. The carrier structure 446 and the adhesive material 448 can be configured to facilitate the safe disposal of the second microelectronic device structure 450 for further processing (e.g., attachment to the first microelectronic device structure 400). Figure 4A As described in more detail below, the carrier structure 446 and adhesive material 448 may correspond to conventional carrier structures (e.g., conventional carrier wafers) and conventional adhesive materials, and are therefore not described in detail herein. Additionally, the substrate structure 414 ( Figure 4B The device can be removed from the second microelectronic device structure 450 using conventional removal processes (e.g., conventional stripping processes, conventional grinding processes) and conventional equipment, which are not described in detail herein.

[0108] Next, see Figure 4D The second microelectronic device structure 450 may be attached (e.g., bonded) to the first microelectronic device structure 400, and the passive device 452 may be formed vertically adjacent to the rear side (e.g., bottom side, lower side) of the first microelectronic device structure 400 to form a microelectronic device structure assembly 460. The second microelectronic device structure 450 may be attached to the first microelectronic device structure 400 without bonding wires. Thereafter, the carrier structure 446 ( Figure 4C ) and adhesive material 448 ( Figure 4C (Can be removed)

[0109] like Figure 4DAs shown, the third interconnect structure 419 of the second microelectronic device structure 450 can be positioned on the first pad structure 410 of the first microelectronic device structure 400. Additionally, the dielectric material (e.g., dielectric oxide material) (for clarity and ease of understanding of the illustrations and related descriptions, see below) Figure 4D (omitted) may cover and surround the first pad structure 410, the second interconnect structure 412, the third interconnect structure 419 and the second pad structure 420, and may at least partially physically couple the second microelectronic device structure 450 to the first microelectronic device structure 400.

[0110] Passive device 452 may include one or more of resistors, capacitors, inductors, and decoupling devices. For example... Figure 4D As shown, passive device 452 may be electrically connected to a filled via 407 (e.g., filled TSV) extending vertically through a semiconductive substrate structure 404 and may include a third wiring structure 454 and a fourth interconnect structure 456 operatively associated therewith. The filled via 407 may be connected to one or more third pad structures 458, one or more of the fourth interconnect structures 456 may extend vertically between one or more of the third pad structures 458 and one or more of the third wiring structures 454 and electrically couple them, and other fourth interconnect structures 456 may extend vertically between portions of the third wiring structures 454 and electrically couple them. The third pad structures 458, third wiring structures 454, and fourth interconnect structures 456 may each be individually formed of and contain conductive material.

[0111] The third pad structure 458 may be formed and connected to the conductive material filling the via 407, for example, after the semiconducting substrate structure 404 has been thinned (e.g., in the Z direction) from the back side of the semiconducting substrate structure 404, to expose the via 407 after the second microelectronic device structure 450 is attached to the first microelectronic device structure 400. In an additional embodiment, the via 407 is formed in the semiconducting substrate structure 404 after the second microelectronic device structure 450 is attached to the first microelectronic device structure 400, and then the third pad structure 458 is formed and connected to the conductive material filling the via 407. Thereafter, the third wiring structure 454 and the fourth interconnect structure 456 may be formed to be electrically connected to the third pad structure 458 (and therefore, the via 407).

[0112] After the microelectronic device structure assembly 460 is formed, the carrier structure 446 can be removed from it using conventional removal processes (e.g., conventional peeling processes, conventional polishing processes) and conventional equipment. Figure 4C ) and adhesive material 448 ( Figure 4C (This is not described in detail in this article.)

[0113] The structures, assemblies, and devices according to embodiments of this disclosure can be used in embodiments of the electronic systems of this disclosure. For example, Figure 5 This is a block diagram of an illustrative electronic system 500 according to embodiments of the present disclosure. The electronic system 500 may include, for example, a computer or computer hardware component, a server or other network-connected hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a tablet computer with Wi-Fi or cellular capabilities (e.g.,...). or Tablet computers, e-books, navigation devices, etc. Electronic system 500 includes at least one memory device 502. Memory device 502 may include, for example, those previously referenced herein. Figure 1C , 1D Embodiments of microelectronic device structures, microelectronic device structure assemblies, and one or more microelectronic devices described in 2D, 3D, and 4D are available. Electronic system 500 may further include at least one electronic signal processor device 504 (commonly referred to as a "microprocessor"). Electronic signal processor device 504 may optionally include embodiments previously referenced herein. Figure 1C , 1D Embodiments of one or more of the microelectronic device structures, microelectronic device structure assemblies, and microelectronic devices described in 2D, 3D, and 4D. Although in Figure 5 The memory device 502 and the electronic signal processor device 504 are depicted as two (2) separate devices, but in additional embodiments, a single (e.g., a unique) memory / processor device having the functionality of both the memory device 502 and the electronic signal processor device 504 is included in the electronic system 500. In these embodiments, the memory / processor device may include those previously referenced herein. Figure 1C , 1D The electronic system 500 may include one or more microelectronic device structures, microelectronic device structure assemblies, and microelectronic devices described in 2D, 3D, and 4D. The electronic system 500 may further include one or more input devices 506 for inputting information to the electronic system 500 by a user, such as a mouse or other pointing device, keyboard, touchpad, button, or control panel. The electronic system 500 may further include one or more output devices 508 for outputting information (e.g., visual or audio output) to the user, such as one or more of a monitor, display, printer, audio output jack, and speaker. In some embodiments, the input device 506 and output device 508 may include a single touchscreen device available for inputting information to the electronic system 500 and outputting visual information to the user. The input device 506 and output device 508 may be electrically connected to one or more of a memory device 502 and an electronic signal processor device 504.

[0114] Therefore, according to embodiments of this disclosure, an electronic system includes an input device, an output device, a processor device operatively coupled to the input device and the output device, and a memory device operatively coupled to the processor device. The memory device includes a stacked structure, a vertically extending string of memory cells within the stacked structure, control logic including a CMOS circuitry underlying the stacked structure, and additional control logic including an additional CMOS circuitry overlying the stacked structure. The stacked structure includes layers, each including a conductive structure and an insulating structure vertically adjacent to the conductive structure. The control logic is configured to implement a portion of the control operation of the vertically extending string of memory cells. The additional control logic has a relatively lower operating voltage requirement than the control logic and is configured to implement an additional portion of the control operation of the vertically extending string of memory cells.

[0115] The methods, structures, assemblies, apparatuses, and systems disclosed herein advantageously promote one or more of the following improvements compared to conventional methods, structures, assemblies, apparatuses, and systems: improved performance, reliability, durability, increased miniaturization of components, improved pattern quality, and greater package density. The methods, structures, and assemblies of this disclosure can substantially mitigate problems associated with the formation and handling of conventional microelectronic devices, such as damage to undesirable features (e.g., corrosion damage), deformation (e.g., warping, bending, denting, folding), and performance limitations (e.g., speed limitations, data transmission limitations, power consumption limitations).

[0116] Additional non-limiting examples of this disclosure are described below.

[0117] Example 1: A microelectronic device comprising: a memory array region, the memory array region including: a stacked structure including vertically alternating conductive and insulating structures; a vertically extending string of memory cells located within the stacked structure; a control logic region underlying the stacked structure and including control logic means configured to implement a portion of control operations on the vertically extending string of memory cells; and an additional control logic region overlying the stacked structure and including additional control logic means configured to implement an additional portion of the control operations on the vertically extending string of memory cells.

[0118] Example 2: The microelectronic device according to Example 1, wherein the additional control logic device of the additional control logic region is configured to operate at an applied voltage of less than or equal to about 1.4V.

[0119] Example 3: The microelectronic device according to Example 1, wherein the additional control logic device of the additional control logic region is configured to operate at an applied voltage in the range of about 0.7V to about 1.3V.

[0120] Example 4: A microelectronic device according to any one of Examples 1 to 3, wherein the control logic device and the additional control logic device each individually include a CMOS circuit system.

[0121] Example 5: A microelectronic device according to any one of Examples 1 to 4, further comprising: a conductive pad structure lying beneath the stacked structure and electrically connected to the control logic device; and an additional conductive pad structure covering the stacked structure and electrically connected to the additional control logic device.

[0122] Example 6: The microelectronic device according to Example 5 further includes at least one conductive contact structure that extends vertically through the stacked structure and is electrically connected to at least one of the conductive pad structures and at least one of the additional conductive pad structures.

[0123] Example 7: The microelectronic device according to any one of Examples 5 and 6 further includes: a conductive line structure vertically located between the stacked structure and the additional conductive pad structure; a conductive wiring structure vertically located between the conductive line structure and the additional conductive pad structure; and an interconnect structure vertically located between the conductive wiring structure and the additional conductive pad structure.

[0124] Example 8: The microelectronic device according to Example 7, wherein: the conductive wiring structure comprises aluminum; and the interconnect structure comprises copper.

[0125] Example 9: A microelectronic device according to any one of Examples 1 to 8, further comprising: an additional memory array region, the additional memory array region being subordinate to the control logic region and including: an additional stacking structure, which includes vertically alternating additional conductive structures and additional insulating structures; and additional vertically extending strings of memory cells located within the additional stacking structure.

[0126] Example 10: A method of forming a microelectronic device, comprising: forming a first microelectronic device structure, the first microelectronic device structure including: a control logic region including control logic devices; and a memory array region located above the control logic region and including: a stacked structure including vertically alternating conductive and insulating structures; and a vertically extending string of memory cells located within the stacked structure; forming a second microelectronic device structure, the second microelectronic device structure including an additional control logic region including additional control logic devices; and attaching the first microelectronic device structure to the second microelectronic device structure such that the stacked structure is vertically inserted between the control logic region and the additional control logic region.

[0127] Example 11: According to the method of Example 10, wherein: forming a first microelectronic device structure includes forming the first microelectronic device structure to further include a bonding pad structure located above and electrically connected to the stacked structure; forming a second microelectronic device structure includes forming the second microelectronic device structure to further include an additional bonding pad structure located above and electrically connected to the additional control logic device in the additional control logic region; and attaching the first microelectronic device structure to the second microelectronic device includes physically contacting and heating the bonding pad structure and the additional bonding pad structure to thereby form an interconnect structure.

[0128] Example 12: The method according to any of Examples 10 and 11 further includes selecting the additional control logic device to include a CMOS circuit system configured to operate at an applied voltage in the range of about 0.7V to about 1.4V.

[0129] Example 13: The method according to Example 12 further includes selecting the control logic device to include an additional CMOS circuit system configured to operate at an applied voltage greater than the applied voltage effectively used to operate the additional control logic device.

[0130] Example 14: The method according to any one of Examples 10 to 13 further includes: forming a third microelectronic device structure, the third microelectronic device structure including: an additional control logic region including additional control logic devices; and an additional memory array region located above the additional control logic region and including: an additional stacking structure including vertically alternating additional conductive structures and additional insulating structures; and additional vertically extending strings of memory cells located within the additional stacking structure; and attaching the third microelectronic device structure to the first microelectronic device structure such that the additional stacking structure lies vertically beneath the stacking structure.

[0131] Example 15: A microelectronic device comprising: a memory array region, the memory array region including: a stacked structure including a vertically alternating sequence of conductive and insulating structures; and a vertically extending string of memory cells located within the stacked structure; a first conductive pad structure underlying the stacked structure of the memory array region; a second conductive pad structure underlying the first conductive pad structure; and a control logic region underlying the second conductive pad structure and including control logic devices, the control logic devices including a CMOS circuit system.

[0132] Example 16: The microelectronic device according to Example 15, wherein the first conductive pad structure is electrically connected to the second conductive pad structure by means of a conductive interconnect structure extending vertically between the first conductive pad structure and the second conductive pad structure.

[0133] Example 17: A microelectronic device according to any one of Examples 15 and 16, wherein the memory array region further includes: a conductive line structure vertically covering the stacked structure; and at least one conductive contact structure extending vertically through the stacked structure and electrically connected to at least one of the conductive line structures and at least one of the first conductive pad structures.

[0134] Example 18: The microelectronic device according to Example 17 further includes: an additional conductive structure covering the conductive line structure and electrically connected to at least some of the conductive line structures; and a bonding pad structure covering the additional conductive structure and electrically connected to it.

[0135] Example 19: The microelectronic device according to Example 18, wherein: the additional conductive structure comprises aluminum; and the bonding pad structure comprises copper.

[0136] Example 20: A microelectronic device according to any one of Examples 15 to 19, further comprising a passive device, the passive device being located beneath the control logic device in the control logic region.

[0137] Example 21: A method of forming a microelectronic device, comprising: forming a first microelectronic device structure including a control logic region, the control logic region including control logic devices; forming a second microelectronic device structure including: a substrate structure; and a memory array region covering the substrate structure and including: a stacked structure including vertically alternating conductive and insulating structures; and a vertically extending string of memory cells located within the stacked structure; removing the substrate structure from the second microelectronic device structure; and attaching the remaining portion of the second microelectronic device structure to the first microelectronic device structure such that the control logic region of the first microelectronic device structure lies beneath the memory array region of the second microelectronic device structure.

[0138] Example 22: According to the method of Example 21, wherein: forming a first microelectronic device structure includes forming the first microelectronic device structure to further include a conductive pad structure covering the control logic device; forming a second microelectronic device structure includes forming the second microelectronic device structure to further include an additional conductive pad structure between the substrate structure and the stacked structure of the memory array region; and attaching the remaining portion of the second microelectronic device structure to the first microelectronic device structure includes positioning the additional conductive pad structure of the second microelectronic device structure above the conductive pad structure of the first microelectronic device structure.

[0139] Example 23: According to the method of Example 21, forming the second microelectronic device structure includes forming the second microelectronic device structure to further include an interconnect region covering the memory array region and including a bonding pad structure.

[0140] Example 24: The method according to Example 23 further includes: attaching a carrier structure to the bonding pad structure before removing the substrate structure from the second microelectronic device structure; positioning the remaining portion of the second microelectronic device structure above the first microelectronic device structure while the carrier structure is attached to the bonding pad structure; and removing the carrier structure after attaching the remaining portion of the second microelectronic device structure to the first microelectronic device structure.

[0141] Example 25: The method according to any one of Examples 21 to 24 further includes forming a passive device below the control logic device after attaching the remaining portion of the second microelectronic device structure to the first microelectronic device structure.

[0142] Example 26: The method according to any one of Examples 21 to 25 further includes: forming the first microelectronic device structure to further include a semiconductive structure covering the control logic region, the semiconductive structure including a conductive doped source region; and forming the memory array region of the second microelectronic device structure to further include a conductive power electrode contact extending vertically through the stacked structure.

[0143] Example 27: According to the method of Example 26, attaching the remaining portion of the second microelectronic device structure to the first microelectronic device structure includes positioning the conductive power electrode contact above and electrically communicating with the conductive doped source electrode region of the semiconductive structure.

[0144] Example 28: The method according to Example 27 further includes forming the semiconductive structure to include monocrystalline silicon.

[0145] Example 29: The method according to any of Examples 27 and 28 further includes forming the semiconductive structure over the control logic region using epitaxial growth.

[0146] Example 30: An electronic system comprising: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and comprising: a stacked structure comprising layers each including a conductive structure and an insulating structure vertically adjacent to the conductive structure; a vertically extending string of memory cells located within the stacked structure; a control logic device including a CMOS circuitry underlying the stacked structure, the control logic device being configured to implement a portion of control operations of the vertically extending string of memory cells; and additional control logic device including an additional CMOS circuitry overlying the stacked structure, the additional control logic device having a relatively lower operating voltage requirement than the control logic device, and being configured to implement an additional portion of the control operations of the vertically extending string of memory cells.

[0147] While this disclosure allows for various modifications and alternatives, specific embodiments are shown by way of example in the drawings and have been described in detail herein. However, this disclosure is not limited to the specific forms disclosed. Rather, this disclosure is intended to cover all modifications, equivalents, and alternatives that fall within the scope of the appended claims and their legal equivalents. For example, elements and features disclosed with respect to one embodiment may be combined with elements and features disclosed with respect to other embodiments of this disclosure.

Claims

1. A microelectronic device comprising: The assembly includes: The memory array region includes: A stacked structure comprising vertically alternating conductive and insulating structures; Memory cell strings, each extending vertically through the stacked structure; and Digital lines, which are overlaid on the stacked structure and coupled to the memory cell string; A control logic region, which lies beneath the stacked structure, and includes control logic means configured to implement a portion of the control operations of the memory cell string; and An additional control logic region, overlying the digital lines, and including additional control logic means configured to implement additional portions of the control operations of the memory cell string; and A microelectronic device structure attached to the assembly and comprising: An additional memory array region, which lies beneath the control logic region of the assembly, the additional memory array region comprising: Additional stacked structures, which include vertically alternating additional conductive structures and additional insulating structures; Additional memory cell strings, each extending vertically through the additional stacking structure; and Additional digital lines, which overlay the additional stacked structure and are coupled to the additional memory cell string; and An additional control logic region, which lies beneath the additional memory array region, includes additional control logic means configured to implement part of the control operations of the additional memory cell string of the additional memory array region.

2. The microelectronic device of claim 1, wherein the additional control logic device of the additional control logic region is configured to operate at an applied voltage of less than or equal to 1.4V.

3. The microelectronic device of claim 1, wherein the additional control logic device of the additional control logic region is configured to operate at an applied voltage in the range of 0.7V to 1.3V.

4. The microelectronic device of claim 1, wherein the control logic device and the additional control logic device each individually comprise a CMOS circuit system.

5. The microelectronic device according to any one of claims 1 to 4, further comprising: A conductive pad structure lies beneath the stacked structure and is electrically connected to the control logic device; and An additional conductive pad structure is overlaid on the stacked structure and electrically connected to the additional control logic device.

6. The microelectronic device of claim 5, further comprising at least one conductive contact structure that extends vertically through the stacked structure and is electrically connected to at least one of the conductive pad structures and at least one of the additional conductive pad structures.

7. The microelectronic device according to claim 5, further comprising: A conductive wire structure, which is vertically positioned between the stacked structure and the additional conductive pad structure; A conductive wiring structure, vertically positioned between the conductive wire structure and the additional conductive pad structure; and An interconnect structure, which is vertically positioned between the conductive wiring structure and the additional conductive pad structure.

8. The microelectronic device according to claim 7, wherein: The conductive wiring structure includes aluminum; and The interconnect structure includes copper.

9. A method of forming a microelectronic device, comprising: A first microelectronic device structure is formed, the first microelectronic device structure comprising: Control logic area, including control logic devices; and The memory array region, located above the control logic region, includes: A stacked structure comprising vertically alternating conductive and insulating structures; Memory cell strings, each extending vertically through the stacked structure; and Digital lines, which are overlaid on the stacked structure and coupled to the memory cell string; A second microelectronic device structure is formed, the second microelectronic device structure including an additional control logic region, which includes additional control logic devices; The first microelectronic device structure is attached to the second microelectronic device structure to form an assembly, the assembly including the stacked structure vertically inserted between the control logic area and the additional control logic area; The third microelectronic device structure comprises: The additional control logic area includes additional control logic devices; and An additional memory array region, located above the additional control logic region, includes: Additional stacked structures, which include vertically alternating additional conductive structures and additional insulating structures; Additional memory cell strings, each extending vertically through the additional stacking structure; and Additional digital lines, which overlay the additional stacked structure and are coupled to the additional memory cell string; and The assembly is attached to the third microelectronic device structure to form a configuration including a control logic region overlying the additional control logic region, and the additional control logic region overlying the control logic region.

10. The method according to claim 9, wherein: Forming a first microelectronic device structure includes forming the first microelectronic device structure as further comprising a bonding pad structure located above and electrically connected to the stacked structure; Forming the second microelectronic device structure includes forming the second microelectronic device structure to further include an additional bonding pad structure located above and electrically connected to the additional control logic device in the additional control logic region; and Attaching the first microelectronic device structure to the second microelectronic device structure includes physically contacting and heating the bonding pad structure and the additional bonding pad structure to thereby form an interconnect structure.

11. The method of claim 9, further comprising selecting the additional control logic device to include a CMOS circuit system configured to operate at an applied voltage in the range of 0.7V to 1.4V.

12. The method of claim 11, further comprising selecting the control logic device to include an additional CMOS circuit system configured to operate at an applied voltage greater than the applied voltage effectively used to operate the additional control logic device.

13. A microelectronic device comprising: A memory device comprising: The memory array region includes: A stacked structure comprising a vertically alternating sequence of conductive and insulating structures; and A vertically extending string of memory cells located within the stacked structure; A first conductive pad structure lies beneath the stacked structure of the memory array region; A second conductive pad structure lies beneath the first conductive pad structure; A control logic region, which lies beneath the second conductive pad structure and includes: Control logic device, including CMOS circuit system; A semiconductive substrate structure, partially embedded in the control logic device; and One or more filled vias comprising a conductive material extending through the semiconductive substrate structure and operatively connected to one or more of the control logic devices; and A passive device, which lies beneath the semiconductive substrate structure of the control logic region and is coupled to the conductive material of the one or more filled vias.

14. The microelectronic device of claim 13, wherein the first conductive pad structure is electrically connected to the second conductive pad structure via a conductive interconnect structure extending vertically between the first conductive pad structure and the second conductive pad structure.

15. The microelectronic device of claim 13, wherein the memory array region further comprises: A conductive wire structure, which is vertically superimposed on the stacked structure; and At least one conductive contact structure extends vertically through the stacked structure and is electrically connected to at least one of the conductive wire structures and at least one of the first conductive pad structures.

16. The microelectronic device of claim 15, further comprising: An additional conductive structure, which covers the conductive wire structure and is electrically connected to at least some of the conductive wire structures; and A bonding pad structure is overlaid on and electrically connected to the additional conductive structure.

17. The microelectronic device according to claim 16, wherein: The additional conductive structure comprises aluminum; and The bonding pad structure comprises copper.

18. The microelectronic device according to any one of claims 13 to 17, further comprising a passive device underlying the control logic device of the control logic region.

19. A method of forming a microelectronic device, comprising: The first microelectronic device structure comprises: Control logic area, the control logic area including control logic devices; and A semiconductive structure is overlaid on the control logic region, the semiconductive structure including a conductive doped source region; forming a second microelectronic device structure, comprising: Substrate structure; and A memory array region, which overlies the substrate structure and includes: A stacked structure comprising vertically alternating conductive and insulating structures; Vertically extending strings of memory cells located within the stacked structure; and A conductive electrode contact extending vertically through the stacked structure; Remove the substrate structure from the second microelectronic device structure; and The remaining portion of the second microelectronic device structure is attached to the first microelectronic device structure such that the control logic region of the first microelectronic device structure lies beneath the memory array region of the second microelectronic device structure.

20. The method of claim 19, wherein: Forming a first microelectronic device structure includes forming the first microelectronic device structure as further including a conductive pad structure covering the control logic device; Forming the second microelectronic device structure includes forming the second microelectronic device structure as further comprising an additional conductive pad structure between the substrate structure and the stacked structure of the memory array region; and Attaching the remaining portion of the second microelectronic device structure to the first microelectronic device structure includes positioning the additional conductive pad structure of the second microelectronic device structure above the conductive pad structure of the first microelectronic device structure.

21. The method of claim 19, wherein forming the second microelectronic device structure comprises: The second microelectronic device structure is further configured to include an interconnect region covering the memory array region and including a bonding pad structure.

22. The method of claim 21, further comprising: The carrier structure is attached to the bonding pad structure before the substrate structure is removed from the second microelectronic device structure; While attaching the carrier structure to the bonding pad structure, the remaining portion of the second microelectronic device structure is positioned above the first microelectronic device structure. and The carrier structure is removed after the remaining portion of the second microelectronic device structure is attached to the first microelectronic device structure.

23. The method according to any one of claims 19 to 22, further comprising: After the remaining portion of the second microelectronic device structure is attached to the first microelectronic device structure, a passive device is formed below the control logic device.

24. The method of claim 19, wherein attaching the remaining portion of the second microelectronic device structure to the first microelectronic device structure comprises: The conductive source electrode contact is positioned above the conductive doped source electrode region of the semiconductive structure and electrically connected to it.

25. The method of claim 24, further comprising: The semiconductive structure is formed to include monocrystalline silicon.

26. The method of claim 24, further comprising: The semiconductive structure is formed over the control logic region using epitaxial growth.

27. An electronic system comprising: Input device; Output device; A processor device operatively coupled to the input device and the output device; and A memory device operatively coupled to the processor device and comprising: The memory array region includes: A stacked structure comprising layers, each including a conductive structure and an insulating structure vertically adjacent to the conductive structure; A string of memory cells, each extending vertically through the stacked structure; A control logic device including a CMOS circuit system embedded in the memory array region, the control logic device being configured to implement a portion of control operations on the vertically extending string of memory cells in the memory array region; and Additional control logic device, comprising an additional CMOS circuit system overlying the memory array region, the additional control logic device having a relatively low operating voltage requirement compared to the control logic device, and configured to implement an additional portion of the control operation of the vertically extending memory cell string of the memory array region; An additional memory array region, which lies beneath the control logic device, the additional memory array region includes: an additional stack structure, which includes stacks of each including an additional conductive structure and an additional insulating structure vertically adjacent to the additional conductive structure; Additional memory cell strings, each extending vertically through the additional stacking structure; and Additionally, a control logic device is located beneath the additional memory array region and configured to perform part of the control operations of the additional memory cell string in the additional memory array region.

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