Reconfigurable field effect transistor based on different-surface contact electrode and preparation method thereof

Abstract

The invention belongs to the technical field of micro-nano semiconductor electronic devices, and discloses a reconfigurable field effect transistor based on different-surface contact electrodes and a preparation method of the reconfigurable field effect transistor. The transistor comprises a SiO2 / Si substrate, an hBN passivation layer, a source / drain Au electrode, a MoTe2 channel, an hBN dielectric layer, a graphene gate and a top gate Au electrode from bottom to top, the source electrode, the drain electrode and the channel form different-surface contact, and an air cavity is formed between the channel and the dielectric layer. The air cavity causes the top gate electric field to generate asymmetric regulation and control on the channel, so that one end of the channel is kept in an eigenstate, and the other end of the channel is regulated and controlled by the gate voltage to form an n-type or p-type region, thereby forming an ni or pi homojunction in the single channel, and realizing reconfigurable carrier transport polarity. The invention further provides a preparation method based on dry transfer, the process is simple, and the preparation method is suitable for a reconfigurable logic circuit and a nano electronic system.

Description

Technical Field

[0001] This application belongs to the field of micro-nano semiconductor electronic device technology, specifically relating to a reconfigurable field-effect transistor based on non-surface contact electrodes and its fabrication method. Background Technology

[0002] In the field of micro / nano semiconductor electronic devices, with the continuous miniaturization of integrated circuit feature sizes, the search for novel channel materials and device architectures that can sustain Moore's Law has become a research focus. Two-dimensional semiconductor materials with atomically thin surfaces, due to their dangling bond-free surfaces, excellent electrostatic gate control capabilities, and compatibility with flexible electronics, are considered important candidate systems for nanoelectronic devices in the post-silicon era. Among them, two-dimensional semiconductors with bipolar conductivity (such as MoTe2 and WSe2) exhibit unique application potential. Their transfer characteristic curves show a "V" or "U" shape, meaning that by adjusting the gate voltage, the same channel can successively exhibit p-type on, off, and n-type on states. This intrinsic gate voltage adjustable polarity provides a physical basis for building reconfigurable logic circuits on a single material platform, potentially simplifying circuit design and increasing functional density.

[0003] However, translating the theoretical potential of two-dimensional bipolar semiconductors into practical reconfigurable devices with superior performance still faces a series of key technological challenges. In traditional top-gate or bottom-gate two-dimensional bipolar field-effect transistors (BFETs), the source and drain electrodes are typically on the same plane as the channel or use the same contact surface. In this configuration, the gate electric field modulates the entire channel region uniformly. When a gate voltage is applied, the entire channel synchronously transitions to n-type or p-type conduction, and the device essentially still exhibits bipolar transport characteristics; that is, under the same gate voltage, both electrons and holes can contribute to the current. This results in a large off-state current, a low on / off ratio, and a subthreshold swing (SS) that is difficult to approach the theoretical limit at room temperature (approximately 60 mV / dec), limiting its application in low-power logic operations.

[0004] Therefore, an innovative device structure and working principle are needed to effectively overcome the above-mentioned technical bottlenecks while retaining the advantages of bipolar semiconductor materials, and to achieve high-performance, reconfigurable unipolar carrier transport. Summary of the Invention

[0005] To address the limitations of existing two-dimensional bipolar semiconductor devices in achieving high-performance, reconfigurable unipolar transport, this application provides a reconfigurable field-effect transistor based on non-surface contact electrodes and its fabrication method. By designing a non-surface contact structure between the source / drain electrodes and the channel layer, an air cavity is formed in a local region of the channel. This non-uniform gate control effect constructs an electrically switchable ni or p homojunction within a single bipolar channel, thereby achieving high-performance, reversible reconfiguration of n-type or p-type unipolar conduction modes within the same device, providing a fundamental device unit for reconfigurable nanoelectronics.

[0006] To achieve the above technical objectives, this application adopts the following technical solution: In one aspect of this application, a reconfigurable field-effect transistor based on anisoplanar contact electrodes is provided, comprising, from bottom to top, a SiO2 / Si substrate, a first two-dimensional hBN layer, a first Au electrode, a two-dimensional MoTe2 layer, a second Au electrode, a second two-dimensional hBN layer, a graphene layer, and a third Au electrode. The first two-dimensional hBN layer serves as a passivation layer to avoid the influence of dangling bonds on the SiO2 / Si substrate surface. The two-dimensional MoTe2 layer serves as a bipolar semiconductor channel; The first Au electrode serves as the source electrode, and the second Au electrode serves as the drain electrode. The first Au electrode and the second Au electrode are in eccentric contact with the upper and lower surfaces of the two-dimensional MoTe2 layer, respectively. The second two-dimensional hBN layer serves as the dielectric layer; The graphene layer and the third Au electrode together constitute the top gate; An air cavity is formed between the two-dimensional MoTe2 layer, the second Au electrode, and the second two-dimensional hBN layer; The air cavity weakens the gate control effect of the top gate on one end of the channel, keeping that end in an intrinsic state, while the other end of the channel forms an n-type or p-type conductive region under the control of the top gate, thereby making the entire channel a ni or pi homojunction and realizing unipolar carrier transport.

[0007] In one embodiment, the thickness of the first two-dimensional hBN layer and the second two-dimensional hBN layer is 10~20 nm.

[0008] In one embodiment, the thickness of the first Au electrode, the second Au electrode, and the third Au electrode is 60-80 nm.

[0009] In one embodiment, the thickness of the two-dimensional MoTe2 layer is 1~5 nm.

[0010] In one embodiment, the thickness of the graphene layer is 1~13 nm.

[0011] In one embodiment, the thickness of the SiO2 layer in the SiO2 / Si substrate is 280 nm.

[0012] In another aspect of this application, a method for fabricating a reconfigurable field-effect transistor based on non-surface contact electrodes is provided, comprising the following steps: The first two-dimensional hBN layer is transferred to the upper surface of the SiO2 / Si substrate using a dry transfer technique as a passivation layer. The first Au electrode is transferred to the upper surface of the first two-dimensional hBN layer as the source electrode by a fixed-point transfer method; A two-dimensional MoTe2 layer is transferred to the upper surface of the first Au electrode and the first two-dimensional hBN layer as a channel; The second Au electrode is transferred to the upper surface of the two-dimensional MoTe2 layer away from the region of the first Au electrode as the drain electrode, so that the drain electrode is in contact with the upper surface of the channel; The second two-dimensional hBN layer is transferred above the channel and drain as a dielectric layer, and an air cavity is formed between the channel, drain and dielectric layer. The graphene layer is transferred to the upper surface of the dielectric layer as a top gate; The third Au electrode is transferred to the upper surface of the graphene layer as the top gate electrode.

[0013] In one embodiment, the first two-dimensional hBN layer and the second two-dimensional hBN layer are made of hBN, the two-dimensional MoTe2 layer is made of MoTe2, the graphene layer is made of graphene, and the first Au electrode, the second Au electrode and the third Au electrode are made of Au. The hBN, MoTe2, and graphene were all prepared by mechanical exfoliation, specifically by using adhesive tape to peel off the corresponding bulk materials, obtaining nanosheets, and then adhering them to a PDMS substrate for later use.

[0014] In one implementation, the dry transfer specifically includes: A SiO2 / Si substrate was fixed on a dry transfer stage, and hBN nanosheets on a PDMS substrate were transferred to the SiO2 / Si substrate as a passivation layer using a micro-focusing system. Au foil on the PDMS substrate was transferred to the passivation layer to serve as the source. MoTe2 nanosheets on a PDMS substrate were transferred to the source and passivation layer to serve as a channel; Another Au foil on the PDMS substrate is transferred to a region on the channel away from the source to serve as the drain. hBN nanosheets on a PDMS substrate were transferred to the channel and drain as a dielectric layer. Graphene nanosheets on a PDMS substrate are transferred above the dielectric layer to serve as a top gate; Another Au foil from the PDMS substrate was transferred onto the graphene nanosheet as the top gate electrode.

[0015] The beneficial effects of this application are as follows: 1) By constructing out-of-plane contacts between the source and drain electrodes and the channel layer, an air cavity structure is formed in a local region of the channel. The presence of this air cavity leads to a significant spatial asymmetry in the control of the channel by the top gate electric field, causing one end of the channel to be controlled by the gate voltage while the other end remains in its intrinsic state. By cleverly utilizing the device's own geometry, rather than external doping, a ni or pi homojunction is dynamically formed within a single homogeneous bipolar semiconductor channel, achieving electrically controlled reconfiguration of carrier transport polarity.

[0016] 2) Employing a homojunction structure, the device exhibits pure unipolar transport characteristics. Experimental results show that this structure effectively suppresses off-state current caused by bipolar transport, significantly improving the device's switching performance. Specifically, the device's on / off ratio exceeds 10. 5 At the same time, a subthreshold swing as low as 75 mV / dec was achieved, which is close to the theoretical limit at room temperature, indicating that the device has excellent gate control efficiency and low power consumption potential.

[0017] 3) The fabrication process of the reconfigurable field-effect transistor in this application is highly compatible with existing dry transfer processes for van der Waals materials, without the need to introduce complex local doping or additional patterned gates. The air cavity, as the core element for realizing the function, is formed by the natural introduction of the electrode thickness, avoiding the complex process of deliberately creating cavities and improving the repeatability and reliability of the fabrication. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of the MoTe2 reconfigurable field-effect transistor based on non-surface contact electrodes in Embodiment 1 of this application; Figure 2 This is an optical microscope image of the device sample from Embodiment 1 of this application; Figure 3 This is a schematic diagram illustrating the energy band structure of the device in Embodiment 1 of this application, where D: drain, S: source, and G: gate. Figure 4 The device in Embodiment 1 of this application has different source and drain voltages. V DS The following is a transfer curve, i.e., source-drain current. I DS With gate voltage V G Relationship curve; a is V DS <0; b is V DS >0; Figure 5 This is a subthreshold swing (SS) curve calculated from the transfer curve of the device in Embodiment 1 of this application; a is... V DS <0; b is V DS >0; Figure 6 The device in Embodiment 2 of this application is an inverter (i.e., a NOT gate) formed by back-to-back connections, which is used as an application demonstration of the device; Figure 7 Example 2 of this application demonstrates the application of the NOT gate at different driving voltages. V DD The input-output performance curves (a and b) and the calculated gain curves (c and d) are shown below. Figure 8 A schematic diagram of the structure of a MoTe2 bottom-gate field-effect transistor based on anisoplanar contact electrodes is shown as a comparative example of this application. Figure 9 This is a graph showing the transfer curves of the comparative device under different source-drain voltages; a is... V DS <0; b is V DS >0; In the figure: 1-SiO2 / Si substrate, 2-first two-dimensional hBN layer, 3-two-dimensional MoTe2 layer, 4-first Au electrode, 5-second Au electrode, 6-second two-dimensional hBN layer, 7-graphene layer, 8-third Au electrode, 9-air cavity. Detailed Implementation

[0019] The technical solution of this application will be clearly and completely described below with reference to specific embodiments. However, those skilled in the art will understand that the embodiments described below are only some embodiments of this application, not all embodiments, and are only used to illustrate this application, and should not be regarded as limiting the scope of this application. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] To overcome the challenge of achieving dynamic, high-performance unipolar transport reconfiguration in existing two-dimensional bipolar semiconductor channels, this application utilizes the intrinsic geometry of the device structure. By designing the source and drain electrodes to form non-planar contacts on the upper and lower surfaces of the channel layer, and by naturally introducing an air gap at the channel-electrode-dielectric layer interface using the electrode thickness itself, this air gap disrupts the uniform control of the top gate electric field on the channel. This results in one end of the channel maintaining its intrinsic state due to a shielding effect, while the other end is effectively controlled by the gate voltage, allowing it to switch between n-type and p-type. This non-uniform gate control effect makes the entire homogeneous channel electrically behave as a ni or pi homojunction that dynamically changes with the gate voltage. This transforms the bipolar transport of the material into electrically controllable, high-performance unipolar transport, achieving dynamic reconfiguration of the channel conductivity type in a single device.

[0021] In one specific embodiment, this application discloses a reconfigurable field-effect transistor based on non-surface contact electrodes, see [link to relevant documentation]. Figure 1 As shown, it has the following stacked structure: The reconfigurable field-effect transistor uses a SiO2 / Si substrate 1 as the supporting substrate. A first two-dimensional hBN layer 2 is covered on the upper surface of the substrate as a passivation layer to isolate the influence of dangling bonds on the substrate surface on the channel electrical performance.

[0022] A first Au electrode 4 is disposed in a local area on the upper surface of the first two-dimensional hBN layer 2, serving as the source electrode of the device.

[0023] A two-dimensional MoTe2 layer 3, covering a portion of the upper surface of the first Au electrode 4 and the adjacent upper surface of the first two-dimensional hBN layer 2, serves as a bipolar semiconductor channel. An ohmic contact or a Schottky contact is formed between the first Au electrode 4 and the lower surface of the two-dimensional MoTe2 layer 3.

[0024] The second Au electrode 5, serving as the drain of the device, is disposed at the end of the upper surface of the two-dimensional MoTe2 layer 3 away from the source region, and forms an ohmic or Schottky contact with the upper surface of the channel layer. Thus, the source and drain are in contact with the lower and upper surfaces of the channel layer, respectively, forming a spatially non-planar contact configuration.

[0025] The second two-dimensional hBN layer 6 serves as the gate dielectric layer, covering the two-dimensional MoTe2 layer 3, the second Au electrode 5, and the partially exposed first two-dimensional hBN layer 2. Since the second Au electrode 5 has a certain thickness, a void structure, i.e., an air cavity 10, is formed between the two-dimensional MoTe2 layer 3 and the second two-dimensional hBN layer 6, corresponding to the end edge region of the second Au electrode 5.

[0026] The graphene layer 7 serves as the conductive channel for the top gate and is disposed on the entire upper surface of the second two-dimensional hBN layer 6. The third Au electrode 8 serves as the electrode for the top gate and is disposed in a local area on the upper surface of the graphene layer 7, forming an electrical connection with the graphene layer to jointly constitute the top gate structure of the device.

[0027] The physical presence of the air cavity 10 significantly weakens the ability of the top gate structure to control the channel region (i.e., the end near the drain) located below the air cavity 10 through the gate electric field applied by the dielectric layer. The Fermi level of the channel in this region is difficult to adjust by the gate voltage, and thus basically maintains its intrinsic (i-type) state. At the same time, the top gate electric field maintains effective control over the channel region (i.e., the end near the source) that is far from the air cavity and where the dielectric layer and channel layer are tightly attached. By applying different gate voltages, the channel in this region can be controlled to be n-type or p-type conductive.

[0028] Based on the aforementioned non-uniform gate control effect, within the same two-dimensional MoTe2 channel, along the source-to-drain direction, a homojunction of either an n-type region and an intrinsic region (ni-type homojunction) or a p-type region and an intrinsic region (pi-type homojunction) is dynamically formed. This homojunction structure determines the device's conduction path and carrier type, enabling the entire device to exhibit pure and reconfigurable unipolar (n-type or p-type) carrier transport characteristics, thus realizing the function of dynamically switching the channel conduction polarity through the gate voltage.

[0029] In some embodiments, the thickness of the first two-dimensional hBN layer 2 and the second two-dimensional hBN layer 6 is 10~20 nm. Specifically, it can be 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, or 20 nm.

[0030] In some embodiments, the thickness of the first Au electrode 4, the second Au electrode 5, and the third Au electrode 8 is 60-80 nm. Specifically, it can be 60 nm, 62 nm, 64 nm, 66 nm, 68 nm, 70 nm, 72 nm, 74 nm, 76 nm, 78 nm, or 80 nm.

[0031] In some embodiments, the thickness of the two-dimensional MoTe2 layer 3 is 1~5 nm. Specifically, it can be 1 nm, 2 nm, 3 nm, 4 nm, or 5 nm.

[0032] In some embodiments, the thickness of the graphene layer 7 is 1 to 13 nm. Specifically, it can be 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, or 13 nm.

[0033] In some embodiments, the thickness of the SiO2 layer in the SiO2 / Si substrate 1 is 280 nm. Specifically, the SiO2 / Si substrate 1 is a composite substrate with a silicon wafer as the substrate and a 280 nm silicon dioxide insulating layer covering the surface.

[0034] In another specific embodiment, a method for fabricating the reconfigurable field-effect transistor based on non-surface contact electrodes is provided, comprising the following steps: A first two-dimensional hBN layer, serving as a passivation layer, is attached to the upper surface of a SiO2 / Si substrate using a dry transfer technique. A first Au electrode is placed at a designated position on the upper surface of the passivation layer using a point-to-point transfer method to form the source. A two-dimensional MoTe2 layer is transferred to the upper surface of the source and the adjacent passivation layer region to form a semiconductor channel. A second Au electrode is transferred to a region on the upper surface of the two-dimensional MoTe2 layer away from the source to form the drain, and contacts the upper surface of the channel. A second two-dimensional hBN layer, serving as a dielectric layer, is transferred to cover the two-dimensional MoTe2 layer, the second Au electrode, and part of the exposed underlying structure; during this process, due to the thickness of the second Au electrode, an air cavity is naturally formed between the two-dimensional MoTe2 layer, the end of the second Au electrode, and the second two-dimensional hBN layer. A graphene layer, serving as a gate conductive layer, is transferred to the upper surface of the second two-dimensional hBN layer, its area covering the underlying channel region. A third Au electrode is transferred to a designated position on the upper surface of the graphene layer to form the gate electrode, thus completing the device fabrication.

[0035] The passivation layer and dielectric layer are made of hexagonal boron nitride (hBN), the two-dimensional semiconductor channel is made of molybdenum ditelluride (MoTe2), the gate conductive layer is made of graphene, and the first, second and third Au electrodes are all made of gold (Au).

[0036] The hBN, MoTe2, and graphene two-dimensional materials were all prepared by mechanical exfoliation. Specifically, the corresponding bulk crystalline materials were repeatedly exfoliated using adhesive tape to obtain nanosheets, which were then adhered to a polydimethylsiloxane (PDMS) elastic substrate.

[0037] The specific operation process of the dry transfer is as follows: The SiO2 / Si substrate is fixed on a transfer stage, and the hBN nanosheets on the PDMS substrate are positioned using a micro-optical system. The PDMS substrate is moved and lowered to make it contact and adhere to the target substrate. Then, the PDMS substrate is slowly raised to release the hBN nanosheets onto the SiO2 / Si substrate, forming a passivation layer.

[0038] By positioning the passivation layer using a microscopic system, the gold foil on the PDMS substrate is transferred to a predetermined position on its surface to form the first Au electrode (source electrode).

[0039] The source and passivation layer regions that have been transferred are located, and the MoTe2 nanosheets on the PDMS substrate are moved to their top. After contact bonding and release, they are transferred to the surface of the source and passivation layer to form a channel.

[0040] Locate the end region of the channel away from the source electrode, and transfer another gold foil from the PDMS substrate to the upper surface of that region to form a second Au electrode (drain electrode).

[0041] Position the formed channel and drain, move the hBN nanosheet on the PDMS substrate to its direct top, and after bonding and releasing, make it cover the channel, drain and surrounding area to form a dielectric layer; in this step, due to the thickness of the drain, an air cavity is formed between the dielectric layer, the channel and the edge of the drain.

[0042] The dielectric layer is positioned by transferring graphene nanosheets from the PDMS substrate to its entire upper surface to form a gate conductive layer.

[0043] The graphene layer is positioned, and the gold foil on the PDMS substrate is transferred to a predetermined position on its surface to form a third Au electrode (gate electrode).

[0044] Example 1 See Figure 1 As shown, a MoTe2 reconfigurable field-effect transistor based on non-surface contact electrodes is presented. This device has a multi-layer stacked structure, with the layers from bottom to top as follows: A SiO2 / Si substrate 1 serves as the mechanical support and back gate substrate for the device. A first two-dimensional hBN layer 2 is disposed on the upper surface of this substrate, acting as a passivation layer to isolate the active region above from interference by dangling bonds on the substrate surface. A first Au electrode 4 is disposed in a portion of the upper surface of the first two-dimensional hBN layer 2, serving as the source of the device. A two-dimensional MoTe2 layer 3 serves as a bipolar semiconductor channel, covering a portion of the upper surface of the first Au electrode 4 and the adjacent upper surface of the first two-dimensional hBN layer 2, with the source forming an electrical contact with the lower surface of this channel layer. A second Au electrode 5 serves as the drain of the device, disposed at one end of the upper surface of the two-dimensional MoTe2 layer 3, with the drain forming an electrical contact with the upper surface of the channel layer. A second two-dimensional hBN layer 6 serves as a gate dielectric layer, covering the two-dimensional MoTe2 layer 3, the second Au electrode 5, and the partially exposed lower layer structure, with an air cavity 10 formed between the two-dimensional MoTe2 layer 3 and the second two-dimensional hBN layer 6, corresponding to the edge region of the drain. The graphene layer 7 serves as the conductive channel for the top gate and is disposed on the entire upper surface of the second two-dimensional hBN layer 6. The third Au electrode 8 serves as the electrode for the top gate and is disposed in a local area on the upper surface of the graphene layer 7. Together, they constitute the top gate structure of the device.

[0045] In this embodiment, the fabrication method of the MoTe2 reconfigurable field-effect transistor based on non-surface contact electrodes specifically includes the following steps: S1. Substrate Cleaning and Preparation Commercially available SiO2 / Si wafers were diced into substrates measuring 1 cm × 1 cm. These substrates were then sequentially placed in acetone, isopropanol, ethanol, and deionized water, and ultrasonically cleaned for 15 minutes at each stage to remove surface organic matter and particulate contamination. After cleaning, the surface was dried with high-purity nitrogen gas to obtain a clean SiO2 / Si substrate 1 for later use.

[0046] S2. Fabrication of Two-Dimensional Materials and Electrodes Two-dimensional material nanosheets were prepared using a mechanical exfoliation method. Bulk crystals of hBN, MoTe2, and graphene were repeatedly torn and peeled off using transparent tape until nanosheets of suitable thickness were obtained. The exfoliated hBN, MoTe2, and graphene nanosheets were then adhered to a polydimethylsiloxane (PDMS) elastic substrate as a material source for transfer.

[0047] Meanwhile, gold foil prepared by thermal evaporation was also attached to another PDMS substrate as a backup Au electrode material.

[0048] S3. Dry transfer and device integration The clean SiO2 / Si substrate 1 prepared in step S1 is fixed on the heated stage of the micromanipulation dry transfer stage.

[0049] With the aid of the focusing and alignment system of an optical microscope, the materials of each layer are transferred sequentially from the corresponding PDMS substrates: a) Transfer passivation layer: Position the hBN nanosheets on the PDMS substrate, align them with the surface of the SiO2 / Si substrate 1 using a moving stage, and then slowly lift the PDMS substrate to release the hBN nanosheets onto the SiO2 / Si substrate 1, forming the first two-dimensional hBN layer 2, i.e., the passivation layer.

[0050] b) Source transfer: Position the passivation layer surface and transfer the gold foil on the PDMS substrate to a predetermined position thereon to form the first Au electrode 4, i.e., the source.

[0051] c) Transfer channel: Locate the transferred source and adjacent passivation layer regions, transfer the MoTe2 nanosheets on the PDMS substrate and cover them on the region to form a two-dimensional MoTe2 layer 3, i.e., the semiconductor channel.

[0052] d) Drain transfer: Position one end of the channel layer away from the source, and transfer another gold foil on the PDMS substrate to the upper surface of that region to form the second Au electrode 5, i.e., the drain.

[0053] e) Transferring the dielectric layer and forming an air cavity: Positioning the integrated channel and drain structure, the hBN nanosheets on the PDMS substrate are transferred and covered over the entire structure to form a second two-dimensional hBN layer 6, i.e., the dielectric layer. During this process, due to the drain thickness, an air cavity 10 is naturally formed between the channel, drain, and dielectric layer.

[0054] f) Transfer gate conductive layer: Position the dielectric layer surface and transfer the graphene nanosheets on the PDMS substrate to its entire upper surface to form graphene layer 7.

[0055] g) Transfer gate electrode: Position the surface of the graphene layer 7 and transfer the gold foil on the PDMS substrate to a predetermined position thereon to form the third Au electrode 8, i.e., the top gate electrode.

[0056] The SiO2 / Si layer in the SiO2 / Si substrate has a thickness of 280 nm; the first two-dimensional hBN layer (passivation layer) has a thickness of 14 nm; the second two-dimensional hBN layer (dielectric layer) has a thickness of 11 nm; the two-dimensional MoTe2 layer has a thickness of 5 nm; the graphene layer has a thickness of 12 nm; and each Au electrode has a thickness of 70 nm.

[0057] Figure 2This is an optical micrograph of the device fabricated in Example 1. In the image, the two Au structures covering the MoTe2 channel are the source and drain electrodes, respectively; the Au structure covering the graphene layer is the top gate electrode. The channel region between the source and drain electrodes is approximately 16 μm long and 11 μm wide. It can be observed that the source and drain electrodes form contacts with the lower and upper surfaces of the channel layer, respectively.

[0058] Figure 3 The diagram illustrates the device's operating principle. An air cavity forms between the drain-end channel and the dielectric layer, preventing the top gate from modulating the Fermi level of this channel, and thus preventing band bending. The source-end channel adheres well to the dielectric layer, allowing effective top gate modulation of the Fermi level, and the band bending is also readily achieved. When the gate voltage... V G When the voltage is greater than 0, the channel at one end of the source is n-type, and the entire device channel forms an ni homojunction. Therefore, the source-drain voltage... V DS At voltages >0, source electrons tunnel through the narrow Schottky junction at the source to conduct electricity, under source-drain voltage conditions. V DS When the gate voltage is less than 0, drain electrons cannot penetrate the wide Schottky barrier at the drain and therefore cannot conduct electricity; V G When the voltage is less than 0, the channel at one end of the source is p-type, and the entire device channel forms a pi homojunction. Therefore, the source-drain voltage... V DS When the source hole is less than 0, it will tunnel through the narrow Schottky junction at the source to conduct electricity. V DS At a voltage level of >0, holes at the drain cannot penetrate the wide Schottky barrier at the drain and therefore cannot conduct electricity.

[0059] Figure 4 (a) shows the device in Example 1. V DS The transfer curve at <0 shows a very obvious p-type unipolar electrical transport characteristic. V DS When the switching ratio exceeds 10 at -1 V, the on / off ratio is greater than 10. 5 ; Figure 4 (b) shows the device in Example 1. V DS The transfer curve at >0 exhibits a very clear n-type unipolar electrical transport characteristic. V DS The switching ratio also exceeds 10 at 1 V. 5 .

[0060] Figure 5 Based on Figure 4The subthreshold swing calculated from the data shows that the larger the source-drain voltage, the larger the minimum subthreshold swing. Specifically, the minimum SS for p-type unipolar is 75 mV / dec, and the minimum SS for n-type unipolar is 125 mV / dec.

[0061] Example 2 Figure 6 An example of an inverter (NOT gate) consisting of two MoTe2 reconfigurable field-effect transistors connected back-to-back based on opposite contact electrodes is shown. The specific structure of the device is as follows: The inverter is constructed on the same SiO2 / Si substrate 1. Two independent top-gate transistor units (T1 and T2) are fabricated on the substrate, sharing the same second Au electrode as the drain (i.e., the output terminal OUT), and each has its own first Au electrode 4 as the source. The structure of each transistor unit is consistent with the single-transistor structure described in Example 1, and from bottom to top, it includes: a first two-dimensional hBN layer 2 as a passivation layer, a first Au electrode 4 as the source, a two-dimensional MoTe2 layer 3 as the channel, a second Au electrode 5 as the drain, a second two-dimensional hBN layer 6 as the dielectric layer, a graphene layer 7 as the gate conductive channel, and a third Au electrode 8 as the gate electrode. The channels of the two transistors are composed of two independent MoTe2 nanosheets. The top gate electrode serves as the input terminal (IN) of the entire inverter. The source electrodes of the two transistors are connected to different potentials: one source is grounded (GND), and the other source is connected to the driving voltage (…). V DD The drain shared by the two transistors serves as the output (OUT) of the entire inverter.

[0062] When a specific gate voltage is applied at the input terminal (IN), due to the identical channel characteristics and symmetrical structure of the two transistors, at a fixed drive voltage ( V DD Under certain polarities, the two transistors will operate in complementary conduction states: one transistor is regulated to n-type conduction, and the other is regulated to p-type conduction, or vice versa. This complementary switching characteristic enables the circuit to perform standard NOT gate (inverter) logic functions, that is, to invert the input voltage and the output voltage.

[0063] Figure 7 In the diagram (a, b), the devices in Example 2 are shown at different driving voltages. V DD The output of the NOT gate V OUT characteristic: V DD When the input is low, V OUT Output high level; V DDWhen the input is high, V OUT Output low level. Figure 9 (c, d) shows the gain calculated from the output characteristic curve of the device in Example 2. V DD When the voltage is 0.3, 0.5, 0.7, 1.0, 2.0, and 3.0 V, the corresponding maximum gains are 1.5, 2, 2.5, 3.9, 9.5, and 11.5, respectively. This example verifies the feasibility of the device in non-logic gate operations and also illustrates the great application potential of the device in other logic gate circuits such as AND gates, OR gates, and XOR gates.

[0064] Comparative Example See Figure 8 As shown, the MoTe2 bottom gate effect transistor based on the non-surface contact electrode serves as a comparative example of Example 1. The structure is the same as that of Example 1, except that the graphene gate and the hBN dielectric layer are placed at the bottom of the entire channel and the source and drain electrodes, and the hBN passivation layer is not required.

[0065] Figure 9 (a) shows the device in V DS The transfer curve at <0 shows a very obvious p-type unipolar electrical transport characteristic. V DS When the switching ratio exceeds 10 at -1 V, the on / off ratio is greater than 10. 3 ; Figure 7 (b) shows the device in V DS The transfer curve at >0 exhibits a very clear n-type unipolar electrical transport characteristic. V DS The switching ratio also exceeds 10 at 1 V. 2 Compared to the top-gate device in Example 1, the on / off ratios are reduced, but significant reconfigurability is still maintained. Calculations show that a smaller source-drain voltage results in a smaller minimum subthreshold swing, with a minimum SS of 115 mV / dec for p-type unipolar and 148 mV / dec for n-type unipolar. The minimum subthreshold swing is also higher than that of the top-gate device in Example 1. Therefore, regardless of whether the device is a top-gate or bottom-gate structure, as long as the source and drain electrodes are in non-surface contact, reconfigurable control of carrier transport can be achieved using the air cavity; however, the minimum subthreshold swing of the top-gate structure device is lower.

[0066] Although the embodiments of this application have been described above in conjunction with the accompanying drawings, this application is not limited to the specific embodiments and application fields described above. The specific embodiments described above are merely illustrative and instructive, not restrictive. Those skilled in the art can make many other forms based on the guidance of this specification and without departing from the scope of protection of the claims of this application, and these are all within the scope of protection of this application.

Claims

1. A reconfigurable field-effect transistor based on non-surface contact electrodes, characterized in that, From bottom to top, it includes a SiO2 / Si substrate, a first two-dimensional hBN layer, a first Au electrode, a two-dimensional MoTe2 layer, a second Au electrode, a second two-dimensional hBN layer, a graphene layer, and a third Au electrode; The first two-dimensional hBN layer serves as a passivation layer to avoid the influence of dangling bonds on the SiO2 / Si substrate surface. The two-dimensional MoTe2 layer serves as a bipolar semiconductor channel; The first Au electrode serves as the source electrode, and the second Au electrode serves as the drain electrode. The first Au electrode and the second Au electrode are in eccentric contact with the upper and lower surfaces of the two-dimensional MoTe2 layer, respectively. The second two-dimensional hBN layer serves as the dielectric layer; The graphene layer and the third Au electrode together constitute the top gate; An air cavity is formed between the two-dimensional MoTe2 layer, the second Au electrode, and the second two-dimensional hBN layer; The air cavity weakens the gate control effect of the top gate on one end of the channel, keeping that end in an intrinsic state, while the other end of the channel forms an n-type or p-type conductive region under the control of the top gate, thereby making the entire channel a ni or pi homojunction and realizing unipolar carrier transport.

2. The reconfigurable field-effect transistor based on non-planar contact electrodes according to claim 1, characterized in that, The thickness of the first two-dimensional hBN layer and the second two-dimensional hBN layer is 10~20 nm.

3. A reconfigurable field-effect transistor based on non-planar contact electrodes according to claim 1, characterized in that, The thickness of the first Au electrode, the second Au electrode, and the third Au electrode is 60~80 nm.

4. A reconfigurable field-effect transistor based on non-planar contact electrodes according to claim 1, characterized in that, The thickness of the two-dimensional MoTe2 layer is 1~5 nm.

5. A reconfigurable field-effect transistor based on non-planar contact electrodes according to claim 1, characterized in that, The thickness of the graphene layer is 1~13 nm.

6. A reconfigurable field-effect transistor based on non-planar contact electrodes according to claim 1, characterized in that, The thickness of the SiO2 layer in the SiO2 / Si substrate is 280 nm.

7. The method for fabricating a reconfigurable field-effect transistor based on non-surface contact electrodes according to any one of claims 1 to 6, characterized in that, Includes the following steps: The first two-dimensional hBN layer is transferred to the upper surface of the SiO2 / Si substrate by dry transfer as a passivation layer; The first Au electrode is transferred to the upper surface of the first two-dimensional hBN layer as the source electrode by a fixed-point transfer method; A two-dimensional MoTe2 layer is transferred to the upper surface of the first Au electrode and the first two-dimensional hBN layer as a channel; The second Au electrode is transferred to the upper surface of the two-dimensional MoTe2 layer away from the region of the first Au electrode as the drain electrode, so that the drain electrode is in contact with the upper surface of the channel; The second two-dimensional hBN layer is transferred above the channel and drain as a dielectric layer, and an air cavity is formed between the channel, drain and dielectric layer. The graphene layer is transferred to the upper surface of the dielectric layer as a top gate; The third Au electrode is transferred to the upper surface of the graphene layer as the top gate electrode.

8. The preparation method according to claim 7, characterized in that, The dry transfer includes: A SiO2 / Si substrate was fixed on a dry transfer stage, and hBN nanosheets on a PDMS substrate were transferred to the SiO2 / Si substrate as a passivation layer using a micro-focusing system. Au foil on the PDMS substrate was transferred to the passivation layer to serve as the source. MoTe2 nanosheets on a PDMS substrate were transferred to the source and passivation layer to serve as a channel; Another Au foil on the PDMS substrate is transferred to a region on the channel away from the source to serve as the drain. hBN nanosheets on a PDMS substrate were transferred to the channel and drain as a dielectric layer. Graphene nanosheets on a PDMS substrate are transferred above the dielectric layer to serve as a top gate; Another Au foil from the PDMS substrate was transferred onto the graphene nanosheet as the top gate electrode.

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