Semiconductor device and method for producing semiconductor device

Abstract

Provided is a semiconductor device including a transistor that achieves both high field effect mobility and high reliability. This semiconductor device includes a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer has a region overlapping the gate electrode with the gate insulating layer interposed therebetween. The semiconductor layer includes a first metal oxide layer, a second metal oxide layer on the first metal oxide layer, and a third metal oxide layer on the second metal oxide layer. The first metal oxide layer, the second metal oxide layer, and the third metal oxide layer each contain indium oxide. The second metal oxide layer has a region having a higher hydrogen concentration than each of the first metal oxide layer and the third metal oxide layer.

Description

Semiconductor device and method for manufacturing a semiconductor device.

[0001] One aspect of the present invention relates to a semiconductor device, a display device, and a method for manufacturing the same. Another aspect of the present invention relates to a transistor and a method for manufacturing the same. Another aspect of the present invention relates to a semiconductor device having a transistor and a display device having a transistor.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), methods for driving them, or methods for manufacturing them.

[0003] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), devices having such circuits, etc. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and may each have a semiconductor device.

[0004] In recent years, there has been a growing demand for high-resolution display devices. Devices requiring high-resolution displays include those for virtual reality (VR), augmented reality (AR), substitute reality (SR), and mixed reality (MR), all of which are being actively developed.

[0005] Examples of display devices include display devices having liquid crystal elements and display devices having light-emitting elements (also called light-emitting devices). Examples of light-emitting elements include organic EL (Electroluminescence) elements and light-emitting diodes (LEDs). Patent Document 1 discloses a high-definition display device using organic EL elements.

[0006] Technology related to transistors using semiconductor thin films is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors are also attracting attention as other materials.

[0007] Examples of oxide semiconductors applicable to transistors include indium oxide and indium gallium zinc oxide. Non-patent document 1 discloses a thin-film transistor using polycrystalline indium hydrogenate formed by low-temperature solid-phase crystallization.

[0008] International Publication No. 2016 / 038508

[0009] Y. Magari et al., “High-mobility hydrogenerated polycrystalline In2O3 (In2O3:H)thin-film transmitters”, Nature Communications, 13, 1078 (2022). Takashi Koida, “High-mobility transparent conductive film”, National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Presentation Meeting 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0010] One aspect of the present invention aims to provide a semiconductor device having a transistor with high field-effect mobility. Alternatively, it aims to provide a semiconductor device having a transistor with high on-current. Alternatively, it aims to provide a semiconductor device having a transistor of a very small size. Alternatively, it aims to provide a semiconductor device having a transistor with a short channel length. Alternatively, it aims to provide a semiconductor device having a transistor with good electrical characteristics. Alternatively, it aims to provide a semiconductor device having a highly reliable transistor. Alternatively, it aims to provide a semiconductor device that operates at high speed. Alternatively, it aims to provide a semiconductor device with a small footprint. Alternatively, it aims to provide a semiconductor device with low wiring resistance. Alternatively, it aims to provide a semiconductor device or display device with low power consumption. Alternatively, it aims to provide a highly reliable display device. Alternatively, it aims to provide a high-definition display device. Alternatively, it aims to provide a method for manufacturing the aforementioned transistor, semiconductor device, or display device. Alternatively, it aims to provide a method for manufacturing a highly productive transistor, semiconductor device, or display device. Alternatively, it aims to provide a novel semiconductor layer, transistor, semiconductor device, display device, or method for manufacturing the same.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims.

[0012] One aspect of the present invention is a semiconductor device having a semiconductor layer. The semiconductor layer includes a first metal oxide layer, a second metal oxide layer on the first metal oxide layer, and a third metal oxide layer on the second metal oxide layer. The first metal oxide layer, the second metal oxide layer, and the third metal oxide layer each contain indium oxide. The second metal oxide layer has a region with a higher hydrogen concentration than the first metal oxide layer and the third metal oxide layer, respectively.

[0013] In the aforementioned semiconductor device, the second metal oxide layer has a hydrogen concentration of 5 × 10 ２０ atoms / cm ３ The above 5 x 10 ２１ atoms / cm ３ Preferably, the following regions are present: The first metal oxide layer and the third metal oxide layer each preferably have a region in which the hydrogen concentration is 1 / 100 or more and 1 / 8 or less of the hydrogen concentration in the second metal oxide layer.

[0014] One aspect of the present invention is a semiconductor device having a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer has a region that overlaps with the gate electrode via the gate insulating layer. The semiconductor layer has a first metal oxide layer, a second metal oxide layer on the first metal oxide layer, and a third metal oxide layer on the second metal oxide layer. The first metal oxide layer, the second metal oxide layer, and the third metal oxide layer each have indium oxide. The second metal oxide layer has a region with a higher hydrogen concentration than the first metal oxide layer and the third metal oxide layer, respectively.

[0015] In the aforementioned semiconductor device, the second metal oxide layer has a hydrogen concentration of 5 × 10 ２０ atoms / cm ３ The above 5 x 10 ２１ atoms / cm ３ Preferably, the following regions are present: The first metal oxide layer and the third metal oxide layer each preferably have a region in which the hydrogen concentration is 1 / 100 or more and 1 / 8 or less of the hydrogen concentration in the second metal oxide layer.

[0016] In the semiconductor device described above, it is preferable that the second metal oxide layer has a region with a lower film density than the first metal oxide layer and the third metal oxide layer, respectively.

[0017] In the aforementioned semiconductor device, it is preferable that the semiconductor layer has crystal grains. It is preferable that the first metal oxide layer, the second metal oxide layer, and the third metal oxide layer have crystal grains.

[0018] In the semiconductor device described above, the thickness of the second metal oxide layer is preferably greater than the thicknesses of the first metal oxide layer and the third metal oxide layer, respectively.

[0019] In the semiconductor device described above, the thickness of the second metal oxide layer is preferably 1 nm or more and 30 nm or less. The thicknesses of the first metal oxide layer and the third metal oxide layer are preferably 0.5 nm or more and 10 nm or less, respectively.

[0020] One aspect of the present invention is a method for manufacturing a semiconductor device having a semiconductor layer, wherein as the semiconductor layer, a first metal oxide layer, a second metal oxide layer, and a third metal oxide layer are formed in this order using a sputtering method. The first metal oxide layer, the second metal oxide layer, and the third metal oxide layer each contain indium oxide. The power density in the film formation of the first metal oxide layer and the third metal oxide layer is higher than the power density in the film formation of the second metal oxide layer, respectively. The pressure in the film formation of the first metal oxide layer and the third metal oxide layer is lower than the pressure in the film formation of the second metal oxide layer, respectively. This is a method for manufacturing a semiconductor device.

[0021] One aspect of the present invention is a method for manufacturing a semiconductor device, wherein a first metal oxide layer, a second metal oxide layer, and a third metal oxide layer are formed in this order using a sputtering method. A gate insulating layer is formed on the third metal oxide layer, and a gate electrode is formed on the gate insulating layer. The first metal oxide layer, the second metal oxide layer, and the third metal oxide layer each contain indium oxide. The power density in the film formation of the first metal oxide layer and the third metal oxide layer is higher than the power density in the film formation of the second metal oxide layer, respectively. The pressure in the film formation of the first metal oxide layer and the third metal oxide layer is lower than the pressure in the film formation of the second metal oxide layer, respectively. This is a method for manufacturing a semiconductor device.

[0022] In the method for manufacturing the semiconductor device described above, the power density in the film formation of the first metal oxide layer and the third metal oxide layer is preferably 0.3 W / cm ２ or more and 2 W / cm ２ or less, respectively. The power density in the film formation of the second metal oxide layer is 0.1 W / cm ２1W / cm or more ２ The following is preferable:

[0023] In the aforementioned method for manufacturing a semiconductor device, the pressure during film formation of the first metal oxide layer and the third metal oxide layer is preferably 0.1 Pa or more and 0.8 Pa or less. The pressure during film formation of the second metal oxide layer is preferably 0.2 Pa or more and 1 Pa or less.

[0024] In the aforementioned method for manufacturing the semiconductor device, it is preferable to use the same sputtering target for depositing the first metal oxide layer, the second metal oxide layer, and the third metal oxide layer.

[0025] In the aforementioned method for manufacturing a semiconductor device, it is preferable to use oxygen gas, hydrogen gas, and argon gas for forming the first metal oxide layer, the second metal oxide layer, and the third metal oxide layer, respectively.

[0026] In the aforementioned method for manufacturing a semiconductor device, it is preferable to improve the crystallinity of the first, second, and third metal oxide layers by performing a heat treatment after forming the first, second, and third metal oxide layers. The heat treatment temperature is preferably 400°C to 670°C.

[0027] In the aforementioned method for manufacturing a semiconductor device, it is preferable that the thickness of the second metal oxide layer is greater than the thickness of the first metal oxide layer and the thickness of the third metal oxide layer.

[0028] In the aforementioned method for manufacturing a semiconductor device, the thickness of the second metal oxide layer is preferably 1 nm or more and 30 nm or less. The thicknesses of the first metal oxide layer and the third metal oxide layer are preferably 0.5 nm or more and 10 nm or less, respectively.

[0029] One aspect of the present invention can provide a semiconductor device having a transistor with high field-effect mobility. Or, a semiconductor device having a transistor with a large on-current. Or, a semiconductor device having a transistor of a very small size. Or, a semiconductor device having a transistor with a short channel length. Or, a semiconductor device having a transistor with good electrical characteristics. Or, a semiconductor device having a highly reliable transistor. Or, a semiconductor device that operates at high speed. Or, a semiconductor device with a small footprint. Or, a semiconductor device with low wiring resistance. Or, a semiconductor device or display device with low power consumption. Or, a highly reliable display device. Or, a high-definition display device. Or, a method for manufacturing the aforementioned transistor, semiconductor device, or display device. Or, a highly productive method for manufacturing a transistor, semiconductor device, or display device. Or, a novel semiconductor layer, transistor, semiconductor device, display device, or method for manufacturing the same.

[0030] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims.

[0031] Figures 1A, 1B, 1C, 1D, 1E, and 1F are cross-sectional views showing an example of a semiconductor device. Figure 2A is a top view showing an example of a semiconductor device. Figures 2B and 2C are cross-sectional views showing an example of a semiconductor device. Figure 3 is a cross-sectional view showing an example of a semiconductor device. Figure 4A is a top view showing an example of a semiconductor device. Figures 4B and 4C are cross-sectional views showing an example of a semiconductor device. Figures 5A and 5B are cross-sectional views showing an example of a semiconductor device. Figures 6A, 6B, and 6C are cross-sectional views showing an example of a semiconductor device. Figures 7A and 7B are cross-sectional views showing an example of a semiconductor device. Figures 8A and 8B are cross-sectional views showing an example of a semiconductor device. Figures 9A and 9B are cross-sectional views showing an example of a semiconductor device. Figure 10A is a top view showing an example of a semiconductor device. Figure 10B is a cross-sectional view showing an example of a semiconductor device. Figure 11A is a top view showing an example of a semiconductor device. Figures 11B and 11C are cross-sectional views showing an example of a semiconductor device. Figure 12A is a top view showing an example of a semiconductor device. Figures 12B and 12C are cross-sectional views showing an example of a semiconductor device. Figures 13A and 13B are cross-sectional views showing an example of a semiconductor device. Figure 14A is a top view showing an example of a semiconductor device. Figures 14B and 14C are cross-sectional views showing an example of a semiconductor device. Figures 15A and 15B are cross-sectional views showing an example of a semiconductor device. Figures 16A and 16B are cross-sectional views showing an example of a semiconductor device. Figure 17A is a top view showing an example of a semiconductor device. Figure 17B is a cross-sectional view showing an example of a semiconductor device. Figures 18A, 18B, 18C, 18D, and 18E are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figures 19A, 19B, and 19C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figures 20A, 20B, and 20C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figures 21A, 21B, and 21C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figures 22A and 22B are diagrams illustrating the carrier concentration dependence of hole mobility. Figure 22C is a cross-sectional view illustrating an indium oxide film. Figure 23 is a perspective view showing an example of a display device. Figures 24A and 24B are cross-sectional views showing an example of a display device. Figure 25 is a cross-sectional view showing an example of a display device.Figure 26 is a cross-sectional view showing an example of a display device. Figures 27A, 27B, and 27C are cross-sectional views showing an example of a display device. Figures 28A and 28B are cross-sectional views showing an example of a display device. Figure 29 is a cross-sectional view showing an example of a display device. Figure 30 is a cross-sectional view showing an example of a display device. Figure 31 is a cross-sectional view showing an example of a display device. Figures 32A, 32B, 32C, and 32D are diagrams showing an example of an electronic device. Figures 33A, 33B, 33C, 33D, 33E, and 33F are diagrams showing an example of an electronic device. Figures 34A, 34B, 34C, 34D, 34E, 34F, and 34G are diagrams showing an example of an electronic device. Figures 35A, 35B, and 35C are diagrams showing the Id-Vg characteristics of a transistor according to an embodiment. Figure 36 is a diagram showing the reliability of a transistor according to an embodiment. Figures 37A, 37B, 37C, and 37D are cross-sectional TEM images of the transistor according to the embodiment. Figures 38A and 38B are schematic cross-sectional diagrams showing the structure of the sample according to the embodiment. Figures 39A and 39B show the SIMS measurement results of the sample according to the embodiment. Figures 40A and 40B show the SIMS measurement results of the sample according to the embodiment. Figures 41A and 41B show the SIMS measurement results of the sample according to the embodiment. Figures 42A and 42B show the SIMS measurement results of the sample according to the embodiment. Figure 43A shows the film density of the sample according to the embodiment. Figure 43B shows the etching rate of the sample according to the embodiment. Figure 44 is a cross-sectional TEM image of the sample according to the embodiment. Figure 45 is a cross-sectional TEM image of the sample according to the embodiment. Figure 46 is a cross-sectional TEM image of the sample according to the embodiment. Figure 47 shows the etching rate of the sample according to the embodiment. Figure 48 is an SEM image of the sample according to the embodiment. Figures 49A and 49B show the Id-Vg characteristics of the transistor according to the embodiment. Figures 50A and 50B show the Id-Vg characteristics of the transistor according to the embodiment. Figures 51A, 51B, and 51C show the Id-Vg characteristics of the transistor according to the embodiment. Figures 52A and 52B show the Id-Vg characteristics of the transistor according to the embodiment. Figures 53A and 53B show the Id-Vg characteristics of the transistor according to the embodiment.Figures 54A, 54B, and 54C show the Id-Vg characteristics of the transistor according to the embodiment. Figures 55A and 55B show the Id-Vg characteristics of the transistor according to the embodiment. Figures 56A and 56B show the Id-Vg characteristics of the transistor according to the embodiment. Figures 57A, 57B, and 57C show the Id-Vg characteristics of the transistor according to the embodiment. Figures 58A and 58B show the Id-Vg characteristics of the transistor according to the embodiment. Figures 59A and 59B show the Id-Vg characteristics of the transistor according to the embodiment. Figures 60A and 60B show the reliability of the transistor according to the embodiment.

[0032] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0033] In the configuration of the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0034] The position, size, and scope of each component shown in the drawings may not represent the actual position, size, and scope for the sake of ease of understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, and scope disclosed in the drawings.

[0035] In this specification, ordinal numbers such as "first," "second," etc., are used to avoid confusion of components and do not limit the number of components or the order of components (e.g., process order or stacking order). Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion of components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, an ordinal number may be omitted in the claims.

[0036] In this specification and drawings, when the same reference numeral is used for multiple elements, and especially when it is necessary to distinguish them, the reference numeral may be accompanied by an identifying numeral such as "_1", "[n]", or "[m,n]". Furthermore, when describing a common matter for multiple elements with identifying numerals, or when it is not necessary to distinguish them, the identifying numeral may be omitted.

[0037] The words "film" and "layer" can be interchanged depending on the context or situation. For example, the term "conductive layer" can be changed to "conductive film." Or, for example, the term "insulating film" can be changed to "insulating layer."

[0038] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0039] The functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably. Furthermore, the names of the source and drain of a transistor can be appropriately rephrased as source terminal and drain terminal, or source electrode and drain electrode, depending on the situation.

[0040] The terms "gate" and "back gate" are interchangeable. Therefore, in this specification, the terms "gate" and "back gate" may be used interchangeably. Furthermore, the names of the gate and back gate of a transistor can be appropriately rephrased as gate electrode and back gate electrode, etc., depending on the context.

[0041] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A and B refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0042] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0043] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0044] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc.

[0045] In this specification, unless otherwise specified, on-current refers to the drain current (also called the conduction state) when the transistor is in the on state. Unless otherwise specified, the on state refers to the state in an n-channel transistor where the voltage between the gate and source (gate voltage, also called Vg or Vgs) is equal to or greater than the threshold voltage (also called Vth), and in a p-channel transistor where it is less than or equal to the threshold voltage.

[0046] In this specification, unless otherwise specified, off-current refers to the source-drain leakage current when the transistor is in the off state (also called the non-conductive state or cutoff state). Unless otherwise specified, the off state refers to the state in an n-channel transistor where the voltage between the gate and source is lower than the threshold voltage, and in a p-channel transistor where it is higher than the threshold voltage.

[0047] In this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less.

[0048] In this specification, the top surface shape of a component refers to the contour shape of the component when viewed from above (also called a plan view). Furthermore, a top view refers to viewing from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0049] In this specification, "matching or roughly matching top shapes" means that at least a portion of the contours overlap between stacked layers. For example, this includes cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer; in this case, it may also be said that the "matching or roughly matching top shapes" apply. Furthermore, when the top shapes match or roughly match, it can also be said that the "edges match or roughly match," or "the edges are aligned or roughly aligned."

[0050] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. The angle formed between the inclined side surface and the substrate surface or the surface to be formed may be called the taper angle.

[0051] In this specification, "step breakage" refers to the phenomenon in which a layer, film, or electrode is divided due to the shape of the surface on which it is formed (e.g., a step).

[0052] In this specification, "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like metal oxide layer refers to a state in which the metal oxide layer and adjacent metal oxide layers are physically separated.

[0053] In this specification, devices fabricated using a metal mask or FMM (Fine Metal Mask, a high-resolution metal mask) may be referred to as MM (Metal Mask) structured devices. Furthermore, in this specification, devices fabricated without using a metal mask or FMM may be referred to as MML (Metal Maskless) structured devices.

[0054] In this specification, a structure in which different light-emitting layers are created using light-emitting devices with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure.

[0055] In this specification, holes or electrons may be referred to as "carriers." For example, in a light-emitting element, a hole injection layer or electron injection layer may be called a "carrier injection layer," a hole transport layer or electron transport layer may be called a "carrier transport layer," and a hole blocking layer or electron blocking layer may be called a "carrier blocking layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier blocking layer may not always be clearly distinguishable. Furthermore, a single layer may combine the functions of two or three of the carrier injection layer, carrier transport layer, and carrier blocking layer.

[0056] In this specification, a light-emitting element has an EL layer between a pair of electrodes (a first electrode and a second electrode). The light-emitting element includes a first electrode, an EL layer on the first electrode, and a second electrode on the EL layer. The EL layer has at least a light-emitting layer. Here, examples of layers (also called functional layers) that the EL layer has include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier block layer (hole block layer and electron block layer). In this specification, a photodetector (also called a photodetector device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes. In this specification, one of the first electrode and the second electrode may be referred to as a pixel electrode, and the other as a common electrode.

[0057] In this specification, flexibility refers to the property of an object being flexible and able to bend. It is the property of an object being able to deform in response to an external force applied to it, regardless of whether it is elastic or able to return to its original shape.

[0058] For example, flexible electronic devices, flexible display devices (also called flexible displays, etc.), flexible batteries (also called flexible batteries, etc.), and flexible substrates (also called flexible substrates, etc.) can each be deformed in response to external forces. Flexible electronic devices, flexible display devices, flexible batteries, and flexible substrates can each be used fixed in a deformed state, used after repeated deformation, or used in an undeformed state. The phrase "deforms in response to external forces" above means that it can be deformed by the average adult's hand without requiring excessive force. Flexibleness can be evaluated using testing machines capable of stress-strain measurement (tensile testing machines, compression testing machines, etc.). In stress-strain measurement, the flexibility of an object can be quantified by applying an external force to the object and measuring the strain of the object caused by the resulting stress.

[0059] In this specification, when an object is described as having flexibility, it means that at least a part of the object is flexible. In other words, a flexible object may also have parts that are not flexible (which can be called rigid parts).

[0060] In this specification, when two objects are deformed by the same external force, the object that deforms more is said to be the object with higher flexibility. Also, when a first part and a second part of an object are deformed by the same external force, the part that deforms more is said to be the part with higher flexibility.

[0061] (Embodiment 1) This embodiment describes a semiconductor device according to one aspect of the present invention. The semiconductor device according to one aspect of the present invention can be suitably used, for example, in one or both of the pixel circuit and the drive circuit of a display device.

[0062] One aspect of the present invention is a semiconductor device having a transistor. The transistor has a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer has a region that overlaps with the gate electrode via the gate insulating layer. The semiconductor layer has a first metal oxide layer, a second metal oxide layer on the first metal oxide layer, and a third metal oxide layer on the second metal oxide layer. The first metal oxide layer, the second metal oxide layer, and the third metal oxide layer each have indium oxide.

[0063] The conductivity of the second metal oxide layer is preferably higher than that of either the first or third metal oxide layer. This ensures that the second metal oxide layer becomes the main current path in the transistor. The first and third metal oxide layers are preferably denser and have fewer defects than the second metal oxide layer. The first or third metal oxide layer has a region that is in contact with the gate insulating layer.

[0064] When using non-single-crystal (e.g., polycrystalline) indium oxide in the semiconductor layer, the carrier mobility can sometimes be increased by increasing the carrier concentration. It is preferable that the carrier concentration of the second metal oxide layer is higher than that of the first and third metal oxide layers. It is preferable that the second metal oxide layer has regions with higher hydrogen concentrations than those of the first and third metal oxide layers. This increases the carrier concentration in the second metal oxide layer, thereby increasing the carrier mobility. Consequently, the conductivity of the second metal oxide layer, which is the main current path, becomes higher, resulting in a transistor with high field-effect mobility.

[0065] By sandwiching the second metal oxide layer between the first and third metal oxide layers, the second metal oxide layer can be moved away from the interface between the semiconductor layer and the gate insulating layer, thereby reducing the trap levels at and near the interface of the second metal oxide layer. This makes it possible to create a transistor with high field-effect mobility.

[0066] Preferably, the first metal oxide layer and the third metal oxide layer each have a region with a lower hydrogen concentration than the second metal oxide layer. This allows for a denser structure with fewer defects. By providing a first or third metal oxide layer with fewer defects in contact with the gate insulating layer, the formation of trap levels at and near the interface between the gate insulating layer and the semiconductor layer can be suppressed. This results in a highly reliable transistor.

[0067] As described above, by sandwiching a second metal oxide layer with high conductivity between a dense first metal oxide layer and a third metal oxide layer with few defects, a transistor can be made that achieves both high field-effect mobility and high reliability. This makes it possible to create a semiconductor device that achieves both high-speed operation and high reliability.

[0068] The first metal oxide layer, the second metal oxide layer, and the third metal oxide layer can be deposited in this order using a sputtering method. Oxygen gas, hydrogen gas, and argon gas can be used as the deposition gas. It is preferable that the power density during deposition of the first and third metal oxide layers is higher than that during deposition of the second metal oxide layer. It is also preferable that the pressure during deposition of the first and third metal oxide layers is lower than that during deposition of the second metal oxide layer. This allows the second metal oxide layer to have a region with a higher hydrogen concentration than the first and third metal oxide layers.

[0069] In the following sections, more specific examples will be explained using Figures 1A to 21C.

[0070] <Configuration Example 1> [Configuration Example 1-1] A transistor applicable to a semiconductor device, which is one aspect of the present invention, will be described. A schematic cross-sectional view of the transistor 10 is shown in Figure 1A.

[0071] The transistor 10 is provided on an insulating surface. For example, the transistor 10 can be provided on a substrate (not shown) having an insulating surface. Alternatively, an insulating film can be provided on a substrate (not shown), and the transistor 10 can be provided on the insulating film.

[0072] The transistor 10 has a semiconductor layer 18, an insulating layer 16, an insulating layer 15, a conductive layer 14, and a conductive layer 13. The conductive layer 13, insulating layer 15, semiconductor layer 18, insulating layer 16, and conductive layer 14 are stacked in this order.

[0073] An insulating layer 16 is provided on a semiconductor layer 18, and a conductive layer 14 is provided on the insulating layer 16. The conductive layer 14 has a region that overlaps with the semiconductor layer 18 via the insulating layer 16. In the transistor 10, the conductive layer 14 functions as a first gate electrode, and the insulating layer 16 functions as a first gate insulating layer. The conductive layer 14 located above the semiconductor layer 18 can be called the top gate electrode, and the insulating layer 16 can be called the top gate insulating layer.

[0074] An insulating layer 15 is provided on the conductive layer 13, and a semiconductor layer 18 is provided on the insulating layer 15. The conductive layer 13 has a region that overlaps with the semiconductor layer 18 via the insulating layer 15. In the transistor 10, the conductive layer 13 functions as a second gate electrode, and the insulating layer 15 functions as a second gate insulating layer. The conductive layer 13 located below the semiconductor layer 18 can be called the bottom gate electrode, and the insulating layer 15 can be called the bottom gate insulating layer. Furthermore, the conductive layer 13 has a region that overlaps with the conductive layer 14 via the insulating layer 15, the semiconductor layer 18, and the insulating layer 16.

[0075] Figure 1A shows a configuration in which the width of the conductive layer 14 and the width of the conductive layer 13 are the same, but the present invention is not limited to this. The width of the conductive layer 14 and the width of the conductive layer 13 can be different. Also, Figure 1A shows a configuration in which the edge of the conductive layer 14 is in contact with the upper surface of the insulating layer 16, that is, the insulating layer 16 has a region that protrudes beyond the edge of the conductive layer 14. The present invention is not limited to this, and the edges of the insulating layer 16 and the conductive layer 14 can be the same or approximately the same.

[0076] In the semiconductor layer 18, the region overlapping with at least one of the conductive layer 14 and the conductive layer 13 functions as a channel-forming region. For the sake of simplicity, the region of the semiconductor layer 18 that overlaps with the conductive layer 14 is sometimes referred to as the channel-forming region, but a region that does not overlap with the conductive layer 14 but overlaps with the conductive layer 13 can also function as a channel-forming region.

[0077] Transistor 10 has gate electrodes (a first gate electrode and a second gate electrode) on both sides of the channel formation region, and can be described as a dual-gate type transistor. Note that one of the first and second gate electrodes may be referred to as the front gate electrode (or simply as the gate electrode), and the other as the back gate electrode.

[0078] By providing a back gate electrode, the on-current of the transistor can be increased. Furthermore, by providing a back gate electrode, the potential on the back gate electrode side (also called the back channel side) of the semiconductor layer 18 is fixed, improving the saturation in the Id-Vd characteristic. Additionally, by fixing the potential on the back channel side of the semiconductor layer 18, the threshold voltage shift can be suppressed. Therefore, a transistor with a small drain current (hereinafter also referred to as cutoff current) when the gate voltage (Vg) is 0V can be created, resulting in a semiconductor device with low power consumption.

[0079] In this specification, the term "high saturation" may be used to describe a transistor where the change in current in the saturation region of the Id-Vd characteristic is small.

[0080] The semiconductor material used for the semiconductor layer 18 is not particularly limited. For example, a semiconductor made of a single element or a compound semiconductor can be used. Examples of semiconductors made of single elements include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS). These semiconductor materials may contain impurities as dopants.

[0081] The crystallinity of the semiconductor material used in the semiconductor layer 18 is not particularly limited, and any amorphous semiconductor, single-crystal semiconductor, or semiconductor having crystalline properties other than single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or semiconductor having a crystalline region in part) can be used. Using a single-crystal semiconductor or a semiconductor having crystalline properties is preferable because it can suppress the degradation of transistor characteristics.

[0082] For example, silicon can be used for the semiconductor layer 18. Examples of silicon include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS). Transistors using amorphous silicon for the channel formation region can be fabricated at low cost on a large glass substrate. Transistors using polycrystalline silicon for the channel formation region have high field-effect mobility and can operate at high speeds. Transistors using microcrystalline silicon for the channel formation region have higher field-effect mobility and can operate at high speeds than transistors using amorphous silicon. Note that transistors using silicon for the channel formation region are sometimes referred to as Si transistors, and transistors using LTPS for the channel formation region are sometimes referred to as LTPS transistors.

[0083] The semiconductor layer 18 preferably has a metal oxide (also called an oxide semiconductor) that exhibits semiconductor properties. The band gap of the metal oxide in the semiconductor layer 18 is preferably 2.0 eV or more, and more preferably 2.5 eV or more. Transistors using oxide semiconductors (hereinafter also referred to as OS transistors) have extremely high field-effect mobility compared to transistors using amorphous silicon. Furthermore, OS transistors have a remarkably small off-current and can retain the charge stored in a capacitor connected in series with the transistor for a long period of time. In addition, the power consumption of semiconductor devices can be reduced by applying OS transistors. When an oxide semiconductor is used for the semiconductor layer, the semiconductor layer can be called an oxide semiconductor layer or a metal oxide layer.

[0084] The metal oxide preferably contains at least indium. The semiconductor layer 18 preferably uses a metal oxide containing indium, and for example, indium oxide (also written as indium oxide) can be suitably used.

[0085] The semiconductor layer 18 is preferably crystalline. Using a crystalline oxide semiconductor for the semiconductor layer 18 is preferable because it suppresses the degradation of transistor characteristics. The semiconductor layer 18 is preferably highly crystalline, and preferably polycrystalline or monocrystalline. A polycrystalline indium oxide film is preferably used as the semiconductor layer 18, and a monocrystalline indium oxide film is more preferably used.

[0086] Single-crystal films are particularly preferred because they do not have grain boundaries, thus suppressing carrier scattering at grain boundaries and enabling transistors with high field-effect mobility. Compared to microcrystalline and amorphous films, polycrystalline films can reduce carrier scattering and enable transistors with high field-effect mobility. When a polycrystalline film is used for the semiconductor layer 18, it is preferable that the grain size of the crystal grains contained in the semiconductor layer 18 is large. By using a polycrystalline film with large grain size, the number of crystal grain boundaries located in the channel formation region can be reduced, and the length of the crystal grain boundaries located in the channel formation region can be shortened, thus enabling transistors with high field-effect mobility. Furthermore, it is preferable that there are few crystal grain boundaries in the channel formation region that intersect with the direction of drain current flow (also known as the channel length direction). Note that even with a polycrystalline film, if there are no crystal grain boundaries in the channel formation region, the same effects as a single-crystal film can be achieved.

[0087] The semiconductor layer 18 can have a single-layer structure or a stacked structure of two or more layers. It is preferable that the semiconductor layer 18 has a stacked structure. Figure 1B shows an enlarged view of the semiconductor layer 18 and its vicinity, as shown in Figure 1A. Figures 1A and 1B show a configuration in which the semiconductor layer 18 has a three-layer structure consisting of semiconductor layer 18a, semiconductor layer 18b on semiconductor layer 18a, and semiconductor layer 18c on semiconductor layer 18b. Semiconductor layer 18b is in contact with and sandwiched between semiconductor layers 18a and 18c. The semiconductor layers 18a, 18b, and 18c can each be made from the materials listed for semiconductor layer 18. It is preferable that semiconductor layers 18a, 18b, and 18c each have a metal oxide exhibiting semiconductor properties.

[0088] The first metal oxide in semiconductor layer 18a, the second metal oxide in semiconductor layer 18b, and the third metal oxide in semiconductor layer 18c can be described by referring to the above-mentioned description of metal oxides. Furthermore, the band gaps of the first metal oxide, the second metal oxide, and the third metal oxide are preferably 2.0 eV or higher, and more preferably 2.5 eV or higher.

[0089] The semiconductor layers 18a, 18b, and 18c can use the same material for each other. This allows for the use of common equipment for depositing the semiconductor layers 18a, 18b, and 18c, thereby reducing the manufacturing cost of semiconductor devices. Alternatively, different materials can be used for at least one of the semiconductor layers 18a, 18b, and 18c. This broadens the range of materials that can be selected for the semiconductor layers 18a, 18b, and 18c.

[0090] In this specification, "different materials" means materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0091] In some cases, the boundaries between semiconductor layer 18a and semiconductor layer 18b, and between semiconductor layer 18b and semiconductor layer 18c, cannot be clearly identified. Therefore, in Figure 1A and other diagrams, these boundaries are shown with dashed lines.

[0092] Preferably, the conductivity of semiconductor layer 18b is higher than that of either semiconductor layer 18a or semiconductor layer 18c. This ensures that the main current path in transistor 10 is through semiconductor layer 18b. On the other hand, in semiconductor layer 18, it is preferable that semiconductor layer 18a, which is in contact with the second gate insulating layer, and semiconductor layer 18c, which is in contact with the first gate insulating layer, are both denser and have fewer defects than semiconductor layer 18b.

[0093] Trap levels caused by impurities or defects may form at the interface between the insulating layer 16, which functions as the first gate insulating layer, and the semiconductor layer 18, and at the interface between the insulating layer 15, which functions as the second gate insulating layer, and the semiconductor layer 18, and at the interface at the interface at the interface at the interface. Furthermore, when the insulating layer 16 is deposited, damage may be inflicted on the interface between the insulating layer 16 and the semiconductor layer 18, causing trap levels to form at the interface between the insulating layer 16 and the semiconductor layer 18, and at the interface

[0094] Here, when a high potential is applied to the conductive layer 14, which functions as the first gate electrode, trap levels may be formed at and near the interface between the insulating layer 16 and the semiconductor layer 18. Similarly, when a high potential is applied to the conductive layer 13, which functions as the second gate electrode, trap levels may be formed at and near the interface between the insulating layer 15 and the semiconductor layer 18. If electrons are trapped in these trap levels, the threshold voltage of the transistor may shift to the positive side, potentially reducing reliability. By providing a semiconductor layer 18c with few defects in contact with the insulating layer 16, the formation of trap levels at and near the interface between the insulating layer 16 and the semiconductor layer 18 can be suppressed. Similarly, by providing a semiconductor layer 18a with few defects in contact with the insulating layer 15, the formation of trap levels at and near the interface between the insulating layer 15 and the semiconductor layer 18 can be suppressed. This makes it possible to create a highly reliable transistor.

[0095] In this way, by sandwiching a highly conductive semiconductor layer 18b between semiconductor layers 18a and 18c, which have few defects, a transistor can be made that achieves both high field-effect mobility and high reliability. Therefore, a semiconductor device can be made that achieves both high-speed operation and high reliability.

[0096] In the channel formation region, it is preferable that the carrier mobility of semiconductor layer 18b is higher than that of semiconductor layer 18a and semiconductor layer 18c. Here, when a non-single-crystal (e.g., polycrystalline) metal oxide is used for the semiconductor layer, the carrier mobility can be increased by increasing the carrier concentration. It is preferable that the carrier concentration of semiconductor layer 18b is higher than that of semiconductor layer 18a and semiconductor layer 18c. As a result, the conductivity of semiconductor layer 18b, which is the main current path, is increased, and a transistor with high field-effect mobility can be made.

[0097] It is preferable that each of the semiconductor layers 18a, 18b, and 18c contains an element that increases the carrier concentration (hereinafter also referred to as the first element). For example, one or more of hydrogen, carbon, and nitrogen can be used as the first element. Hydrogen can be suitably used as the first element. Hydrogen reacts with oxygen bonded to the metal atoms of the metal oxide to form water, thereby creating oxygen vacancies (V) in the metal oxide. Ｏ ) is formed. Furthermore, oxygen deficiency (V Ｏ A defect (V) into which hydrogen has entered Ｏ H) functions as a donor, generating electrons, which are carriers, thereby increasing the carrier concentration in the metal oxide. Note that in the following explanation, hydrogen may be used as the first element.

[0098] In the channel formation region, it is preferable that semiconductor layer 18b has a region with a higher concentration of the first element compared to semiconductor layer 18a and semiconductor layer 18c. Typically, it is preferable that semiconductor layer 18b has a region with a higher hydrogen concentration compared to semiconductor layer 18a and semiconductor layer 18c. In the channel formation region, semiconductor layer 18b has a concentration of the first element (for example, hydrogen) of 1 × 10⁻¹⁰. １９ atoms / cm ３ The above 1 x 10 ２２ atoms / cm ３ Preferably, it has the following region, and more preferably 1 × 10 ２０ atoms / cm ３ The above 1 x 10 ２２ atoms / cm ３Preferably, it has the following region, and more preferably 5 × 10 ２０ atoms / cm ３ The above 1 x 10 ２２ atoms / cm ３ Preferably, it has the following region, and more preferably 5 × 10 ２０ atoms / cm ３ The above 5 x 10 ２１ atoms / cm ３ It is preferable to have the following regions. If the concentration of the first element in the semiconductor layer 18b is too low, the carrier concentration will be low, and there is a risk that the carrier mobility will be low. On the other hand, if the concentration of the first element in the semiconductor layer 18b is too high, the V of the channel formation region Ｏ An increase in the amount of H may cause a shift in the threshold voltage and a corresponding increase in the cutoff current. By setting the concentration of the first element in the semiconductor layer 18b within the aforementioned range, a transistor can be made that achieves both high field-effect mobility and a small cutoff current. The concentration of the first element in the semiconductor layer 18 may have a gradient in the thickness direction of the semiconductor layer 18. It is preferable that the maximum value of the concentration of the first element in the semiconductor layer 18b is within the aforementioned range. However, the concentration of the first element in the semiconductor layer 18b is not limited to the aforementioned range.

[0099] In the channel formation region, it is preferable that semiconductor layer 18a and semiconductor layer 18c each have regions where the concentration of the first element is lower than that of semiconductor layer 18b. In the channel formation region, it is preferable that semiconductor layer 18a and semiconductor layer 18c each have regions where the concentration of the first element (e.g., hydrogen) is 1 / 100 to 1 / 2 of the concentration of the first element in semiconductor layer 18b, more preferably 1 / 100 to 1 / 4, more preferably 1 / 100 to 1 / 6, more preferably 1 / 100 to 1 / 8, and more preferably 1 / 100 to 1 / 10. If the concentration of the first element in semiconductor layer 18a and semiconductor layer 18c is too high, the film density will be low, and there is a risk of many defects. On the other hand, if the concentration of the first element in semiconductor layer 18a and semiconductor layer 18c is too low, the carrier concentration will be low, resulting in low carrier mobility, which may lead to low field-effect mobility. By setting the concentration of the first element in semiconductor layer 18a and semiconductor layer 18c within the aforementioned range, a transistor can be made that achieves both high field-effect mobility and high reliability. As mentioned above, the concentration of the first element in semiconductor layer 18 may have a gradient in the thickness direction of semiconductor layer 18. It is preferable that the minimum value of the concentration of the first element in semiconductor layer 18a and the minimum value of the concentration of the first element in semiconductor layer 18c are within the aforementioned range. However, the concentration of the first element in semiconductor layer 18a and semiconductor layer 18c is not limited to the aforementioned range.

[0100] For analyzing the concentration of the first element in the semiconductor layer 18, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used. XPS is sometimes called ESCA (Electron Spectrometer for Chemical Analysis). For example, SIMS can be suitably used for analyzing hydrogen concentration. However, the reliability of measurement values ​​may be low at the interface between the semiconductor layer 18 and the layer in contact with the semiconductor layer 18, and in its vicinity, due to the matrix effect. For example, when measuring in the direction from the insulating layer 16 toward the semiconductor layer 18, the reliability of measurement values ​​may be low at the interface between the insulating layer 16 and the semiconductor layer 18, and in its vicinity. Measurement values ​​in the unreliable region will not be treated as the concentration of the first element in the semiconductor layer 18. Furthermore, by combining measurements taken from the insulating layer 16 towards the semiconductor layer 18 and measurements taken from the insulating layer 15 towards the semiconductor layer 18, the accuracy of the analysis of the concentration of the first element in the semiconductor layer 18 may be improved.

[0101] In concentration analysis, the intensity of the constituent elements of the metal oxide can sometimes be used to estimate the location of the interface between the insulating layer 16 and the semiconductor layer 18, and the location of the interface between the insulating layer 15 and the semiconductor layer 18. For example, the semiconductor layer 18 can be defined as the range in which the intensity of the constituent elements of the metal oxide present in the semiconductor layer 18 is 1 / 2 or more of its maximum value. It is more preferable that these constituent elements are not included in the main components of the insulating layer 16. When indium oxide is used for the semiconductor layer 18 and SIMS is used for the concentration analysis of the first element, the range in which the secondary ion intensity of indium is 1 / 2 or more of its maximum value can be defined as the semiconductor layer 18, and the range in which it is less than 1 / 2 of its maximum value can be defined as layers other than the semiconductor layer 18 (for example, the insulating layer 15 and the insulating layer 16). Alternatively, the range in which the secondary ion intensity of indium-containing clusters (for example, clusters of indium and oxygen) is 1 / 2 or more of its maximum value can be referred to as the semiconductor layer 18, and the range in which it is less than 1 / 2 of its maximum value can be referred to as the layers other than the semiconductor layer 18 (for example, the insulating layer 15 and the insulating layer 16).

[0102] Preferably, the film density of semiconductor layer 18a and semiconductor layer 18c is higher than that of semiconductor layer 18b. This reduces defects in semiconductor layer 18a and semiconductor layer 18c. Furthermore, by providing a semiconductor layer 18c with a high film density on semiconductor layer 18b, damage to semiconductor layer 18b during the deposition of the insulating layer 16 can be suppressed. Film density can be evaluated using, for example, Rutherford backscattering spectrum (RBS) or X-ray reflectivity (XRR).

[0103] Differences in film density can sometimes be evaluated using a cross-sectional transmission electron microscope (TEM) image. In TEM observation, a high film density results in a darker (darker) transmission electron (TE) image, while a low film density results in a fainter (brighter) transmission electron (TE) image. Therefore, even when the same material, such as indium oxide, is used for semiconductor layers 18a, 18b, and 18c, differences in film density among these layers can sometimes be observed as differences in contrast in cross-sectional TEM observations. Specifically, in the TE image, semiconductor layers 108a and 108c may have darker (darker) regions compared to semiconductor layer 108b. Also, semiconductor layer 108b may have lighter (brighter) regions compared to semiconductor layers 108a and 108c.

[0104] Furthermore, the film densities of semiconductor layer 18a and semiconductor layer 18c can be the same as, or lower than, the film densities of semiconductor layer 18b, respectively.

[0105] Even when using the same material, the etching rate may be slower if the film is denser and has a higher film density. It is preferable that the etching rate at one etchant of semiconductor layer 18a and semiconductor layer 18c is slower than the etching rate of semiconductor layer 18b. It is also preferable to provide a semiconductor layer 18c with a slow etching rate on top of semiconductor layer 18b. This makes it possible to suppress the disappearance of semiconductor layer 18c in the etching process after the formation of semiconductor layer 18, and to suppress the thinning of the thickness of semiconductor layer 18.

[0106] The semiconductor layer 18 can be formed by depositing a metal oxide film and processing the metal oxide film into island shapes. It is preferable to perform a heat treatment to crystallize the metal oxide film after depositing it or after processing the metal oxide film into island shapes. By performing the heat treatment, the particle size of the crystal grains contained in the semiconductor layer 18 can be increased and the crystallinity of the semiconductor layer 18 can be improved. In addition, the heat treatment can reduce defects in the semiconductor layer 18. Furthermore, the heat treatment can remove impurities contained in the semiconductor layer 18 or adsorbed on its surface.

[0107] When the semiconductor layer 18 has a three-layer structure consisting of semiconductor layer 18a, semiconductor layer 18b, and semiconductor layer 18c, the metal oxide films are formed in the following order: a first metal oxide film which will become semiconductor layer 18a, a second metal oxide film which will become semiconductor layer 18b, and a third metal oxide film which will become semiconductor layer 18c.

[0108] The first, second, and third metal oxide films are preferably deposited by sputtering using a metal target or a metal oxide target. Alternatively, the first, second, and third metal oxide films are preferably deposited by atomic layer deposition (ALD). The ALD method allows for easy control of the deposition rate, enabling the deposition of thin films with good yield. Therefore, the ALD method is particularly suitable when the metal oxide film is thin. Chemical vapor deposition (CVD) can also be used to deposit the metal oxide film.

[0109] Examples of power supplies used in sputtering apparatuses include DC (Direct Current) power supplies, RF (Radio Frequency) power supplies, and AC (Alternating Current) power supplies. A pulsed DC power supply that applies a pulsed voltage to the target can also be used. Furthermore, the magnetron sputtering method, which utilizes the magnetic field of a magnet, offers a high deposition rate, thus increasing productivity. The deposition of the first, second, and third metal oxide films can be suitably performed using sputtering methods, particularly magnetron sputtering. In the following, the magnetron sputtering method may be used as an example to describe the deposition methods for the first, second, and third metal oxide films.

[0110] When forming the first metal oxide film, the second metal oxide film, and the third metal oxide film, an inert gas (for example, helium gas, argon gas, xenon gas, etc.) can be used.

[0111] It is preferable to deposit a second metal oxide film in a vacuum after depositing a first metal oxide film, without exposing the surface of the first metal oxide film to the atmosphere. Similarly, it is preferable to deposit a third metal oxide film in a vacuum after depositing a second metal oxide film, without exposing the surface of the second metal oxide film to the atmosphere. By depositing the first, second, and third metal oxide films in succession, it is possible to suppress the adhesion of airborne impurities to the surfaces of the first and second metal oxide films. Examples of such impurities include water and organic matter.

[0112] When using the same material for two or more of the first, second, and third metal oxide films, the films can be deposited in the same processing chamber using the same sputtering target.

[0113] It is particularly preferable that semiconductor layers 18a, 18b, and 18c use the same material. The first metal oxide film, the second metal oxide film, and the third metal oxide film can be deposited continuously in the same processing chamber using the same sputtering target. This increases the productivity of semiconductor devices and reduces manufacturing costs. Furthermore, it is possible to suppress the adhesion of airborne impurities to the surfaces of the first metal oxide film and the second metal oxide film.

[0114] When using one or more different materials for semiconductor layer 18a, semiconductor layer 18b, and semiconductor layer 18c, that is, when using two or more sputtering targets, it is preferable to continuously deposit the metal oxide film in a vacuum within the same apparatus without exposing the surface of the metal oxide film to the atmosphere. For example, it is preferable to continuously deposit each metal oxide film in different processing chambers within the same apparatus in a vacuum.

[0115] As mentioned above, there are cases where the boundary between semiconductor layer 18a and semiconductor layer 18b, and the boundary between semiconductor layer 18b and semiconductor layer 18c cannot be clearly identified. In particular, in configurations where the same material is used for semiconductor layer 18a, semiconductor layer 18b, and semiconductor layer 18c, these boundaries may not be clearly identified. Furthermore, by continuously depositing the first metal oxide film, the second metal oxide film, and the third metal oxide film in a vacuum, no interface may be formed between each metal oxide film, and these boundaries may not be identified. In such cases, semiconductor layer 18a, semiconductor layer 18b, and semiconductor layer 18c can be read as the first region, the second region, and the third region. Semiconductor layer 18 has a first region (corresponding to semiconductor layer 18a) on the insulating layer 15 side, a third region (corresponding to semiconductor layer 18c) on the insulating layer 16 side, and a second region (corresponding to semiconductor layer 18b) between the first region and the third region.

[0116] Preferably, the concentration of the first element in the second region is higher than the concentration of the first element in the first region and higher than the concentration of the first element in the third region. The concentration of the first element in the second region can be determined by referring to the description of the concentration of the first element in the semiconductor layer 18b described above. The concentrations of the first element in the first region and the third region can be determined by referring to the descriptions of the concentrations of the first element in the semiconductor layer 18a and the semiconductor layer 18c described above, respectively. Note that the concentrations of the first element in the first region, the second region, and the third region are not limited to the ranges described above.

[0117] Preferably, the film density of the first region and the third region is higher than the film density of the second region. When observing the cross-section of the semiconductor layer 18 using TEM, the TE image may show that the first region and the third region are denser (darker) compared to the second region. Also, the second region may be thinner (brighter) compared to the first region and the third region.

[0118] Here, by varying the deposition conditions for the metal oxide film, the film quality of the metal oxide film (later the semiconductor layer) can be varied. Examples of film quality include conductivity, band gap, defect amount, impurity concentration, and crystallinity. Examples of deposition conditions include power density, pressure, gas type, gas flow rate, substrate temperature, and the distance between the sputtering target and the substrate (also called T-S distance or TS distance). When varying the deposition conditions, one or more of the power density, pressure, gas type, gas flow rate, substrate temperature, and T-S distance can be varied. Note that changing the substrate temperature and T-S distance may take time. Therefore, when depositing two or more metal oxide films in the same processing chamber, it is preferable to keep the substrate temperature and T-S distance the same. Note that even when using the same material, the band gap may differ by varying the deposition conditions.

[0119] It is preferable that the deposition conditions for the first metal oxide film (hereinafter also referred to as the first deposition conditions) are different from those for the second metal oxide film (hereinafter also referred to as the second deposition conditions). It is preferable that the deposition conditions for the third metal oxide film (hereinafter also referred to as the third deposition conditions) are different from those for the second deposition conditions. For example, it is preferable that one or both of the power density and pressure in the first deposition conditions are different from those in the second deposition conditions. Similarly, it is preferable that one or both of the power density and pressure in the third deposition conditions are different from those in the second deposition conditions. It is particularly preferable that the power density and pressure in the first deposition conditions are different from those in the second deposition conditions, and that the power density and pressure in the third deposition conditions are different from those in the second deposition conditions.

[0120] The power density under the first and third film deposition conditions is preferably higher than the power density under the second film deposition condition. By increasing the power density, dense semiconductor layers 18a and 18c with few defects can be obtained. The power density under the first and third film deposition conditions is preferably 0.3 W / cm². ２ More than 2W / cm ２ The following is preferable, and more preferably 0.4 W / cm².２ More than 2W / cm ２ The following is preferable, and more preferably 0.5 W / cm². ２ More than 2W / cm ２ The following is preferable, and more preferably 0.6 W / cm². ２ More than 2W / cm ２ The following is preferable, and more preferably 0.6 W / cm². ２ 1W / cm or more ２ The following is preferable. If the power density is too low, there is a risk of an increase in defects in the semiconductor layer 18a and semiconductor layer 18c, while if the power density is too high, there is a risk of an increased load on the device. By setting the power density in the first and third film deposition conditions to the aforementioned range, it is possible to obtain dense semiconductor layers 18a and semiconductor layer 18c with few defects, and to reduce the load on the device. Note that the power density in the first and third film deposition conditions is not limited to the aforementioned range.

[0121] Power density is calculated by dividing the power applied to the substrate by the magnet area. The magnet area is the area of ​​the surface of the magnet that overlaps with the sputtering target.

[0122] The power density under the second film deposition condition was 0.1 W / cm². ２ 1W / cm or more ２ The following is preferable, and more preferably 0.2 W / cm². ２ 1W / cm or more ２ The following is preferable, and more preferably 0.2 W / cm². ２ 0.8W / cm or more ２ The following is preferable, and more preferably 0.2 W / cm². ２ 0.6W / cm or more ２ The following is preferable, and more preferably 0.3 W / cm². ２ 0.6W / cm or more ２The following is preferable. Furthermore, it is preferable that the power density under the second film deposition condition is lower than the power density under the first and third film deposition conditions. If the power density is too high, the conductivity of the semiconductor layer 18b may be low, while if the power density is too low, the film deposition rate will be slow, which may reduce productivity. Also, if the power density is too low, the discharge may become unstable. By setting the power density under the second film deposition condition within the above range, it is possible to obtain a semiconductor layer 18b with high conductivity and increase productivity. Note that the power density under the second film deposition condition is not limited to the above range.

[0123] The pressure in the first and third film deposition conditions is preferably lower than the pressure in the second film deposition condition. By lowering the pressure, dense semiconductor layers 18a and 18c with few defects can be obtained. The pressure in the first and third film deposition conditions is preferably 0.1 Pa or more and 0.8 Pa or less, more preferably 0.1 Pa or more and 0.6 Pa or less, more preferably 0.1 Pa or more and 0.4 Pa or less, and more preferably 0.1 Pa or more and 0.3 Pa or less. If the pressure is too high, there is a risk of an increase in defects in the semiconductor layers 18a and 18c, while if the pressure is too low, it may take a long time to adjust the pressure in the processing chamber, which may reduce productivity. Also, if the pressure is too low, arcing may occur, making it difficult to discharge. By setting the pressure in the first and third film deposition conditions within the above range, dense semiconductor layers 18a and 18c with few defects can be obtained, and productivity can be increased. Furthermore, the pressures in the first and third film deposition conditions are not limited to the ranges described above.

[0124] The pressure in the second film deposition condition is preferably 0.2 Pa or more and 1 Pa or less, more preferably 0.3 Pa or more and 1 Pa or less, more preferably 0.4 Pa or more and 1 Pa or less, and more preferably 0.4 Pa or more and 0.8 Pa or less. Furthermore, the pressure in the second film deposition condition is preferably higher than the pressure in the first and third film deposition conditions. If the pressure is too low, the conductivity of the semiconductor layer 18b may be low. On the other hand, if the pressure is too high, the film deposition rate will be slow, which may reduce productivity. Also, if the pressure is too high, discharge may become difficult. By setting the pressure in the second film deposition condition within the above range, it is possible to obtain a semiconductor layer 18b with high conductivity and increase productivity. Note that the pressure in the second film deposition condition is not limited to the above range.

[0125] It is particularly preferable that the power density under the first and third film deposition conditions is higher than the power density under the second film deposition condition, and that the pressure under the first and third film deposition conditions is lower than the pressure under the second film deposition condition. This makes it possible to increase the conductivity of the semiconductor layer 18b and to make the semiconductor layers 18a and 18c denser and reduce defects.

[0126] Here, a configuration is shown in which the power density and pressure in the first and third film deposition conditions are different from those in the second film deposition condition; however, the present invention is not limited to this. It is also possible to differ other parameters (for example, gas flow rate) between the first and third film deposition conditions and the second film deposition condition.

[0127] Furthermore, the first film deposition conditions and the third film deposition conditions can be the same or different. By making the first and third film deposition conditions the same, that is, by making the film quality of semiconductor layer 18a and semiconductor layer 18c the same, the number of film types that need to be controlled in the manufacturing of semiconductor devices can be reduced. This can increase productivity. Alternatively, the first and third film deposition conditions can be different, that is, the film quality of semiconductor layer 18a and semiconductor layer 18c can be different. Since damage may occur to the semiconductor layer 18c when depositing the insulating layer 16, it is preferable that the third film deposition conditions be denser and less prone to defects compared to the first film deposition conditions. For example, one or both of the power density and pressure in the third film deposition conditions can be different from the power density and pressure in the first film deposition conditions. Specifically, the power density under the third film deposition condition can be made higher than the power density under the first film deposition condition. Furthermore, the pressure under the third film deposition condition can be made lower than the pressure under the first film deposition condition.

[0128] In the following, matters common to the first metal oxide film, the second metal oxide film, and the third metal oxide film may be described simply as "metal oxide film." Similarly, matters common to the first film formation conditions, the second film formation conditions, and the third film formation conditions may be described simply as "film formation conditions."

[0129] It is preferable to use conditions that result in low crystallinity of the metal oxide film when forming the metal oxide film. By performing a heat treatment after forming a metal oxide film with low crystallinity to induce crystallization, the grain size can be increased. If the number of grains contained in the metal oxide film is large at the time of film formation, the grain size of the grains after heat treatment may become small. Therefore, it is preferable that the number of grains contained in the metal oxide film is small at the time of film formation, and that the metal oxide film has low crystallinity.

[0130] When forming a metal oxide film, a gas containing hydrogen (for example, H) ２ or H ２It is preferable to use O). This reduces the number of crystal grains generated during the formation of the metal oxide film, resulting in a metal oxide film with low crystallinity. Furthermore, by using hydrogen gas as the film formation gas for the metal oxide film, the carrier concentration in the semiconductor layer 18 increases, and the carrier mobility can be increased. For example, hydrogen gas and argon gas can be suitably used as the film formation gas for the metal oxide film. The ratio of the flow rate of hydrogen gas to the total film formation gas when forming the metal oxide film (hereinafter also referred to as the hydrogen flow rate ratio) is preferably higher than 0% and 20% or less, more preferably higher than 0% and 15% or less, and even more preferably higher than 0% and 10% or less. If the hydrogen flow rate ratio is too low, there is a risk that the number of crystal grains contained in the metal oxide film will increase at the stage when the metal oxide film is formed, and the hydrogen concentration contained in the semiconductor layer 18 will decrease, which may result in low carrier mobility. On the other hand, if the hydrogen flow rate ratio is too high, the V in the channel formation region Ｏ An increase in the amount of H can shift the threshold voltage, potentially leading to a larger cutoff current. By keeping the hydrogen flow rate ratio within the aforementioned range, a transistor with both high field-effect mobility and a small cutoff current can be achieved. Note that the hydrogen flow rate ratio in metal oxide film deposition is not limited to the aforementioned range. Furthermore, metal oxide films can be deposited without using a gas containing hydrogen as the deposition gas.

[0131] By using oxygen gas as the deposition gas for metal oxide films, oxygen vacancies (V) can be created in the metal oxide film. Ｏ This can suppress the occurrence of oxygen deficiencies (V) in the semiconductor layer 18. Furthermore, by using oxygen gas as the deposition gas for the metal oxide film, the amount of oxygen contained in the metal oxide film can be increased, which can promote crystallization in the subsequent heat treatment. In addition, oxygen can be supplied to the insulating layer 15 during the deposition of the metal oxide film. As a result, oxygen is supplied from the insulating layer 15 to the semiconductor layer 18 in a later process, and oxygen deficiencies (V) in the semiconductor layer 18 can be suppressed. Ｏ ), and V Ｏ H can be reduced. Therefore, good electrical characteristics can be observed even in transistors with short channel lengths.

[0132] For example, oxygen gas and argon gas can be suitably used as the film-forming gas for the metal oxide film. On the other hand, if the oxygen flow rate ratio when forming the metal oxide film is high, there is a risk that the number of crystal grains contained in the metal oxide film will increase at the stage of film formation. The ratio of the flow rate of oxygen gas to the total film-forming gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow rate ratio) is preferably higher than 0% and 10% or less, more preferably higher than 0% and 7% or less, and even more preferably higher than 0% and 5% or less. By setting the oxygen flow rate ratio within the above range, the crystallinity of the metal oxide film can be reduced, and oxygen vacancies and V in the semiconductor layer 18 can be reduced. Ｏ H can be reduced. Note that the oxygen flow rate ratio in metal oxide film deposition is not limited to the range mentioned above.

[0133] A mixture of hydrogen gas, oxygen gas, and an inert gas can be used as the film-forming gas for the metal oxide film. Typically, hydrogen gas, oxygen gas, and argon gas can be suitably used as the film-forming gas for the metal oxide film. The hydrogen flow rate ratio and oxygen flow rate ratio are preferably within the aforementioned ranges. This makes it possible to lower the crystallinity of the metal oxide film and increase the grain size of the crystal grains after heat treatment. Furthermore, oxygen vacancies and V in the semiconductor layer 18 can be reduced. Ｏ H can be reduced.

[0134] When forming a metal oxide film, a low substrate temperature is preferable. For example, it is preferable to form the metal oxide film without heating the substrate. This reduces the number of crystal grains generated during the formation of the metal oxide film, resulting in a metal oxide film with low crystallinity. The substrate temperature during metal oxide film formation is preferably between room temperature (e.g., 25°C) and 150°C, more preferably between room temperature and 100°C, more preferably between room temperature and 80°C, and more preferably between room temperature and 50°C. In particular, it is preferable to form the metal oxide film at room temperature or without heating the substrate. Note that the substrate temperature during metal oxide film formation is not limited to the above range.

[0135] When using the ALD method for depositing metal oxide films, it is preferable to use a film deposition method such as the thermal ALD method or the PEALD (Plasma Enhanced ALD) method. The thermal ALD method is preferred because it exhibits extremely high coverage. The PEALD method is preferred because, in addition to exhibiting high coverage, it allows for low-temperature film deposition.

[0136] Metal oxide films can be formed, for example, by the ALD method using a precursor containing the constituent metal elements and an oxidizing agent.

[0137] For example, when forming an indium oxide film, an indium-containing precursor can be used. Examples of indium-containing precursors include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, indium(III) chloride, [3-(dimethylamino)propyl]dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amide]-indium.

[0138] Examples of oxidizing agents include ozone, oxygen, hydrogen peroxide, and water.

[0139] Methods for controlling the composition of the resulting film include adjusting one or more of the type of raw material gas, the flow rate ratio of the raw material gases, the duration of the raw material gas flow, and the order in which the raw material gases are flowed. By adjusting these factors, the composition of the metal oxide film can be controlled. Furthermore, by adjusting these factors, it is also possible to deposit a metal oxide film with a continuously changing composition.

[0140] It is preferable to use a high temperature for the heat treatment after forming a metal oxide film or after processing the metal oxide film into island shapes. By increasing the heat treatment temperature, the crystallinity of the semiconductor layer 18 can be improved. In the semiconductor layer 18, regions with low crystallinity (e.g., amorphous regions) may exist between crystal grains. In particular, if regions with low crystallinity exist in the channel formation region, there is a risk that the field-effect mobility of the transistor will decrease due to carrier scattering. By increasing the heat treatment temperature, the grain size of the crystal grains increases, and the regions with low crystallinity between crystal grains can be reduced. This makes it possible to create a transistor with high field-effect mobility. In addition, by increasing the heat treatment temperature, the grain size of the crystal grains contained in the semiconductor layer 18 may increase. By increasing the heat treatment temperature, defects in the semiconductor layer 18 can be further reduced. Furthermore, impurities contained in the semiconductor layer 18 or adsorbed on the surface can be efficiently removed by the heat treatment.

[0141] The temperature for the heat treatment is preferably 100°C or higher and below the strain point of the substrate, more preferably 200°C or higher and 670°C or lower, more preferably 300°C or higher and 670°C or lower, more preferably 350°C or higher and 670°C or lower, more preferably 400°C or higher and 670°C or lower, and more preferably 450°C or higher and 670°C or lower. It is preferable that the temperature of the substrate during the heat treatment falls within the above temperature range. However, the temperature of the substrate during the heat treatment is not limited to the above range.

[0142] The heat treatment can be carried out in an atmosphere containing one or more noble gases, nitrogen, or oxygen. Dry air (CDA: Clean Dry Air) can be used as the nitrogen-containing or oxygen-containing atmosphere. It is preferable to carry out the heat treatment in an oxygen-containing atmosphere. Performing the heat treatment in an oxygen-containing atmosphere may enhance effects such as defect reduction and increased grain size. CDA can be suitably used as the atmosphere for the heat treatment. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with a very low content of hydrogen, water, etc., it is possible to prevent hydrogen, water, etc. from being incorporated into the semiconductor layer 18 as much as possible.

[0143] The apparatus used for the heat treatment is not particularly limited, and for example, an apparatus that heats by heat conduction or thermal radiation from a heating element can be used. For example, an oven or a rapid thermal annealing (RTA) apparatus can be used for the heat treatment. As an RTA apparatus, an LRTA (Lamp RTA) apparatus that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp can be used. Examples of such lamps include halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Alternatively, as an RTA apparatus, a GRTA (Gas RTA) apparatus that heats the workpiece using high-temperature gas can be used. By using an RTA apparatus, the heat treatment time can be shortened. The treatment time is preferably 1 minute or more and 10 minutes or less, more preferably 3 minutes or more and 10 minutes or less, and more preferably 5 minutes or more and 10 minutes or less. Furthermore, when using an RTA device and shortening the heat treatment time, the heating temperature can be set above the strain point of the substrate. This further shortens the heat treatment time. Typically, a heat treatment of 6 minutes at 650°C can be used with a GRTA device. In a method for manufacturing a semiconductor device according to one aspect of the present invention, transistors with good electrical characteristics and high reliability can be obtained even when the heat treatment temperature is low (e.g., 350°C). Therefore, semiconductor devices can be produced with a high yield even in production facilities using large glass substrates (e.g., G8.5) where it is difficult to raise the heat treatment temperature. When using an oven for heat treatment, a heat treatment of 1 hour at 350°C can typically be used.

[0144] The grain size of the crystal grains contained in the semiconductor layer 18 is preferably 0.1 μm or larger, more preferably 0.2 μm or larger, more preferably 0.3 μm or larger, more preferably 0.4 μm or larger, more preferably 0.5 μm or larger, more preferably 0.6 μm or larger, and more preferably 0.7 μm or larger. Since a larger grain size is preferable, no upper limit is set for the grain size. Note that the grain size of the crystal grains is not limited to the above range.

[0145] The crystallinity of the semiconductor layer 18 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods can be used for the analysis.

[0146] The grain size of the crystal grains contained in the semiconductor layer 18 can be analyzed, for example, by transmission electron microscopy (TEM), scanning transmission electron microscopy (STEM), or electron backscatter diffraction (EBSD or EBSP). Alternatively, a combination of these methods can be used for analysis. For example, the average grain size of multiple crystal grains can be used as the grain size. Furthermore, the grain size of a crystal grain can be defined, for example, as the diameter of a circle with the same area as the crystal grain. This diameter is sometimes called the equivalent diameter. Also, for cubic In ２ O ３ The crystal structure of this material belongs, for example, to space group Ia-3 (space group number 206).

[0147] In this specification, a grain boundary refers to, for example, the boundary between adjacent grains with different crystal orientations. Therefore, in this specification, boundaries between adjacent grains with the same crystal orientation are not included in grain boundaries. For example, even if a boundary is observed between two grains in a TEM image, if the crystal orientations of those two grains are the same or approximately the same, the boundary may not be called a grain boundary. Also, in EBSD, if the difference in crystal orientation between adjacent measurement points is small (for example, if the difference in crystal orientation is less than 5 degrees), these measurement points can be considered to belong to the same grain.

[0148] In this specification, space groups are denoted using the international notation (or Hermann-Mauguin notation) Short notation. In addition, space group numbers from the International Tables for Crystallography Volume A (hereinafter also referred to as ITA) may be included. Furthermore, Miller indices are used to indicate crystal planes and crystal directions. In crystallography, space groups, crystal planes, and crystal directions are indicated by a bar above the number, but in this specification, due to formatting constraints, a minus sign (-) may be placed before the number instead of a bar above it. In addition, individual orientations indicating directions within a crystal are indicated by [ ], collective orientations indicating all equivalent directions are indicated by < >, individual planes indicating crystal planes are indicated by ( ), and collective planes with equivalent symmetry are indicated by {}. Note that even with the same space group number, the notation for the space group may differ depending on how the crystal axis is defined.

[0149] When the same material is used for semiconductor layers 18a, 18b, and 18c, a single crystal grain may grow across two or more of these semiconductor layers during the crystallization of the semiconductor layer 18. In particular, if no interface is formed between these semiconductor layers, a single crystal grain may grow across two or more of these semiconductor layers. Therefore, in TEM observation of the cross-section of the semiconductor layer 18, one or more crystal grains spanning semiconductor layers 18a and 18b, crystal grains spanning semiconductor layers 18b and 18c, and crystal grains spanning semiconductor layers 18a, 18b, and 18c may be observed. The existence of a crystal grain spanning semiconductor layers 18a, 18b, and 18c can also be said to mean that semiconductor layers 18a, 18b, and 18c have such a crystal grain. The growth of a crystal grain across two or more semiconductor layers is preferable because it can increase the grain size of the crystal grain. Furthermore, for example, in crystal grains spanning semiconductor layers 18a, 18b, and 18c, a grain boundary with an adjacent crystal grain may be formed in the thickness direction of the semiconductor layer 18. When the boundaries between semiconductor layers cannot be clearly identified, it can be said that one or more crystal grains spanning the first and second regions, the second and third regions, and the first, second, and third regions may be observed.

[0150] The grain size of the crystal grains can also be confirmed, for example, by optical microscopy or scanning electron microscopy (SEM). Furthermore, by creating irregularities on the surface of the semiconductor layer 18 using etchants with different etching rates depending on the crystal plane or crystallinity, the crystal grains can be more easily observed with an optical microscope or scanning electron microscope (SEM). When an indium oxide film is used as the semiconductor layer 18, the crystal grains of indium oxide can be more easily observed by using an etchant containing an acid. For example, one or more of phosphoric acid, oxalic acid, nitric acid, and hydrochloric acid can be used as the acid. However, if the etching rate is too fast, a part of the semiconductor layer 18 may disappear, making it difficult to observe the crystal grains. Therefore, it is preferable to adjust the etching rate by controlling the concentration, temperature, and processing time of the etchant so that the semiconductor layer 18 does not disappear but its thickness is reduced (also called half-etching). By performing half-etching, it becomes possible to easily observe the crystal grains.

[0151] Furthermore, if the thickness of the semiconductor layer 18 is thin, it may be difficult to evaluate the crystallinity and grain size of the semiconductor layer 18.

[0152] It is preferable that the concentration of impurities in the channel-forming region be low. It is also preferable that the channel-forming region be of high purity. In the channel-forming region, impurities can act as carrier scattering sources and thus can be a factor in reducing field-effect mobility. Furthermore, impurities can also be a factor in inhibiting crystal growth.

[0153] Examples of impurities in the indium oxide film include gallium, zinc, boron, aluminum, and silicon. In the channel-forming region, the concentration of each of these impurities is preferably 1 atomic% or less, more preferably 0.1 atomic% or less, and even more preferably 0.01 atomic% (100 ppm) or less. The aforementioned concentrations are the concentrations of each element when the sum of the concentrations of all elements detected in the measurement region is taken as 100%. ppm is an abbreviation for "parts per million," and 1 ppm is 1 × 10⁻¹⁶. −６That is the case.

[0154] For analyzing the concentration of impurities in the semiconductor layer 18, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used. When using XPS analysis, the concentration distribution in the depth direction (also known as the thickness direction) can be determined by combining ion sputtering from the front or back side of the sample with XPS analysis. However, in areas with low concentrations, quantitative analysis may be difficult or the concentration may fall below the detection limit.

[0155] The concentrations of gallium, zinc, boron, aluminum, and silicon in the channel-forming region are, respectively, 1 × 10⁻⁶. ２０ atoms / cm ３ The following is preferable, and moreover, 5 × 10 １９ atoms / cm ３ The following is preferable, and moreover, 3 × 10 １９ atoms / cm ３ The following are preferable, and moreover, 1 × 10 １９ atoms / cm ３ The following is preferable, and moreover, 3 × 10 １８ atoms / cm ３ The following are preferable, and moreover, 1 × 10 １８ atoms / cm ３ The following are preferable.

[0156] By using an indium oxide film with large grain size and low impurity concentration in the transistor, the field-effect mobility of the transistor can be increased to 50 cm⁻¹. ２ / (V・s) or more, and even 100 cm ２ / (V・s) or more, and even 150cm ２ / (V・s) or more, and even 200 cm ２ / (V・s) or more, and even 250 cm ２ It can be set to (V・s) or more.

[0157] As mentioned above, by using indium oxide in the semiconductor layer, a transistor with a large on-current can be made. Therefore, a semiconductor device that operates at high speed can be made. When a semiconductor device according to one aspect of the present invention is applied to a display device, a display device that operates at high speed and has high display quality can be made. Furthermore, because transistors using indium oxide in the semiconductor layer have high field-effect mobility, a large on-current can be obtained even with a small channel width. Therefore, the area occupied by the transistor can be reduced, and thus the area occupied by the semiconductor device can be reduced. When a semiconductor device according to one aspect of the present invention is applied to the pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be made. Furthermore, when a semiconductor device according to one aspect of the present invention is applied to the drive circuit of a display device (for example, one or both of the gate line drive circuit and the source line drive circuit), the area occupied by the drive circuit can be reduced, and a narrow-bezel display device can be made.

[0158] In Figure 1B, the thicknesses T18a of semiconductor layer 18a, T18b of semiconductor layer 18b, and T18c of semiconductor layer 18c are indicated by solid arrows. Thicknesses T18a, T18b, and T18c are the thicknesses of each layer in the region of semiconductor layer 18 that overlaps with the conductive layer 14 in a cross-sectional view. Note that thicknesses T18a, T18b, and T18c can be controlled by the processing time (also referred to as deposition time) during the deposition of semiconductor layers 18a, 18b, and 18c, respectively.

[0159] A thickness T18b is preferably thick. A thickness T18b is preferably thicker than either thickness T18a or thickness T18c. By increasing the thickness T18b of the semiconductor layer 18b, which is the main current path, a transistor with a large on-current can be made. However, if the thickness T18b is too thick, oxygen vacancies (V) in the semiconductor layer 18b may occur. Ｏ ) and V ＯAn increase in the amount of H can cause a shift in the transistor's threshold voltage, potentially leading to a larger cutoff current. The thickness T18b is preferably 1 nm to 30 nm, more preferably 2 nm to 30 nm, more preferably 2 nm to 20 nm, more preferably 4 nm to 20 nm, and more preferably 4 nm to 10 nm. By setting the thickness T18b within the above range, a transistor with a large on-current can be made. Furthermore, by suppressing the shift in the threshold voltage, the cutoff current can be reduced, resulting in a normally-off transistor. Note that the thickness T18b is not limited to the above range.

[0160] It is preferable that thicknesses T18a and T18c are each thinner than thickness T18b. Furthermore, thicknesses T18a and T18c are preferably 0.5 nm to 10 nm, more preferably 0.5 nm to 6 nm, more preferably 0.5 nm to 4 nm, more preferably 0.5 nm to 3 nm, and more preferably 1 nm to 3 nm. If thickness T18c is too thick, the physical distance between the conductive layer 14, which functions as the first gate electrode, and the semiconductor layer 18b becomes longer, which may result in a decrease in field-effect mobility. On the other hand, if thickness T18c is too thin, the physical distance between the trap levels at the interface and near the interface of the insulating layer 16 and the semiconductor layer 18b, and the semiconductor layer 18b, which is the main current path, becomes shorter, which may result in a decrease in field-effect mobility. In addition, reliability may decrease. The same applies to thickness T18a. By setting the thicknesses T18a and T18c within the aforementioned ranges, a transistor with high field-effect mobility and high reliability can be obtained. Note that the thicknesses T18a and T18c are not limited to the aforementioned ranges.

[0161] The thickness T18a and thickness T18c can be the same or different. When the film quality and thickness T18a of the semiconductor layer 18a are the same as those of the semiconductor layer 18c, that is, when the first film deposition conditions and deposition time are the same as those of the third film deposition conditions and deposition time, the processing program (also called a recipe) used for deposition of the semiconductor layer 18a and the recipe used for deposition of the semiconductor layer 18c can be made common. This reduces the number of recipes to be managed in the manufacturing of semiconductor devices, thereby increasing productivity. Alternatively, the thickness T18c can be made thicker than the thickness T18a. When the insulating layer 16 is deposited, damage may occur at the interface between the insulating layer 16 and the semiconductor layer 18 and its vicinity. By increasing the thickness T18c, damage to the semiconductor layer 18b when the insulating layer 16 is deposited can be effectively suppressed. Furthermore, the relative sizes of thickness T18a and thickness T18c are not particularly limited; for example, a configuration in which thickness T18a is thicker than thickness T18c is also possible.

[0162] In some cases, the boundaries between semiconductor layer 18a and semiconductor layer 18b, and between semiconductor layer 18b and semiconductor layer 18c, cannot be clearly identified, making it impossible to measure the thicknesses T18a, T18b, and T18c.

[0163] Figures 1A and 1B show a configuration in which the transistor has a first gate electrode (here, a conductive layer 14) and a second gate electrode (here, a conductive layer 13), but the present invention is not limited to this. The transistor can have a configuration in which it has only one of the first gate electrode and the second gate electrode.

[0164] The following describes a configuration example that differs in some aspects from the aforementioned Configuration Example 1-1. Note that in the following, explanations of parts that overlap with Configuration Example 1-1 may be omitted. Furthermore, in the drawings shown below, parts having the same function as Configuration Example 1-1 may use the same hatching pattern and may not be labeled.

[0165] [Configuration Example 1-2] Figure 1C shows a schematic cross-sectional view of a transistor 10A that can be applied to a semiconductor device according to one aspect of the present invention.

[0166] Transistor 10A differs from transistor 10 primarily in that it does not have a conductive layer 13. Transistor 10A has a semiconductor layer 18, an insulating layer 16, an insulating layer 15, and a conductive layer 14. The insulating layer 15, semiconductor layer 18, insulating layer 16, and conductive layer 14 are stacked in this order. In transistor 10A, the conductive layer 14 functions as a gate electrode, and the insulating layer 16 functions as a gate insulating layer. By not providing a conductive layer 13, the manufacturing process can be simplified and productivity can be increased. Transistor 10A can be described as a single-gate type transistor. Transistor 10A can also be described as a top-gate type transistor.

[0167] By providing a semiconductor layer 18c between the insulating layer 16, which functions as a gate insulating layer, and the semiconductor layer 18b, a transistor can be made that achieves both high field-effect mobility and high reliability. Therefore, a semiconductor device can be made that achieves both high-speed operation and high reliability.

[0168] It is preferable to use a material that is difficult for substances to permeate in one or more of the layers constituting the insulating layer 15. This layer can also be said to function as a barrier film. By providing a layer that functions as a barrier film, it is possible to suppress the diffusion of impurities contained below the transistor 10A (for example, the substrate) into the transistor 10A.

[0169] In this specification, the term "barrier film" refers to a film that possesses barrier properties. Barrier properties refer to one or both of the following functions: a function that makes it difficult for the target substance to diffuse, thereby suppressing the permeation of the substance through the film (also known as low permeability), and a function that captures or fixes the substance (also known as gettering).

[0170] The barrier film can be made from, for example, one or more oxides having aluminum and / or hafnium, an oxide having magnesium, an oxide having gallium, a nitride having silicon, and a silicon nitride oxide. Typically, the barrier film can be made from one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, silicon nitride, and silicon nitride oxide.

[0171] Figure 1C shows a configuration in which an insulating layer 15 is provided, but the present invention is not limited to this. A configuration without an insulating layer 15 is also possible. By omitting the insulating layer 15, the process can be simplified and productivity can be increased.

[0172] Furthermore, transistor 10A and transistor 10 can be mounted on the same substrate by sharing some of the manufacturing processes. In that case, by also providing an insulating layer 15 to transistor 10A, the processes other than the formation of the conductive layer 13 can be shared, thereby increasing productivity.

[0173] If the conductive layer 13 is not provided, the semiconductor layer 18a can be omitted, as shown in the transistor 10B in Figure 1D. The semiconductor layer 18 has a two-layer structure consisting of semiconductor layer 18b and semiconductor layer 18c. For details on semiconductor layer 18b and semiconductor layer 18c, please refer to the previous description. By omitting the semiconductor layer 18a, the process can be simplified and productivity can be increased.

[0174] [Configuration Example 1-3] Figure 1E shows a schematic cross-sectional view of a transistor 10C that can be applied to a semiconductor device according to one aspect of the present invention.

[0175] Transistor 10C differs from transistor 10 primarily in that it does not have a conductive layer 14. Transistor 10C has a semiconductor layer 18, an insulating layer 16, an insulating layer 15, and a conductive layer 13. The conductive layer 13, insulating layer 15, semiconductor layer 18, and insulating layer 16 are stacked in this order. In transistor 10C, the conductive layer 13 functions as a gate electrode, and the insulating layer 15 functions as a gate insulating layer. By omitting the conductive layer 14, the manufacturing process can be simplified, and productivity can be increased. Transistor 10C can be described as a single-gate type transistor. Transistor 10C can also be described as a bottom-gate type transistor.

[0176] By providing a semiconductor layer 18a between the insulating layer 15, which functions as a gate insulating layer, and the semiconductor layer 18b, a transistor can be made that achieves both high field-effect mobility and high reliability. Therefore, a semiconductor device can be made that achieves both high-speed operation and high reliability.

[0177] The insulating layer 16 functions as a protective layer. Furthermore, one or more layers constituting the insulating layer 16 may be provided with a barrier layer. By providing a barrier layer, the diffusion of impurities contained in the layers above the transistor 10C into the transistor 10C can be suppressed. For details on the barrier layer, please refer to the previous description.

[0178] Figure 1E shows a configuration in which an insulating layer 16 is provided, but the present invention is not limited to this. A configuration without an insulating layer 16 is also possible. By omitting the insulating layer 16, the process can be simplified and productivity can be increased.

[0179] Furthermore, transistor 10C and transistor 10 can be mounted on the same substrate by sharing some manufacturing processes. In this case, by providing an insulating layer 16 to transistor 10C as well, the processes other than the formation of the conductive layer 14 can be shared, thereby increasing productivity. Also, transistor 10C, transistor 10A, and transistor 10 can be mounted on the same substrate by sharing some manufacturing processes.

[0180] If the conductive layer 14 is not provided, the semiconductor layer 18c can be omitted, as shown in the transistor 10D in Figure 1F. The semiconductor layer 18 has a two-layer structure consisting of semiconductor layer 18a and semiconductor layer 18b. The semiconductor layers 18a and 18b can be described in the previous section. By omitting the semiconductor layer 18c, the process can be simplified and productivity can be increased. However, if the semiconductor layer 18 is damaged when the insulating layer 16 is formed, it is preferable to provide the semiconductor layer 18c as shown in Figure 1E. This can suppress damage to the semiconductor layer 18b and result in a transistor with high field-effect mobility.

[0181] Here, an example configuration is shown in which the semiconductor layer 18 has a two-layer or three-layer structure, but the present invention is not limited to these. The semiconductor layer 18 can have a single-layer structure. For example, the semiconductor layer 18 can have a single-layer structure of semiconductor layer 18a, semiconductor layer 18b, or semiconductor layer 18c. Alternatively, the semiconductor layer 18 can have a stacked structure of four or more layers.

[0182] [Semiconductor Layer 18] The metal oxides that can be used in the semiconductor layer 18 (semiconductor layer 18a, semiconductor layer 18b, and semiconductor layer 18c) will be described in detail. As mentioned above, it is preferable that the metal oxide contains at least indium. Indium oxide can be suitably used as the metal oxide. Alternatively, for example, gallium oxide or zinc oxide can be used as the metal oxide. Alternatively, it is preferable that the metal oxide contains one or both of indium and zinc. Alternatively, it is preferable that the metal oxide has one or more elements selected from indium, element M, and zinc. Element M is a metal element or metalloid with a high bond energy with oxygen, for example, a metal element or metalloid with a higher bond energy with oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M present in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferable because they have high bonding energy with oxygen and similar ionic radii to indium or zinc. Furthermore, tin is more preferable because its tetravalent state enhances carrier mobility. In this specification, metallic elements and metalloid elements are sometimes collectively referred to as "metallic elements," and the term "metallic elements" as used here may include metalloid elements.

[0183] The semiconductor layer 18 is, for example, made of indium zinc oxide (In-Zn oxide, also known as IZO®), indium tin oxide (In-Sn oxide, also known as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also known as IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also known as IGTO), gallium zinc oxide (Ga-Zn oxide, also known as GZO), and aluminum zinc oxide (Al-Zn oxide). Other suitable materials include indium aluminum zinc oxide (also written as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also written as ITZO®), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO, IGZAO, or IAGZO), etc. Alternatively, silicon-containing indium tin oxide (also written as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc.

[0184] Furthermore, the metal oxide can be composed of one or more metal elements with high periodic numbers in the periodic table, either in place of indium or in addition to indium. The greater the overlap of the metal element orbitals, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including metal elements with high periodic numbers, the field-effect mobility of the transistor can be increased. Examples of metal elements with high periodic numbers include those belonging to the 5th period and those belonging to the 6th period. Specifically, these metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0185] Metal oxides may contain one or more nonmetallic elements. The presence of nonmetallic elements in metal oxides can increase carrier concentration or reduce the band gap, potentially improving the field-effect mobility of transistors. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0186] By increasing the ratio of indium atoms to the sum of all metal element atoms in the metal oxide, the field-effect mobility of the transistor can be increased. Furthermore, a transistor with a high on-current can be realized.

[0187] In this specification, the ratio of the number of indium atoms to the sum of the total number of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. If element M contains multiple elements, the sum of the ratios of the number of atoms of element M to the sum of the total number of atoms of all contained metal elements may be referred to as the element M content.

[0188] By increasing the zinc content in a metal oxide, a highly crystalline metal oxide is obtained, which suppresses the diffusion of impurities within the metal oxide. Therefore, fluctuations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.

[0189] By increasing the content of element M in the metal oxide, a metal oxide with a large band gap can be obtained. Furthermore, oxygen vacancies (V) can be added to the metal oxide. Ｏ The formation of oxygen deficiency (V) is suppressed, Ｏ This suppresses carrier generation caused by (), thereby preventing a shift in the transistor's threshold voltage. This allows for a smaller cutoff current, enabling a normally-off transistor. It also allows for a transistor with a small off-current. Furthermore, it suppresses fluctuations in the transistor's electrical characteristics, improving reliability.

[0190] The electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide applied to the semiconductor layer 18. Therefore, by varying the composition of the metal oxide according to the electrical characteristics and reliability required for the transistor, it is possible to create a semiconductor device that achieves both excellent electrical characteristics and high reliability.

[0191] When the metal oxide is an In-M-Zn oxide, it is preferable that the atomic ratio of In in the In-M-Zn oxide is equal to or greater than the atomic ratio of element M. Examples of such atomic ratios of metal elements in an In-M-Zn oxide include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, and In:M Compositions such as Zn=5:1:9, In:M:Zn=6:1:6, In:M:Zn=10:1:1, In:M:Zn=10:1:3, In:M:Zn=10:1:4, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, and compositions near these. In this specification, "nearby composition" includes a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-current or field-effect mobility of the transistor.

[0192] The atomic ratio of In in an In-M-Zn oxide can be less than the atomic ratio of element M. Examples of such atomic ratios of metal elements in an In-M-Zn oxide include In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6, and compositions close to these. By increasing the proportion of M atoms in the metal oxide, oxygen deficiency (V) can be reduced. Ｏ This can suppress the generation of ()

[0193] Furthermore, if element M comprises multiple elements, the sum of their atomic ratios can be used as the atomic ratio of element M.

[0194] By using a material with a high indium content in the semiconductor layer 18, the on-current or field-effect mobility of the transistor can be increased. Furthermore, the presence of element M allows for oxygen deficiency (V ＯThe generation of ) can be suppressed. The content of element M (the ratio of the number of atoms of element M to the sum of the number of atoms of all contained metal elements) is preferably 0.1% to 25%, more preferably 0.1% to 20%, more preferably 0.1% to 10%, more preferably 0.1% to 8%, more preferably 0.1% to 6%, and more preferably 0.1% to 4%. This makes it possible to make a transistor with good electrical properties. For example, it is preferable to use a metal oxide in which In:M:Zn = 40:1:10 or a nearby ratio. Element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, a metal oxide in which In:Sn:Zn = 40:1:10 or a nearby ratio can be suitably used. Alternatively, a metal oxide in which In:Al:Zn = 40:1:10 or a nearby ratio can be suitably used.

[0195] A metal oxide that does not contain element M can be applied to the semiconductor layer 18. When the metal oxide is an In-Zn oxide, examples of atomic ratios of the metal elements include In:Zn=1:1, In:Zn=2:1, In:Zn=1:2, In:Zn=3:1, In:Zn=3:2, In:Zn=2:3, In:Zn=4:1, In:Zn=4:3, In:Zn=5:1, In:Zn=5:2, In:Zn=5:3, In:Zn=5:4, In:Zn=5:6, In:Zn=5:7, In:Zn=5:8, In:Zn=5:9, In:Zn=7:1, In:Zn=10:1, In:Zn=10:3, In:Zn=10:7, and compositions near these. Furthermore, it is more preferable that the atomic ratio of In is greater than or equal to the atomic ratio of Zn. By increasing the atomic ratio of indium in a metal oxide, the on-current or field-effect mobility of a transistor can be increased.

[0196] For analyzing the composition of the semiconductor layer 18, for example, energy-dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled high-frequency plasma atomic emission spectroscopy (ICP-AES) can be used. Alternatively, a combination of these methods can be used for analysis. It is preferable to separate the peaks of the spectrum obtained by the analysis and then identify and quantify the elements. Note that for elements with low content, the actual content may differ from the content obtained by the analysis due to the effect of the analysis accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, it may be difficult to quantify the content of element M, or element M may be below the detection limit.

[0197] Furthermore, when depositing metal oxide films by sputtering, the composition of the deposited metal oxide film may differ from the composition of the sputtering target. In particular, the zinc content in the deposited metal oxide film may decrease to about 50% of the content in the sputtering target.

[0198] It is preferable to use a crystalline metal oxide for the semiconductor layer 18. Examples of crystalline metal oxide structures include CAAC (c-axis aligned crystal) structure, polycrystalline structure, microcrystalline structure, and nanocrystalline (nc: nano-crystal) structure. By using a crystalline metal oxide, the defect level density in the semiconductor layer 18 can be reduced, and a highly reliable semiconductor device can be realized.

[0199] The semiconductor layer 18 preferably uses CAAC-OS or nc-OS.

[0200] CAAC-OS has a plurality of layered crystals. The c-axis of the crystal is oriented in the normal direction of the formation surface. The semiconductor layer 18 preferably has layered crystals parallel or substantially parallel to the formation surface. For example, the semiconductor layer 18 preferably has layered crystals parallel or substantially parallel to the upper surface of the insulating layer 15. By adopting such a configuration, the layered crystals of the semiconductor layer 18 are formed parallel or substantially parallel to the channel length direction of the transistor, so that a transistor with a large on-current can be obtained.

[0201] When a metal oxide is used for the semiconductor layer 18, it is preferable to reduce the V Ｏ H as much as possible and make it highly pure intrinsic or substantially highly pure intrinsic. In this way, in order to obtain a metal oxide with sufficiently reduced V Ｏ H, it is necessary to remove impurities such as water and hydrogen in the metal oxide (which may be described as dehydration and dehydrogenation treatment), and supply oxygen to the metal oxide to repair oxygen vacancies (V Ｏ ). It is important to repair the oxygen vacancies (V Ｏ ). By using a metal oxide with sufficiently reduced impurities such as V Ｏ H in the channel formation region, a transistor with stable electrical characteristics can be obtained. In addition, supplying oxygen to the metal oxide to repair oxygen vacancies (V Ｏ ) may be referred to as an oxygen addition treatment.

[0202] The OS transistor has small fluctuations in electrical characteristics due to radiation irradiation, that is, high resistance to radiation, so it can be preferably used even in an environment where radiation can enter. It can be said that the OS transistor has high reliability against radiation. For example, the OS transistor can be preferably used for the pixel circuit of an X-ray flat panel detector. In addition, the OS transistor can be preferably used for semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton beams, and neutron beams).

[0203] The semiconductor layer 18 may have a layer-like substance that functions as a semiconductor. The layer-like substance is a general term for a group of materials having a layered crystal structure. The layer-like substance has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0204] Examples of the above layer-like substances include, for example, graphene, silicene, chalcogenides, etc. Chalcogenides are compounds containing chalcogens (elements belonging to Group 16). Further, examples of chalcogenides include transition metal chalcogenides, Group 13 chalcogenides, etc. Specific examples of transition metal chalcogenides applicable as the channel formation region of a transistor include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ [ ), tungsten selenide (typically WSe ２ ), tungsten telluride (typically WTe ２ [[ID=1 ] 5]), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ), etc. < (

[0205] The semiconductor device, which is one aspect of the present invention, will be described more specifically.

[0206] <Configuration Example 2> [Configuration Example 2-1] The top view (also referred to as a plan view) of the semiconductor device 20, which is one aspect of the present invention, is shown in FIG. 2A. The cross-sectional view of the cut surface along the dashed-dotted line A1 - A2 shown in FIG. 2A is shown in FIG. 2B, and the cross-sectional view of the cut surface along the dashed-dotted line B1 - B2 is shown in FIG. 2C. In FIG. 2A, a part of the components of the semiconductor device 20 (such as the gate insulating layer, etc.) is omitted. Regarding the top view of the semiconductor device, in the following drawings, a part of the components will be omitted in the same manner as in FIG. 2A.

[0207] The semiconductor device 20 has a transistor 100. The transistor 100 has a conductive layer 103 on a substrate 102, an insulating layer 105 on the conductive layer 103, a semiconductor layer 108 on the insulating layer 105, an insulating layer 106 on the semiconductor layer 108, and a conductive layer 104 on the insulating layer 106.

[0208] The insulating layer 106 has a region that is in contact with the upper surface of the semiconductor layer 108. The conductive layer 104 is provided on the insulating layer 106. The conductive layer 104 has a region that overlaps with the semiconductor layer 108 via the insulating layer 106. In the transistor 100, the conductive layer 104 functions as a first gate electrode, and the insulating layer 106 functions as a first gate insulating layer.

[0209] The conductive layer 103 has a region that overlaps with the semiconductor layer 108 via the insulating layer 105. The conductive layer 103 functions as a second gate electrode, and the insulating layer 105 functions as a second gate insulating layer. Furthermore, the conductive layer 103 has a region that overlaps with the conductive layer 104 via the insulating layer 105, the semiconductor layer 108, and the insulating layer 106.

[0210] The transistor 100 has gate electrodes (a first gate electrode and a second gate electrode) on both sides of the channel formation region, and can be described as a dual-gate type transistor.

[0211] The conductive layer 103, insulating layer 105, semiconductor layer 108, insulating layer 106, and conductive layer 104 correspond to the conductive layer 13, insulating layer 15, semiconductor layer 18, insulating layer 16, and conductive layer 14 shown in Figure 1A. For details on the conductive layer 103, insulating layer 105, semiconductor layer 108, insulating layer 106, and conductive layer 104, refer to the descriptions related to the conductive layer 13, insulating layer 15, semiconductor layer 18, insulating layer 16, and conductive layer 14. In the following, the conductive layer 103 may be described as a back gate electrode and the insulating layer 105 as a back gate insulating layer.

[0212] An insulating layer 195 is provided on the conductive layer 104 and the insulating layer 106, and an insulating layer 218 is provided on the insulating layer 195. The insulating layer 195 and the insulating layer 218 each function as protective layers for the transistor 100. It is also possible to omit the insulating layer 218.

[0213] The semiconductor layer 108 can have a single-layer structure or a stacked structure of two or more layers. It is preferable that the semiconductor layer 108 has a stacked structure. Figure 3 shows an enlarged view of the semiconductor layer 108 and its vicinity, as shown in Figure 2B. Figures 2B and others show a configuration in which the semiconductor layer 108 has a three-layer structure consisting of semiconductor layer 108a, semiconductor layer 108b on semiconductor layer 108a, and semiconductor layer 108c on semiconductor layer 108b. Semiconductor layer 108b is in contact with and sandwiched between semiconductor layers 108a and 108c. For details on semiconductor layers 108a, 108b, and 108c, refer to the descriptions relating to semiconductor layers 18a, 18b, and 18c.

[0214] Preferably, the conductivity of semiconductor layer 108b is higher than that of either semiconductor layer 108a or semiconductor layer 108c. This ensures that the main current path in transistor 10 is semiconductor layer 108b. On the other hand, it is preferable that semiconductor layer 108a and semiconductor layer 108c are denser and have fewer defects than semiconductor layer 108b. By sandwiching semiconductor layer 108b between semiconductor layers 108a and 108c, a transistor 100 can be made that achieves both high field-effect mobility and high reliability. Therefore, a semiconductor device 20 can be made that achieves both high-speed operation and high reliability.

[0215] In Figure 3, the thickness T108a of semiconductor layer 108a, the thickness T108b of semiconductor layer 108b, and the thickness T108c of semiconductor layer 108c are indicated by solid arrows. Thicknesses T108a, T108b, and T108c are the thicknesses of each layer in the region of semiconductor layer 108 that overlaps with the conductive layer 104 in a cross-sectional view. It is preferable that thickness T108b is thicker than either thickness T108a or thickness T108c. For thicknesses T108a and T108c, refer to the descriptions related to thicknesses T18a, T18b, and T18c.

[0216] The semiconductor layer 108 has a region that overlaps with the conductive layer 104 via the insulating layer 106, and a pair of regions (region 108P and region 108Q) that sandwich this region. Regions 108P and 108Q are regions that do not overlap with the conductive layer 104. In the transistor 100, the region of the semiconductor layer 108 that overlaps with the conductive layer 104 functions as a channel-forming region, region 108P functions as one of the source region and drain region, and region 108Q functions as the other of the source region and drain region. In the semiconductor layer 108, the channel-forming region is located between the source region and the drain region. For the sake of simplicity, the region of the semiconductor layer 108 that overlaps with the conductive layer 104 is sometimes referred to as the channel-forming region, but a region that does not overlap with the conductive layer 104 but overlaps with the conductive layer 103 can also function as a channel-forming region.

[0217] Figure 2B, etc., shows a configuration in which the edge of the insulating layer 106 coincides with, or roughly coincides with, the edge of the conductive layer 104. The edge of the insulating layer 106 is in contact with the upper surface of the semiconductor layer 108. It can also be said that the edge of the insulating layer 106 overlaps with, or is located on, the semiconductor layer 108. Furthermore, the insulating layer 106 does not overlap with either region 108P or region 108Q. It can also be said that the upper surface shape of the insulating layer 106 coincides with, or roughly coincides with, the conductive layer 104. The insulating layer 106 can be formed, for example, by processing using a resist mask for processing the conductive layer 104.

[0218] As shown in Figure 2B and other figures, it is preferable that the sides of the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 each have a tapered shape. This improves the coverage of the layers provided on the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 (for example, the insulating layer 195), and suppresses the occurrence of defects such as stepped breaks or porosity in these layers.

[0219] The insulating layer 195 has regions that are in contact with the upper and side surfaces of the semiconductor layer 108, the side surfaces of the insulating layer 106, the upper and side surfaces of the conductive layer 104, and the upper surface of the insulating layer 105.

[0220] The insulating layer 195 has regions in contact with region 108P and region 108Q. The insulating layer 195 also has an opening 147a reaching region 108P and an opening 147b reaching region 108Q. A conductive layer 112a is provided so as to cover the opening 147a. At the opening 147a, the conductive layer 112a is in contact with region 108P and connected to region 108P. A conductive layer 112b is provided so as to cover the opening 147b. At the opening 147b, the conductive layer 112b is in contact with region 108Q and connected to region 108Q. In the transistor 100, the conductive layer 112a functions as one of the source electrode and drain electrode, and the conductive layer 112b functions as the other of the source electrode and drain electrode. An insulating layer 218 is provided on the conductive layer 112a, the conductive layer 112b and the insulating layer 195.

[0221] By supplying impurities to the semiconductor layer 108 using the conductive layer 104, which functions as the gate electrode, as a mask, regions 108P and 108Q, which function as the source and drain regions, can be formed in a self-aligned manner. Transistor 100 can be described as a TGSA (Top Gate Self-Aligned) type transistor. In a TGSA type transistor, the physical distance between the conductive layers 112a and 112b, which function as the source and drain electrodes, and the conductive layer 104, which functions as the gate electrode, can be increased, thereby reducing the parasitic capacitance between them.

[0222] Regions 108P and 108Q contain impurities. By supplying impurities to the semiconductor layer 108, the electrical resistance of regions 108P and 108Q can be lowered. The concentration of impurities in regions 108P and 108Q is higher than the concentration of impurities in the channel-forming region. The elements contained in the impurities (hereinafter also referred to as the second element) can be one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and noble gases. Representative examples of noble gases include helium, neon, argon, krypton, and xenon. It is particularly preferable to use one or more of hydrogen, boron, phosphorus, aluminum, magnesium, and silicon as the second element.

[0223] For supplying impurities, methods such as plasma treatment or treatment utilizing thermal diffusion by heating can be used. In the case of plasma treatment, impurities can be supplied by generating plasma in a gas atmosphere containing the impurities to be supplied and performing plasma treatment. As a device for generating plasma, for example, a dry etching device, an ashing device, a plasma CVD device, or a high-density plasma CVD device can be used.

[0224] When hydrogen is used as the second element, by performing plasma processing in an atmosphere containing a hydrogen-containing gas using a plasma CVD apparatus, hydrogen can be supplied to regions of the semiconductor layer 108 that do not overlap with the conductive layer 104. This makes it possible to form regions 108P and 108Q containing impurities. Furthermore, by using a plasma CVD apparatus for supplying impurities and depositing the insulating layer 195, the supply of impurities and the deposition of the insulating layer 195 can be performed continuously within the apparatus, thereby increasing productivity. Moreover, by performing the supply of impurities and the deposition of the insulating layer 195 continuously in the same processing chamber, productivity can be further increased.

[0225] The method of supplying impurities is not limited to this, and for example, ion implantation can be suitably used. Ion implantation allows for highly precise control of the concentration profile in the depth direction by adjusting the ion acceleration energy and dose amount. The acceleration energy can be adjusted by the acceleration voltage in ion implantation. Furthermore, by using an ion implantation method that ionizes the source gas and supplies the ions after mass separation, it is possible to supply ions of a specific mass and increase the purity of the supplied impurities. Alternatively, productivity can be increased by using an ion implantation method that supplies ions without mass separation. Unless otherwise specified in this specification, the presence or absence of mass separation is not limited. Note that the method of supplying ions after mass separation is sometimes called ion implantation, and the method of supplying ions without mass separation is sometimes called ion doping.

[0226] When an element that readily bonds with oxygen is used as the second element, the second element removes oxygen from the semiconductor layer 108 and exists in a state bonded with oxygen. In addition, oxygen vacancies (V) exist in the semiconductor layer 108. Ｏ ) is generated. If an element that becomes stable when bonded with oxygen is used as the second element, the second element in the semiconductor layer 108 exists stably in an oxidized state, so it is less likely to desorb due to heat applied during the semiconductor device manufacturing process, and the electrical resistance of regions 108P and 108Q can be kept low. For this reason, it is preferable to use an element as the second element in which its oxide can exist as a solid at least at the temperature during the manufacturing process. Boron and phosphorus, or both, can be suitably used as the second element.

[0227] When boron is used as the second element, the boron contained in regions 108P and 108Q can exist in a state bonded with oxygen. This is evident in XPS analysis, B ２ O ３ This can be confirmed by observing spectral peaks caused by bonding. Furthermore, in XPS analysis, spectral peaks caused by the element boron in its elemental state may not be observed, or their intensity may be extremely low, almost at background levels.

[0228] Hydrogen, through its supply, can fill oxygen deficiencies (V Ｏ ) occurs, along with oxygen deficiency (V Ｏ By entering V Ｏ Because H is generated, the electrical resistance of regions 108P and 108Q can be efficiently reduced. Therefore, hydrogen can be suitably used as the second element.

[0229] In supplying impurities, it is preferable to adjust the supply conditions so that the concentration of impurities is highest on the surface of the semiconductor layer 108, or in a region close to the surface.

[0230] The raw material used to supply impurities can, for example, be a gas containing a second element. When supplying boron, typically B ２ H ６ Gas, or BF ３One or more gases can be used. Also, when supplying phosphorus, typically pH ３ Gases can be used. Alternatively, gases obtained by diluting these source gases with noble gases can also be used.

[0231] For example, CH4 is used as a raw material for supplying impurities. ４ , N ２ NH ３ , AlH ３ AlCl ３ SiH ４ Si ２ H ６ F ２ HF, H ２ , (C ５ H ５ ) ２ Mg and noble gases can be used. The raw materials are not limited to gases; solids or liquids can also be heated and vaporized for use.

[0232] The supply of impurities can be controlled by setting conditions such as acceleration voltage and dose amount, taking into consideration the composition, density, and thickness of the semiconductor layer 108. Note that impurities may also be supplied to regions of the insulating layer 105 that do not overlap with the conductive layer 104, resulting in those regions containing impurities.

[0233] The conductive layer 103 preferably has a region that protrudes from the edge of the conductive layer 104. This enhances the effect of making it difficult for electric fields generated outside the transistor to act on the channel formation region (also known as the electric field shielding effect).

[0234] The conductive layer 103 can be configured to be connected to either the conductive layer 112a or the conductive layer 112b. For example, by providing openings in the insulating layer 195 and the insulating layer 105 that reach the conductive layer 103, and providing the conductive layer 112a so as to cover these openings, the conductive layer 103 and the conductive layer 112a can be in contact. By connecting the conductive layer 112a and the conductive layer 103, the source electrode and the drain electrode and the back gate electrode can be brought to the same potential. For example, when the conductive layer 112a functions as the source electrode, a shift in the threshold voltage of the transistor 100 can be suppressed. Furthermore, the reliability of the transistor 100 can be improved.

[0235] The conductive layer 103 can be configured to be connected to the conductive layer 104. For example, by providing openings in the insulating layer 106 and the insulating layer 105 that reach the conductive layer 103, and providing the conductive layer 104 so as to cover the openings, the conductive layer 103 and the conductive layer 104 can be in contact. By connecting the gate electrode and the back gate electrode, the back gate electrode and the gate electrode can be brought to the same potential, and the on-current of the transistor 100 can be increased.

[0236] Figures 4A to 4C show examples of configurations different from those shown in Figures 2A to 2C. Figure 4A is a top view of a semiconductor device 20A according to one embodiment of the present invention. Figure 4B is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 4A, and Figure 4C is a cross-sectional view of the section along the dashed line B1-B2.

[0237] The semiconductor device 20A has a transistor 100A. Transistor 100A differs from transistor 100 shown in Figure 2A, etc., mainly in that it does not have a conductive layer 103. By not providing the conductive layer 103, the manufacturing process can be simplified and productivity can be increased. In transistor 100A, the conductive layer 104 functions as a gate electrode, and the insulating layer 106 functions as a gate insulating layer. Transistor 100A can be described as a single-gate type transistor. Transistor 100A can also be described as a top-gate type transistor.

[0238] By providing a semiconductor layer 108c between the insulating layer 106, which functions as a gate insulating layer, and the semiconductor layer 108b, a transistor can be made that achieves both high field-effect mobility and high reliability. Therefore, a semiconductor device can be made that achieves both high-speed operation and high reliability.

[0239] Figures 5A and 5B show configuration examples different from those shown in Figures 4A to 4C. Figures 5A and 5B are cross-sectional views of a semiconductor device 20B according to one embodiment of the present invention. A top view of the semiconductor device 20B can be found in Figure 4A. Figure 5A is a cross-sectional view of the section along the dashed-dotted line A1-A2 shown in Figure 4A, and Figure 5B is a cross-sectional view of the section along the dashed-dotted line B1-B2.

[0240] The semiconductor device 20B has a transistor 100B. If the conductive layer 103 is not provided, the semiconductor layer 108a can be omitted, as in the case of the transistor 100B. The semiconductor layer 108 has a two-layer structure consisting of semiconductor layer 108b and semiconductor layer 108c. For semiconductor layers 108b and 108c, please refer to the above description. By omitting the semiconductor layer 108a, the process can be simplified and productivity can be increased.

[0241] The materials that can be used for each component will be explained.

[0242] [Insulating layer 106, insulating layer 105] It is preferable that insulating layer 106 and insulating layer 105 each have one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxidized nitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, zinc gallium oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxidized nitrides include silicon oxidized nitride, aluminum oxidized nitride, gallium oxidized nitride, yttrium oxidized nitride, and hafnium oxidized nitride. Examples of nitride oxides include silicon nitride and aluminum nitride.

[0243] In this specification, the term "oxidogenic nitride" refers to a material whose composition contains more oxygen than nitrogen. The term "nitride oxide" refers to a material whose composition contains more nitrogen than oxygen.

[0244] The insulating layer 106 has a region that is in contact with the semiconductor layer 108. When a metal oxide is used for the semiconductor layer 108, it is preferable that at least a portion of the region of the insulating layer 106 that is in contact with the semiconductor layer 108 contains oxygen in order to improve the interfacial characteristics between the semiconductor layer 108 and the insulating layer 106. Specifically, it is preferable that the region of the insulating layer 106 that is in contact with the channel-forming region of the semiconductor layer 108 contains oxygen. One or more oxides and oxiditrides can be suitably used in the region of the insulating layer 106 that is in contact with the channel-forming region of the semiconductor layer 108. The same applies to the insulating layer 105. For example, it is preferable that the insulating layer 106 and the insulating layer 105 each contain silicon and oxygen, respectively. Silicon oxide or silicon oxiditride can be suitably used for the insulating layer 106 and the insulating layer 105, respectively.

[0245] In the case of miniature transistors, if the thickness of the gate insulating layer is reduced, the leakage current may increase. By using a material with a high dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxiditrides having aluminum and hafnium, oxides having silicon and hafnium, oxiditrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0246] In Figure 2B and other figures, the insulating layer 106 and insulating layer 105 are shown as single-layer structures, but the present invention is not limited to this. One or both of the insulating layer 106 and insulating layer 105 can be made into a laminated structure of two or more layers. When one or both of the insulating layer 106 and insulating layer 105 are made into a laminated structure, the insulating layer on the semiconductor layer 108 side preferably has an oxide or oxidizride. The insulating layer on the semiconductor layer 108 side can preferably be made of one or more of silicon oxide, silicon oxidizride, or aluminum oxide.

[0247] A barrier layer can be provided on one or more of the layers constituting the insulating layer 106. This suppresses the diffusion of metal components contained in the conductive layer 104 and impurities (e.g., water and hydrogen) contained in the layers formed on the transistor 100 into the semiconductor layer 108 via the insulating layer 106. Furthermore, it suppresses the diffusion of oxygen contained in the semiconductor layer 108 into the conductive layer 104 side via the insulating layer 106. This prevents oxygen deficiencies (V) in the semiconductor layer 108. ＯThis can suppress the formation of ) and prevent oxidation of the conductive layer 104 by oxygen contained in the semiconductor layer 108, thereby preventing an increase in the electrical resistance of the conductive layer 104. As a result, a transistor with good electrical characteristics and high reliability can be obtained. One or more oxides and oxidized nitrides can be used as the barrier film of the insulating layer 106, for example, aluminum oxide can be suitably used. Similarly, it is preferable to provide a layer that functions as a barrier film in one or more of the layers constituting the insulating layer 105. One or more nitrides and nitride oxides can be used as the barrier film of the insulating layer 105, for example, silicon nitride can be suitably used.

[0248] The insulating layer 106 can be, for example, a laminated structure of a silicon oxidizide film and a silicon nitride film on the silicon oxidizide film. Alternatively, the insulating layer 106 can be a laminated structure of a silicon oxidizide film and an aluminum oxide film on the silicon oxidizide film. Alternatively, the insulating layer 106 can be a laminated structure of an aluminum oxide film and a silicon oxidizide film on the aluminum oxide film. Alternatively, the insulating layer 106 can be a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film. Here, an example is shown in which the insulating layer 106 has a two-layer laminated structure, but the present invention is not limited to this. The insulating layer 106 can also have a laminated structure of three or more layers.

[0249] Figure 6A shows an example of a configuration different from those shown in Figures 2B and 2C. Figure 6A is a cross-sectional view of a semiconductor device 20C according to one aspect of the present invention. A top view of the semiconductor device 20C can be found in Figure 2A. Figure 6A is a cross-sectional view of the cross-section along the dashed line A1-A2 shown in Figure 2A.

[0250] The semiconductor device 20C has a transistor 100C. Transistor 100C differs from transistor 100 shown in Figure 2A, etc., in that its insulating layer 105 has a multilayer structure. Figure 6A shows a configuration in which the insulating layer 105 has a two-layer structure consisting of an insulating layer 105a and an insulating layer 105b on top of the insulating layer 105a.

[0251] For example, a layer that functions as a barrier film can be used as the insulating layer 105a. Furthermore, the insulating layer 105b in contact with the semiconductor layer 108 can be an oxide or an oxidized nitride. Typically, silicon nitride can be preferably used for the insulating layer 105a, and silicon oxidized nitride for the insulating layer 105b. Here, an example is shown where the insulating layer 105 has a two-layer laminated structure, but the present invention is not limited to this. The insulating layer 105 can also have a three-layer or more laminated structure.

[0252] [Conductive layer 112a, conductive layer 112b, conductive layer 103, conductive layer 104] Conductive layers 112a, 112b, 103, and 104 can each be a single layer or a laminated structure of two or more layers. Materials that can be used for conductive layers 112a, 112b, 103, and 104 include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys comprising one or more of the aforementioned metals. Conductive layers 112a, 112b, 103, and 104 can preferably be conductive materials with low electrical resistivity that contain one or more of copper, silver, gold, and aluminum. Copper or aluminum are particularly preferred because they are easy to mass-produce.

[0253] Conductive layers 112a, 112b, 103, and 104 can each be made of a conductive metal oxide (also called an oxide conductor (OC)). Examples of oxide conductors include indium oxide, zinc oxide, In-Sn oxide (ITO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (also called silicon-containing ITO or ITSO), zinc oxide with added gallium, and In-Ga-Zn oxide. Oxide conductors containing indium are particularly preferred due to their high conductivity.

[0254] When oxygen vacancies are formed in a metal oxide with semiconductor properties, and hydrogen is added to these vacancies, donor levels are formed near the conduction band. As a result, the metal oxide becomes highly conductive and turns into a conductor. A metal oxide that has become conductive can be called an oxide conductor.

[0255] The conductive layers 112a, 112b, 103, and 104 can each have a laminated structure consisting of a conductive film containing the aforementioned oxide conductor (metal oxide) and a conductive film containing a metal or alloy. By using a conductive film containing a metal or alloy, the wiring resistance can be reduced.

[0256] Conductive layers 112a, 112b, 103, and 104 can each be made of nitride conductors. Examples of nitride conductors include tantalum nitride and titanium nitride.

[0257] Conductive layers 112a, 112b, 103, and 104 can each be made of a Cu-X alloy film (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). Using a Cu-X alloy film allows for processing by wet etching, thus reducing manufacturing costs.

[0258] Note that conductive layers 112a, 112b, 103, and 104 can be made of the same material. Alternatively, at least one of them can be made of a different material.

[0259] It is preferable that the conductive layer 103 is made of a material that can withstand heat-inducing processes after the formation of the conductive layer 103 (for example, heat treatment in the formation of the semiconductor layer 108). It is preferable that the conductive layer 103 is made of a high-melting-point material that provides both heat resistance and conductivity. As a high-melting-point material, for example, tungsten and molybdenum, or both, can be suitably used.

[0260] Figure 6A shows an example of a configuration in which the conductive layer 104 has a laminated structure. Figure 6B shows an enlarged view of the conductive layer 104 and its vicinity. Figures 6A and 6B show a configuration in which the conductive layer 104 has a two-layer structure consisting of conductive layer 104a and conductive layer 104b on conductive layer 104a. The conductive layer 104a and conductive layer 104b can be made from the materials listed for conductive layer 112a, conductive layer 112b, conductive layer 103, and conductive layer 104, respectively.

[0261] It is preferable to use a conductive material with low electrical resistivity for the conductive layer 104b. For example, it is preferable that the conductive layer 104b contains one or more of copper, aluminum, gold, and silver. In particular, it is preferable that the conductive layer 104b contains one or more of copper or aluminum. This makes it possible to make the electrical resistance of the conductive layer 104 extremely low. It is preferable to use a conductive material for the conductive layer 104b that has lower electrical resistivity than the conductive layer 104a. Also, it is preferable that the thickness of the conductive layer 104b is greater than the thickness of the conductive layer 104a.

[0262] The conductive layer 104a can be made of a different material than the conductive layer 104b. It is preferable that the conductive layer 104a, which is provided in contact with the insulating layer 106, be made of a conductive material that is resistant to oxidation, or a conductive material that maintains low electrical resistance even when oxidized. This prevents the conductive layer 104 from being oxidized by oxygen contained in the insulating layer 106, thereby suppressing an increase in the electrical resistance of the conductive layer 104. For example, it is preferable to use one or more of titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, and nitrides containing tantalum and aluminum as the conductive layer 104a.

[0263] By providing a conductive layer 104a between the insulating layer 106 and the conductive layer 104b, the diffusion of metal components (e.g., copper) contained in the conductive layer 104b into the semiconductor layer 108 via the insulating layer 106 can be suppressed. This makes it possible to create a highly reliable transistor.

[0264] The angle θ104a between the side surface of the conductive layer 104a and the surface to be formed can be configured to be different from the angle θ104b between the side surface of the conductive layer 104b and the surface to be formed. Figure 6B shows a configuration in which angle θ104b is larger than angle θ104a. This reduces the step difference on the surface to be formed of the layer (for example, the insulating layer 195) provided on the semiconductor layer 108, the insulating layer 106, and the conductive layer 104, thereby suppressing defects such as step breaks or porosity in the layer. However, the present invention is not limited to this embodiment, and it is also possible to configure the angle θ104b to be the same as angle θ104a, or angle θ104b to be smaller than angle θ104a.

[0265] Figures 6A and 6B show a configuration in which the conductive layer 104 has a two-layer structure, but one aspect of the present invention is not limited thereto, and the conductive layer 104 can also have a laminated structure of three or more layers.

[0266] Figure 6C shows an example of a conductive layer 104 having a three-layer structure. The conductive layer 104 comprises a conductive layer 104a, a conductive layer 104b on conductive layer 104a, and a conductive layer 104c on conductive layer 104b. The conductive layer 104c can preferably be made from the materials listed for conductive layer 104a. Typically, titanium can be used for conductive layer 104a and conductive layer 104c, and copper or aluminum can be used for conductive layer 104b.

[0267] When a material that is easily oxidized is used for the conductive layer 104b, the surface of the conductive layer 104b may oxidize when forming the insulating layer 195, potentially increasing the electrical resistance of the conductive layer 104. Furthermore, there is a risk that metal components (e.g., copper) contained in the conductive layer 104b may diffuse into the surrounding layers. Therefore, by sandwiching the conductive layer 104b between conductive layers 104a and 104c, oxidation of the conductive layer 104b and diffusion of metal components contained in the conductive layer 104b into the surrounding layers can be suppressed. This prevents the electrical resistance of the conductive layer 104 from increasing and results in a highly reliable transistor.

[0268] [Insulating layer 195, insulating layer 218] The insulating layer 195 preferably has one or more inorganic insulating layers. The inorganic insulating layer can be made from the materials listed for insulating layer 106 and insulating layer 105. For example, the insulating layer 195 can preferably be made from one or more of silicon oxynitride, silicon nitride, silicon oxide nitride, and aluminum oxide.

[0269] As the insulating layer 218, either an inorganic insulating layer or an organic insulating layer, or both, can be used. The inorganic insulating layer can be made from the materials listed for insulating layer 106 and insulating layer 105. Examples of materials that can be used for the organic insulating layer include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimidoamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins. The organic insulating layer functions as a planarizing layer that reduces irregularities caused by the transistor.

[0270] It is preferable to provide a layer that functions as a barrier film on one or both of the insulating layer 195 and the insulating layer 218. This suppresses the diffusion of impurities (e.g., water and hydrogen) into the transistor from the outside, and suppresses a shift in the threshold voltage. Therefore, a highly reliable semiconductor device can be made. Furthermore, if impurities can diffuse into the semiconductor layer 108 via the conductive layer 112a and the conductive layer 112b, it is preferable to provide a layer that functions as a barrier film on the insulating layer 218. The barrier film can be described in the above description. The insulating layer 195 and the insulating layer 218 can preferably be one or more of, for example, silicon nitride, silicon oxide nitride, and aluminum oxide. When an aluminum oxide film is used as the barrier film, it is preferable because it has extremely high barrier properties even when thin.

[0271] The insulating layer 195 and the insulating layer 218 can each be a single-layer structure or a laminated structure.

[0272] Figure 7A shows an example of a configuration in which the insulating layer 218 has a laminated structure. The semiconductor device 20D shown in Figure 7A has a transistor 100D. An insulating layer 195 is provided on the transistor 100D, and an insulating layer 218 is provided on the insulating layer 195. For details on transistor 100D, please refer to the description relating to transistor 100C. Figure 7A shows a configuration in which the insulating layer 218 has a laminated structure of insulating layer 218a and insulating layer 218b on insulating layer 218a. It is preferable to provide a layer that functions as a barrier film on one or both of the insulating layer 218a and insulating layer 218b. This enhances the effect of suppressing the diffusion of impurities into the transistor from the outside. For example, aluminum oxide can be suitably used for insulating layer 218a, silicon nitride for insulating layer 218b, and silicon nitride oxide for insulating layer 195. Furthermore, the aluminum oxide film can be formed using the sputtering method, and the silicon nitride film and silicon nitride oxide film can be formed using the plasma CVD method, respectively. In this case, the sputtering method has lower coverage compared to the plasma CVD method. Therefore, by creating a laminated structure of an insulating layer 218a deposited using the sputtering method and an insulating layer 218b deposited using the plasma CVD method, the barrier properties of the insulating layer 218 can be further improved. Similarly, the insulating layer 195 can also be made into a laminated structure.

[0273] [Substrate 102] There are no major restrictions on the material of the substrate 102, but it must have at least enough heat resistance to withstand subsequent heat treatments. For example, single-crystal semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, or resin substrates made of silicon or silicon carbide can be used as the substrate 102. In addition, a substrate on which semiconductor elements are provided can be used as the substrate 102. A substrate with an insulating film formed on its surface can be used as the substrate 102. The shape of the substrate 102 is not particularly limited and can be circular or rectangular, for example.

[0274] A flexible substrate can be used as the substrate 102, and transistors 100, etc., can be formed directly on the flexible substrate. Alternatively, a release layer can be provided between the substrate 102 and the transistors 100, etc. By providing a release layer, after partially or completely completing the semiconductor device on it, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistors 100, etc., can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0275] Figure 7B shows an example of a configuration different from that shown in Figure 6C. Figure 7B is a cross-sectional view of a semiconductor device 20E according to one aspect of the present invention. A top view of the semiconductor device 20E can be found in Figure 2A. Figure 7B is a cross-sectional view of the cross-section along the dashed line A1-A2 shown in Figure 2A.

[0276] The semiconductor device 20E differs from the semiconductor device 20C shown in Figure 6C in that it has an insulating layer 183. The semiconductor device 20E has a transistor 100E. An insulating layer 195 is provided on the transistor 100E, an insulating layer 183 is provided on the insulating layer 195, and an insulating layer 218 is provided on the insulating layer 183. For details on transistor 100E, refer to the description for transistor 100C.

[0277] The insulating layer 183 is located between the conductive layer 112a, the conductive layer 112b, the insulating layer 218, and the insulating layer 195. The insulating layer 183 is provided so as to cover the insulating layer 195 and has regions that are in contact with the upper surface and side surfaces of the insulating layer 195. The insulating layer 183 also has a region that is in contact with region 108P at the opening 147a and a region that is in contact with region 108Q at the opening 147b. For example, after forming the insulating layer 195 having openings 147a and 147b, an insulating film is formed over the insulating layer 195. Then, by providing openings in the region of the insulating film that overlaps with opening 147a and the region that overlaps with opening 147b, the insulating layer 183 can be formed.

[0278] The insulating layer 183 preferably functions as a barrier film. This suppresses the diffusion of impurities (e.g., water and hydrogen) into the transistor from the outside, and suppresses the shift in the threshold voltage. Therefore, a highly reliable semiconductor device can be made. The barrier film can be described in the above description. The insulating layer 183 can preferably be one or more of silicon nitride, silicon oxide nitride, and aluminum oxide. When an aluminum oxide film is used as the barrier film, it is preferable because it has extremely high barrier properties even when thin. The insulating layer 183 can have a single-layer structure or a multilayer structure.

[0279] The following describes a configuration example that differs in some aspects from the aforementioned Configuration Example 2-1. Note that in the following, explanations of parts that overlap with Configuration Example 2-1 may be omitted. Furthermore, in the drawings shown below, parts having the same function as Configuration Example 2-1 may use the same hatching pattern and may not be labeled with reference numerals.

[0280] [Configuration Example 2-2] Figures 8A and 8B show cross-sectional views of a semiconductor device 20F according to one aspect of the present invention. A top view of the semiconductor device 20F can be found in Figure 2A. Figure 8A is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 2A, and Figure 8B is a cross-sectional view of the section along the dashed line B1-B2.

[0281] The semiconductor device 20F has a transistor 100F. Transistor 100F differs from transistor 100 shown in Figure 2B, etc., in that the insulating layer 106 is in contact with region 108P and region 108Q.

[0282] The insulating layer 106 has regions that are in contact with the upper and side surfaces of the semiconductor layer 108. An insulating layer 195 is provided on the insulating layer 106 and the conductive layer 104. The insulating layer 106 and the insulating layer 195 have openings 147a that reach region 108P and openings 147b that reach region 108Q. Conductive layers 112a and 112b are provided so as to cover openings 147a and 147b.

[0283] Regions 108P and 108Q can be formed by supplying impurities to the semiconductor layer 108 via the insulating layer 106, using the conductive layer 104 as a mask. The method for supplying impurities can be found in the previously described section. For example, ion implantation can be suitably used for supplying impurities. Furthermore, the supply of impurities can be controlled by setting conditions such as acceleration voltage and dose amount, taking into account the composition, density, and thickness of the insulating layer 106 and the semiconductor layer 108. Note that regions of the insulating layer 106 that do not overlap with the conductive layer 104 may also contain impurities due to the supply of impurities to those regions.

[0284] [Configuration Example 2-3] Figures 9A and 9B show cross-sectional views of a semiconductor device 20G, which is one embodiment of the present invention. A top view of the semiconductor device 20G can be found in Figure 2A. Figure 9A is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 2A, and Figure 9B is a cross-sectional view of the section along the dashed line B1-B2.

[0285] The semiconductor device 20G has a transistor 100G. Transistor 100G differs from transistor 100 shown in Figure 2B, etc., in that its insulating layer 106 has a region that protrudes more than the conductive layer 104.

[0286] The edges of the insulating layer 106 are located on the semiconductor layer 108, and the edges of the conductive layer 104 are located on the insulating layer 106. It can also be said that the edges of the insulating layer 106 are located outside the edges of the conductive layer 104. The insulating layer 106 has a region that overlaps with the conductive layer 104 and a region that does not overlap with the conductive layer 104 on the semiconductor layer 108.

[0287] The semiconductor layer 108 has a channel formation region, regions 108R and 108S that sandwich the channel formation region, and regions 108P and 108Q located outside of them. Regions 108R and 108S are regions of the semiconductor layer 108 that overlap with the insulating layer 106 and do not overlap with the conductive layer 104. Region 108R is located between the channel formation region and region 108P, and region 108S is located between the channel formation region and region 108Q.

[0288] Regions 108R and 108S function as buffer regions to mitigate the drain electric field. Since regions 108R and 108S do not overlap with the conductive layer 104, channels are hardly formed in these regions even when a gate voltage is applied to the conductive layer 104. It is preferable that the carrier concentration in regions 108R and 108S is higher than that in the channel formation region. This allows regions 108R and 108S to function as LDD (Lightly Doped Drain) regions.

[0289] Regions 108R and 108S can also be described as regions with similar or lower electrical resistance, similar or higher carrier concentration, similar or higher oxygen defect density, and similar or higher impurity concentration compared to the channel-forming region.

[0290] Regions 108R and 108S can also be described as regions with similar or higher electrical resistance, similar or lower carrier concentration, similar or lower oxygen defect density, and similar or lower impurity concentration, compared to regions 108P and 108Q.

[0291] By providing region 108R between the channel formation region and region 108P, the physical distance between the channel formation region and region 108P can be increased. Similarly, by providing region 108S, the physical distance between the channel formation region and region 108Q can be increased. This suppresses the diffusion of impurities contained in regions 108P and 108Q into the channel formation region. Therefore, a decrease in the electrical characteristics and reliability of the transistor can be suppressed.

[0292] The insulating layer 195 has regions that are in contact with the upper and side surfaces of the semiconductor layer 108, the upper and side surfaces of the insulating layer 106, and the upper and side surfaces of the conductive layer 104.

[0293] Figures 10A and 10B show configuration examples different from those shown in Figures 9A and 9B. Figure 10A is a top view of a semiconductor device 20H, which is one embodiment of the present invention. Figure 10B is a cross-sectional view of the section along the dashed-dotted line A1-A2 shown in Figure 10A. For a cross-sectional view of the section along the dashed-dotted line B1-B2, refer to Figure 8B.

[0294] The semiconductor device 20H has a transistor 100H. Transistor 100H differs from transistor 100G shown in Figure 9A, etc., in that conductive layers 112a and 112b are formed in the same process as conductive layer 104.

[0295] The insulating layer 106 has openings 147a and 147b that reach the semiconductor layer 108. Conductive layers 112a and 112b are provided so as to cover a portion of opening 147a and a portion of opening 147b. Conductive layer 112a has a region that contacts the semiconductor layer 108 at opening 147a, and conductive layer 112b has a region that contacts the semiconductor layer 108 at opening 147b.

[0296] Conductive layers 104, 112a, and 112b can be formed using the same material and the same process. For example, an insulating layer 106 having openings 147a and 147b is formed on a semiconductor layer 108. Then, a conductive film is deposited to cover the insulating layer 106, openings 147a and 147b, and the conductive layer 104, 112a, and 112b can be formed by processing the conductive film. By forming conductive layers 112a and 112b using the same process as conductive layer 104, the process can be simplified.

[0297] By supplying impurities to the semiconductor layer 108 using conductive layers 104, 112a, and 112b as masks, regions 108P and 108Q can be formed in a self-aligned manner. Regions 108P and 108Q are formed in regions of the semiconductor layer 108 that do not overlap with any of the conductive layers 104, 112a, 112b, and insulating layer 106. In addition, regions 108R and 108S are formed in regions of the semiconductor layer 108 that do not overlap with any of the conductive layers 104, 112a, and 112b, but overlap with the insulating layer 106.

[0298] The region of the semiconductor layer 108 that is in contact with the conductive layer 112a, and the region 108P in contact with said region, function as one of the source region and the drain region. The region of the semiconductor layer 108 that is in contact with the conductive layer 112b, and the region 108Q in contact with said region, function as the other of the source region and the drain region.

[0299] An insulating layer 195 is provided on the transistor 100H, and an insulating layer 218 is provided on the insulating layer 195. Alternatively, one or both of the insulating layers 195 and 218 may be omitted.

[0300] <Configuration Example 3> [Configuration Example 3-1] Figure 11A shows a top view of a semiconductor device 30, which is one embodiment of the present invention. Figure 11B shows a cross-sectional view of the cross-section along the dashed-dotted line A1-A2 shown in Figure 11A, and Figure 11C shows a cross-sectional view of the cross-section along the dashed-dotted line B1-B2.

[0301] The semiconductor device 30 has a transistor 200. The transistor 200 has a conductive layer 103 on a substrate 102, an insulating layer 105 on the conductive layer 103, a semiconductor layer 108 on the insulating layer 105, conductive layers 212a and 212b on the semiconductor layer 108, an insulating layer 106 on the semiconductor layer 108, conductive layers 212a and 212b, and a conductive layer 104 on the insulating layer 106.

[0302] In transistor 200, the conductive layer 104 functions as a first gate electrode, and the insulating layer 106 functions as a first gate insulating layer. The conductive layer 103 functions as a second gate electrode, and the insulating layer 105 functions as a second gate insulating layer.

[0303] The conductive layers 212a and 212b are provided between the semiconductor layer 108 and the insulating layer 106. In the transistor 200, the conductive layer 212a functions as one of the source electrode and drain electrode, and the conductive layer 212b functions as the other of the source electrode and drain electrode.

[0304] The conductive layer 212a and the conductive layer 212b each have a region in contact with the upper surface of the semiconductor layer 108. The region of the semiconductor layer 108 in contact with the conductive layer 212a functions as one of the source region and the drain region. The region of the semiconductor layer 108 in contact with the conductive layer 212b functions as the other of the source region and the drain region. Among the semiconductor layer 108, the region overlapping the conductive layer 103 via the insulating layer 105 between the source region and the drain region functions as a channel formation region.

[0305] The transistor 200 has a region where the source electrode and the drain electrode (conductive layer 212a and conductive layer 212b) are in contact with the upper surface of the semiconductor layer 108, and can be said to be a top contact type transistor. Further, the transistor 200 has gate electrodes (first gate electrode and second gate electrode) on both sides sandwiching the channel formation region, and can be said to be a dual gate type transistor.

[0306] A top contact type transistor can reduce the number of masks used in manufacturing the transistor, so that the manufacturing cost of the semiconductor device can be kept low.

[0307] Note that there may be a recess in a region that does not overlap with either the conductive layer 212a or the conductive layer 212b of the semiconductor layer 108. For example, a conductive film can be formed on the semiconductor layer 108, and the conductive layer 212a and the conductive layer 212b can be formed by processing the conductive film. When processing the conductive film, a recess may be formed in the semiconductor layer 108 due to removal of a part of the semiconductor layer 108. In this case, it is preferable to increase the thickness of the semiconductor layer 108c so that the semiconductor layer 108c of the channel formation region remains. For example, in the region overlapping the conductive layer 212a, it is preferable to make the thickness of the semiconductor layer 108c thicker than the thickness of the semiconductor layer 108a. By leaving the semiconductor layer 108c of the channel formation region, the semiconductor layer 108b can be separated from the interface between the insulating layer 106 and the semiconductor layer 108, and the trap levels at the interface and in the vicinity of the interface of the semiconductor layer 108b can be reduced.

[0308] An insulating layer 218 is provided on the conductive layer 104 and the insulating layer 106. The insulating layer 218 functions as a protective layer of the transistor 200.

[0309] FIGS. 11A to 11C show a configuration in which the transistor has a first gate electrode (here, the conductive layer 104) and a second gate electrode (here, the conductive layer 103), but one aspect of the present invention is not limited thereto. The transistor may have a configuration having only one of the first gate electrode and the second gate electrode.

[0310] Configuration examples different from the configuration shown in FIGS. 11A to 11C are shown in FIGS. 12A to 12C. FIG. 12A is a top view of a semiconductor device 30A which is one aspect of the present invention. FIG. 12B is a cross-sectional view of a cut surface along the dashed-dotted line A1 - A2 shown in FIG. 12A, and FIG. 12C is a cross-sectional view of a cut surface along the dashed-dotted line B1 - B2.

[0311] The semiconductor device 30A has a transistor 200A. The transistor 200A is mainly different from the transistor 200 shown in FIG. 11A etc. in that it does not have the conductive layer 104. By not providing the conductive layer 104, the process can be simplified and the productivity can be increased. In the transistor 200A, the conductive layer 103 functions as a gate electrode, and the insulating layer 105 functions as a gate insulating layer. The transistor 200A is a so-called bottom gate type transistor having a gate electrode below the semiconductor layer 108, and can be called a BGTC (Bottom Gate Top Contact) type transistor.

[0312] By providing the semiconductor layer 108a between the insulating layer 105 functioning as a gate insulating layer and the semiconductor layer 108b, a transistor with both high field-effect mobility and high reliability can be obtained. Therefore, a semiconductor device with both high-speed operation and high reliability can be obtained.

[0313] Figures 13A and 13B show configuration examples different from those shown in Figures 12A to 12C. Figures 13A and 13B are cross-sectional views of a semiconductor device 30B according to one embodiment of the present invention. A top view of the semiconductor device 30B can be found in Figure 12A. Figure 13A is a cross-sectional view of the section along the dashed-dotted line A1-A2 shown in Figure 12A, and Figure 13B is a cross-sectional view of the section along the dashed-dotted line B1-B2.

[0314] The semiconductor device 30B has a transistor 200B. If the conductive layer 104 is not provided, the semiconductor layer 108c can be omitted, as in the case of transistor 200B. The semiconductor layer 108 has a two-layer structure consisting of semiconductor layer 108a and semiconductor layer 108b. Refer to the above description for semiconductor layer 108a and semiconductor layer 108b. By omitting the semiconductor layer 108c, the process can be simplified and productivity can be increased. However, if the semiconductor layer 108 is damaged when the insulating layer 106 is formed, it is preferable to provide the semiconductor layer 108c as shown in Figures 12B and 12C. This can suppress damage to the semiconductor layer 108b and result in a transistor with high field-effect mobility.

[0315] Figures 14A to 14C show configuration examples different from those shown in Figures 11A to 11C. Figure 14A is a top view of a semiconductor device 30C according to one embodiment of the present invention. Figure 14B is a cross-sectional view of the section along the dashed-dotted line A1-A2 shown in Figure 14A, and Figure 14C is a cross-sectional view of the section along the dashed-dotted line B1-B2.

[0316] The semiconductor device 30C has a transistor 200C. Transistor 200C differs from transistor 200 shown in Figure 11A, etc., in that it does not have a conductive layer 103. By not providing the conductive layer 103, the manufacturing process can be simplified and productivity can be increased. In transistor 200C, the conductive layer 104 functions as a gate electrode, and the insulating layer 106 functions as a gate insulating layer. Transistor 200C is a so-called top-gate type transistor, having a gate electrode above the semiconductor layer 108, and can be called a TGTC (Top Gate Top Contact) type transistor.

[0317] By providing a semiconductor layer 108c between the insulating layer 106, which functions as a gate insulating layer, and the semiconductor layer 108b, a transistor can be made that achieves both high field-effect mobility and high reliability. Therefore, a semiconductor device can be made that achieves both high-speed operation and high reliability.

[0318] Figures 15A and 15B show configuration examples different from those shown in Figures 14A to 14C. Figures 15A and 15B are cross-sectional views of a semiconductor device 30D according to one embodiment of the present invention. A top view of the semiconductor device 30D can be seen by referring to Figure 14A. Figure 15A is a cross-sectional view of the section along the dashed-dotted line A1-A2 shown in Figure 14A, and Figure 15B is a cross-sectional view of the section along the dashed-dotted line B1-B2.

[0319] The semiconductor device 30D has a transistor 200D. If the conductive layer 103 is not provided, the semiconductor layer 108a can be omitted, as in the case of the transistor 200D. The semiconductor layer 108 has a two-layer structure consisting of semiconductor layer 108b and semiconductor layer 108c. For semiconductor layers 108b and 108c, please refer to the above description. By omitting the semiconductor layer 108a, the process can be simplified and productivity can be increased.

[0320] The following describes a configuration example that differs in some aspects from the aforementioned Configuration Example 3-1. Note that in the following, explanations of parts that overlap with Configuration Example 3-1 may be omitted. Furthermore, in the drawings shown below, parts having the same function as Configuration Example 3-1 may use the same hatching pattern and may not be labeled with reference numerals.

[0321] [Configuration Example 3-2] Figures 16A and 16B show cross-sectional views of a semiconductor device 30E, which is one embodiment of the present invention. A top view of the semiconductor device 30E can be found in Figure 11A. Figure 16A is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 11A, and Figure 16B is a cross-sectional view of the section along the dashed line B1-B2.

[0322] The semiconductor device 30E has a transistor 200E. The transistor 200E mainly differs from the transistor 200 shown in Figure 11B, etc., in that it has an insulating layer 187.

[0323] The insulating layer 187 is provided on the semiconductor layer 108. The insulating layer 187 has a region that overlaps with the conductive layer 103 via the semiconductor layer 108 and the insulating layer 105. Part of the conductive layer 212a and part of the conductive layer 212b are provided on the insulating layer 187.

[0324] The insulating layer 187 functions as a channel protection film that protects the channel formation region when forming the conductive layers 212a and 212b. The conductive layers 212a and 212b can be formed by providing the insulating layer 187 on the semiconductor layer 108, depositing a conductive film on the insulating layer 187, and processing the conductive film. Since the channel formation region is not exposed during the deposition and processing of the conductive film, damage to the channel formation region can be suppressed. Therefore, a transistor with good electrical characteristics can be obtained. A transistor having a channel protection film, such as transistor 200E, can be called a channel-protected transistor. On the other hand, a transistor without a channel protection film (for example, transistors 200 to 200D) can be called a channel-etched transistor.

[0325] The insulating layer 187 has a region that is in contact with the semiconductor layer 108. Preferably, at least a portion of the region of the insulating layer 187 that is in contact with the semiconductor layer 108 contains oxygen. For example, the insulating layer 187 preferably contains silicon and oxygen. Silicon oxide or silicon oxynitride can preferably be used for the insulating layer 187.

[0326] Figures 17A and 17B show configuration examples different from those shown in Figures 16A and 16B. Figure 17A is a top view of a semiconductor device 30F, which is one embodiment of the present invention. Figure 17B is a cross-sectional view of the section along the dashed-dotted line A1-A2 shown in Figure 17A. For a cross-sectional view of the section along the dashed-dotted line B1-B2, refer to Figure 16B.

[0327] The semiconductor device 30F has a transistor 200F. Transistor 200F differs from transistor 200E shown in Figure 16A, etc., in that its insulating layer 187 has openings 181a and 181b.

[0328] The insulating layer 187 has openings 181a and 181b that reach the semiconductor layer 108. Conductive layers 212a and 212b are provided so as to cover openings 181a and 181b. Conductive layer 212a has a region that contacts the semiconductor layer 108 at opening 181a, and conductive layer 212b has a region that contacts the semiconductor layer 108 at opening 181b.

[0329] Although Figures 11A to 17B show examples of top-contact type transistors, the present invention is not limited to these. For example, a bottom-contact type transistor can be constructed in which the conductive layers 212a and 212b are located between the semiconductor layer 108 and the insulating layer 105. Since the semiconductor layer 108 is formed after the conductive layers 212a and 212b are formed on the insulating layer 105, damage to the semiconductor layer 108 during the formation of the conductive layers 212a and 212b can be avoided.

[0330] The configuration examples shown in this embodiment, and the corresponding drawings, etc., can be appropriately combined with other configuration examples or drawings, etc., at least in part.

[0331] A method for manufacturing a semiconductor device according to one aspect of the present invention will be described. Note that explanations regarding the materials and formation methods of each element may be omitted if they have already been described.

[0332] Thin films (insulating films, semiconductor films, and conductive films, etc.) that constitute semiconductor devices can be deposited using sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), atomic layer deposition (ALD), and other methods. CVD methods include plasma enhanced chemical vapor deposition (PECVD) and thermal CVD. One type of thermal CVD method is metal-organic chemical vapor deposition (MOCVD).

[0333] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by wet deposition methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0334] When processing thin films that constitute semiconductor devices, lithography or similar methods can be used. Alternatively, thin films can be processed by nanoimprint lithography, sandblasting, lift-off methods, etc. Furthermore, island-shaped thin films can be directly formed by deposition methods using shielding masks such as metal masks.

[0335] There are two main methods of lithography. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and finally removing the resist mask. The other method involves forming a photosensitive thin film, then exposing and developing it to process the thin film into the desired shape.

[0336] In the lithography method, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, etc. can also be used. Further, exposure can also be performed by immersion lithography technology. Moreover, extreme ultraviolet (EUV) light or X-rays can be used as the light for exposure. Instead of the light used for exposure, an electron beam can also be used. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because extremely fine processing becomes possible. Note that when performing exposure by scanning a beam such as an electron beam, a photomask is not required.

[0337] For the etching of the thin film, one or more of a dry etching method, a wet etching method, and a sandblasting method can be used.

[0338] <Example of Fabrication Method 1> Here, an example of the fabrication method of the semiconductor device 20 shown in FIGS. 2A to 2C will be described using FIGS. 18A to 20C. FIGS. 18A to 20C show a cross-sectional view between the dashed-dotted line A1 - A2 shown in FIG. 2B and a cross-sectional view between the dashed-dotted line B1 - B2 shown in FIG. 2C side by side.

[0339] First, a conductive film is formed on the substrate 102, and the conductive film is processed to form the conductive layer 103. For the formation of the conductive film, a sputtering method can be preferably used.

[0340] Subsequently, an insulating layer 105 is formed on the conductive layer 103 and the substrate 102 (FIG. 18A). For the formation of the insulating layer 105, a sputtering method or a plasma CVD method can be preferably used.

[0341] Subsequently, a metal oxide film 108f that becomes the semiconductor layer 108 is formed on the insulating layer 105 (FIG. 18B). The metal oxide film 108f is provided in contact with the upper surface of the insulating layer 105. Here, a metal oxide film 108af that becomes the semiconductor layer 108a, a metal oxide film 108bf that becomes the semiconductor layer 108b, and a metal oxide film 108cf that becomes the semiconductor layer 108c are formed.

[0342] For metal oxide films 108af, 108bf, and 108cf, refer to the descriptions relating to the first, second, and third metal oxide films, respectively. Furthermore, for the film formation conditions of metal oxide films 108af, 108bf, and 108cf, refer to the descriptions relating to the first, second, and third film formation conditions mentioned above. It is preferable that the power density during film formation of metal oxide film 108af and metal oxide film 108cf is higher than the power density during film formation of metal oxide film 108bf. Also, it is preferable that the pressure during film formation of metal oxide film 108af and metal oxide film 108cf is lower than the pressure during film formation of metal oxide film 108bf.

[0343] It is particularly preferable that the metal oxide films 108af, 108bf, and 108cf use the same material. Furthermore, it is preferable that the metal oxide films 108af, 108bf, and 108cf are deposited continuously in the same processing chamber using the same sputtering target. This increases the productivity of semiconductor devices and reduces manufacturing costs. In addition, it is possible to suppress the adhesion of airborne impurities to the surface of the metal oxide film 108af and the surface of the metal oxide film 108bf.

[0344] Before forming the metal oxide film 108f, it is preferable to perform at least one of the following: a treatment to desorb water, hydrogen, and organic matter adsorbed on the surface of the insulating layer 105, and a treatment to supply oxygen into the insulating layer 105. For example, a heat treatment can be performed in a reduced-pressure atmosphere at a temperature of 70°C to 200°C. Alternatively, a plasma treatment can be performed in an oxygen-containing atmosphere. Alternatively, nitrous oxide (N) can be used. ２ Plasma treatment in an atmosphere containing an oxidizing gas such as 0) can supply oxygen to the insulating layer 105. Plasma treatment in an atmosphere containing nitrous oxide gas can suitably remove organic matter from the surface of the insulating layer 105 while supplying oxygen. After such treatment, it is preferable to continuously form a metal oxide film 108f without exposing the surface of the insulating layer 105 to the atmosphere.

[0345] Next, the metal oxide film 108f is processed into an island shape to form metal oxide layers 108F (metal oxide layer 108aF, metal oxide layer 108bF, and metal oxide layer 108cF) (Figure 18C). When indium oxide is used for the semiconductor layer 108, the metal oxide film 108f and metal oxide layer 108F can be called indium oxide layers or indium oxide films.

[0346] The metal oxide layer 108F can be suitably formed using a wet etching method. In this case, a portion of the insulating layer 105 in areas that do not overlap with the metal oxide layer 108F may be etched and thinned. However, by using a material with a high selectivity ratio for the insulating layer 105 during etching of the metal oxide film 108f, the thinning of the insulating layer 105 can be suppressed.

[0347] Next, a heat treatment is performed. The heat treatment causes the metal oxide layer 108F to crystallize, forming the semiconductor layer 108 (Figure 18D). The temperature, atmosphere, and apparatus used for the heat treatment can be found in the previously mentioned description.

[0348] A semiconductor layer 108 can be obtained by forming a metal oxide layer 108F by depositing a metal oxide film 108f with low crystallinity and processing the metal oxide film 108f into island shapes, and then crystallizing it by heat treatment. This makes it possible to increase the grain size of the crystal grains contained in the semiconductor layer 108. Furthermore, since the metal oxide film 108f can be processed into island shapes at a low crystallinity stage, processing becomes easier, and the productivity of semiconductor devices can be increased. However, the present invention is not limited to this embodiment, and a semiconductor layer 108 can be formed by depositing a metal oxide film 108f with low crystallinity, crystallizing it by heat treatment, and then processing it into island shapes.

[0349] By heat treatment, oxygen can also be supplied from the insulating layer 105 to the metal oxide film 108f or the semiconductor layer 108.

[0350] Note that heat treatment is not performed at this stage, and can be combined with heat treatment performed in a later step. In addition, a heat treatment in a later step (for example, a film formation step) may also serve as this heat treatment.

[0351] Next, an insulating film 106f is formed to cover the semiconductor layer 108 and the insulating layer 105, forming the insulating layer 106 (Figure 18E). For forming the insulating film 106f, plasma CVD, sputtering, or ALD methods can be suitably used.

[0352] When an oxide semiconductor is used for the semiconductor layer 108, it is preferable that the insulating layer 106 functions as a barrier film that suppresses the diffusion of oxygen. By having the function of the insulating layer 106 that suppresses the diffusion of oxygen, the detachment of oxygen from the semiconductor layer 108 is suppressed, and oxygen vacancies (V) are formed in the semiconductor layer 108. Ｏ This suppresses the increase of ). Furthermore, the diffusion of oxygen from the semiconductor layer 108 to the conductive layer 104 via the insulating layer 106 is suppressed, thereby suppressing oxidation of the conductive layer 104. As a result, a transistor with good electrical characteristics and high reliability can be made.

[0353] By increasing the temperature during film formation of the insulating film 106f, a gate insulating layer with fewer defects can be obtained. However, if the temperature during film formation of the insulating film 106f is high, oxygen will be desorbed from the semiconductor layer 108, resulting in oxygen vacancies and V in the semiconductor layer 108. Ｏ In some cases, the H content may increase. The substrate temperature during the formation of the insulating layer 106 is preferably 180°C to 450°C, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, and more preferably 300°C to 400°C. By setting the substrate temperature during the deposition of the insulating film 106f within the above range, defects in the insulating layer 106 can be reduced, and the detachment of oxygen from the semiconductor layer 108 can be suppressed. Therefore, a transistor with good electrical characteristics and high reliability can be obtained.

[0354] Before depositing the insulating film 106f, the surface of the semiconductor layer 108 can be subjected to plasma treatment. This plasma treatment can reduce impurities such as water adsorbed on the surface of the semiconductor layer 108. This reduces impurities at the interface between the semiconductor layer 108 and the insulating layer 106, enabling the realization of a highly reliable transistor. This is particularly suitable when the surface of the semiconductor layer 108 is exposed to the atmosphere between the formation of the semiconductor layer 108 and the deposition of the insulating film 106f. The plasma treatment can be performed in an atmosphere such as oxygen, ozone, nitrogen, nitrous oxide, or argon. Furthermore, it is preferable that the plasma treatment and the deposition of the insulating film 106f are performed continuously without exposure to the atmosphere.

[0355] After the insulating film 106f is formed, oxygen can be supplied to the insulating film 106f. As a method of supplying oxygen, for example, ion implantation or plasma treatment can be used. As the plasma treatment, a device that turns a gas into plasma using high-frequency power can be suitably used. Examples of devices that turn a gas into plasma using high-frequency power include a plasma CVD device, a plasma etching device, and a plasma ashing device. Plasma treatment is preferably carried out in an atmosphere containing oxygen. For example, oxygen, nitrous oxide (N) ２ O), Nitrogen dioxide (NO) ２ It is preferable to perform the plasma treatment in an atmosphere containing one or more of the following: carbon monoxide and carbon dioxide. The amount of oxygen supplied can be adjusted, for example, by the power and treatment time in the plasma treatment.

[0356] It is preferable to deposit a film 139 on the insulating film 106f (Figure 19A). Sputtering is preferably used to deposit the film 139. By depositing the film 139 in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 106f.

[0357] The conductivity of the film 139 is not required. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the film 139. For example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can be used as the film 139.

[0358] It is preferable to use an oxide material containing one or more of the same elements as the semiconductor layer 108 as the film 139. In particular, it is preferable to use an oxide semiconductor material applicable to the semiconductor layer 108.

[0359] When forming the film 139, the higher the oxygen flow rate ratio of the film-forming gas introduced into the processing chamber of the film-forming apparatus, or the higher the oxygen partial pressure in the processing chamber, the greater the amount of oxygen supplied to the insulating film 106f. The oxygen flow rate ratio is preferably 50% to 100%, more preferably 60% to 100%, more preferably 70% to 100%, more preferably 80% to 100%, and more preferably 90% to 100%. Typically, the oxygen flow rate ratio can be set to 100%. Note that the oxygen flow rate ratio can be interpreted as the ratio of the oxygen partial pressure to the pressure in the processing chamber.

[0360] Thus, by forming the film 139 by sputtering in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 106f during the formation of the film 139, while preventing oxygen from being released from the insulating film 106f. As a result, a large amount of oxygen can be trapped in the insulating film 106f. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 by subsequent heat treatment. As a result, oxygen vacancies and V in the semiconductor layer 108 can be reduced. Ｏ This allows for a reduction in H, resulting in a transistor that exhibits good electrical characteristics and is highly reliable.

[0361] It is preferable to perform a heat treatment after forming the film 139. By performing a heat treatment after forming the film 139, oxygen can be effectively supplied from the insulating film 106f to the semiconductor layer 108. In addition, oxygen can be supplied from the film 139 to the insulating film 106f.

[0362] The heat treatment temperature is preferably 150°C or higher and below the strain point of the substrate, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, more preferably 300°C to 400°C, and more preferably 350°C to 400°C. The heat treatment can be carried out in an atmosphere containing one or more noble gases, nitrogen, or oxygen. Dry air (CDA) can be used as the nitrogen-containing atmosphere or the oxygen-containing atmosphere. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with a minimum content of hydrogen, water, etc., it is possible to prevent hydrogen, water, etc. from being incorporated into the insulating film 106f as much as possible. The heat treatment can be carried out using an oven, RTA device, etc.

[0363] After the film 139 is formed, or after the aforementioned heat treatment, oxygen can be supplied to the insulating film 106f via the film 139. For example, ion implantation or plasma treatment can be used as methods for supplying oxygen. A detailed explanation of plasma treatment is omitted here, as it can be found in the previous description.

[0364] Next, the film 139 is removed. Removing the film 139 exposes the insulating film 106f. There are no particular limitations on the method for removing the film 139, but a wet etching method can be preferably used. By using a wet etching method, etching of the insulating film 106f during the removal of the film 139 can be suppressed. This prevents the thickness of the insulating film 106f from becoming thinner, and the thickness of the insulating layer 106 can be made uniform.

[0365] The process of supplying oxygen to the insulating film 106f is not limited to the methods described above. For example, oxygen radicals, oxygen atoms, oxygen atom ions, or oxygen molecular ions can be supplied to the insulating film 106f by ion implantation or plasma treatment. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating film 106f, and then oxygen can be supplied to the insulating film 106f through this film. It is preferable to remove the film after supplying oxygen. As the film that suppresses oxygen desorption mentioned above, a conductive film or semiconductor film having one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten can be used.

[0366] Next, a conductive film 104f, which will become the conductive layer 104, is formed on the insulating film 106f (Figure 19B). The conductive film 104f can be formed by, for example, sputtering, thermal CVD (including MOCVD), or ALD.

[0367] Next, the conductive film 104f and the insulating film 106f are processed to form the conductive layer 104 and the insulating layer 106 (Figure 19C). For example, a wet etching method can be suitably used to form the conductive layer 104. For example, a dry etching method can be suitably used to form the insulating layer 106.

[0368] The conductive layer 104 and the insulating layer 106 can be formed, for example, using the same resist mask. A resist mask can be formed on the conductive film 104f, and the conductive film 104f and the insulating film 106f can be processed using the resist mask as a mask. By using the same resist mask for forming the conductive layer 104 and the insulating layer 106, productivity can be increased. Furthermore, the edges of the conductive layer 104 and the insulating layer 106 can be made to coincide or approximately coincide. However, it is also possible to have a configuration where the edges of the conductive layer 104 and the insulating layer 106 do not coincide (see Figures 9A and 9B). In addition, different resist masks can be used for forming the conductive layer 104 and the insulating layer 106.

[0369] Next, using the conductive layer 104 as a mask, impurities 190 are supplied (also called added or injected) to the semiconductor layer 108. As a result, regions 108P and 108Q are formed in the region of the semiconductor layer 108 that does not overlap with the conductive layer 104 (Figure 20A). At this time, it is preferable to determine the conditions for supplying impurities by considering the material and thickness of the conductive layer 104 that serves as the mask, so that as little impurities 190 as possible are supplied to the region of the semiconductor layer 108 that overlaps with the conductive layer 104. This makes it possible to form a channel-forming region with a sufficiently reduced impurity concentration in the region of the semiconductor layer 108 that overlaps with the conductive layer 104. Figure 20A schematically shows the supply of impurities 190 to the semiconductor layer 108 with arrows. It is preferable that the impurities 190 contain the second element mentioned above.

[0370] Next, an insulating film 195f is formed to cover the conductive layer 104, the insulating layer 106, and the semiconductor layer 108, forming the insulating layer 195 (Figure 20B). Plasma CVD can be suitably used to form the insulating film 195f.

[0371] For example, by using a plasma CVD apparatus and performing plasma processing in an atmosphere containing a gas with a second element, the second element can be supplied to a region of the semiconductor layer 108 that does not overlap with the conductive layer 104. Furthermore, by using a plasma CVD apparatus for supplying impurities 190 and for forming the insulating film 195f, the supply of impurities 190 and the formation of the insulating layer 195 can be performed continuously within the apparatus, thereby increasing productivity.

[0372] A gas containing a second element can be used to deposit the insulating film 195f. For example, when hydrogen is used as the second element, the insulating film 195f can be deposited using a gas containing hydrogen (e.g., ammonia gas and hydrogen gas). This allows the supply of impurities 190 and the deposition of the insulating film 195f to be carried out continuously within the apparatus, thereby increasing productivity. For example, when silicon oxynitride is used for the insulating film 195f, it is preferable to use a mixed gas of a silicon-containing depositing gas, an oxidizing gas, and a gas containing hydrogen. When silicon nitride is used as the insulating film 195f, it is preferable to use a mixed gas of a silicon-containing depositing gas, nitrogen gas, an oxidizing gas, and a gas containing hydrogen. As the silicon-containing depositing gas, for example, one or more of silane, disilane, trisilane, and silane fluoride can be used. As the oxidizing gas, a gas containing oxygen can be suitably used. As the oxidizing gas, for example, oxygen (O) ２ ), ozone (O ３ ), nitrous oxide (N ２ O), nitric oxide (NO) and nitrogen dioxide (NO) ２ One or more of the following can be used: Typically, when silicon oxidiznitride is used for the insulating film 195f, silane gas, nitrous oxide (N) ２ O) A mixture of gas and ammonia gas can be used. When silicon nitride oxide is used for the insulating film 195f, silane gas, nitrogen gas, nitrous oxide (N) can be used. ２ A mixture of gas O and ammonia gas can be used.

[0373] If the deposition temperature of the insulating film 195f is too high, impurities contained in regions 108P and 108Q may diffuse into the peripheral areas of the semiconductor layer 108, including the channel formation region. Furthermore, the electrical resistance of regions 108P and 108Q may increase. Therefore, it is preferable to determine the deposition temperature of the insulating film 195f considering the diffusion of impurities.

[0374] The deposition temperature for the insulating film 195f is preferably, for example, 150°C to 400°C, more preferably 200°C to 350°C, more preferably 250°C to 350°C, and more preferably 250°C to 300°C. By depositing the insulating film 195f at a low temperature, a transistor with good electrical characteristics can be obtained even with a short channel length.

[0375] After forming the insulating film 195f, a heat treatment can be performed. This heat treatment may further reduce the electrical resistance of regions 108P and 108Q. Since details of the heat treatment can be found in the previous description, a detailed explanation is omitted here. Note that if the heat treatment temperature is too high (for example, above 500°C), impurities may diffuse into the channel formation region, potentially leading to a decrease in the electrical characteristics and reliability of the transistor.

[0376] Note that this heat treatment is not required. Alternatively, the heat treatment at this stage can be omitted and combined with a heat treatment performed in a later step. Furthermore, if there is a heat treatment in a later step (e.g., a film formation process), this heat treatment may also be combined with that process.

[0377] Next, a portion of the insulating film 195f is removed to form openings 147a and 147b that reach regions 108P and 108Q (Figure 20C). This forms the insulating layer 195. For example, a dry etching method can be suitably used to form openings 147a and 147b.

[0378] Next, conductive layers 112a and 112b are formed to cover openings 147a and 147b (Figure 20C).

[0379] Next, an insulating layer 218 is formed on the insulating layer 195, conductive layer 112a, and conductive layer 112b (Figures 2B and 2C). Plasma CVD can be suitably used to form the insulating layer 218.

[0380] By following the above steps, a semiconductor device 20 according to one aspect of the present invention can be manufactured.

[0381] <Example of Manufacturing Method 2> Here, an example of a manufacturing method for the semiconductor device 20F shown in Figures 8A and 8B will be explained using Figures 21A to 21C. Figures 21A to 21C show side by side the cross-sectional view between the dashed lines A1 and A2 shown in Figure 8A and the cross-sectional view between the dashed lines B1 and B2 shown in Figure 8B. Note that explanations of parts that overlap with the aforementioned Manufacturing Method Example 1 may be omitted.

[0382] First, the conductive film 104f is formed in the same manner as in example 1 of the manufacturing method (Figure 19B).

[0383] Next, a resist mask 192 is formed on the conductive film 104f. The resist mask 192 is placed at the position where the conductive layer 104 is to be formed. Then, the conductive film 104f is processed using the resist mask 192 as a mask to form the conductive layer 104 (Figure 21A).

[0384] Next, impurities 190 are supplied to the semiconductor layer 108 using the resist mask 192 and the conductive layer 104 as masks. As a result, regions 108P and 108Q are formed in the region of the semiconductor layer 108 that does not overlap with the conductive layer 104 (Figure 21A). The impurities 190 are supplied to regions 108P and 108Q via the insulating film 106f. The supply of impurities 190 can be controlled by setting conditions such as acceleration voltage and dose amount, taking into account the composition, density, and thickness of the insulating film 106f and the semiconductor layer 108. At this time, it is preferable to determine the conditions for supplying impurities by taking into account the material and thickness of the resist mask 192 and the conductive layer 104, which serve as masks, so that as little impurities 190 as possible are supplied to the region of the semiconductor layer 108 that overlaps with the conductive layer 104. As a result, a channel formation region with a sufficiently reduced impurity concentration can be formed in the region of the semiconductor layer 108 that overlaps with the conductive layer 104. Figure 21A schematically shows, with arrows, how impurities 190 are supplied to the semiconductor layer 108. It is preferable that the impurities 190 contain the second element mentioned above. Note that impurities may also be supplied to regions of the insulating layer 106 that do not overlap with the conductive layer 104, and regions of the insulating layer 105 that do not overlap with the conductive layer 104, resulting in these regions containing impurities.

[0385] Although Figure 21A shows a configuration in which impurities 190 are supplied to the semiconductor layer 108 via an insulating film 106f (later the insulating layer 106), the present invention is not limited to this. For example, in the semiconductor device 20 shown in Figure 2B and the semiconductor device 20G shown in Figure 9A, impurities are supplied to regions 108P and 108Q without going through the insulating layer 106. Furthermore, impurities are supplied to regions 108R and 108S via the insulating layer 106.

[0386] Next, remove the resist mask 192.

[0387] Although Figure 21A shows a configuration in which impurities 190 are supplied using the resist mask 192 and the conductive layer 104 as masks, the present invention is not limited to this. After removing the resist mask 192, impurities 190 can also be supplied using the conductive layer 104 as a mask.

[0388] Next, an insulating film 195f is formed to cover the conductive layer 104 and the insulating film 106f, which will become the insulating layer 195 (Figure 21B).

[0389] A heat treatment can be performed after the deposition of the insulating film 195f. However, this heat treatment is not required. Alternatively, the heat treatment at this stage can be omitted and combined with a heat treatment performed in a later step. Furthermore, if there is a heat treatment in a later step (e.g., a film deposition step), this heat treatment can also be combined with that step.

[0390] Next, portions of the insulating film 195f and insulating film 106f are removed to form openings 147a and 147b that reach regions 108P and 108Q (Figure 21C). This forms the insulating layer 195 and the insulating layer 106.

[0391] Next, conductive layers 112a and 112b are formed to cover openings 147a and 147b (Figure 21C).

[0392] Next, an insulating layer 218 is formed on the insulating layer 195, conductive layer 112a, and conductive layer 112b (Figures 8A and 8B).

[0393] By following the above steps, a semiconductor device 20F according to one aspect of the present invention can be manufactured.

[0394] (Embodiment 2) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a semiconductor device according to one aspect of the present invention.

[0395] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0396] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (IGZO) and zinc oxide.

[0397] The carrier concentration dependence of the hole (Hall) mobility of indium oxide, silicon, and IGZO is described. Figure 22A shows silicon (Si) and indium oxide (InO Ｘ Figure 22B is a schematic diagram of the carrier concentration dependence of hole mobility for IGZO.

[0398] As shown by the arrows in Figure 22B, IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, as shown by the arrows in Figure 22A, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases (see Non-Patent Literature 2). This trend is similar to that of silicon, where the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that the properties of indium oxide shown in Figure 22A are assumed to be those of a single crystal. Therefore, when indium oxide is not a single crystal (for example, polycrystalline), the properties may differ from those shown in Figure 22A.

[0399] In Figure 22A, the low carrier concentration range R1 exhibits extremely high hole mobility, making it a suitable carrier concentration range for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 has a carrier concentration of 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0400] Furthermore, in indium oxide, the region where the carrier concentration is within the range R1 may contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Other elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0401] On the other hand, the range R2 with high carrier concentration has low electrical resistance and can be said to be a suitable range of carrier concentration for applications such as the source and drain regions of a transistor, or resistors, or transparent conductive films. Range R2 is when the carrier concentration value is 1 × 10⁻⁶ ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the electrical resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0402] Furthermore, in the indium oxide, the region where the carrier concentration is in the range R2 may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements in which the oxide is conductive or semiconducting.

[0403] In this way, indium oxide uses regions with low carrier concentrations for the transistor's channel formation region and regions with high carrier concentrations for the transistor's source and drain regions. In other words, indium oxide can be said to be an oxide in which valence electron control is possible. In contrast, with IGZO, strain can form in the source and drain regions due to stress on the electrodes in contact with IGZO, and n-type regions may be formed. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require strain to form in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 22A within the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Valence electron control in silicon transistors is generally known. On the other hand, valence electron control in indium oxide transistors is a novel technological concept that would not normally be conceived. For example, transistors having indium oxide as described herein have high mobility, low off-current, and are normally-off.

[0404] Next, we will describe indium oxide films applied to transistors. Indium oxide films are preferably crystalline (i.e., they have crystal grains). Examples of films with crystal grains include single-crystal films, polycrystalline films, or amorphous films containing crystal grains (also called microcrystalline films). In particular, polycrystalline films are preferred for indium oxide films, and single-crystal films are more preferred. Single-crystal films do not have crystal grain boundaries. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at crystal grain boundaries. By using a single-crystal film, carrier scattering at crystal grain boundaries can be suppressed, enabling the realization of transistors exhibiting high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these crystal grain boundaries.

[0405] Polycrystalline films are preferred over microcrystalline or amorphous films because they can reduce carrier scattering and exhibit high field-effect mobility. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline indium oxide film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which single-crystal indium oxide is applied.

[0406] In this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel-forming region can be called a single crystal film. Furthermore, a semiconductor layer in which, within a single crystal grain in the channel-forming region, the direction of other crystal axes changes continuously with respect to a certain crystal axis or crystal orientation as the axis of rotation can also be called a single crystal film.

[0407] The crystal grains, grain boundaries, crystal axes, and crystal orientations in the channel formation region can be confirmed by cross-sectional observation along the channel length of the semiconductor layer (for example, cross-sectional observation including the semiconductor layer, source electrode, and drain electrode).

[0408] Furthermore, the indium oxide film in the channel-forming region may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0409] One of the characteristics of indium oxide films is that they have higher oxygen permeability (diffusivity) compared to IGZO films. As shown in Figure 22C, indium oxide films (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and oxygen molecules (O) ２ It is released as water molecules (H) by reacting with hydrogen contained in the membrane. ２ It may also be released as O. Furthermore, oxygen deficiencies (V) can form in the membrane. Ｏ If oxygen atoms are present, diffusing oxygen atoms will fill the oxygen deficiency. Indium oxide films allow oxygen to diffuse easily, so they can be said to fill oxygen deficiencies more easily than IGZO films.

[0410] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0411] As shown in Figure 22C, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the indium oxide film and forms hydrogen molecules (H ２ It is released as ) or, by reacting with oxygen contained in the membrane, it is released as water molecules.

[0412] Transistors using indium oxide films are storage-type transistors that use electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, in a transistor, the on-current or field-effect mobility of the transistor can be increased.

[0413] Table 1 shows single crystal indium oxide (here, In ２ O ３ Table 1 shows the effective mass of indium oxide (FLA) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in transistors, transistors with high field-effect mobility and high frequency characteristics (also called f-characteristics) can be realized. In addition, because the effective hole mass is large, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) in an environment of 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰ −２１ A) The following is possible. Also, as shown in Table 1, indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, so it may be possible to realize a transistor with higher field-effect mobility and lower off-current than a Si transistor.

[0414]

[0415] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This can improve the crystallinity of the indium oxide film. A substrate (for example, a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0416] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0417] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0418] Typically, indium oxide crystals have a cubic structure (bixbite type), while yttria-stabilized zirconia (YSZ) crystals have a cubic structure (fluorite type). The lattice mismatch of indium oxide crystals with respect to cubic YSZ crystals is in the range of -2% to 2%, allowing for the epitaxial growth of indium oxide single crystal films on YSZ substrates.

[0419] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified type structures. YbFe ２ O４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a type structure is IGZO.

[0420] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0421] (Embodiment 3) In this embodiment, a display device according to one aspect of the present invention will be described with reference to Figures 23 to 31.

[0422] The display device of this embodiment can be a high-resolution display device or a large-screen display device. Therefore, the display device of this embodiment can be used in electronic devices with relatively large screens, such as television equipment, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal information terminals, and audio playback devices.

[0423] The display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, as a display unit for information terminals (wearable devices) such as wristwatches and bracelets, as well as as a display unit for wearable devices that can be worn on the head, such as VR devices such as head-mounted displays (HMDs) and AR devices such as glasses.

[0424] A semiconductor device according to one aspect of the present invention can be used as a display device or a module having said display device. Examples of modules having said display devices include a module to which a connector such as a flexible printed circuit board (FPC) or TCP (Tape Carrier Package) is attached, and a module on which an integrated circuit (IC) is mounted using the COG (Chip On Glass) method or COF (Chip On Film) method.

[0425] The display device of this embodiment may also function as a touch panel. For example, the display device can be fitted with various detection elements (also called sensor elements) that can detect the proximity or contact of an object to be detected, such as a finger.

[0426] Examples of sensor types include capacitive, resistive, surface acoustic wave, infrared, optical, and pressure-sensitive sensors.

[0427] Examples of capacitance methods include surface capacitance and projected capacitance. Furthermore, projected capacitance methods include self-capacitance and mutual capacitance. Mutual capacitance is preferable because it enables simultaneous multi-point detection.

[0428] Examples of touch panels include out-cell, on-cell, and in-cell types. An in-cell type touch panel refers to a configuration in which electrodes constituting the sensing element are provided on one or both of the substrate supporting the display element and the opposing substrate.

[0429] <Example of Display Device Configuration 1> Figure 23 shows a perspective view of the display device 50A.

[0430] The display device 50A has a configuration in which substrate 152 and substrate 151 are bonded together. In Figure 23, substrate 152 is shown with a dashed line.

[0431] The display device 50A includes a display unit 162, a connection unit 140, a circuit unit 164, a conductive layer 165, etc. Figure 23 shows an example in which the IC 173 and FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Figure 23 can also be described as a display module having the display device 50A, the IC, and the FPC.

[0432] The connection portion 140 is provided on the outside of the display unit 162. The connection portion 140 can be provided along one or more sides of the display unit 162. There can be one or more connection portions 140. Figure 23 shows an example in which the connection portion 140 is provided so as to surround all four sides of the display unit 162. The connection portion 140 connects the common electrode of the display element to the conductive layer, and can supply potential to the common electrode.

[0433] The circuit section 164 includes, for example, a scan line drive circuit (also called a gate driver). Alternatively, the circuit section 164 can be configured to include both a scan line drive circuit and a signal line drive circuit (also called a source driver).

[0434] The circuit section 164 can utilize various circuits, including shift register circuits, level shifter circuits, inverter circuits, latch circuits, analog switch circuits, demultiplexer circuits, and logic circuits. The circuit section 164 can also utilize transistors and capacitive elements. The transistors in the circuit section 164 can be formed using the same process as the transistors in the pixel circuit.

[0435] The conductive layer 165 has the function of supplying signals and power to the display unit 162 and the circuit unit 164. These signals and power are input to the conductive layer 165 from the outside via the FPC 172, or from the IC 173.

[0436] Figure 23 shows an example where IC 173 is mounted on the substrate 151 using the COG method. IC 173 can be an IC having, for example, one or both of a scan line drive circuit and a signal line drive circuit. Note that the display device 50A and the display module can also be configured without an IC. Furthermore, the IC can be mounted on the FPC using the COF method or the like.

[0437] A semiconductor device according to one aspect of the present invention can be applied, for example, to one or both of the display unit 162 and the circuit unit 164 of a display device 50A. Oxide semiconductors (OS) can preferably be used in the channel formation region of the transistors in the display device. By using OS transistors, a display device with low power consumption can be made. Furthermore, the semiconductor device according to one aspect of the present invention can be used in both the display unit 162 and the circuit unit 164, that is, all of the transistors in the display device can be OS transistors. By making all of the transistors in the display device OS transistors in this way, the manufacturing cost can be kept low.

[0438] For example, when a semiconductor device according to one aspect of the present invention is applied to the pixel circuit of a display device, the occupied area of ​​the pixel circuit can be reduced, resulting in a high-definition display device. Also, for example, when a semiconductor device according to one aspect of the present invention is applied to the drive circuit of a display device (for example, one or both of a gate line drive circuit and a source line drive circuit), the occupied area of ​​the drive circuit can be reduced, resulting in a narrow-bezel display device. Furthermore, because the semiconductor device according to one aspect of the present invention has good electrical characteristics, its use in a display device can improve the reliability of the display device.

[0439] The display unit 162 is the area in the display device 50A that displays images, and has a plurality of pixels 201 arranged periodically. Figure 23 shows a magnified view of one pixel 201.

[0440] There are no particular limitations on the pixel arrangement in the display device of this embodiment, and various methods can be applied. Examples of pixel arrangements include stripe arrangements, S-stripe arrangements, matrix arrangements, delta arrangements, Bayer arrangements, and pentile arrangements.

[0441] The pixel 201 shown in Figure 23 has a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light. The number of sub-pixels that a single pixel may have is not particularly limited.

[0442] Each sub-pixel 11R, 11G, and 11B includes a display element and a circuit that controls the driving of the display element.

[0443] Various elements can be used as display elements, such as liquid crystal elements and light-emitting elements. In addition, display elements using shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems), microcapsule-type, electrophoretic-type, electrowetting-type, or electronic powder fluid (registered trademark)-type methods can also be used. Furthermore, QLEDs (Quantum-dot LEDs) using a light source and color conversion technology using quantum dot materials can be used.

[0444] Examples of quantum dot materials used in the color conversion layer include Group 14 elements, Group 15 elements, Group 16 elements, compounds consisting of multiple Group 14 elements, compounds of elements belonging to Groups 4 to 14 and Group 16 elements, compounds of Group 2 elements and Group 16 elements, compounds of Group 13 elements and Group 15 elements, compounds of Group 13 elements and Group 17 elements, compounds of Group 14 elements and Group 15 elements, compounds of Group 11 elements and Group 17 elements, iron oxides, titanium oxides, chalcogenide spinels, and various semiconductor clusters.

[0445] Specifically, cadmium selenide, cadmium sulfide, cadmium telluride, zinc selenide, zinc oxide, zinc sulfide, zinc telluride, mercury sulfide, mercury selenide, mercury telluride, indium arsenide, indium phosphide, gallium arsenide, gallium phosphide, indium nitride, gallium nitride, indium antimonide, gallium antimonide, aluminum phosphide, aluminum arsenide, aluminum antimonide, lead selenide, lead telluride, lead sulfide, indium selenide, telluride Indium sulfide, indium sulfide, gallium selenide, arsenic sulfide, arsenic selenide, arsenic telluride, antimony sulfide, antimony selenide, antimony telluride, bismuth sulfide, bismuth selenide, bismuth telluride, silicon, silicon carbide, germanium, tin, selenium, tellurium, boron, carbon, phosphorus, boron nitride, boron phosphide, boron arsenide, aluminum nitride, aluminum sulfide, barium sulfide, barium selenide, barium telluride, calcium sulfide, gallium selenide Calcium, calcium telluride, beryllium sulfide, beryllium selenide, beryllium telluride, magnesium sulfide, magnesium selenide, germanium sulfide, germanium selenide, germanium telluride, tin sulfide, tin selenide, tin telluride, lead oxide, copper fluoride, copper chloride, copper bromide, copper iodide, copper oxide, copper selenide, nickel oxide, cobalt oxide, cobalt sulfide, iron oxide, iron sulfide, manganese oxide, molybdenum sulfide, vanadium oxide, tungsten oxide, tungsten oxide Examples include carbon dioxide, titanium dioxide, zirconium dioxide, silicon nitride, germanium nitride, aluminum oxide, barium titanate, compounds of selenium, zinc, and cadmium, compounds of indium, arsenic, and phosphorus, compounds of cadmium, selenium, and sulfur, compounds of cadmium, selenium, and tellurium, compounds of indium, gallium, and arsenic, compounds of indium, gallium, and selenium, compounds of indium, selenium, and sulfur, compounds of copper, indium, and sulfur, and combinations thereof. In addition, so-called alloy-type quantum dots, whose composition is expressed in any ratio, can be used.

[0446] Examples of quantum dot structures include core-type, core-shell-type, and core-multishell-type structures. Furthermore, because quantum dots have a high proportion of surface atoms, they are highly reactive and prone to aggregation. Therefore, to prevent aggregation and improve dispersibility in the dispersion medium, it is preferable that a protective agent is attached to the surface of the quantum dots, or that protective groups are provided. This can also reduce reactivity and improve electrical stability.

[0447] As the size of a quantum dot decreases, its band gap increases, so its size is adjusted appropriately to obtain light of a desired wavelength. As the size decreases, the emission of quantum dots shifts towards the blue side, that is, towards higher energy, so by changing the size of the quantum dots, the emission wavelength can be adjusted across the ultraviolet, visible, and infrared spectral wavelength ranges. The size (diameter) of a quantum dot is, for example, 0.5 nm to 20 nm, preferably 1 nm to 10 nm. Furthermore, the narrower the size distribution of quantum dots, the narrower the emission spectrum becomes, and the better the color purity of the emission can be obtained. The shape of the quantum dots is not particularly limited and may be spherical, rod-shaped, disc-shaped, or other shapes. A quantum rod, which is a rod-shaped quantum dot, has the function of exhibiting directional light.

[0448] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0449] Modes that can be used in display devices using liquid crystal elements include, for example, Vertical Alignment (VA) mode, FFS (Fringe Field Switching) mode, IPS (In-Plane-Switching) mode, TN (Twisted Nematic) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, and ECB (Electrically Examples of VA modes include Controlled Birefringence mode and Guest Host mode. Examples of VA modes include MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, and ASV (Advanced Super View) mode.

[0450] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, polymer dispersed liquid crystals (PDLC), polymer network liquid crystals (PNLC), ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, these liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, blue phases, etc. Furthermore, either positive-type or negative-type liquid crystals can be used as the liquid crystal material, and can be selected according to the applied mode or design.

[0451] Examples of light-emitting elements include self-emissive light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers. For example, mini-LEDs and micro-LEDs can be used as LEDs.

[0452] The light-emitting element can emit light in the following colors: infrared, red, green, blue, cyan, magenta, yellow, or white. Furthermore, the color purity can be improved by adding a microcavity structure to the light-emitting element.

[0453] Of the pair of electrodes in a light-emitting element, one electrode functions as the anode and the other electrode functions as the cathode.

[0454] Furthermore, a display device according to one aspect of the present invention may be any of the following: a top-emission type that emits light in the direction opposite to the substrate on which the light-emitting element is formed; a bottom-emission type that emits light toward the substrate on which the light-emitting element is formed; or a dual-emission type that emits light on both sides.

[0455] One embodiment of the present invention is a semiconductor device having a transistor with a high on-current. A suitable material for the channel formation region of the transistor can be an oxide semiconductor (OS), resulting in a transistor with a low off-current. This semiconductor device can be suitably used in either or both of the display unit 162 and the circuit unit 164. Furthermore, this semiconductor device can be used in both the display unit 162 and the circuit unit 164, meaning all transistors in the display device can be OS transistors. By using OS transistors for all transistors in the display device in this way, manufacturing costs can be kept low.

[0456] Figure 24A shows an example of a cross-section obtained by cutting a portion of the display device 50A, including the FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the end section.

[0457] The display device 50A shown in Figure 24A has transistors 205D, 205R, 205G, 205B, light-emitting elements 130R, 130G, and 130B between substrates 151 and 152. Light-emitting element 130R is a display element of a sub-pixel 11R that emits red light, light-emitting element 130G is a display element of a sub-pixel 11G that emits green light, and light-emitting element 130B is a display element of a sub-pixel 11B that emits blue light.

[0458] The display device 50A employs an SBS structure. Because the SBS structure allows for the optimization of materials and configurations for each light-emitting element, it increases the freedom of material and configuration selection, making it easier to improve brightness and reliability.

[0459] The display device 50A is a top-emission type. In the top-emission type, transistors and the like can be placed overlapping with the light-emitting region of the light-emitting element, which allows for a higher aperture ratio of pixels compared to the bottom-emission type.

[0460] Transistors 205D, 205R, 205G, and 205B are all formed on the substrate 151. Transistor 205D is provided in the circuit section 164, while transistors 205R, 205G, and 205B are provided in the display section 162. These transistors can be manufactured using the same process. Note that transistors with different structures can also be used for transistors 205D, 205R, 205G, and 205B.

[0461] This embodiment shows an example in which OS transistors are used for transistors 205D, 205R, 205G, and 205B. Transistors according to one aspect of the present invention can be used for transistors 205D, 205R, 205G, and 205B. In other words, the display device 50A has transistors according to one aspect of the present invention in both the display unit 162 and the circuit unit 164. By using transistors according to one aspect of the present invention in the display unit 162, the pixel size can be reduced and higher resolution can be achieved. Furthermore, by using transistors according to one aspect of the present invention in the circuit unit 164, the occupied area of ​​the circuit unit 164 can be reduced and the bezel can be narrowed. For details on transistors according to one aspect of the present invention, refer to the description in the previous embodiment.

[0462] Figure 24A shows an example configuration in which transistors 205D, 205R, 205G, and 205B are replaced with transistor 100 as shown in Figure 2B. By using TGSA type transistors, the parasitic capacitance between the source electrode, drain electrode, and gate electrode can be reduced. Therefore, the degradation of display quality caused by parasitic capacitance can be suppressed.

[0463] Transistors 205D, 205R, 205G, and 205B each have a conductive layer 104 functioning as a first gate, a conductive layer 103 functioning as a second gate electrode, an insulating layer 106 functioning as a first gate insulating layer, a second gate insulating layer 105, conductive layers 112a and 112b functioning as source and drain electrodes, and a semiconductor layer 108 having a metal oxide. Here, the same hatching pattern is applied to multiple layers obtained by processing the same conductive film.

[0464] Furthermore, the transistors in the display device of this embodiment are not limited to those of one aspect of the present invention. For example, the transistors of one aspect of the present invention may be combined with transistors of other structures.

[0465] The display device of this embodiment may have, for example, one or more of planar transistors, staggered transistors, or inverse staggered transistors. The transistors in the display device of this embodiment may be top-gate or bottom-gate types. Alternatively, gates may be provided above and below the semiconductor layer in which the channel is formed.

[0466] The display device of this embodiment may also have Si transistors.

[0467] To increase the luminescence brightness of a light-emitting element included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting element. To achieve this, it is necessary to increase the source-drain voltage of the drive transistor included in the pixel circuit. Compared to Si transistors, OS transistors have a higher breakdown voltage between the source and drain, so a higher voltage can be applied to the source-drain of an OS transistor. Therefore, by using an OS transistor as the drive transistor in the pixel circuit, the amount of current flowing through the light-emitting element can be increased, thereby increasing the luminescence brightness of the light-emitting element.

[0468] When a transistor operates in the saturation region, an OS transistor exhibits a smaller change in source-drain current in response to a change in gate-source voltage than a Si transistor. Therefore, by using an OS transistor as the driving transistor in a pixel circuit, the current flowing between the source and drain can be precisely controlled by the change in gate-source voltage, thereby allowing control of the current flowing to the light-emitting element. This allows for an increase in the number of grayscale levels in the pixel circuit.

[0469] In terms of the saturation of the current flowing when a transistor operates in the saturation region, OS transistors can supply a more stable current (saturation current) than Si transistors, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be supplied to a light-emitting element even if there are variations in the current-voltage characteristics of the light-emitting element. In other words, when operating in the saturation region, OS transistors can stabilize the luminescence brightness of a light-emitting element because the change in source-drain current is small even when the source-drain voltage is changed.

[0470] The transistors in the circuit unit 164 and the transistors in the display unit 162 may have the same structure or different structures. The structures of the multiple transistors in the circuit unit 164 may all be the same or there may be two or more different structures. Similarly, the structures of the multiple transistors in the display unit 162 may all be the same or there may be two or more different structures.

[0471] All of the transistors in the display unit 162 may be OS transistors, all of the transistors in the display unit 162 may be Si transistors, or some of the transistors in the display unit 162 may be OS transistors and the rest may be Si transistors.

[0472] For example, by using both an LTPS transistor and an OS transistor in the display unit 162, a display device with low power consumption and high driving capability can be realized. Furthermore, a configuration combining an LTPS transistor and an OS transistor is sometimes referred to as LTPO. A more preferable example is a configuration in which an OS transistor is used for transistors that function as switches to control conduction and non-conduction between wires, and an LTPS transistor is used for transistors that control current.

[0473] For example, one of the transistors in the display unit 162 functions as a transistor for controlling the current flowing to the light-emitting element, and can also be called a drive transistor. One of the source and drain of the drive transistor is connected to the pixel electrode of the light-emitting element. It is preferable to use an LTPS transistor for the drive transistor. This makes it possible to increase the current flowing to the light-emitting element in the pixel circuit.

[0474] On the other hand, the other transistor in the display unit 162 functions as a switch for controlling the selection and deselection of pixels, and can also be called a selection transistor. The gate of the selection transistor is connected to the gate line, and one of the source and drain is connected to the source line (signal line). It is preferable to use an OS transistor for the selection transistor. This makes it possible to maintain the gradation of pixels even when the frame frequency is significantly low (for example, 1 fps or less), and thus power consumption can be reduced by stopping the driver when displaying a still image.

[0475] An insulating layer 218 is provided so as to cover transistors 205D, 205R, 205G, and 205B. As mentioned above, the insulating layer 218 can be an inorganic insulating layer, an organic insulating layer, or both. Preferably, the insulating layer 218 has an organic insulating layer that functions as a planarizing layer. Alternatively, the insulating layer 218 can have a laminated structure of an organic insulating layer and an inorganic insulating layer. Preferably, the outermost layer of the insulating layer 218 functions as an etching protection layer. An inorganic insulating layer can be suitably used as the etching protection layer. This makes it possible to suppress the formation of recesses in the insulating layer 218 when processing the pixel electrodes 111R, 111G, and 111B. Alternatively, recesses may be provided in the insulating layer 218 when processing the pixel electrodes 111R, 111G, and 111B. Note that the pixel electrodes 111R, 111G, and 111B are sometimes collectively referred to as the pixel electrode 111.

[0476] A light-emitting element 130R, a light-emitting element 130G, and a light-emitting element 130B are provided on the insulating layer 218.

[0477] The light-emitting element 130R has a pixel electrode 111R on an insulating layer 218, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. The light-emitting element 130R shown in Figure 24A emits red light (R). The EL layer 113R has a light-emitting layer that emits red light.

[0478] The light-emitting element 130G has a pixel electrode 111G on an insulating layer 218, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G. The light-emitting element 130G shown in Figure 24A emits green light (G). The EL layer 113G has a light-emitting layer that emits green light.

[0479] The light-emitting element 130B has a pixel electrode 111B on an insulating layer 218, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B. The light-emitting element 130B shown in Figure 24A emits blue light (B). The EL layer 113B has a light-emitting layer that emits blue light.

[0480] In Figure 24A, EL layers 113R, 113G, and 113B are all shown to be the same thickness, but this is not the only option. The thicknesses of EL layers 113R, 113G, and 113B may be different. For example, it is preferable to set the thickness of EL layers 113R, 113G, and 113B so that the optical path length is such that the light emitted by each is intensified. This makes it possible to realize a microcavity structure and improve the color purity of the light emitted from each light-emitting element.

[0481] The pixel electrode 111R is in contact with the conductive layer 112b of the transistor 205R at an opening provided in the insulating layer 218, and is connected to the conductive layer 112b. Similarly, the pixel electrode 111G is connected to the conductive layer 112b of the transistor 205G, and the pixel electrode 111B is connected to the conductive layer 112b of the transistor 205B.

[0482] The ends of the pixel electrodes 111R, 111G, and 111B are covered by an insulating layer 237. The insulating layer 237 functions as a partition. The insulating layer 237 can be provided in a single-layer or multi-layer structure using one or both inorganic insulating materials and / or organic insulating materials. For example, the insulating layer 237 can be made of a material that can be used for the insulating layer 218. The insulating layer 237 electrically insulates the pixel electrodes from the common electrode. In addition, the insulating layer 237 electrically insulates adjacent light-emitting elements from each other.

[0483] The insulating layer 237 is provided at least on the display unit 162. The insulating layer 237 may be provided not only on the display unit 162, but also on the connection unit 140 and the circuit unit 164. Furthermore, the insulating layer 237 may extend to the end of the display device 50A.

[0484] The common electrode 115 is a continuous film provided in common to the light-emitting element 130R, light-emitting element 130G, and light-emitting element 130B. The common electrode 115, which is shared by multiple light-emitting elements, is connected to a conductive layer 123 provided at the connection portion 140. It is preferable to use a conductive layer for the conductive layer 123 that is made of the same material and formed by the same process as the pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B.

[0485] In a display device according to one aspect of the present invention, among the pixel electrodes and common electrodes, the electrode that extracts light is preferably made of a conductive film that transmits visible light. Furthermore, it is preferable that the electrode that does not extract light is made of a conductive film that reflects visible light.

[0486] A conductive film that transmits visible light may also be used on the electrode that does not extract light. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. In other words, the light emitted from the EL layer may be reflected by the reflective layer and extracted from the display device.

[0487] As the material for forming the pair of electrodes of the light-emitting element, metals, alloys, electrically conductive compounds, and mixtures thereof can be used as appropriate. Specifically, such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and alloys containing these in appropriate combinations. Other examples of such materials include ITO, ITSO, indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Furthermore, examples of such materials include aluminum-containing alloys such as aluminum, nickel, and lanthanum alloys (Al-Ni-La), as well as silver-containing alloys such as silver-magnesium alloys and silver-palladium-copper alloys (Ag-Pd-Cu, also written as APC). Other materials include elements belonging to Group 1 or Group 2 of the periodic table not exemplified above (e.g., lithium, cesium, calcium, strontium), rare earth metals such as europium and ytterbium, alloys containing these in appropriate combinations, graphene, and the like.

[0488] It is preferable that the light-emitting element has a microcavity structure. Therefore, it is preferable that one of the pair of electrodes in the light-emitting element is a semitransmitting / semi-reflective electrode that transmits and reflects visible light, and the other is a reflective electrode that reflects visible light. By having a microcavity structure in the light-emitting element, the light emitted from the light-emitting layer can be resonated between the two electrodes, thereby strengthening the light emitted from the light-emitting element.

[0489] The light transmittance of the transparent electrode shall be 40% or more. For example, it is preferable to use an electrode with a transmittance of 40% or more for visible light (light with a wavelength of 400 nm or more and less than 750 nm) for the transparent electrode of the light-emitting element. The visible light reflectance of the semi-transparent and semi-reflective electrodes shall be 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode shall be 40% or more and 100% or less, preferably 70% or more and 100% or less. Furthermore, the electrical resistivity of these electrodes shall be 1 × 10⁻⁶−２ A value of Ωcm or less is preferable.

[0490] The EL layers 113R, 113G, and 113B are each provided in an island-like manner. In Figure 24A, the edges of adjacent EL layers 113R and 113G overlap, the edges of adjacent EL layers 113G and 113B overlap, and the edges of adjacent EL layers 113R and 113B overlap. When forming island-like EL layers using a fine metal mask, the edges of adjacent EL layers may overlap as shown in Figure 24A, but this is not the only case. In other words, adjacent EL layers may not overlap and may be separated from each other. Furthermore, in a display device, there may be both regions where adjacent EL layers overlap and regions where adjacent EL layers do not overlap and are separated.

[0491] Each of the EL layers 113R, 113G, and 113B has at least one light-emitting layer. The light-emitting layer has one or more types of light-emitting materials. As the light-emitting material, a material that exhibits a light-emitting color such as blue, purple, blue-violet, green, yellow-green, yellow, orange, or red can be used as appropriate. In addition, a material that emits near-infrared light can also be used as the light-emitting material.

[0492] Examples of luminescent materials include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (such as quantum dot materials).

[0493] Examples of quantum dot materials include colloidal quantum dots, alloy quantum dots, core-shell quantum dots, and core quantum dots. Furthermore, quantum dot materials containing elemental groups of Group 2 and Group 16, Group 13 and Group 15, Group 13 and Group 17, Group 11 and Group 17, or Group 14 and Group 15 can be used. Alternatively, quantum dot materials containing elements such as cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As), and aluminum (Al) can be used.

[0494] The light-emitting layer may contain one or more types of organic compounds (host material, assist material, etc.) in addition to the light-emitting substance (guest material). One or more of the organic compounds may be substances with high hole transport properties (hole transport material) and / or substances with high electron transport properties (electron transport material). Alternatively, one or more of the organic compounds may be bipolar substances (substances with high electron and hole transport properties) or TADF materials.

[0495] The light-emitting layer preferably comprises, for example, a phosphorescent material and a combination of a hole-transporting material and an electron-transporting material that readily forms an excitation complex. This configuration allows for efficient emission using ExTET (Exciplex-Triplet Energy Transfer), which is energy transfer from the excitation complex to the light-emitting substance (phosphorescent material). By selecting a combination that forms an excitation complex that exhibits emission overlapping with the wavelength of the lowest-energy absorption band of the light-emitting substance, energy transfer becomes smoother, and light emission can be obtained efficiently. This configuration enables high efficiency, low-voltage operation, and a long lifespan for the light-emitting element.

[0496] The EL layer may have, in addition to the light-emitting layer, one or more of the following: a layer containing a material with high hole injection properties (hole injection layer), a layer containing a hole transport material (hole transport layer), a layer containing a material with high electron blocking properties (electron blocking layer), a layer containing a material with high electron injection properties (electron injection layer), a layer containing an electron transport material (electron transport layer), and a layer containing a material with high hole blocking properties (hole blocking layer). Furthermore, the EL layer may contain either or both a bipolar material and a TADF material.

[0497] The light-emitting element can be made of either low-molecular-weight compounds or high-molecular-weight compounds, and may also contain inorganic compounds. The layers constituting the light-emitting element can be formed by methods such as vapor deposition (including vacuum deposition), transfer, printing, inkjet, and coating.

[0498] The light-emitting element may be a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units). Each light-emitting unit has at least one light-emitting layer. The tandem structure is a configuration in which multiple light-emitting units are connected in series via a charge generation layer. The charge generation layer has the function of injecting electrons into one of the two light-emitting units and holes into the other when a voltage is applied between a pair of electrodes. By using a tandem structure, a light-emitting element capable of high-brightness emission can be made. Furthermore, compared to a single structure, the tandem structure can reduce the current required to obtain the same brightness, thus improving reliability. The tandem structure can also be called a stack structure.

[0499] In Figure 24A, when a tandem light-emitting element is used, it is preferable that the EL layer 113R has a structure having multiple light-emitting units that emit red light, the EL layer 113G has a structure having multiple light-emitting units that emit green light, and the EL layer 113B has a structure having multiple light-emitting units that emit blue light.

[0500] A protective layer 131 is provided on the light-emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 152 are bonded together via an adhesive layer 142. A light-shielding layer 117 is provided on the substrate 152. For sealing the light-emitting elements, for example, a solid sealing structure or a hollow sealing structure can be applied. In Figure 24A, the space between the substrate 152 and the substrate 151 is filled with the adhesive layer 142, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 142 may be provided in a frame shape so as not to overlap with the light-emitting elements. Furthermore, the space may be filled with a resin different from the adhesive layer 142 provided in a frame shape.

[0501] The protective layer 131 is provided at least on the display section 162, and preferably so as to cover the entire display section 162. It is preferable that the protective layer 131 covers not only the display section 162, but also the connection section 140 and the circuit section 164. Furthermore, it is preferable that the protective layer 131 extends to the end of the display device 50A. On the other hand, in the connection section 197, there is an area where the protective layer 131 is not provided in order to connect the FPC 172 and the conductive layer 166.

[0502] By providing a protective layer 131 on the light-emitting elements 130R, 130G, and 130B, the reliability of the light-emitting elements can be improved.

[0503] The protective layer 131 can be a single layer or a laminated structure of two or more layers. Furthermore, the conductivity of the protective layer 131 is not required. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the protective layer 131.

[0504] The presence of an inorganic film in the protective layer 131 prevents oxidation of the common electrode 115 and suppresses the intrusion of impurities (such as moisture and oxygen) into the light-emitting element, thereby suppressing degradation of the light-emitting element and improving the reliability of the display device.

[0505] The protective layer 131 preferably has one or more inorganic insulating layers. The protective layer 131 can be made of the same material that can be used for the insulating layer 106 and the insulating layer 105. In particular, the protective layer 131 preferably uses a nitride or nitride oxide, and more preferably uses a nitride.

[0506] The protective layer 131 may also be an inorganic film containing ITO, In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, or IGZO. The inorganic film is preferably highly resistive, and more specifically, it is preferably more resistive than the common electrode 115. The inorganic film may further contain nitrogen.

[0507] When the light emitted from a light-emitting element is extracted via a protective layer 131, it is preferable that the protective layer 131 has high transmittance (also referred to as light transmission) to visible light. For example, ITO, IGZO, and aluminum oxide are preferred because they are inorganic materials with high transmittance to visible light.

[0508] As the protective layer 131, for example, a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a laminated structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used. By using such a laminated structure, it is possible to suppress the penetration of impurities (water, oxygen, etc.) into the EL layer.

[0509] Furthermore, the protective layer 131 may have an organic layer. For example, the protective layer 131 may have both an organic layer and an inorganic layer. Examples of organic layers that can be used in the protective layer 131 include organic insulating layers that can be used in the insulating layer 218.

[0510] A connection portion 197 is provided in the region of substrate 151 where substrate 152 does not overlap. At the connection portion 197, the conductive layer 165 is connected to the FPC 172 via the conductive layer 166 and the connection layer 242. Figure 24A shows an example in which the conductive layer 165 is formed by processing the same conductive film as conductive layers 112a and 112b. The conductive layer 166 is shown as an example in which it is formed by processing the same conductive film as the pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B. The connection portion between conductive layer 165 and conductive layer 166 can be configured similarly to the connection portion between pixel electrode 111 and conductive layer 112b. Specifically, Figure 24A shows an example in which an opening is provided in the insulating layer 218, and the conductive layer 166 is in contact with the upper surface of the conductive layer 165 at this opening. The conductive layer 166 is exposed on the upper surface of the connection portion 197. This allows the connection part 197 and the FPC 172 to be connected via the connection layer 242.

[0511] The display device 50A is of the top-emission type. The light emitted by the light-emitting element is emitted towards the substrate 152. It is preferable to use a material with high transmittance to visible light for the substrate 152. The pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that transmits visible light.

[0512] It is preferable to provide a light-shielding layer 117 on the surface of the substrate 152 that faces the substrate 151. The light-shielding layer 117 can be provided between adjacent light-emitting elements, in connection portions 140, and in circuit portions 164, etc.

[0513] A colored layer, such as a color filter, may be provided on the surface of the substrate 152 facing the substrate 151, or on the protective layer 131. By placing a color filter on top of the light-emitting element, the color purity of the light emitted from the pixel can be increased.

[0514] A colored layer is a colored layer that selectively transmits light in a specific wavelength range and absorbs light in other wavelength ranges. For example, a red (R) color filter that transmits light in the red wavelength range, a green (G) color filter that transmits light in the green wavelength range, and a blue (B) color filter that transmits light in the blue wavelength range can be used. One or more of the following can be used for each colored layer: metal materials, resin materials, pigments, and dyes. The colored layers are formed at the desired positions using methods such as printing, inkjet printing, and photolithography etching.

[0515] Various optical components can be placed on the outside of the substrate 152 (the side opposite to the substrate 151). Examples of optical components include polarizing plates, phase difference plates, light diffusion layers (such as diffusion films), anti-reflective layers, and light-gathering films. In addition, surface protection layers such as an antistatic film to suppress the adhesion of dust, a water-repellent film to make it difficult for dirt to adhere, a hard coat film to suppress the occurrence of scratches during use, and a shock-absorbing layer may be placed on the outside of the substrate 152. For example, a glass layer or a silica layer (SiO ｘProviding a protective layer (where x is a real number greater than 0) is preferable as it can suppress surface contamination and scratching. Alternatively, DLC (diamond-like carbon), aluminum oxide, polyester-based materials, or polycarbonate-based materials may be used as the surface protective layer. It is preferable to use a material with high transmittance to visible light for the surface protective layer. Furthermore, it is preferable to use a material with high hardness for the surface protective layer.

[0516] The substrates 151 and 152 can be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, etc., respectively. The substrate on the side that extracts light from the light-emitting element should be made of a material that transmits the light. If flexible materials are used for substrates 151 and 152, the flexibility of the display device can be increased, and a flexible display can be realized. In addition, a polarizing plate may be used as at least one of substrates 151 and 152.

[0517] As substrates 151 and 152, various materials can be used, such as polyester resins like polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamide-imide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. At least one of substrates 151 and 152 may be made of glass of a thickness sufficient to provide flexibility.

[0518] Furthermore, when a circular polarizing plate is superimposed on a display device, it is preferable to use a substrate with high optical isotropy for the substrate of the display device. A substrate with high optical isotropy has low birefringence (or a small amount of birefringence). Examples of films with high optical isotropy include triacetylcellulose (TAC, also called cellulose triacetate) film, cycloolefin polymer (COP) film, cycloolefin copolymer (COC) film, and acrylic film.

[0519] Various types of curing adhesives can be used as the adhesive layer 142, including UV-curing adhesives, reaction-curing adhesives, thermosetting adhesives, and anaerobic adhesives. Examples of these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. Materials with low moisture permeability, such as epoxy resins, are particularly preferred. Two-component mixed resins may also be used. Adhesive sheets may also be used.

[0520] As the connecting layer 242, an anisotropic conductive film (ACF), anisotropic conductive paste (ACP), etc., can be used.

[0521] <Example of Display Device Configuration 2> Figure 24B shows an example of a cross-section of the display unit 162 of the display device 50B. The display device 50B differs from the display device 50A in that each sub-pixel of each color uses a light-emitting element having a common EL layer 113 and a coloring layer (such as a color filter). The configuration shown in Figure 24B can be combined with the configuration of the region including the FPC 172, the circuit unit 164, the laminated structure from the substrate 151 to the insulating layer 218 of the display unit 162, the connection unit 140, and the end portion shown in Figure 24A. Note that in the following description of the display device, parts that are the same as those described earlier may be omitted.

[0522] The display device 50B shown in Figure 24B includes light-emitting elements 130R, 130G, 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light, etc.

[0523] The light-emitting element 130R includes a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113. The light emitted from the light-emitting element 130R is extracted as red light to the outside of the display device 50B via the colored layer 132R.

[0524] The light-emitting element 130G includes a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113. The light emitted from the light-emitting element 130G is extracted as green light to the outside of the display device 50B via the colored layer 132G.

[0525] The light-emitting element 130B includes a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113. The light emitted from the light-emitting element 130B is extracted as blue light to the outside of the display device 50B via the colored layer 132B.

[0526] The light-emitting elements 130R, 130G, and 130B each share an EL layer 113 and a common electrode 115. Providing a common EL layer 113 for each sub-pixel of each color reduces the number of manufacturing steps compared to providing a different EL layer for each sub-pixel of each color.

[0527] For example, the light-emitting elements 130R, 130G, and 130B shown in Figure 24B emit white light. The white light emitted by the light-emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, thereby obtaining light of a desired color.

[0528] A light-emitting element that emits white light preferably includes two or more light-emitting layers. When obtaining white light emission using two light-emitting layers, the light-emitting layers can be selected such that their emission colors are complementary. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary, a configuration can be obtained in which the entire light-emitting element emits white light. Furthermore, when obtaining white light emission using three or more light-emitting layers, the emission colors of the three or more light-emitting layers combine to create a configuration in which the entire light-emitting element emits white light.

[0529] The EL layer 113 preferably has, for example, an emissive layer having a light-emitting material that emits blue light, and an emissive layer having a light-emitting material that emits visible light with a longer wavelength than blue. The EL layer 113 preferably has, for example, an emissive layer that emits yellow light and an emissive layer that emits blue light. Alternatively, the EL layer 113 preferably has, for example, an emissive layer that emits red light, an emissive layer that emits green light, and an emissive layer that emits blue light.

[0530] For light-emitting elements that emit white light, a tandem structure is preferable. Specifically, a two-stage tandem structure having a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light, a two-stage tandem structure having a light-emitting unit that emits red and green light and a light-emitting unit that emits blue light, a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, and a light-emitting unit that emits blue light in that order, or a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, a light-emitting unit that emits red light, and a light-emitting unit that emits blue light in that order. For example, the number of layers and color order of the light-emitting unit can be, from the anode side, a two-layer structure of B and Y, a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y, B, or a three-layer structure of B, X, B. The number of layers and color order of the light-emitting layers in light-emitting unit X can be, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R, G, or a three-layer structure of R, G, R. In addition, other layers may be provided between the two light-emitting layers.

[0531] Furthermore, by applying a microcavity structure, a light-emitting element that normally emits white light may also emit light of specific wavelengths, such as red, green, or blue, with increased intensity.

[0532] Alternatively, for example, the light-emitting elements 130R, 130G, and 130B shown in Figure 24B emit blue light. In this case, the EL layer 113 has one or more light-emitting layers that emit blue light. In the sub-pixel 11B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. In the sub-pixel 11R that emits red light and the sub-pixel 11G that emits green light, by providing a color conversion layer between the light-emitting element 130R or light-emitting element 130G and the substrate 152, the blue light emitted by the light-emitting element 130R or light-emitting element 130G can be converted into longer wavelength light, and red or green light can be extracted. The color conversion layer can be described in the above description. Specifically, the various quantum dot materials described above can be used for the color conversion layer. Furthermore, it is preferable to provide a coloring layer 132R between the color conversion layer and the substrate 152 on the light-emitting element 130R, and a coloring layer 132G between the color conversion layer and the substrate 152 on the light-emitting element 130G. Some of the light emitted by a light-emitting element may pass through without being converted by the color conversion layer. By extracting the light that has passed through the color conversion layer via a colored layer, the color of light other than the desired color can be absorbed by the colored layer, thereby increasing the color purity of the light exhibited by the subpixel.

[0533] <Example of Display Device Configuration 3> The display device 50C shown in Figure 25 differs from the display device 50A in that it has a conductive layer 234p, a conductive layer 234a, a conductive layer 234b, and an insulating layer 239.

[0534] An insulating layer 239 is provided on the conductive layer 234p, conductive layer 234a, conductive layer 234b, and insulating layer 218, and light-emitting elements 130R, 130G, and 130B are provided on the insulating layer 239. The insulating layer 239 can be made from the same materials as those used for the insulating layer 218.

[0535] The conductive layer 234p is provided so as to cover the opening provided in the insulating layer 218. The conductive layer 234p is in contact with the conductive layer 112b of the transistor 205R at the opening and is connected to the conductive layer 112b.

[0536] The pixel electrode 111R is provided so as to cover an opening in the insulating layer 239. The pixel electrode 111R is in contact with the conductive layer 234p at the opening and is connected to the conductive layer 234p. In other words, the pixel electrode 111R is connected to the conductive layer 112b via the conductive layer 234p. The same applies to the pixel electrode 111G and the pixel electrode 111B.

[0537] The conductive layer 234a is provided so as to cover the opening provided in the insulating layer 218. The conductive layer 234a is in contact with the conductive layer 165 at the opening and is connected to the conductive layer 165.

[0538] The conductive layer 166 is provided so as to cover the opening provided in the insulating layer 239. The conductive layer 166 is in contact with the conductive layer 234a at the opening and is connected to the conductive layer 234a. In other words, the conductive layer 166 is connected to the conductive layer 165 via the conductive layer 234a.

[0539] Figure 25 shows a configuration in which the circuit section 164 has a conductive layer 234b. It is also possible to configure the conductive layer 234b to be connected to the transistor 205D.

[0540] The conductive layers 234p, 234a, and 234b can be formed by processing the same conductive film. Furthermore, each of the conductive layers 234p, 234a, and 234b functions as wiring. The conductive layers 234p, 234a, and 234b are provided on different layers from the conductive layers 112a, 112b, 104, and 103. Therefore, since wiring can be arranged on each layer, the degree of layout flexibility is increased, and the circuit's occupied area can be reduced.

[0541] The conductive layers 234p, 234a, and 234b can be made from the materials listed for conductive layers 112a, 112b, and 104. The conductive layers 234p, 234a, and 234b can be formed in the same process. For example, the conductive layers 234p, 234a, and 234b can be formed by depositing a conductive film and then processing the conductive film.

[0542] <Example of Display Device Configuration 4> The display device 50D shown in Figure 26 differs from the display device 50B mainly in that it is a bottom-emission type display device.

[0543] The light emitted by the light-emitting element is emitted towards the substrate 151. It is preferable to use a material with high transmittance to visible light for the substrate 151. On the other hand, the light transmittance of the material used for the substrate 152 is not a requirement.

[0544] It is preferable to form a light-shielding layer 117 between the substrate 151 and the transistors. Figure 26 shows an example in which a light-shielding layer 117 is provided on the substrate 151, an insulating layer 153 is provided on the light-shielding layer 117, and transistors 205D, 205R (not shown), 205G, and 205B are provided on the insulating layer 153. In addition, a colored layer 132R, a colored layer 132G, and a colored layer 132B are provided on the insulating layer 195, and an insulating layer 218 is provided on the colored layer 132R, a colored layer 132G, and a colored layer 132B.

[0545] The light-emitting element 130R, which overlaps with the colored layer 132R, has a pixel electrode 111R, an EL layer 113, and a common electrode 115.

[0546] The light-emitting element 130G, which overlaps with the colored layer 132G, has a pixel electrode 111G, an EL layer 113, and a common electrode 115.

[0547] The light-emitting element 130B, which overlaps with the colored layer 132B, has a pixel electrode 111B, an EL layer 113, and a common electrode 115.

[0548] The pixel electrodes 111R, 111G, and 111B are made of materials with high transmittance to visible light. It is preferable to use a material that reflects visible light for the common electrode 115. In a bottom-emission type display device, a metal with low electrical resistivity can be used for the common electrode 115, thereby suppressing voltage drops caused by the electrical resistance of the common electrode 115 and achieving high display quality.

[0549] A transistor according to one aspect of the present invention can be miniaturized and have a smaller occupied area, which allows for an increase in the aperture ratio of pixels or a reduction in the size of pixels in a display device with a bottom emission structure.

[0550] <Example of Display Device Configuration 5> The display device 50E shown in Figure 27A differs from the display device 50A mainly in that it has a light-receiving element 130S.

[0551] The display device 50E has a light-emitting element and a light-receiving element in each pixel. In the display device 50E, it is preferable to use an organic EL element as the light-emitting element and an organic photodiode as the light-receiving element. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be incorporated into a display device using an organic EL element.

[0552] In a display device 50E having light-emitting and light-receiving elements in its pixels, the pixels have a light-receiving function, allowing for the detection of contact or proximity of an object while displaying an image. Therefore, the display unit 162 has, in addition to an image display function, one or both of an imaging function and a sensing function. For example, the display device 50E can not only display an image using all of its subpixels, but some subpixels can also emit light as a light source, some other subpixels can perform light detection, and the remaining subpixels can display an image.

[0553] Therefore, it is not necessary to provide a light receiving unit and a light source separately from the display device 50E, and the number of components in the electronic device can be reduced. For example, there is no need to separately provide a biometric auth...

Claims

Having a semiconductor layer, The semiconductor layer comprises a first metal oxide layer, a second metal oxide layer on the first metal oxide layer, and a third metal oxide layer on the second metal oxide layer. The first metal oxide layer, the second metal oxide layer, and the third metal oxide layer each contain indium oxide. A semiconductor device wherein the second metal oxide layer has a region with a higher hydrogen concentration than the first metal oxide layer and the third metal oxide layer, respectively. 　 In claim 1, The second metal oxide layer has a hydrogen concentration of 5 × 10 ２０ atoms / cm ３ The above 5 x 10 ２１ atoms / cm ３ The region has the following characteristics: A semiconductor device wherein the first metal oxide layer and the third metal oxide layer each have a region in which the hydrogen concentration is 1 / 100 or more and 1 / 8 or less of the hydrogen concentration in the second metal oxide layer. 　 It has a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer has a region that overlaps with the gate electrode via the gate insulating layer, The semiconductor layer comprises a first metal oxide layer, a second metal oxide layer on the first metal oxide layer, and a third metal oxide layer on the second metal oxide layer. The first metal oxide layer, the second metal oxide layer, and the third metal oxide layer each contain indium oxide. A semiconductor device wherein the second metal oxide layer has a region with a higher hydrogen concentration than the first metal oxide layer and the third metal oxide layer, respectively. 　 In claim 3, The second metal oxide layer has a hydrogen concentration of 5 × 10 ２０ atoms / cm ３ The above 5 x 10 ２１ atoms / cm ３ The region has the following characteristics: A semiconductor device wherein the first metal oxide layer and the third metal oxide layer each have a region in which the hydrogen concentration is 1 / 100 or more and 1 / 8 or less of the hydrogen concentration in the second metal oxide layer. 　 In any one of claims 1 to 4, A semiconductor device wherein the second metal oxide layer has regions with lower film density than the first metal oxide layer and the third metal oxide layer, respectively. 　 In any one of claims 1 to 4, The semiconductor layer has crystal grains, A semiconductor device having the first metal oxide layer, the second metal oxide layer, and the third metal oxide layer. 　 In any one of claims 1 to 4, A semiconductor device wherein the thickness of the second metal oxide layer is greater than the thickness of the first metal oxide layer and the thickness of the third metal oxide layer, respectively. 　 In claim 7, The thickness of the second metal oxide layer is 1 nm or more and 30 nm or less. A semiconductor device in which the thickness of the first metal oxide layer and the third metal oxide layer are each 0.5 nm or more and 10 nm or less. 　 A method for fabricating a semiconductor device having a semiconductor layer, As the semiconductor layer, a first metal oxide layer, a second metal oxide layer, and a third metal oxide layer are deposited in this order using a sputtering method. The first metal oxide layer, the second metal oxide layer, and the third metal oxide layer each contain indium oxide. The power density during film formation of the first metal oxide layer and the third metal oxide layer is higher than the power density during film formation of the second metal oxide layer. A method for manufacturing a semiconductor device, wherein the pressure used in the deposition of the first metal oxide layer and the third metal oxide layer is lower than the pressure used in the deposition of the second metal oxide layer. 　 The first metal oxide layer, the second metal oxide layer, and the third metal oxide layer are deposited in this order using the sputtering method. A gate insulating layer is formed on the third metal oxide layer. A gate electrode is formed on the gate insulating layer. The first metal oxide layer, the second metal oxide layer, and the third metal oxide layer each contain indium oxide. The power density during film formation of the first metal oxide layer and the third metal oxide layer is higher than the power density during film formation of the second metal oxide layer. A method for manufacturing a semiconductor device, wherein the pressure used in the deposition of the first metal oxide layer and the third metal oxide layer is lower than the pressure used in the deposition of the second metal oxide layer. 　 In claim 9 or claim 10, The power density in the film formation of the first metal oxide layer and the third metal oxide layer is respectively 0.3 W / cm ２ or more and 2 W / cm ２ or less, and The power density during the deposition of the second metal oxide layer is 0.1 W / cm². ２ 1W / cm or more ２ The following is a method for manufacturing a semiconductor device. 　 In claim 9 or claim 10, The pressure during the deposition of the first metal oxide layer and the third metal oxide layer is 0.1 Pa or more and 0.8 Pa or less, respectively. A method for manufacturing a semiconductor device, wherein the pressure used in forming the second metal oxide layer is 0.2 Pa or more and 1 Pa or less. 　 In claim 9 or claim 10, A method for manufacturing a semiconductor device, wherein the deposition of the first metal oxide layer, the second metal oxide layer, and the third metal oxide layer is performed using the same sputtering target. 　 In claim 9 or claim 10, A method for manufacturing a semiconductor device, wherein the deposition of the first metal oxide layer, the second metal oxide layer, and the third metal oxide layer is performed using oxygen gas, hydrogen gas, and argon gas, respectively. 　 In claim 9 or claim 10, By performing a heat treatment after forming the first metal oxide layer, the second metal oxide layer, and the third metal oxide layer, the crystallinity of the first metal oxide layer, the second metal oxide layer, and the third metal oxide layer is increased. A method for manufacturing a semiconductor device, wherein the temperature of the heat treatment is 400°C or higher and 670°C or lower. 　 In claim 9 or claim 10, A method for manufacturing a semiconductor device, wherein the thickness of the second metal oxide layer is greater than the thickness of the first metal oxide layer and the thickness of the third metal oxide layer, respectively. 　 In claim 16, The thickness of the second metal oxide layer is 1 nm or more and 30 nm or less. A method for manufacturing a semiconductor device, wherein the thickness of the first metal oxide layer and the third metal oxide layer are each 0.5 nm or more and 10 nm or less.

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