Dead time control circuit and electronic device

Abstract

The application discloses a dead time control circuit and electronic equipment, and belongs to the technical field of electronics. The dead time control circuit comprises an inductive element, a first field effect tube connected with the inductive element, a second field effect tube connected with the inductive element and the first field effect tube, a detection circuit for detecting a first switching state of the first field effect tube, a second switching state of the second field effect tube and a current flow direction of the inductive element, a logic judgment circuit for outputting an adjustment mode signal of a dead time, a first off time and a second off time according to the first switching state, the second switching state and the current flow direction, an operation circuit for outputting a dead time control signal according to the first off time and the second off time in an adjustment direction indicated by the adjustment mode signal, and a time delay circuit, wherein the dead time control signal is used for adjusting a time delay value of the time delay circuit to adjust the dead time of the first field effect tube and the second field effect tube.

Description

Technical Field

[0001] This application belongs to the field of electronic technology, specifically relating to a dead-time control circuit and electronic device. Background Technology

[0002] The buck (step-down switching circuit) in a power management integrated circuit (PMIC) is divided into complementary MOS (Metal-Oxide-Semiconductor) architecture buck and dual NMOS (N-channel Metal-Oxide-Semiconductor) architecture buck, depending on the internal architecture. The former achieves buck output through complementary control of NMOS and PMOS (P-channel Metal-Oxide-Semiconductor), while the latter achieves output through two NMOS.

[0003] Compared to the complementary MOS architecture bucket, the dual NMOS architecture bucket offers advantages such as lower conduction losses, higher efficiency, shorter switching delay, and suitability for high-frequency applications. Therefore, the dual NMOS architecture bucket is more widely used. Dead time is a critical factor in switching circuit design, ensuring safe switching between the two MOS transistors. Properly setting the dead time is essential for optimizing system efficiency and reliability.

[0004] However, in related technologies, for the dead time of a dual NMOS architecture BUCK, the hardware-based dead time control method has a fixed dead time, which has poor robustness and significant limitations. On the other hand, the adaptive dead time control method mostly relies on software control, which has a slow response speed. Summary of the Invention

[0005] The purpose of this application is to provide a dead-time control circuit and electronic device that can realize dead-time adaptive control based on pure hardware circuits, thereby improving the robustness of dead-time control and increasing the response speed of dead-time control.

[0006] In a first aspect, embodiments of this application provide a dead-time control circuit, comprising: an inductor; a first field-effect transistor (FET) connected to the inductor; a second FET of the same type as the first FET, connected to both the inductor and the first FET; a detection circuit connected to both the first and second FETs, used to detect a first switching state of the first FET, a second switching state of the second FET, and the current flow direction of the inductor; a logic judgment circuit connected to the detection circuit, used to output a dead-time adjustment mode signal, a first turn-off time of the first FET, and a second turn-off time of the second FET based on the first switching state, the second switching state, and the current flow direction; an arithmetic circuit connected to the logic judgment circuit, used to output a dead-time control signal based on the first turn-off time and the second turn-off time according to the adjustment direction indicated by the adjustment mode signal; and a delay circuit connected to the arithmetic circuit, the first FET, and the second FET, wherein the dead-time control signal is used to adjust the delay value of the delay circuit to adjust the dead time of the first and second FETs.

[0007] Secondly, embodiments of this application provide an electronic device, including: a dead-time control circuit as described in the first aspect.

[0008] The dead-time control circuit provided in this application includes an inductor, a first field-effect transistor (FET) and a second FET of the same type, a detection circuit, a logic judgment circuit, an arithmetic circuit, and a delay circuit. The first FET is connected to the inductor, the second FET is connected to both the inductor and the first FET, the detection circuit is connected to both the first and second FETs, the logic judgment circuit is connected to the detection circuit, the arithmetic circuit is connected to the logic judgment circuit, and the delay circuit is connected to the arithmetic circuit, the first FET, and the second FET. During the operation of the dead-time control circuit, the detection circuit detects the first switching state of the first field-effect transistor (FET), the second switching state of the second FET, and the current flow direction of the inductor. The logic judgment circuit outputs a dead-time adjustment mode signal, the first turn-off time of the first FET, and the second turn-off time of the second FET based on the first and second switching states and the current flow direction. The arithmetic circuit, following the adjustment direction indicated by the adjustment mode signal, outputs a dead-time control signal based on the first and second turn-off times. This dead-time control signal adjusts the delay value of the delay circuit, thereby adjusting the dead time of the first and second FETs. This dead-time control circuit, based on three-terminal sampling and detection of the high and low-side NMOS voltage and current (i.e., the first switching state of the first FET, the second switching state of the second FET, and the current flow direction of the inductor), utilizes the detection circuit, logic judgment circuit, arithmetic circuit, and delay circuit to achieve adaptive dead-time control based on a purely hardware circuit. This achieves adaptive dead-time control, thereby improving the robustness of dead-time control and increasing its response speed. Attached Figure Description

[0009] Figure 1 One of the schematic diagrams of the dead-time control circuit provided in the embodiments of this application;

[0010] Figure 2 A second schematic diagram of the dead-time control circuit provided in an embodiment of this application;

[0011] Figure 3 This is one of the schematic diagrams for dead-time control in related technologies;

[0012] Figure 4 This is the second schematic diagram of dead-time control in related technologies;

[0013] Figure 5 This is one of the control flowcharts for dead time provided in the embodiments of this application;

[0014] Figure 6 One of the schematic diagrams for dead-time control provided in the embodiments of this application;

[0015] Figure 7The second control flowchart for dead time provided in the embodiments of this application;

[0016] Figure 8 The second schematic diagram of dead time control provided in the embodiments of this application;

[0017] Figure 9 An equivalent architecture diagram of the dead-time control circuit provided in the embodiments of this application;

[0018] Figure 10 A structural block diagram of an electronic device provided in an embodiment of this application.

[0019] Figure label:

[0020] 100 Dead-time control circuit, 102 Detection circuit, 104 Logic judgment circuit, 106 Operation circuit, 108 Delay circuit, 110 First comparator, 112 Second comparator, 114 Third comparator, 116 First flip-flop, 118 Second flip-flop, 120 Third flip-flop, 122 First time counter, 124 First time register, 126 Second time counter, 128 Second time register, 130 Logic judgment module, 132 Variable capacitor, 134 Delay network, 136 First field-effect transistor, 138 Second field-effect transistor, 140 Inductor, 200 Electronic equipment. Detailed Implementation

[0021] The embodiments of this application will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0022] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0023] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0024] The dead-time control circuit and electronic device according to embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0025] like Figure 1 and Figure 2 As shown in the figure, this application embodiment provides a dead time control circuit 100. The dead time control circuit 100 is used to control the dead time of a buck switching circuit.

[0026] Specifically, the buck switching circuit is a dual NMOS architecture BUCK.

[0027] Understandably, the dual NMOS architecture bucket has the following advantages compared to the complementary MOS architecture bucket: Since the dual NMOS architecture uses NMOS as the high-side drive switch, the electron mobility of NMOS is approximately three times higher than that of PMOS in the complementary MOS architecture. Therefore, the on-resistance of NMOS is lower, and under the same current output conditions, the conduction loss of the dual NMOS architecture bucket is lower than that of the complementary MOS architecture bucket, resulting in better efficiency. Furthermore, NMOS has a smaller gate charge than a PMOS of the same specifications, approximately 70% to 80%. Therefore, the switching delay of NMOS is relatively smaller, making it more suitable for high-frequency bucket applications. Based on these reasons, the dual NMOS architecture bucket is more widely used than the complementary MOS architecture bucket.

[0028] Dead time is a critical factor in switching circuit design. It is the safe interval between the switching of two MOSFETs from one state to another. During the dead time, both MOSFETs remain off to prevent a short circuit caused by simultaneous conduction. In other words, dead time ensures safe switching between the two MOSFETs, specifically ensuring that each MOSFET has sufficient time to turn off before the other turns on, preventing short circuits caused by simultaneous conduction. A dead time that is too short may result in shoot-through between the two MOSFETs, while a dead time that is too long may cause unnecessary energy loss and reduced efficiency.

[0029] Specifically, for the dual-NMOS architecture BUCK, improper dead-time settings may lead to the following problems: At the moment the high-side NMOS is turned off, the switching node voltage jumps, and energy is coupled to the gate of the high-side NMOS through the Miller capacitance, generating a positive voltage spike. If the dead-time is insufficiently controlled, the high-side NMOS may be mis-turned on, resulting in shoot-through current and causing the NMOS to burn out. The dual-NMOS architecture introduces a bootstrap capacitor. When the duty cycle is >95%, the bootstrap capacitor's recharge time is insufficient, and the bootstrap voltage is at risk of dropping. This reduces the voltage between the gate and source of the high-side NMOS, increasing the high-side NMOS turn-on delay and thus creating shoot-through current that burns out the NMOS. When the PMIC operates under heavy loads, the device temperature rises sharply, leading to increased turn-on delay, decreased turn-off delay, and dead-time drift, posing a risk of NMOS burnout. Therefore, correctly setting the dead-time is crucial for optimizing system efficiency and reliability.

[0030] For dead-time control methods in dual NMOS architecture BUCK, the main technologies include fixed dead-time control and adaptive dead-time control. Among them, for fixed dead-time control, such as... Figure 3 As shown, the implementation involves inserting a fixed time interval between the drive signals of the high and low-side NMOS transistors using hardware circuits such as a PWM (Pulse Width Modulation) modulator, RC (Resistance Capacitance) delay, inverters, and AND gates. This achieves dead-time control through a fixed RC delay and logic control. However, this control method cannot adapt to load changes and temperature drift, exhibiting poor robustness. Furthermore, due to the fixed RC delay, it is unsuitable for high-frequency scenarios, resulting in significant limitations. In contrast, adaptive dead-time control, such as... Figure 4 As shown, most rely on software control. The main implementation method is to sample the bias voltage of the high and low side NMOS, combine it with a comparator to obtain the MOS switching information, and then use a state machine to judge and compensate and adjust. The main controller calculates the driving logic, and then uses a PWM modulator to drive the output, thus obtaining the driving control signal for the high and low side NMOS. The response speed is slow. On the other hand, the few pure hardware control methods mostly rely on multiple diode clamping, resulting in poor device reliability and short lifespan.

[0031] Therefore, this application provides a dead-time control circuit 100, which can realize dead-time adaptive control based on pure hardware circuit for dual NMOS architecture BUCK, improving the robustness of dead-time control while increasing the response speed of dead-time control.

[0032] Specifically, such as Figure 1 and Figure 2As shown, the dead time control circuit 100 includes an inductor 140, a first field-effect transistor 136, a second field-effect transistor 138, a detection circuit 102, a logic judgment circuit 104, an arithmetic circuit 106, and a time delay circuit 108.

[0033] The first field-effect transistor 136 and the second field-effect transistor 138 are of the same type, and both the first field-effect transistor 136 and the second field-effect transistor 138 are NMOS field-effect transistors.

[0034] Optionally, the first field-effect transistor 136 is a high-side NMOS and the second field-effect transistor 138 is a low-side NMOS.

[0035] Optionally, the first field-effect transistor 136 is connected to the inductor 140, and the second field-effect transistor 138 is connected to both the inductor 140 and the first field-effect transistor 136.

[0036] Specifically, the drain of the first field-effect transistor 136 is connected to the power supply, the source of the first field-effect transistor 136 and the drain of the second field-effect transistor 138 are both connected to the first end of the inductor 140, the source of the second field-effect transistor 138 is grounded, and the second end of the inductor 140 is connected to the input capacitor, i.e., the load end.

[0037] Optionally, the detection circuit 102 is connected to both the first field-effect transistor 136 and the second field-effect transistor 138.

[0038] Optionally, the detection circuit 102 is used to detect the first switching state of the first field-effect transistor 136, the second switching state of the second field-effect transistor 138, and the current flow direction of the inductor 140. Thus, the dead-time control circuit 100 provided in this embodiment of the application, based on three-terminal sampling and detection of the high- and low-side NMOS voltage and current, achieves dead-time control, which can improve the accuracy of judgment and thereby enhance the accuracy of dead-time control.

[0039] The first switch state is used to indicate the on or off status of the first field-effect transistor 136, and the second switch state is used to indicate the on or off status of the second field-effect transistor 138.

[0040] Optionally, the logic judgment circuit 104 is connected to the detection circuit 102.

[0041] Optionally, the logic judgment circuit 104 is used to output the dead time adjustment mode signal, the first turn-off time of the first field-effect transistor 136, and the second turn-off time of the second field-effect transistor 138 according to the first switch state, the second switch state, and the current flow direction.

[0042] The adjustment mode signal is used to indicate the adjustment direction of the dead time of the first field-effect transistor 136 and the second field-effect transistor 138. The adjustment direction includes increasing the dead time, decreasing the dead time, and keeping the dead time unchanged.

[0043] Optionally, the first turn-off time is used to indicate the duration of each time the first field-effect transistor 136 enters the turn-off state, and the second turn-off time is used to indicate the duration of each time the second field-effect transistor 138 enters the turn-off state.

[0044] Optionally, the arithmetic circuit 106 is connected to the logic judgment circuit 104.

[0045] Optionally, the arithmetic circuit 106 is used to output a dead time control signal according to the adjustment direction indicated by the adjustment mode signal and based on the first off time and the second off time.

[0046] The dead time control signal is used to adjust the delay value of the delay circuit 108.

[0047] In practical applications, the operational circuit 106 can be composed of hardware such as adders and multipliers, and no specific restrictions are made here.

[0048] Optionally, the delay circuit 108 is connected to the operational circuit 106, the first field-effect transistor 136, and the second field-effect transistor 138.

[0049] Optionally, the delay value of the delay circuit 108 is adjustable. The delay value of the delay circuit 108 affects the dead time of the first field-effect transistor 136 and the second field-effect transistor 138. By adjusting the delay value of the delay circuit 108 through the dead time control signal, the dead time of the first field-effect transistor 136 and the second field-effect transistor 138 can be adjusted. In this way, based on the adjustable delay value of the delay circuit 108, adaptive adjustment and control of the dead time is realized, which facilitates the improvement of PMIC efficiency and reduces the risk of burnout of the dual NMOS architecture BUCK.

[0050] The dead-time control circuit 100 according to an embodiment of this application includes an inductor 140, a first field-effect transistor 136 and a second field-effect transistor 138 of the same type, a detection circuit 102, a logic judgment circuit 104, an arithmetic circuit 106, and a delay circuit 108. The first field-effect transistor 136 is connected to the inductor 140, the second field-effect transistor 138 is connected to both the inductor 140 and the first field-effect transistor 136, the detection circuit 102 is connected to both the first field-effect transistor 136 and the second field-effect transistor 138, the logic judgment circuit 104 is connected to the detection circuit 102, the arithmetic circuit 106 is connected to the logic judgment circuit 104, and the delay circuit 108 is connected to the arithmetic circuit 106, the first field-effect transistor 136, and the second field-effect transistor 138. During the operation of the dead time control circuit 100, the detection circuit 102 detects the first switching state of the first field-effect transistor 136, the second switching state of the second field-effect transistor 138, and the current flow direction of the inductor 140. The logic judgment circuit 104 outputs the dead time adjustment mode signal, the first turn-off time of the first field-effect transistor 136, and the second turn-off time of the second field-effect transistor 138 according to the first switching state, the second switching state, and the current flow direction. The arithmetic circuit 106 outputs the dead time control signal according to the adjustment direction indicated by the adjustment mode signal and the first turn-off time and the second turn-off time. The dead time control signal is used to adjust the delay value of the delay circuit 108, thereby adjusting the dead time of the first field-effect transistor 136 and the second field-effect transistor 138. The aforementioned dead-time control circuit 100, based on three-terminal sampling and detection of the high- and low-side NMOS voltage and current—namely, the first switching state of the first field-effect transistor 136, the second switching state of the second field-effect transistor 138, and the current flow direction of the inductor 140—utilizes a detection circuit 102, a logic judgment circuit 104, an arithmetic circuit 106, and a delay circuit 108 to achieve dead-time adaptive control based on a purely hardware circuit. This improves both the robustness and response speed of dead-time control by achieving adaptive dead-time control.

[0051] According to some embodiments of this application, optionally, such as Figure 1 and Figure 2 As shown, the detection circuit 102 includes a first comparator 110, a second comparator 112, and a third comparator 114.

[0052] The first comparator 110 is connected to the first field-effect transistor 136.

[0053] Optionally, the first comparator 110 is used to output a first switching signal based on the first bias voltage of the first field-effect transistor 136.

[0054] The first switching signal is used to indicate the first switching state of the first field-effect transistor 136.

[0055] In practical applications, the first switching signal can be either 1 or 0. A first switching signal of 1 indicates that the first field-effect transistor 136 is in the off state, while a first switching signal of 0 indicates that the first field-effect transistor 136 is in the on state.

[0056] Specifically, the decision condition of the first comparator 110 can be expressed as follows:

[0057] and ;

[0058] in, This is the source-drain voltage of the high-side NMOS, i.e., the first field-effect transistor 136. This is the first bias voltage of the drain and source of the first field-effect transistor 136 under the working state, and it is also the voltage drop of the first field-effect transistor 136 when it is actually working. This is the plateau voltage of the first field-effect transistor 136, that is, To minimize the gate-source voltage required for the first field-effect transistor 136 to begin forming a channel. , that is, To minimize the time required for the first field-effect transistor 136 to start conducting , Controls whether the first field-effect transistor 136 is turned on; V1 is the first voltage threshold. T1 is the on-time of the first field-effect transistor 136; T1 is the first time threshold. When the first field-effect transistor 136 is turned off, Approximately equal to the input voltage V applied to the drain of the first field-effect transistor 136 IN When the first field-effect transistor 136 is turned on, ,in, The current flowing through the first field-effect transistor 136, The internal resistance between the source and drain of the first field-effect transistor 136 is given.

[0059] That is, the determination condition of the first comparator 110 is: the first bias voltage of the first field-effect transistor 136 is greater than the sum of the plateau voltage of the first field-effect transistor 136 and the first voltage threshold, and is maintained at the first time threshold. If the first bias voltage of the first field-effect transistor 136 satisfies the above determination condition, it can be determined that the first field-effect transistor 136 is fully turned on; otherwise, it is determined that the first field-effect transistor 136 is turned off.

[0060] In practical applications, the first comparator 110 can specifically determine, at a time threshold interval, whether the first bias voltage of the first field-effect transistor 136 is greater than the sum of the plateau voltage of the first field-effect transistor 136 and the first voltage threshold. If the first bias voltage of the first field-effect transistor 136 is determined to be greater than the sum of the plateau voltage of the first field-effect transistor 136 and the first voltage threshold twice consecutively, the first field-effect transistor 136 is determined to be fully turned on; otherwise, the first field-effect transistor 136 is determined to be turned off. Based on this, the first comparator 110 then outputs the corresponding first switching signal in real time according to the determination result.

[0061] In addition, in practical applications, those skilled in the art can set the specific values ​​of the first voltage threshold and the first time threshold according to the actual situation, and no specific restrictions are imposed here. For example, the first voltage threshold can be 0.3V and the first time threshold can be 5ns.

[0062] Optionally, the second comparator 112 is connected to the second field-effect transistor 138.

[0063] Optionally, the second comparator 112 is used to output a second switching signal based on the second bias voltage of the second field-effect transistor 138.

[0064] The second switching signal is used to indicate the second switching state of the second field-effect transistor 138.

[0065] In practical applications, the second switch signal can be either 1 or 0. A second switch signal of 1 indicates that the second field-effect transistor 138 is in the off state, while a second switch signal of 0 indicates that the second field-effect transistor 138 is in the on state.

[0066] Specifically, the decision condition of the second comparator 112 can be expressed as follows:

[0067] and ;

[0068] in, This is the source-drain voltage of the low-side NMOS, i.e., the second field-effect transistor 138. This is the second bias voltage of the drain and source of the second field-effect transistor 138 under the working state, and it is also the voltage drop of the second field-effect transistor 138 when it is actually working. This is the plateau voltage of the second field-effect transistor 138, that is, To minimize the gate-source voltage required for the second field-effect transistor 138 to begin forming a channel. , that is, To minimize the time required for the second field-effect transistor 138 to start conducting , Controls whether the second field-effect transistor 138 is turned on; V2 is the second voltage threshold. T1 is the on-time of the second field-effect transistor 138; T2 is the second time threshold. When the second field-effect transistor 138 is turned off, Approximately equal to the input voltage V applied to the drain of the second field-effect transistor 138. IN When the second field-effect transistor 138 is turned on, ,in, The current flowing through the second field-effect transistor 138, The internal resistance between the source and drain of the second field-effect transistor 138 is given.

[0069] That is, the determination condition of the second comparator 112 is: the second bias voltage of the second field-effect transistor 138 is greater than the sum of the plateau voltage of the second field-effect transistor 138 and the second voltage threshold, and is maintained for the second time threshold. If the second bias voltage of the second field-effect transistor 138 satisfies the above determination condition, it can be determined that the second field-effect transistor 138 is fully turned on; otherwise, it is determined that the second field-effect transistor 138 is turned off.

[0070] In practical applications, the second comparator 112 can specifically determine, at a second time threshold interval, whether the second bias voltage of the second field-effect transistor 138 is greater than the sum of the plateau voltage of the second field-effect transistor 138 and the second voltage threshold. If the second bias voltage of the second field-effect transistor 138 is determined to be greater than the sum of the plateau voltage of the second field-effect transistor 138 and the second voltage threshold twice consecutively, the second field-effect transistor 138 is determined to be fully turned on; otherwise, the second field-effect transistor 138 is determined to be turned off. Based on this, the second comparator 112 then outputs the corresponding second switching signal in real time according to the determination result.

[0071] In addition, in practical applications, those skilled in the art can set the specific values ​​of the second voltage threshold and the second time threshold according to the actual situation, and no specific restrictions are imposed here. For example, the second voltage threshold can be 0.3V and the second time threshold can be 5ns.

[0072] Optionally, the third comparator 114 is connected to both the first field-effect transistor 136 and the second field-effect transistor 138.

[0073] Optionally, the third comparator 114 is used to output a current edge signal based on the first bias voltage and the second bias voltage.

[0074] The current edge signal is used to indicate the current flow direction of the inductor 140. The current edge signal specifically includes rising edge signal and falling edge signal.

[0075] Specifically, the current flow direction of the inductor element 140 can be determined by the polarity of the first bias voltage and the second bias voltage: V DS_H>0 and V DS_L When V > 0, the current is a positive current. The specific principle is: if V DS_H >0, the current transmission path is V IN →First field-effect transistor 136 →Inductor 140 →Load, if V DS_L If the current is greater than 0, the inductor current of inductor 140 will freewheel through the second field-effect transistor 138; while V DS_H When V < 0, no reverse current will occur. DS_L When the value is less than 0, energy flows back from the output terminal, resulting in a reverse current.

[0076] In practical applications, the first comparator 110 and the second comparator 112 can be high-speed comparators, and the third comparator 114 can be a differential comparator; no specific restrictions are imposed here.

[0077] According to the dead-time control circuit 100 of this application embodiment, the detection circuit 102 includes a first comparator 110, a second comparator 112, and a third comparator 114. The first comparator 110 is connected to a first field-effect transistor 136, the second comparator 112 is connected to a second field-effect transistor 138, and the third comparator 114 is connected to both the first and second field-effect transistors 136 and 138. The first comparator 110 outputs a first switching signal based on a first bias voltage of the first field-effect transistor 136, indicating a first switching state. The second comparator 112 outputs a second switching signal based on a second bias voltage of the second field-effect transistor 138, indicating a second switching state. The third comparator 114 outputs a current edge signal based on the first and second bias voltages, indicating the current flow direction. In this way, by using a comparator, based on the magnitude and polarity of the bias voltage of the high and low side NMOS in the dual NMOS architecture BUCK, three-terminal sampling and detection of the high and low side NMOS can be achieved, which improves the accuracy of the detection results and thus improves the accuracy of subsequent dead time control.

[0078] According to some embodiments of this application, optionally, such as Figure 1 and Figure 2 As shown, the detection circuit 102 also includes a first flip-flop 116, a second flip-flop 118, and a third flip-flop 120.

[0079] The first flip-flop 116 is connected to the first comparator 110.

[0080] Optionally, the first flip-flop 116 is used to sequentially transmit the first switching signal output by the first comparator 110 according to the first clock signal.

[0081] Optionally, the second flip-flop 118 is connected to the second comparator 112.

[0082] Optionally, the second flip-flop 118 is used to sequentially transmit the second switching signal output by the second comparator 112 according to the second clock signal.

[0083] Optionally, the third flip-flop 120 is connected to the third comparator 114.

[0084] Optionally, the third flip-flop 120 is used to sequentially transmit the current edge signal output by the third comparator 114 in accordance with the third clock signal.

[0085] The first clock signal, the second clock signal, and the third clock signal are synchronized with each other.

[0086] The first flip-flop 116, the second flip-flop 118, and the third flip-flop 120 can all transmit signals outward at the rising edge of the corresponding clock signal or at the falling edge of the corresponding clock signal; no specific restrictions are imposed here.

[0087] According to the dead-time control circuit 100 of this application embodiment, the detection circuit 102 further includes a first flip-flop 116, a second flip-flop 118, and a third flip-flop 120. The first flip-flop 116 is connected to the first comparator 110, the second flip-flop 118 is connected to the second comparator 112, and the third flip-flop 120 is connected to the third comparator 114. The first flip-flop 116 is used to transmit a first switching signal according to a first clock signal; the second flip-flop 118 is used to transmit a second switching signal according to a second clock signal; and the third flip-flop 120 is used to transmit a current edge signal according to a third clock signal. The first, second, and third clock signals are synchronized with each other. Thus, by setting a flip-flop at the rear end of the comparators, clock synchronization between the output signals of each comparator is achieved, which can match the switching timing of the NMOS transistor, thereby preventing metastable timing disorders and improving the stability of dead-time control.

[0088] According to some embodiments of this application, optionally, such as Figure 1 and Figure 2 As shown, the logic judgment circuit 104 includes a first time counter 122, a first time register 124, a second time counter 126, a second time register 128, and a logic judgment module 130.

[0089] The first time counter 122 is connected to the first trigger 116.

[0090] Optionally, the first time counter 122 is used to perform timing based on the first switch signal. Specifically, when the first time counter 122 receives the first switch signal indicating that the first field-effect transistor 136 is in the off state, that is, when the first time counter 122 receives the first switch signal with a value of 1, it starts timing once, and when it receives the first switch signal indicating that the first field-effect transistor 136 is in the on state, that is, when it receives the first switch signal with a value of 0, it ends timing and outputs the corresponding first off time in real time.

[0091] Optionally, the first time register 124 is connected to the first time counter 122 and the arithmetic circuit 106.

[0092] Optionally, the first time register 124 is used to cache the first shutdown time output in real time by the first time counter 122 for subsequent retrieval by the arithmetic circuit 106.

[0093] Optionally, the second time counter 126 is connected to the second trigger 118.

[0094] Optionally, the second time counter 126 is used to perform timing based on the second switch signal. Specifically, when the second time counter 126 receives the second switch signal indicating that the second field-effect transistor 138 is in the off state, that is, when the second time counter 126 receives the second switch signal with a value of 1, it starts timing once, and when it receives the second switch signal indicating that the second field-effect transistor 138 is in the on state, that is, when it receives the second switch signal with a value of 0, it ends timing and outputs the corresponding second off time in real time.

[0095] Optionally, the second time register 128 is connected to the second time counter 126 and the arithmetic circuit 106.

[0096] Optionally, the second time register 128 is used to buffer the second shutdown time output by the second time counter 126 for subsequent retrieval by the arithmetic circuit 106.

[0097] Optionally, the logic judgment module 130 is connected to the first flip-flop 116, the second flip-flop 118, and the third flip-flop 120.

[0098] Optionally, the logic judgment module 130 stores a truth table for dead-zone control logic.

[0099] The dead-time control logic truth table is used to indicate the correspondence between the first switch signal, the second switch signal, and the current edge signal and the adjustment direction of the dead time.

[0100] In practical applications, the truth table for dead-time control logic can be specifically shown in Table 1 below:

[0101] CAMP_H CAMP_L Current edge signal Adjust direction 1 0 Falling edge Reduce dead time 0 1 rising edge Increase dead time 0 0 Falling edge Increase dead time 1 1 \ Dead time remains unchanged

[0102] Where CAMP_H represents the first switching signal and CAMP_L represents the second switching signal. As shown in Table 1, when the first MOSFET 136 is off, the second MOSFET 138 is on, and the current edge is a falling edge, the dead time needs to be reduced because the second bias voltage of the second MOSFET 138 cannot rise to the turn-off threshold in time before the first MOSFET 136 is turned on. When the first MOSFET 136 is on, the second MOSFET 138 is off, and the current edge is a rising edge, the dead time needs to be increased because the first bias voltage of the first MOSFET 136 cannot rise to the turn-off threshold in time before the second MOSFET 138 is turned on. When both the first MOSFET 136 and the second MOSFET 138 are on, and the current edge is a falling edge, the dead time needs to be increased. When both the first MOSFET 136 and the second MOSFET 138 are off, the dead time remains unchanged.

[0103] Specifically, the logic judgment module 130 is used to compare the first switch signal, the second switch signal and the current edge signal acquired in real time with the pre-stored dead time control logic truth table, and then determine the adjustment direction of the dead time based on the comparison result, and output the dead time adjustment mode signal.

[0104] According to the dead-time control circuit 100 of this application embodiment, the logic judgment circuit 104 includes a first time counter 122, a first time register 124, a second time counter 126, a second time register 128, and a logic judgment module 130. The first time counter 122 is connected to a first flip-flop 116, the first time register 124 is connected to the first time counter 122, the second time counter 126 is connected to the second flip-flop 118, the second time register 128 is connected to the second time counter 126, and the logic judgment module 130 is connected to the first flip-flop 116, the second flip-flop 118, and the third flip-flop 120. The first time counter 122 is used to time according to the first switch signal and output the first turn-off time; the first time register 124 is used to buffer the first turn-off time; the second time counter 126 is used to time according to the second switch signal and output the second turn-off time; the second time register 128 is used to buffer the second turn-off time; the logic judgment module 130 stores a dead-time control logic truth table, and the logic judgment module 130 is used to output an adjustment mode signal according to the dead-time control logic truth table, based on the first switch signal, the second switch signal, and the current edge signal. Thus, based on the three-terminal sampling detection results of the high and low side NMOS, i.e., the switching state and current direction of the high and low side NMOS, the adjustment direction of the dead time is determined, improving the accuracy of the adjustment direction determination, and thus improving the accuracy of subsequent dead-time control.

[0105] According to some embodiments of this application, optionally, such as Figure 1 As shown, the time delay circuit 108 includes a variable capacitor 132.

[0106] The variable capacitor 132 is connected to the operational circuit 106, the first field-effect transistor 136, and the second field-effect transistor 138.

[0107] Optionally, the capacitance value of the variable capacitor 132 changes with the control voltage of the variable capacitor 132. Specifically, the capacitance value of the variable capacitor 132 is proportional to the control voltage of the variable capacitor 132.

[0108] Optionally, the specific formula for the charging and discharging delay of the variable capacitor 132 can be:

[0109] ;

[0110] in, R is the dead time adjustment amount, and R is the resistance value of the delay circuit 108. This is the reference capacitance value for variable capacitor 132. The control voltage for variable capacitor 132, This is a function representing the capacitance value of variable capacitor 132 as a function of the control voltage. This is the charging voltage of variable capacitor 132. This is the platform voltage of variable capacitor 132.

[0111] Optionally, the dead time control signal is used to control the charging and discharging state of the variable capacitor 132 and control the charging and discharging cutoff voltage of the variable capacitor 132, so as to control the charging and discharging duration of the variable capacitor 132, thereby controlling the delay value of the delay circuit 108, and achieving the purpose of controlling the dead time of the first field-effect transistor 136 and the second field-effect transistor 138.

[0112] According to the dead-time control circuit 100 of this application embodiment, the delay circuit 108 includes a variable capacitor 132. The variable capacitor 132 is connected to the operational circuit 106, the first field-effect transistor 136, and the second field-effect transistor 138. The dead-time control signal is used to control the charging and discharging state of the variable capacitor 132 and to control the charging and discharging cutoff voltage of the variable capacitor 132. In this way, the dead time is adjusted by adjusting the charging and discharging duration of the variable capacitor 132, thereby adjusting the delay value of the delay circuit 108. This achieves adaptive adjustment and control of the dead time, which facilitates improved PMIC efficiency and reduces the risk of burnout of the dual NMOS architecture's buck circuit.

[0113] According to some embodiments of this application, the operational circuit 106 may optionally include the following operational steps:

[0114] (1) Determine the actual dead time of the first field-effect transistor 136 and the second field-effect transistor 138 based on the first turn-off time and the second turn-off time.

[0115] The actual dead time of the first field-effect transistor 136 and the second field-effect transistor 138 is the intersection of the first turn-off time and the second turn-off time.

[0116] In addition, it is understandable that the field-effect transistor is not turned off instantaneously. There is a turn-off delay during the turn-off process. In order to ensure the accuracy of dead time control, before determining the actual dead time of the first field-effect transistor 136 and the second field-effect transistor 138, the turn-off time of the first turn-off time and the second turn-off time should be subtracted from the turn-off delay of the corresponding field-effect transistor respectively.

[0117] The turn-off delays of the first field-effect transistor 136 and the second field-effect transistor 138 can both be determined by the following formula:

[0118] ;

[0119] in, For the turn-off delay of the field-effect transistor; This is the gate drive resistor of the field-effect transistor; This is the driving voltage of the field-effect transistor; This is the input capacitor of the field-effect transistor; This is the plateau voltage of the field-effect transistor.

[0120] (2) Determine the time error based on the actual dead zone time and the target dead zone time.

[0121] The target dead time is a preset dead time that ensures safe turn-off between the first field-effect transistor 136 and the second field-effect transistor 138.

[0122] Optionally, the aforementioned time error is specifically the difference between the actual dead time and the target dead time; that is, the aforementioned time error can be determined using the following formula:

[0123] ;

[0124] in, Due to time error, This is the actual dead time. The target dead zone time.

[0125] (3) Determine the dead time adjustment amount based on the time error.

[0126] In practical applications, the dead time adjustment amount can be determined using the following formula:

[0127] ;

[0128] in, This is the dead time adjustment amount; This is the proportionality coefficient. is the integral coefficient.

[0129] In this way, the error between the actual dead time and the target dead time is optimized, which can further ensure the accuracy of dead time control.

[0130] (4) Determine the target capacitance value of variable capacitor 132 based on the dead time adjustment amount.

[0131] Specifically, based on the charging and discharging delay formula of the variable capacitor 132 mentioned above, the dead time adjustment amount is obtained through real-time calculation. Replace the dead time adjustment in the charge / discharge delay formula This allows us to deduce the target capacitance value that the variable capacitor 132 needs to achieve.

[0132] (5) Determine the charging and discharging cutoff voltage of variable capacitor 132 based on the target capacitance value.

[0133] Among them, the charge / discharge cutoff voltage is the target control voltage corresponding to the target capacitance value.

[0134] Specifically, based on the proportional relationship between the capacitance value of the variable capacitor 132 and the control voltage of the variable capacitor 132, the target control voltage required by the variable capacitor 132, i.e. the charge / discharge cutoff voltage, is determined according to the target capacitance value.

[0135] That is, when the delay circuit 108 includes a variable capacitor 132, such as Figure 5 As shown, the control flow for dead time may specifically include the following steps S502 to S512:

[0136] S502: Calculate the actual dead time.

[0137] S504: Determine if the dead time needs adjustment. If yes, proceed to S506; otherwise, proceed to S512.

[0138] S506: Calculate the dead time adjustment.

[0139] S508: Calculate the target control voltage for the variable capacitor.

[0140] S510: Judgment: V ctrl =V tar If yes, execute S512; otherwise, execute S506.

[0141] S512: Output drive signal.

[0142] Among them, V ctrl The control voltage for variable capacitor 132, V tar The target control voltage.

[0143] In other words, when the delay circuit 108 includes a variable capacitor 132, the core of dead-time control is to calculate the actual dead time of the first field-effect transistor 136 and the second field-effect transistor 138, and determine whether the dead time needs to be adjusted based on the adjustment direction indicated by the adjustment mode signal output by the logic judgment circuit 104. When the dead time needs to be adjusted, the variable capacitor 132 is charged and discharged using the characteristic that its capacitance value is proportional to the control voltage, until the capacitance value of the variable capacitor 132 is adjusted to the target value, that is, until the control voltage of the variable capacitor 132 reaches the target control voltage, at which point charging and discharging stops. At this point, by adding the delay circuit 108 to the loop, dead-time control can be achieved.

[0144] For example, when the dead time is too small, based on the control flow of "increase in the control voltage of the variable capacitor → increase in the capacitance value of the variable capacitor → increase in the delay value of the delay circuit → increase in the dead time", the variable capacitor 132 is charged, which increases the control voltage of the variable capacitor 132, thereby increasing the capacitance value of the variable capacitor 132, increasing the delay value of the delay circuit 108, and increasing the dead time, until the control voltage of the variable capacitor 132 reaches the target control voltage, then charging stops, and the high and low side drive signals are output.

[0145] For example, when the dead time is too large, based on the control flow of "reducing the control voltage of the variable capacitor → reducing the capacitance value of the variable capacitor → reducing the delay value of the delay circuit → reducing the dead time", the variable capacitor 132 is discharged, which reduces the control voltage of the variable capacitor 132, thereby reducing the capacitance value of the variable capacitor 132, reducing the delay value of the delay circuit 108, and reducing the dead time, until the control voltage of the variable capacitor 132 reaches the target control voltage, the discharge stops, and the high and low side drive signals are output.

[0146] At this point, the working principle of the dead time control circuit 100 can be specifically described as follows: Figure 6 As shown. Specifically, the detection circuit 102 performs three-terminal sampling detection on the high- and low-side NMOS. Based on the three-terminal sampling detection results, the logic judgment circuit 104 and the arithmetic circuit 106 perform processing and calculation, and output a dead time control signal. Based on the target control voltage indicated by the dead time control signal, the output voltage of the control voltage source is controlled, thereby controlling the charging and discharging of the variable capacitor 132 to adjust the capacitance value of the variable capacitor 132, thereby adjusting the turn-off time of the high- and low-side NMOS, and thus adjusting the dead time.

[0147] Specifically, when the delay circuit 108 includes a variable capacitor 132, the dead-time control circuit 100 acquires voltage information from the high-side and low-side NMOS transistors and uses a high-speed comparator and a differentiating comparator to determine the switching state and current edge changes of the high-side and low-side NMOS transistors, thereby determining the turn-off time and dead-time adjustment direction of the high-side and low-side NMOS transistors. Based on this, the actual dead time of the high-side and low-side NMOS transistors is calculated, and based on the actual dead time and the preset target dead time, the dead-time adjustment amount is calculated using hardware such as adders and multipliers. Then, based on the dead-time adjustment amount, the target capacitance value of the variable capacitor 132 and the corresponding target control voltage are derived from the charging and discharging delay formula of the variable capacitor 132. Based on this, a dead-time control signal is generated, which causes the control voltage source to output the target control voltage to adjust the capacitance value of the variable capacitor 132, thereby achieving adaptive adjustment of the dead time.

[0148] According to the dead-time control circuit 100 of this application embodiment, the arithmetic circuit 106 is specifically used to: determine the actual dead time of the first field-effect transistor 136 and the second field-effect transistor 138 based on the first turn-off time and the second turn-off time; determine the time error based on the actual dead time and the target dead time; determine the dead-time adjustment amount based on the time error; determine the target capacitance value of the variable capacitor 132 based on the dead-time adjustment amount; and determine the charging and discharging cutoff voltage of the variable capacitor 132 based on the target capacitance value. Thus, based on the charging and discharging control of the variable capacitor 132, the time delay value of the delay circuit 108 is controlled, thereby achieving adaptive adjustment control of the dead time.

[0149] According to some embodiments of this application, optionally, such as Figure 2 As shown, the delay circuit 108 includes multiple delay networks 134.

[0150] Specifically, the delay network 134 can be an RC network, that is, the delay circuit 108 is an RC array circuit including multiple RC networks.

[0151] Optionally, each delay network 134 is connected to the operational circuit 106, the first field-effect transistor 136, and the second field-effect transistor 138.

[0152] Optionally, different delay networks 134 have different delay values, and the dead time control signal is used to control the on / off state of each delay network 134.

[0153] According to the dead-time control circuit 100 of this application embodiment, the delay circuit 108 includes multiple delay networks 134, each of which is connected to the arithmetic circuit 106, the first field-effect transistor 136, and the second field-effect transistor 138. The delay values ​​of the different delay networks 134 are different, and the dead-time control signal is used to control the on / off state of each delay network 134. Thus, by using multiple delay networks 134, the purpose of adjusting the dead time by switching delay networks 134 with different delay values ​​is achieved, realizing adaptive adjustment control of the dead time. This facilitates improved PMIC efficiency and reduces the risk of burnout in the dual NMOS architecture.

[0154] According to some embodiments of this application, the operational circuit 106 may optionally include the following operational steps:

[0155] (1) Determine the actual dead time of the first field-effect transistor 136 and the second field-effect transistor 138 based on the first turn-off time and the second turn-off time. The method for determining the actual dead time is the same as described above, and will not be repeated here.

[0156] (2) Determine the time error based on the actual dead time and the target dead time. The method for determining the time error is the same as described above, and will not be repeated here.

[0157] (3) Determine the dead time adjustment amount based on the time error. The method for determining the dead time adjustment amount is the same as described above, and will not be repeated here.

[0158] (4) Update the target dead time based on the dead time adjustment amount and the actual dead time.

[0159] The updated target dead time is specifically the sum of the dead time adjustment and the actual dead time. That is, the updated target dead time can be determined using the following formula:

[0160] ;

[0161] in, The updated target dead time; This represents the actual dead time.

[0162] (5) Switch the delay network 134, whose delay value is closest to the updated target dead time, to the on state.

[0163] Specifically, the computing circuit 106 can calculate the dead time corresponding to each delay network 134, and then switch the delay network 134 whose dead time is less than the updated target dead time to the on state.

[0164] Among them, the dead time corresponding to multiple delay networks 134 can be an arithmetic sequence, and the preset difference is determined according to the common difference of the arithmetic sequence. Specifically, the preset difference can be less than half of the common difference.

[0165] That is, when the delay circuit 108 includes multiple delay networks 134 with different delay values, such as Figure 7 As shown, the control flow for dead time may specifically include the following S602 to S614:

[0166] S602: Calculate the actual dead time.

[0167] S604: Determine if the dead time needs adjustment. If yes, proceed to S606; otherwise, proceed to S614.

[0168] S606: Calculate the dead time adjustment.

[0169] S608: Calculate the target dead time.

[0170] S610: Switching to a latency network.

[0171] S612 judgment: |t dead_new -tRC If |<ΔT, execute S614; otherwise, execute S606.

[0172] S614: Output drive signal.

[0173] Among them, t RC ΔT represents the dead time corresponding to delay network 134, and ΔT is the preset difference.

[0174] At this point, the working principle of the dead time control circuit 100 can be specifically described as follows: Figure 8 As shown. Specifically, the detection circuit 102 performs three-terminal sampling detection on the high and low side NMOS. Based on the three-terminal sampling detection results, the logic judgment circuit 104 and the arithmetic circuit 106 perform processing and calculation to output a dead time control signal. Based on the dead time control signal, the on / off state of the multi-stage RC network is controlled, and a selector selects one RC network to be turned on, so that the dead time corresponding to the turned-on RC network is closest to the calculated target dead time.

[0175] Specifically, when the delay circuit 108 includes multiple delay networks 134, the dead time control circuit 100 acquires voltage information from the high-side and low-side NMOS transistors and uses a high-speed comparator and a differentiating comparator to determine the switching state and current edge changes of the high-side and low-side NMOS transistors, thereby determining the turn-off time of the high-side and low-side NMOS transistors and the adjustment direction of the dead time. Based on this, the actual dead time of the high-side and low-side NMOS transistors is calculated based on their turn-off times. Then, based on the actual dead time of the high-side and low-side NMOS transistors and a preset target dead time, the dead time adjustment amount is calculated using hardware such as adders and multipliers. The target dead time is then updated based on the dead time adjustment amount, and the delay network 134 whose dead time is closest to the updated target dead time is determined based on the updated target dead time. Finally, a dead time control signal is generated, which controls the on / off state of the multi-stage delay networks 134, thereby adjusting the delay value of the delay circuit 108 and achieving adaptive adjustment of the dead time.

[0176] According to the dead-time control circuit 100 of this application embodiment, the arithmetic circuit 106 is specifically used to: determine the actual dead time of the first field-effect transistor 136 and the second field-effect transistor 138 based on the first turn-off time and the second turn-off time; determine the time error based on the actual dead time and the target dead time; determine the dead-time adjustment amount based on the time error; update the target dead time based on the dead-time adjustment amount and the actual dead time; and switch the delay network 134 whose delay value is closest to the updated target dead time to the on state. In this way, by controlling the on and off states of the multi-level delay network 134, the delay value of the delay circuit 108 is controlled, thereby realizing the adaptive adjustment control of the dead time.

[0177] According to some embodiments of this application, optionally, the first field-effect transistor 136 and the second field-effect transistor 138 are both N-type field-effect transistors.

[0178] That is, the dead time control circuit 100 in this application embodiment is used to control the dead time of the buck switching circuit with dual NMOS architecture.

[0179] Among them, the first field-effect transistor 136 is a high-side NMOS, and the second field-effect transistor 138 is a low-side NMOS.

[0180] According to the dead-time control circuit 100 of this application embodiment, both the first field-effect transistor 136 and the second field-effect transistor 138 are N-type field-effect transistors. This enables adaptive dead-time control based on pure hardware circuitry for a dual-NMOS architecture BUCK, facilitating wider application of the dual-NMOS architecture BUCK.

[0181] In summary, the dead-time control circuit 100 provided in this application embodiment can be equivalent to... Figure 9 The architecture diagram shown includes three parts: a detection module, a calculation module, and an execution module. Figure 9 AND gate correspondence in Figure 1 and Figure 2 The first time counter 122, the first time register 124, the second time counter 126, the second time register 128, and the logic judgment module 130 are all controlled by digital gate circuits. Figure 9 The multiplexer in the middle is responsible for selecting the adjustment mode signal that indicates the adjustment direction of the dead time based on the comparison result of the truth table of the dead time control logic. Figure 9 The dead-time register in the circuit is used to store the parameter values ​​calculated by the preceding circuit, so that the following circuit can read and calculate them. Figure 9 The combination of adders and multipliers, dead-time registers, and voltage-controlled delay lines in the code corresponds to... Figure 1 and Figure 2 The combination of adder, multiplier, and delay circuit 108.

[0182] According to some embodiments of this application, optionally, such as Figure 10 As shown, this application embodiment also provides an electronic device 200. The electronic device 200 includes the dead-time control circuit 100 from any of the above embodiments.

[0183] The electronic device 200 provided in this application includes the dead time control circuit 100 in any of the above embodiments and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0184] It should be noted that the electronic device 200 in the embodiments of this application includes mobile electronic devices and non-mobile electronic devices.

[0185] In practical applications, the electronic device 200 can be a terminal or other devices besides a terminal. For example, the electronic device 200 can be a mobile phone, tablet computer, laptop computer, handheld computer, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. The embodiments of this application do not specifically limit it.

[0186] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0187] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A dead-time control circuit, characterized in that, include: Inductive components; The first field-effect transistor is connected to the inductor; The second field-effect transistor is of the same type as the first field-effect transistor, and the second field-effect transistor is connected to both the inductor and the first field-effect transistor; The detection circuit is connected to both the first field-effect transistor and the second field-effect transistor, and is used to detect the first switching state of the first field-effect transistor, the second switching state of the second field-effect transistor, and the current flow direction of the inductor. A logic judgment circuit, connected to the detection circuit, is used to output a dead time adjustment mode signal, a first turn-off time of the first field-effect transistor, and a second turn-off time of the second field-effect transistor based on the first switch state, the second switch state, and the current flow direction. The arithmetic circuit, connected to the logic judgment circuit, is used to output a dead time control signal according to the adjustment direction indicated by the adjustment mode signal and based on the first shutdown time and the second shutdown time. The delay circuit is connected to the operational circuit, the first field-effect transistor, and the second field-effect transistor. The dead time control signal is used to adjust the delay value of the delay circuit to adjust the dead time of the first field-effect transistor and the second field-effect transistor.

2. The dead-time control circuit according to claim 1, characterized in that, The detection circuit includes: A first comparator, connected to the first field-effect transistor, is used to output a first switching signal based on a first bias voltage of the first field-effect transistor. The first switching signal is used to indicate the first switching state. The second comparator, connected to the second field-effect transistor, is used to output a second switching signal based on the second bias voltage of the second field-effect transistor. The second switching signal is used to indicate the second switching state. A third comparator, connected to both the first and second field-effect transistors, is used to output a current edge signal based on the first and second bias voltages, the current edge signal being used to indicate the direction of current flow.

3. The dead-time control circuit according to claim 2, characterized in that, The detection circuit further includes: A first flip-flop, connected to the first comparator, is used to transmit the first switching signal according to a first clock signal; The second flip-flop, connected to the second comparator, is used to transmit the second switching signal according to the second clock signal; The third flip-flop, connected to the third comparator, is used to transmit the current edge signal according to the third clock signal; The first clock signal, the second clock signal, and the third clock signal are synchronized with each other.

4. The dead-time control circuit according to claim 3, characterized in that, The logic judgment circuit includes: A first time counter, connected to the first trigger, is used to time according to the first switch signal and output the first off time; A first time register, connected to the first time counter, is used to cache the first shutdown time; The second time counter, connected to the second trigger, is used to time according to the second switch signal and output the second off time; The second time register, connected to the second time counter, is used to cache the second shutdown time; The logic judgment module is connected to the first flip-flop, the second flip-flop, and the third flip-flop. The logic judgment module stores a dead-time control logic truth table. The logic judgment module is used to output the adjustment mode signal according to the dead-time control logic truth table, based on the first switch signal, the second switch signal, and the current edge signal.

5. The dead-time control circuit according to claim 1, characterized in that, The time delay circuit includes: A variable capacitor is connected to the operational circuit, the first field-effect transistor, and the second field-effect transistor. The dead time control signal is used to control the charging and discharging state of the variable capacitor and to control the charging and discharging cutoff voltage of the variable capacitor.

6. The dead-time control circuit according to claim 5, characterized in that, The operational circuit is specifically used for: The actual dead time of the first field-effect transistor and the second field-effect transistor is determined based on the first turn-off time and the second turn-off time. The time error is determined based on the actual dead time and the target dead time. The dead time adjustment amount is determined based on the aforementioned time error; The target capacitance value of the variable capacitor is determined based on the dead time adjustment amount. The charge / discharge cutoff voltage of the variable capacitor is determined based on the target capacitance value.

7. The dead-time control circuit according to claim 1, characterized in that, The time delay circuit includes: Multiple delay networks, each of which is connected to the computing circuit, the first field-effect transistor, and the second field-effect transistor; The delay values ​​of the different delay networks are different, and the dead time control signal is used to control the on / off state of each delay network.

8. The dead-time control circuit according to claim 7, characterized in that, The operational circuit is specifically used for: The actual dead time of the first field-effect transistor and the second field-effect transistor is determined based on the first turn-off time and the second turn-off time. The time error is determined based on the actual dead time and the target dead time. The dead time adjustment amount is determined based on the aforementioned time error; The target dead time is updated based on the dead time adjustment amount and the actual dead time; The latency network whose latency value is closest to the updated target dead time is switched to the on state.

9. The dead-time control circuit according to any one of claims 1 to 8, characterized in that, Both the first field-effect transistor and the second field-effect transistor are N-type field-effect transistors.

10. An electronic device, characterized in that, include: The dead time control circuit as described in any one of claims 1 to 9.

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