Phased Array Antenna Systems

Abstract

The phased array antenna system includes antenna elements of a radio frequency front end, each antenna element propagating a wireless beam portion. The digital beamforming system generates a digital beam corresponding to a wireless beam transmitted or received from the phased array antenna system. The digital beamforming processors are each associated with a proper subset of the antenna elements. The digital beamforming processors can be collectively configured to iteratively process the digital beam portions of the digital beams in a plurality of iteration stages, the plurality of iteration stages including a lowest iteration stage associated with a lowest level digital beam portion corresponding to each wireless beam portion at each antenna element and a highest iteration stage associated with the digital beam. Each digital beam portion associated with a given iteration stage includes a sum of smaller digital beam portions from the next lower iteration stage.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. patent application serial number 16 / 804,833, filed on February 28, 2020, the contents of which are incorporated herein in their entirety.

[0003] Government interests

[0004] This invention was made pursuant to a government contract. Therefore, the United States Government owns the invention under that contract. Technical Field

[0005] The present disclosure relates generally to communications and, more particularly, to phased array antenna systems. Background Art

[0006] Modern wireless communications implement a variety of different physical arrangements for associated antennas for transmitting and receiving wireless beams. One example is arranged as a phased array antenna including an array of antenna elements. Each antenna element can be configured to propagate (e.g., transmit or receive) a portion of a wireless beam, wherein a portion of the wireless beam is associated with a delay and amplitude of the wireless beam to provide beam steering of the wireless beam. For received wireless beams, the received wireless beam portions can be combined and processed to determine a composite wireless beam that can be digitized and processed (e.g., to determine the data modulated therein). For transmitted wireless beams, digital beams can be generated and the digital beams can be decomposed into individual analog portions that are provided to the antenna elements with their respective delays and amplitudes for transmission of the wireless beams. The process of converting between digital beams and wireless beam portions is called beamforming, and the process is typically performed by a beamforming processor that is coupled to the antenna elements via large fan-out conductors. Summary of the invention

[0007] The phased array antenna system includes antenna elements of a radio frequency (RF) front end, each antenna element propagating a wireless beam portion. A digital beamforming system generates a digital beam corresponding to a wireless beam transmitted or received from the phased array antenna system. Each digital beamforming processor is associated with a proper subset of the antenna elements. The digital beamforming processors can be configured together to iteratively process digital beam portions of a digital beam in multiple iteration levels, the multiple iteration levels including a lowest iteration level associated with a lowest level digital beam portion and a highest iteration level associated with a digital beam, the lowest level digital beam portion corresponding to each wireless beam portion at each antenna element. Each digital beam portion associated with a given iteration level includes the sum of smaller and relatively delayed digital beam portions from the next lower iteration level.

[0008] Another example includes a method for receiving a wireless beam through a phased array antenna system. The method includes receiving a portion of a wireless beam at each of a plurality of antenna elements arranged in an array, and the antenna elements are associated with an RF front end. The method also includes converting the wireless beam portion associated with each antenna element into a respective lowest-level digital beam portion through respective multiple analog-to-digital converters (ADCs). The method also includes adding the lowest-level digital beam portion associated with each of a plurality of true subsets of antenna elements through each of a plurality of digital beamforming processors to generate a plurality of digital beam portions at the lowest iteration level of iterative processing of the wireless beam. The method also includes iteratively adding digital beam portions in a plurality of iteration levels including a lowest iteration level and a highest iteration level via the digital beamforming processor. Each digital beam portion associated with a given iteration level includes the sum of smaller and relatively delayed digital beam portions from the next lower iteration level of the iterative processing. The method also includes adding the digital beam portion associated with the highest iteration level to generate a digital beam corresponding to the wireless beam.

[0009] Another example includes a method for transmitting a wireless beam through a phased array antenna system. The method includes generating a digital beam corresponding to a wireless beam transmitted from the phased array antenna system. The method includes allocating a digital beam portion from a digital beam at a highest iteration level of multiple iteration levels of iterative processing of the digital beam by a plurality of digital beamforming processors. The method also includes iteratively allocating the digital beam portion in a plurality of iteration levels including a highest iteration level and a lowest iteration level via the digital beamforming processor. Each digital beam portion associated with a given iteration level is allocated from the given iteration level to the next lower iteration level of the iterative processing as a plurality of smaller digital beam portions with relatively different time delays, wherein the smaller digital beam portions are generally equal to the respective digital beam portions. The method also includes allocating a plurality of digital beam portions to generate a plurality of lowest-level digital beam portions associated with each of a plurality of antenna elements by each of a plurality of digital beamforming processors, the lowest iteration level of the iterative processing of the digital beam. The method also includes converting the lowest-level digital beam portion into a wireless beam portion associated with each of the respective plurality of antenna elements via respective plurality of digital-to-analog converters (DACs), and transmitting the wireless beam portion as a wireless beam from each of the respective plurality of antenna elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1An example diagram of a phased array antenna system is shown.

[0011] Figure 2 An example diagram of a digital beamformer processor is shown.

[0012] Figure 3 An example diagram of antenna elements of an RF front end is shown.

[0013] Figure 4 Another example diagram of antenna elements of an RF front end is shown.

[0014] Figure 5 Another example diagram of antenna elements of an RF front end is shown.

[0015] Figure 6 Another example diagram of antenna elements of an RF front end is shown.

[0016] Figure 7 Yet another example diagram of an antenna element of an RF front end is shown.

[0017] Figure 8 An example diagram of an iterative beamforming process is shown.

[0018] Fig. 9 Another example diagram of an iterative beamforming process is shown.

[0019] Fig.10 An example of a method of receiving a wireless beam via a phased array antenna system is shown.

[0020] Fig.11 An example of a method of transmitting a wireless beam via a phased array antenna system is shown. DETAILED DESCRIPTION

[0021] The present disclosure relates generally to communications, and more particularly to phased array antenna systems. Phased array antenna systems are implemented in any of a variety of communication applications for achieving beam steering or multi-directional signal reception. The phased array antenna system includes a radio frequency (RF) front end, the RF front end including an array of antenna elements, each of which can be configured to propagate a wireless beam portion. As described herein, the term "propagation" with respect to wireless beams and wireless beam portions means signal transmission or reception, such that the phased array antenna system can transmit and receive wireless beams. Therefore, the wireless beam portions can have different phase and / or amplitude components, which can correspond to beamforming of the wireless beam, such as for transmitting a wireless beam from the phased array antenna system in a predetermined direction, or for processing a source from which the phased array antenna system receives the wireless beam.

[0022] The phased array antenna system also includes a digital beamforming system configured to generate a digital beam. For example, the digital beam may contain modulated data. The digital beam may correspond to a wireless beam transmitted from or received at an RF front end, and the digital beam may be generated to have corresponding delay and amplitude components that may be associated with beamforming of the wireless beam. The phased array antenna system also includes a digital signal conditioner system configured to provide signal conditioning and analog / digital conversion of respective digital beams / wireless beams. For example, signal conditioning may include tuning, filtering, extraction, and / or time-alignment of a portion of the digital beam, and may also include an analog-to-digital converter (ADC) that converts a received analog wireless beam into a digital beam and a digital-to-analog converter (DAC) that converts a digital beam into an analog wireless beam for transmission.

[0023] In addition, the digital beamforming system includes a plurality of digital beamforming processors. The digital beamforming processors may be distributed across the antenna element array such that each digital beamforming processor may be associated with a proper subset of the antenna elements. Thus, each digital beamforming processor may be communicatively coupled to a portion of the antenna elements to process a lowest-level digital beam portion associated with each corresponding antenna element in the proper subset. As described herein, the term "processing" refers to an additive combination (e.g., for a received wireless beam) or allocation (e.g., for a transmitted wireless beam) of digital beam portions at each of a plurality of iteration levels between the lowest-level digital beam portions associated with each of the individual antenna elements and the digital beam as a set of all lowest-level digital beam portions. At each iteration level, delay information may be applied to the respective digital beam portions of each iteration group of antenna elements to perform iterative beamforming.

[0024] For example, as described in more detail herein, the application of delays in the receive direction involves delaying a given lower iteration level digital beam portion so as to be time-aligned with at least one of the other lower iteration level digital beam portions that form a given next higher iteration level digital beam portion (e.g., the digital beam portion that is delayed to arrive the largest based on the beam direction of the received wireless beam). Thus, for example, the digital beam portion with the longest delay in the set of digital beam portions corresponds to the portion of the antenna array that is closest in direction to the source that transmits the received wireless beam. Similarly, as described in more detail herein, the application of delays in the transmit direction involves delaying each lower iteration level digital beam portion individually relative to each other. Thus, for example, the digital beam portion with the longest delay in the set of digital beam portions corresponds to the portion of the antenna array that is closest in direction to the direction in which the wireless beam is transmitted. As another example, the delay associated with the lowest level digital beam portion at the antenna element level can be achieved by phase shifting the digital signals or analog signals associated with the antenna elements relative to each other, such as approximating a delay within a limited frequency range. Furthermore, while the above examples of applying delays may correspond to processing a plane wave at a digital beamforming system, it should be understood that delays of digital beam portions may be provided in a variety of different ways for beamforming purposes. While relative delays are described throughout this document, it should also be understood that amplitude information may also be applied to each digital beam portion in each iteration stage. As used herein, the term "allocate" and variations thereof refer to allocating a given digital beam portion associated with a given iteration stage as a plurality of digital beam portions from a digital beamforming processor to respective different digital beamforming processors.

[0025] As described in more detail herein, the digital beamforming processor can iteratively process digital beam portions of a digital beam together in a plurality of iteration stages. The iteration stages can include a lowest iteration stage associated with a lowest level digital beam portion associated with each respective antenna element, the iteration stages can include a highest iteration stage associated with the digital beam itself, and can include at least one iteration stage therein. Thus, each digital beam portion associated with a given iteration stage can include the sum of smaller digital beam portions from the next lower iteration stage. By providing iterative processing of digital beam portions associated with a digital beam, the phased array antenna system can therefore more efficiently provide beamforming of the digital beam, rather than assigning beamforming component signals from each individual antenna element to a processor.

[0026] Figure 1 An example diagram of a phased array antenna system 10 is shown. The phased array antenna system 10 may be implemented in any of a variety of communications applications that implement beam steering or multi-directional signal reception.

[0027] exist Figure 1 In the example of FIG. 1 , a phased array antenna system 10 includes a radio frequency (RF) front end 12 including a plurality of antenna elements 14 arranged in an array. Each antenna element 14 may be configured to propagate a wireless beam portion. Figure 1 In the example of , the wireless beam is shown as a wireless signal “WB (wireless signal)”, and the wireless beam portion is shown as a signal set WBP (wireless beam portion). For example, the phased array antenna system 10 can be bidirectional, so that the wireless beam WB can be received by the phased array antenna system 10 or transmitted from the phased array antenna system 10. Therefore, the wireless beam portion WBP can have different phase and / or amplitude components corresponding to the beamforming of the wireless beam WB, for example, for transmitting the wireless beam WB from the phased array antenna system 10 in a predetermined direction, or for pointing the phased array antenna system 10 to the transmission source of the wireless beam WB received by the phased array antenna system 10.

[0028] The phased array antenna system 10 also includes a digital beamforming system 16 configured to generate digital beams, such as Figure 1 As shown in the example of , as a signal DB (digital beam). For example, the digital beam DB may include modulated data, such as communication data, radar data, or any other type of baseband data that can be modulated onto a higher frequency carrier. The digital beam DB may correspond to a wireless beam WB transmitted from or received at the RF front end 12, and may be generated to have corresponding delay and amplitude components as provided on the wireless beam portion WBP that may be associated with beamforming of the wireless beam WB.

[0029] The phased array antenna system 10 also includes a digital signal conditioner system 18 configured to provide signal conditioning and analog / digital conversion between the respective digital beams DB and wireless beams WB. Figure 1 In the example of , the digital signal conditioner system 18 includes a collection of analog-to-digital converters (ADC) and digital-to-analog converters (DAC), collectively referred to as "DAC / ADC" 20. The analog-to-digital converter (ADC) is used to convert an analog wireless beam WB into a digital beam DB, and the digital-to-analog converter (DAC) is used to convert the digital beam DB into an analog wireless beam WB for transmission. In addition, the digital signal conditioner system 18 may include various other signal conditioning elements that may provide tuning, filtering, extraction, and / or time alignment of a lowest-level digital beam portion (hereinafter referred to as "lowest-level digital beam portion (LDBP)") corresponding to an extracted portion of the digital beam DB.

[0030] In addition, the digital signal conditioner system 18 includes a plurality of digital beamforming processors (DBF) ("DBF processors") 22. For example, the digital beamforming processors 22 may be configured as any of a variety of processing devices, such as a processor, an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other types of processing devices. The digital beamforming processors 22 may be distributed throughout the array of antenna elements 14 such that each digital beamforming processor 22 may be associated with a proper subset of the antenna elements 14. Thus, each digital beamforming processor 22 may be communicatively coupled to a portion of the antenna elements 14 to process a respective lowest level digital beam portion associated with each corresponding antenna element 14 in the proper subset. As described in more detail herein, the digital beamforming processors 22 may collectively iteratively process the digital beam portions of the digital beam DB in multiple iteration stages. The iteration levels may include a lowest iteration level associated with a lowest level digital beam portion corresponding to each of the respective antenna elements 14, and may include a highest iteration level associated with a digital beam DB, and may include at least one iteration level therebetween.

[0031] Each digital beam portion associated with a given iteration level may include a collection of smaller digital beam portions from the next lower iteration level. For example, each digital beam portion is associated with a plurality of lowest-level digital beam portions corresponding to a subset of antenna elements 14. Thus, the digital beam portion associated with a given iteration level includes a subset of antenna elements 14 that is larger than the subset of antenna elements 14 associated with the next lower iteration level of the iterative process. In addition, at each iteration level, the digital beamforming processor 22 may add or apply delay information to the respective digital beam portions for each successive iteration group of antenna elements 14 to perform iterative beamforming. Based on the fact that the delay values ​​of physically proximal antenna elements 14 are relatively close, while the delay values ​​of relatively distal antenna elements 14 are diametrically opposed, this iterative application of delays in each iteration level provides efficient processing by the digital beamforming processor. In other words, for any given beam direction, the amount of delay required for digital beamforming is similar for antenna elements 14 that are physically close to each other, while the delay difference is greatest for antenna elements 14 that are physically far apart. By providing iterative processing of digital beam portions associated with digital beam DB, the phased array antenna system 10 may therefore more efficiently provide beamforming for the digital beam DB rather than distributing the beamforming component signals from one processor to each individual antenna element 14 .

[0032] In addition, the digital signal conditioner system 18 may include multiple separate frequency channels, each channel being associated with a respective separate frequency. Each frequency channel may be coupled to each of the multiple digital beamforming processors 22, so that the iterative beamforming described herein may be implemented simultaneously on multiple different signals, each having a respective separate frequency. For example, a digital beam portion DBP from the highest iteration level or a lowest level digital beam portion LDBP from the lowest iteration level may be frequency converted to different frequency bands, and different delays may be applied to each antenna element 14. Additionally or optionally, the phased array antenna system 10 may be configured to simultaneously process multiple wireless beams WB having similar or identical frequency bands based on wireless beam portions WBP having different delays and / or amplitude components for each antenna element 14, which may be provided to or received from different directions. For example, different signals may be at the same or different frequency bands, and a separate wireless beam WB may be assigned to each of the antenna elements 14, wherein each composite wireless beam portion WBP may have a different delay at any one of the antenna elements 14. The delayed wireless beam portions WBP of the separate wireless beams WB may be summed before being output through each respective one of the antenna elements 14, wherein the respective separate wireless beam portions WBP for the respective separate wireless beams WB have different delays. In addition, the phased array antenna system 10 may be configured to iteratively process the digital beam portions of the transmitted and received wireless beams, respectively, in parallel based on the conductive connections between the digital beamforming processors 22, as described in more detail herein.

[0033] Figure 2 An example schematic diagram 50 of a digital beamforming processor is shown, illustrated diagrammatically at 52. Schematic diagram 50 illustrates a visual depiction of an iterative process of providing a digital beamforming DB in an iterative level structure. For example, digital beamforming processor 52 may correspond to Figure 1 The digital beamforming processor 22 in the example of FIG. Figure 2 In the description of the example, reference will be made to Figure 1 .

[0034] Schematic diagram 50 shows N iteration stages of an iterative process, where N is a positive integer greater than or equal to 2. The iteration stages include a first iteration stage 54, denoted as “1-stage array processing”, a second iteration stage 56, denoted as “2-stage array processing”, and an N-th iteration stage 58, denoted as “N-stage array processing”. It should be understood that the digital beamforming processor 52 may implement additional iteration stages between the second iteration stage 56 and the N-th iteration stage 58. Figure 2In the example of , the iteration stages 54 , 56 , and 58 are arranged between the digital beam DB provided to and from the Nth iteration stage 58 and the plurality of lowest level digital beam parts LDBP provided to and from the first iteration stage 54 .

[0035] As an example, for a received radio beam WB, each antenna element 14 may provide individual radio beam portions associated with the amplitude and relative delay of the individual radio beams WB. The radio beam portions may all be digitized (e.g., by an ADC 20 associated with a digital signal conditioner system 18) to generate a lowest-level digital beam portion LDBP as a digital equivalent of the radio beam portion. The digital beamforming processor 52 may therefore apply respective delays between the lowest-level digital beam portions LDBP in a given set of antenna elements 14, and add each lowest-level digital beam portion LDBP in a plurality of sets of lowest-level digital beam portions LDBP to the first iteration stage 54 to generate a first iteration stage digital beam portion DBP1. As an example, a relative delay may be assigned to each first iteration stage digital beam portion DBP1, such as corresponding to the minimum delay of a single antenna element 14 in the set of antenna elements 14 associated with the respective first iteration stage digital beam portion DBP1. Each first iteration level digital beam portion DBP1 may correspond to the sum of the lowest level digital beam portions LDBP associated with a given proper subset of antenna elements 14. For example, each digital beamforming processor 52 is configured to generate a respective first iteration level digital beam portion DBP1. As another example, each proper subset of antenna elements 14 may be approximately equal relative to the number of antenna elements 14.

[0036] exist Figure 2In an example of , the digital beamforming processor 52 may apply respective delays between first iteration level digital beam parts DBP1 of a relatively large set of antenna elements 14, and may add the first iteration level digital beam parts DBP1 in the second iteration level 56 to generate second iteration level digital beam parts DBP2. As an example, a relative delay may be assigned to each second iteration level digital beam part DBP2, such as a minimum delay of the first iteration level digital beam parts DBP1 of the set of antenna elements 14 associated with the respective second iteration level digital beam parts DBP2. As another example, the next higher iteration level of the digital beamforming processor 52 may apply delays between the first iteration level digital beam parts DBP1 to achieve beamforming of the received wireless beam WB. As an example, each second iteration level digital beam part DBP2 may include the sum of the set of first iteration level digital beam parts DBP1 in the second iteration level 56, so that the number of second iteration level digital beam parts DBP2 is less than the number of first iteration level digital beam parts DBP1. Thus, each second iteration level digital beam portion DBP2 corresponds to the sum of the lowest level digital beam portions LDBP from a number of antenna elements 14 that is greater than the number of antenna elements 14 associated with each first iteration level digital beam portion DBP2. As an example, a proper subset of the digital beamforming processors 52 may be configured to generate a respective one of the second iteration level digital beam portions DBP2.

[0037] Thus, the digital beamforming processors 52 may continue to iteratively apply respective delays to the digital beam portions DBPX and add successive digital beam portions DBPX, where X corresponds to a given iteration level. For example, different sets of digital beamforming processors 52 may be configured to add digital beam portions DBPX from a given iteration level relative to other iteration levels, such that a given one of the digital beamforming processors 52 does not generate digital beam portions DBP from more than two separate iteration levels (e.g., the first iteration level 54 and one other iteration level). Figure 2 In the example of , the Nth iteration stage 58 receives the digital beam part DBPN-1 from the N-1 iteration stage and adds the digital beam part DBPN-1 to generate the digital beam DB. For example, the digital beam DB may thus correspond to the sum of the lowest level digital beam parts LDBP of each antenna element 14 of the RF front end 12, and may thus correspond to the wireless beam WB. As an example, in response to adding the digital beam part DBPN-1, the digital beam DB may be generated by a single digital beamforming processor 52 in the digital beamforming processors 52.

[0038] The digital beam DB may be provided to the digital beamforming system 16 for processing the digital beam DB corresponding to the wireless beam WB. For example, the digital beamforming system 16 may process the data associated with the digital beam DB to provide delay and amplitude information associated with the wireless beam portion WBP associated with each antenna element 14. Therefore, the beamforming information associated with the digital beam DB determined by the digital beamforming system 16 may facilitate demodulation of the data in the digital beam DB in the receiving direction, for example, for signal detection, signal characterization, radar image processing, and / or other receiver applications. In addition, as previously described, the digital beam portion at each iteration level may correspond to the beamforming of multiple digital beam DBs, each of which has a respective separate frequency, for example, for concurrent transmission, reception, or a combination of transmission and reception of multiple corresponding wireless beams.

[0039] As an example, the iterative processing of the digital beamforming processor 52 can be substantially reversed to transmit the wireless beam WB. For example, the digital beamforming system 16 can generate a digital beam DB based on a desired beamforming characteristic associated with a desired direction of the wireless beam WB to be transmitted. Therefore, the digital beam DB can be provided to a digital beamforming processor 52, which is configured to allocate a digital beam portion DBPN-1 from the digital beam DB in the Nth iteration stage 58. For example, the digital beamforming processor 52 can allocate the digital beam portion DBPN-1 and can apply a relatively different delay to each digital beam portion DBPX in each consecutive iteration stage to steer the wireless beam WB to the desired direction. In the example of transmitting multiple wireless beams WB from the phased array antenna system 10, the digital beamforming processor 52 can receive a digital beam portion DBPN-1 for each of the multiple digital beams DB in different transmission directions, apply multiple delays associated with different directions and different antenna elements 14, and sum the delayed wireless beam portions WBP ultimately provided to the specific antenna element 14.

[0040] Each digital beam portion DBPN-1 is provided to a separate digital beamforming processor 52 for processing in the N-1 iteration stage. Thus, the digital beamforming processor 52 may continue to iteratively allocate successive digital beam portions DBPX using different sets of digital beamforming processors 52 for allocating digital beam portions DBPX from a given iteration stage relative to other iteration stages. For example, at each successive iteration stage, the digital beamforming processor 52 may apply a different relative delay to each different digital beam portion DBPX, such as a minimum delay associated with a given one of the antenna elements 14 relative to other antenna elements 14 in the respective corresponding set of antenna elements 14 of the respective digital beam portion DBPX. At the first iteration stage 54, respective lowest level digital beam portions LDBP may be allocated from each digital beam portion DBP1 by respective digital beamforming processors 52, wherein each lowest level digital beam portion LDBP has a respective relative delay for transmitting a respective corresponding wireless beam portion WBP. The lowest level digital beam portion LDBP may be converted to an analog wireless beam portion (e.g., by Figure 1 DAC 20 in the example of ), so that each wireless beam part WBP can be transmitted from each antenna element 14. As another example, the digital baseband data associated with the lowest-level digital beam part LDBP can be a digital stream to be modulated for a communication link (e.g., before or after the associated DAC), or it can be a low-frequency waveform (e.g., a complex digital representation centered around about 0 Hz, or a real digital representation with positive frequencies above about 0 Hz) that can be converted to a higher frequency for transmission (e.g., analog, digital, or a combination of analog and digital). Therefore, the common transmission of the wireless beam parts WBP from the various antenna elements 14 can result in the transmission of a wireless beam WB based on the desired beamforming characteristics of the generated digital beam DB.

[0041] like Figure 2 For an example, refer to Figure 3-Figure 7 The example further describes the iterative level processing between the digital beam DB and the lowest level digital beam part LDBP. Figure 3-Figure 7 An example diagram of antenna elements of an RF front end is shown. Figure 3-Figure 7 The RF front end in the example may correspond to Figure 1 Therefore, in the following Figure 3-Figure 7 In the description of the example, reference will be made to Figure 1 and Figure 2 .

[0042] Figure 3The example of FIG. 1 shows a schematic diagram 100 of an array of antenna elements 102. For example, the array of antenna elements 102 may correspond to the antenna elements 14 in the RF front end 12. Each antenna element 102 may be configured to propagate a respective wireless beam portion WBP, wherein the wireless beam portions WBP collectively correspond to the wireless beam WB. For example, the antenna elements 102 may be bidirectional to transmit or receive the wireless beam WB, thereby transmitting or receiving the respective wireless beam portions WBP on the respective antenna elements 102. Figure 3 In the example of FIG. 1 , the schematic diagram 100 shows an array of 1024 antenna elements in a square array of 32 columns and 32 rows. However, it should be understood that the array of antenna elements 102 is not limited to the number of antenna elements 102 in the schematic diagram 100, and is also not limited to a square geometry with the same number of rows and columns. As described herein, each antenna element 102 may have a relative delay associated therewith, which collectively corresponds to a transmitted or received wireless beam WBP.

[0043] Figure 4 The example of FIG. 1 shows a schematic diagram 150 of an array of antenna elements 102. As an example, the schematic diagram 150 may correspond to the lowest iteration level of the iterative process (e.g., Figure 2 In the first iteration stage 54 in the example of Figure 4 In the example of FIG. 1 , antenna elements 102 are organized into proper subsets 152, where each proper subset 152 includes four antenna elements 102. Figure 4 In an example, the RF front end includes 256 proper subsets 152 of the antenna elements 102. As an example, each proper subset 152 can correspond to a single respective digital beamforming processor, such that the associated phased array antenna system can include 256 digital beamforming processors that are collectively configured to perform iterative processing of the digital beam DB. As an example, the digital beamforming processors can be distributed in an array of antenna elements 102 arrays to significantly reduce conductive coupling of the digital beamforming processors with the respective antenna elements 102. As another example, the digital beamforming processors can be communicatively coupled to each other, such as based on each digital beamforming processor being communicatively coupled to a proximal digital beamforming processor to pass digital beam portions to each other to perform iterative processing, as described in more detail herein.

[0044] In the example of receiving wireless beam WB, Figure 4In the lowest iteration level of the example, each wireless beam portion WBP may be digitized (e.g., by an ADC 20 that may be included in the digital beamforming processor 52) to generate a lowest-level digital beam portion LDBP that is digitally equivalent to the wireless beam portion WBP. Therefore, each digital beamforming processor 52 may add the lowest-level digital beam portion LDBP from each respective antenna element 102 in a given proper subset 152 to generate a respective first-level digital beam portion DBP1. Therefore, each first-level digital beam portion DBP1 may correspond to the sum of the four lowest-level digital beam portions LDBP associated with the respective four antenna elements 102 in a given proper subset 152. In addition, the relative delay between each lowest-level digital beam part LDBP in a given proper subset 152 can be applied (for example, as described above, before adding the lowest-level digital beam part LDBP), and the first-iteration level digital beam part DBP1 associated with a given proper subset 152 can be assigned a relative delay relative to the first-iteration level digital beam part DBP1 associated with other proper subsets 152, the relative delay corresponding to the maximum value of the delay associated with one of the given antenna elements 102 in the respective proper subset 152 (for example, corresponding to the last received wireless beam part WBP in the respective proper subset 152).

[0045] Similarly, in the example of transmitting the wireless beam WB, Figure 4 In the lowest iteration level of the example, each digital beamforming processor 52 may therefore allocate four lowest-level digital beam parts LDBP from the first iteration level digital beam part DBP1 to a given proper subset 152, such that each of the four lowest-level digital beam parts LDBP corresponds to a corresponding one of the four antenna elements 102 in the respective proper subset 152. Each lowest-level digital beam part LDBP may be converted into an analog quantity (e.g., by a DAC 20, which may be included in the digital beamforming processor 52) to generate a radio beam part WBP, which is to be transmitted as a radio beam WB from each antenna element 102. In addition, for time-staggered transmission of the radio beam WBP corresponding to beam steering of the radio beam WB, each lowest-level digital beam part LDBP in a given proper subset 152 may be allocated respective time delays associated with each other.

[0046] Figure 5 The example of FIG. 200 shows a schematic diagram 200 of an array of antenna elements 102. As an example, the schematic diagram 200 may correspond to a second iteration stage (eg, Figure 2 The second iteration stage 56 in the example). Figure 5In the example of FIG. 1 , the antenna elements 102 are organized into proper subsets 202 , wherein each proper subset 202 includes Figure 4 In the example, there are four proper subsets 152. Therefore, each proper subset 202 includes 16 antenna elements 102. Figure 5 In the example of , the RF front end includes 64 proper subsets 202 of the antenna elements 102 .

[0047] In the example of receiving wireless beam WB, Figure 5 In the second iteration stage of the example, one of the digital beamforming processors 52 may be associated with each proper subset 202. Therefore, each of some of the digital beamforming processors 52 may transmit the respective first iteration stage digital beam portion DBP1 to another digital beamforming processor 52, so that the other digital beamforming processor 52 adds the first iteration stage digital beam portion DBP1 to generate the second iteration stage digital beam portion DBP2, which is the sum of the first iteration stage digital beam portions DBP1 provided to it. For example, due to Figure 5 The second iteration level in the example shows that each proper subset 202 includes Figure 4 In the example of four proper subsets 152, the three digital beamforming processors 52 associated with the respective three proper subsets 152 may provide the respective first iteration-level digital beam parts DBP1 to the fourth digital beamforming processor 52, and the fourth digital beamforming processor 52 may add the four first iteration-level digital beam parts DBP1 (e.g., the three first iteration-level digital beam parts DBP1 provided to the fourth digital beamforming processor 52, and the first iteration-level digital beam parts DBP1 generated by the respective fourth digital beamforming processor 52) to generate the second iteration-level digital beam part DBP2. Therefore, the second iteration-level digital beam part DBP2 may correspond to the sum of the lowest-level digital beam parts LDBP of each of the respective 16 antenna elements 102 in the respective proper subset 202. In addition, a relative delay between each first iteration level digital beam part DBP1 in a given proper subset 202 can be applied, and a second iteration level digital beam part DBP2 associated with a given proper subset 202 can be assigned a relative delay relative to the second iteration level digital beam part DBP2 associated with other proper subsets 202, the relative delay corresponding to a maximum value of the delay associated with a given antenna element 102 in the respective proper subset 202.

[0048] Similarly, in the example of transmitting the wireless beam WB, Figure 5In the second iteration stage of the example, each digital beamforming processor 52 in a group of digital beamforming processors 52 may allocate four first iteration stage digital beam parts DBP1 from the respective second iteration stage digital beam parts DBP2 to one of the given proper subsets 202, so that each of the four first iteration stage digital beam parts DBP1 corresponds to Figure 4 In the example, a corresponding proper subset 152. Furthermore, each first iteration stage digital beam part DBP1 in a given proper subset 202 may be assigned a respective time delay relative to each other for beam steering a wireless beam WB emitted from the antenna element 102 array.

[0049] Figure 6 The example of FIG. 250 shows a schematic diagram 250 of an array of antenna elements 102. As an example, the schematic diagram 250 may correspond to a third iteration stage of the iterative process. Figure 6 In the example of FIG. 1 , the antenna elements 102 are organized into proper subsets 252 , wherein each proper subset 252 includes Figure 5 There are four proper subsets 202 in the example. Therefore, each proper subset 252 includes 64 antenna elements 102. Therefore, in Figure 6 In the example of , the RF front end includes 16 proper subsets 252 of antenna elements 102 .

[0050] In the example of receiving wireless beam WB, Figure 6 In the example third iteration stage, one digital beamforming processor 52 may be associated with each respective proper subset 252. For example, each digital beamforming processor 52 associated with a proper subset 252 may be different from the digital beamforming processor 52 associated with the proper subset of any other iteration stage. Thus, each of some of the digital beamforming processors 52 may transmit a respective second iteration stage digital beam portion DBP2 to another digital beamforming processor 52 for the other digital beamforming processor 52 to add the second iteration stage digital beam portion DBP2 to generate a third iteration stage digital beam portion DBP3, the third iteration stage digital beam portion DBP3 being the sum of the second iteration stage digital beam portions DBP2 provided to it. For example, due to Figure 6 The third iteration level in the example shows that each proper subset 252 includes Figure 5In the example of four proper subsets 202, four digital beamforming processors 52 associated with the respective four proper subsets 202 may provide respective second iteration digital beam parts DBP2 to the fifth digital beamforming processor 52, and the fifth digital beamforming processor 52 may add the four second iteration digital beam parts DBP2 to generate the third iteration digital beam part DBP3. Therefore, the third iteration digital beam part DBP3 may correspond to the sum of the lowest level digital beam parts LDBP of each antenna element 64 in the respective 64 antenna elements 102 in the respective proper subsets 252. In addition, the relative delay between each second iteration digital beam part DBP2 in a given proper subset 252 may be applied, and the third iteration digital beam part DBP3 associated with a given proper subset 252 may be assigned a related delay relative to the third iteration digital beam part DBP3 associated with other proper subsets 252, the related delay corresponding to the maximum value of the delay associated with a given antenna element 102 in the respective proper subset 252.

[0051] Similarly, in the example of transmitting the wireless beam WB, Figure 6 In the third iteration stage of the example, each digital beamforming processor 52 in a group of digital beamforming processors 52 may allocate four second iteration stage digital beam parts DBP2 from the respective third iteration stage digital beam parts DBP3 to a given proper subset 252, so that each of the four second iteration stage digital beam parts DBP2 corresponds to Figure 5 In the example, a corresponding proper subset 202. In addition, each second iteration stage digital beam part DBP2 in a given proper subset 252 can be assigned respective time delays relative to each other for beam steering a wireless beam WB emitted from the antenna element 102 array.

[0052] Figure 7 The example of FIG. 3 shows a schematic diagram 300 of an array of antenna elements 102. As an example, the schematic diagram 300 may correspond to a fourth iteration stage of the iterative process. Figure 7 In the example of FIG. 1 , the antenna elements 102 are organized into proper subsets 302 , wherein each proper subset 302 includes Figure 6 There are four proper subsets 252 in the example. Therefore, each proper subset 302 includes 256 antenna elements 102. Therefore, in Figure 7 In the example of , the RF front end includes four proper subsets 302 of the antenna elements 102 .

[0053] In the example of receiving wireless beam WB, Figure 7In the third iteration stage of the example, one of the digital beamforming processors 52 may be associated with each corresponding proper subset 302. For example, each digital beamforming processor 52 associated with one proper subset 302 may be different from the digital beamforming processor 52 associated with the proper subset of any other iteration stage. Therefore, each of some of the digital beamforming processors 52 may transmit the corresponding third iteration stage digital beam portion DBP3 to another digital beamforming processor 52 for the other digital beamforming processor 52 to add the third iteration stage digital beam portion DBP3 to generate a fourth iteration stage digital beam portion DBP4, which is the sum of the third iteration stage digital beam portions DBP3 provided to it. For example, due to Figure 7 The fourth iteration level in the example shows that each proper subset 302 includes Figure 6 In the example of the four proper subsets 252, the four digital beamforming processors 52 associated with the respective four proper subsets 252 may provide the fifth digital beamforming processor 52 with the respective third iteration digital beam parts DBP3, and the fifth digital beamforming processor 52 may add the four third iteration digital beam parts DBP3 to generate the fourth iteration digital beam part DBP4. Therefore, the fourth iteration digital beam part DBP4 may correspond to the sum of the lowest level digital beam parts LDBP of each antenna element 102 of the respective 256 antenna elements 102 in the respective proper subset 302. In addition, the relative delay between each third iteration digital beam part DBP3 in the given proper subset 302 may be applied, and the fourth iteration digital beam part DBP4 associated with the given proper subset 302 may be assigned a related delay relative to other fourth iteration digital beam parts associated with the respective proper subset 302, the related delay corresponding to the maximum value of the delay associated with a given antenna element 102 in the respective proper subset 302.

[0054] Similarly, in the example of transmitting the wireless beam WB, Figure 7 In the fourth iteration stage of the example, each digital beamforming processor 52 in a group of digital beamforming processors 52 may allocate four third iteration stage digital beam parts DBP3 from the respective fourth iteration stage digital beam parts DBP4 to a given proper subset 302, so that each of the four third iteration stage digital beam parts DBP3 corresponds to Figure 6 In the example, a corresponding proper subset 252. In addition, each third iteration-level digital beam part DBP3 in a given proper subset 302 can be assigned respective time delays relative to each other for beam steering a wireless beam WB emitted from the antenna element 102 array.

[0055] Figure 3-Figure 7 The iterative processing of the example may also include a highest level iterative processing, where the highest level iterative processing includes all antenna elements 102 in the array. For example, in the example of receiving wireless beam WB, four digital beam portions DBP4 may be added to generate digital beam portion DBP5, which corresponds to the sum of the lowest level digital beam portions LDBP of all antenna elements 102 of the array. Therefore, digital beam portion DBP5 may correspond to digital beam DB, which may be provided to the digital beamforming system 16 to process and demodulate the digital beam DB to determine the data therein. In the example of transmitting wireless beam WB, four digital beam portions DBP4 may be allocated from digital beam portion DBP5 and further iteratively allocated, as shown. Figure 3-Figure 7 As shown in the example, when the digital beam DB is generated, the wireless beam WB is generated based on the beamforming characteristics defined by the digital beamforming system 16 in reverse order.

[0056] The operation of the digital beamforming processor 52 provides a more efficient way to process the digital beam DB for transmitting or receiving wireless beams WB by shifting the processing burden of processing the digital beam DB to the digital beamforming processor 52, rather than providing all the processing of the digital beam DB at the digital beamforming system 16. Therefore, the processing of the digital beam DB by the digital beamforming processor 52 can significantly alleviate the potential processing bottleneck provided by the digital beamforming system 16. In addition, by implementing the distribution of the digital beamforming processor 52 on the RF front end 12 relative to the antenna element 102, as provided in a typical phased array antenna system, the phased array antenna system 10 can have a significantly more efficient design by reducing the interconnection between the digital beamforming system 16 and each individual antenna element 102.

[0057] In addition, the digital beamforming system 16 can communicate with one or more digital beamforming processors 52, such as in association with an iterative process that processes certain higher iteration levels. Thus, the digital beamforming system 16 can effectively monitor the iterative process to determine the adequacy of a given digital beam DB (e.g., in response to receiving a wireless beam WB). For example, the digital beamforming system 16 can monitor higher iteration levels (e.g., at one or more respective digital beamforming processors 52) to determine whether a given received wireless beam WB satisfies certain predetermined criteria. If it is not determined that the digital beam DB satisfies the predetermined criteria at a given iteration level, and therefore the digital beam DB is not a signal of interest to the phased array antenna system 10, the digital beamforming system 16 can stop processing the digital beam DB to save bandwidth and / or processing overhead of the digital beamforming processor 52.

[0058] As another example, at higher iteration levels, the digital beamforming processor 52 can achieve a higher resolution (e.g., lower precision) delay at a lower digital sampling rate. Therefore, each physical delay element can achieve a larger delay with fewer memory elements. At lower iteration levels, the sampling rate can be increased, or perhaps only the lowest iteration level will have a higher sampling rate to achieve fine resolution of the delay. As yet another example, instead of increasing the sampling rate at the lowest iteration level, the lowest iteration can use a phase shift (e.g., as an approximation of a narrowband delay). Therefore, the beamforming system can implement a hybrid phase shift (e.g., at the lowest iteration level) and delay (e.g., at a higher iteration level) to effectively achieve beam steering. Therefore, for the reasons described herein, the phased array antenna system 10 can provide a more efficient and more effective design for beamforming of wireless beams WB.

[0059] Figure 8 An example diagram 350 of an iterative beamforming process is shown. Diagram 350 illustrates a first proper subset of antenna elements 352 and a first digital beamforming processor 354, and a second proper subset of antenna elements 356 and a second digital beamforming processor 358. Antenna elements 352 and 356 may correspond to Figure 1 and Figure 3-Figure 7 The antenna elements 14 and 102 in the respective examples, and the digital beamforming processors 354 and 358 may correspond to Figure 2 The digital beamforming processor 52 in the example. Figure 8 In the description of the example, reference will be made to Figure 1-Figure 7 .

[0060] exist Figure 8In the example of , the digital beamforming processors 354 and 358 may correspond to two digital beamforming processors of a plurality (X) of digital beamforming processors that are distributed as an array on an antenna element array (e.g., antenna element 102), where X is a positive integer greater than 1. The digital beamforming processor 354 is therefore labeled “DBF-P1” and the digital beamforming processor 358 is labeled “DBF-PX.” Similar to the above, each of the digital beamforming processors 354 and 358 is communicatively coupled to a respective proper subset of the antenna elements 352 and 356. Therefore, each of the digital beamforming processors 354 and 358 is associated with each of the plurality (Y) of antenna elements 352 and 356, respectively, where Y is a positive integer greater than 1. Thus, antenna elements 352 are labeled "AE1_1" through "AE1_Y" and antenna elements 352 are labeled "AEX_1" through "AEX_Y" to designate the association with respective digital beamforming processors 354 and 358 and the number of each of the corresponding proper subsets. Figure 3-Figure 7 In the example of , X is equal to 256 and Y is equal to 4. For example, a proper subset of antenna elements 352 can be closest to digital beamforming processor 354 and a proper subset of antenna elements 356 can be closest to digital beamforming processor 358 to provide shorter conductive interconnects between the antenna elements and the digital beamforming processor across the RF front end 12.

[0061] exist Figure 8In the example of FIG. 1 , each of the antenna elements 352 and 356 is configured to propagate a wireless beam portion WBP, which is labeled “WBP1_1” to “WBP1_Y” and “WBPX_1” to “WBPX_Y” to correspond to the respective antenna elements 352 and 356, which collectively correspond to the wireless beam WB. For example, for a received wireless beam WB, each antenna element 14 may provide the respective wireless beam portions WBP1_1 to WBP1_Y and WBPX_1 to WBPX_Y associated with the respective wireless beam WB to the digital beamforming processors 354 and 358, respectively. Each of the wireless beam portions WBP1_1 to WBP1_Y and WBPX_1 to WBPX_Y may be digitized, for example, by the digital beamforming processors 354 and 358 (e.g., by the ADC 20 as part of the functionality of the digital beamforming processors 354 and 358) to generate a respective lowest level digital beam portion LDBP, which is the digital equivalent of the wireless beam portions WBP1_1 to WBP1_Y and WBPX_1 to WBPX_Y. Alternatively, the digitization may be performed by separate components of the digital beamforming processors 354 and 358. Thus, the digital beamforming processor 354 may add the respective lowest level digital beam portions in the first iteration stage 54 to generate the respective first iteration level digital beam portion DBP1_1, and thus the digital beamforming processor 358 may add the respective lowest level digital beam portions in the first iteration stage 54 to generate the respective first iteration level digital beam portion DBP1_X. The first iteration level digital beam portion DBP1_1 may correspond to the sum of the lowest level digital beam portions LDBP associated with the wireless beam portions WBP1_1 to WBP1_Y, and the first iteration level digital beam portion DBP1_X may correspond to the sum of the lowest level digital beam portions LDBP associated with the wireless beam portions WBPX_1 to WBPX_Y. In addition, as described above, the relative delays of the wireless beam portions WBP1_1 to WBP1_Y and WBPX_1 to WBPX_Y may be applied to the received / transmitted wireless beam portions WBP1_1 to WBP1_Y and WBPX_1 to WBPX_Y.

[0062] exist Figure 8In the example of , the digital beamforming processors 354 and 358 can be communicatively coupled to each other. For example, the digital beamforming processors 354 and 358 can be closest to (e.g., adjacent to) each other in the digital beamforming processor array associated with the antenna element array, so that the proper subset of antenna elements 352 can be adjacent to the proper subset of antenna elements 356. For example, each digital beamforming processor 52 in the digital beamforming processor array can be closest to (e.g., adjacent to) at least two other digital beamforming processors 52 corresponding to adjacent antenna array proper subsets, and can be conductively coupled to one or more (e.g., up to four) closest (e.g., adjacent) digital beamforming processors 52 (e.g., corresponding to a 2×2 array of digital beamforming processors 52). Therefore, each of the proximal digital beamforming processors 52 can be communicatively coupled to each other to significantly reduce the interconnect length so as to more efficiently transfer beamforming information between the digital beamforming processors 52.

[0063] As a result of the closest digital beamforming processors 52 being conductively coupled to each other, the digital beamforming processors 52 are configured to provide the digital beam portions to the closest digital beamforming processors 52 so that the closest digital beamforming processors 52 perform the next iteration level of the iterative processing. In addition, some digital beamforming processors 52 can be communicatively coupled to another digital beamforming processor 52 to pass the processed digital beam portions (e.g., allocated or added) to another digital beamforming processor 52 to perform the next iteration level of processing. Figure 8 In the example of FIG. 1 , the digital beamforming processor 354 is shown as passing the signal “DBP1_1” corresponding to the first iteration digital beam part DBP1_1 to the digital beamforming processor 358. Therefore, the digital beamforming processor 358 can communicate with the digital beamforming processors (in FIG. Figure 8The digital beamforming processor 358 processes the second iteration level digital beam portion DBP2 together with the first iteration level digital beam portion DBP1_X (not shown in the example) and other first iteration level digital beam portions DBP1. For example, the digital beamforming processor 358 can generate the second iteration level digital beam portion DBP2 based on the first iteration level digital beam portions DBP1_1, DBP1_X and DBP1, and can provide the second iteration level digital beam portion DBP2 to another digital beamforming processor for generating a third iteration level digital beam portion for the received wireless beam WB (for example, together with other second iteration level digital beam portions). As another example, the digital beamforming processor 358 can receive the second iteration level digital beam portion DBP2 from another digital beamforming processor, so that the digital beamforming processor 358 can allocate the first iteration level digital beam portions DBP1_1, DBP1_X and DBP1 from the second iteration level digital beam portion DBP2 for transmitting the wireless beam WB.

[0064] Fig. 9 An example schematic diagram 400 of an iterative beamforming process is shown. Schematic diagram 400 demonstrates 16 digital beamforming processors arranged in an approximate array. Schematic diagram 400 includes a first set of digital beamforming processors at 402, the first set of digital beamforming processors 402 including digital beamforming processor 404, digital beamforming processor 406, digital beamforming processor 408, and digital beamforming processor 410. Schematic diagram 400 also includes a second set of digital beamforming processors at 412, the second set of digital beamforming processors 412 including digital beamforming processor 414, digital beamforming processor 416, digital beamforming processor 418, and digital beamforming processor 420. Schematic diagram 400 also includes a third set of digital beamforming processors at 422, the third set of digital beamforming processors 422 including digital beamforming processor 424, digital beamforming processor 426, digital beamforming processor 428, and digital beamforming processor 430. Schematic diagram 400 also includes a fourth set of digital beamforming processors at 432, including digital beamforming processor 434, digital beamforming processor 436, digital beamforming processor 438, and digital beamforming processor 440. The digital beamforming processors in schematic diagram 400 may correspond to Figure 2 The digital beamforming processor 52 in the example. Fig. 9 In the description of the example, reference will be made to Figure 1-Figure 8 In addition, an example of beamforming of the received wireless beam is provided. Fig. 9Iterative processing is demonstrated in the examples. However, it should be understood that for the example of beamforming of the transmitted wireless beams, the direction of the data flow can be reversed.

[0065] The digital beamforming processors in the schematic 400 are labeled with the name "DBF-PN_M", where "N" corresponds to the set of digital beamforming processors to which the digital beamforming processors 402, 412, 422, and 432 belong, and "M" corresponds to the respective name of the respective set of digital beamforming processors. Each of the digital beamforming processors in the schematic 400 can be associated with a respective proper subset of the antenna elements. For example, each of the digital beamforming processors in the schematic 400 can be communicatively coupled to four independent antenna elements 102 of the antenna element array, such that each digital beamforming processor can be associated with Figure 4 4. Similarly to the above, the digital beamforming processors in the schematic diagram 400 can be arranged in an array, wherein each of the sets of digital beamforming processors 402, 412, 422, and 432 is associated with a respective adjacent proper subset 152 of the antenna elements 102. Thus, each digital beamforming processor is configured to implement a first iteration stage of the iterative processing, corresponding to processing the lowest level digital beam part LDBP, which corresponds to the wireless beam part WBP of each corresponding antenna element in the given proper subset 152. Thus, in Fig. 9 In the example of , each digital beamforming processor processes a corresponding first iteration level digital beam portion labeled "DBP1_N_M", where "1" corresponds to the first iteration level.

[0066] exist Fig. 9In the example of , the digital beamforming processor 404 generates a first iteration-level digital beam portion DBP1_1_1, the digital beamforming processor 406 generates a first iteration-level digital beam portion DBP1_1_2, the digital beamforming processor 408 generates a first iteration-level digital beam portion DBP1_1_3, and the digital beamforming processor 410 generates a first iteration-level digital beam portion DBP1_1_4. Similarly, the digital beamforming processor 414 generates a first iteration-level digital beam portion DBP1_2_1, the digital beamforming processor 416 generates a first iteration-level digital beam portion DBP1_2_2, the digital beamforming processor 418 generates a first iteration-level digital beam portion DBP1_2_3, and the digital beamforming processor 420 generates a first iteration-level digital beam portion DBP1_2_4. Similarly, the digital beamforming processor 424 generates a first iteration digital beam portion DBP1_3_1, the digital beamforming processor 426 generates a first iteration digital beam portion DBP1_3_2, the digital beamforming processor 428 generates a first iteration digital beam portion DBP1_3_3, and the digital beamforming processor 430 generates a first iteration digital beam portion DBP1_3_4. Similarly, the digital beamforming processor 434 generates a first iteration digital beam portion DBP1_4_1, the digital beamforming processor 436 generates a first iteration digital beam portion DBP1_4_2, the digital beamforming processor 438 generates a first iteration digital beam portion DBP1_4_3, and the digital beamforming processor 440 generates a first iteration digital beam portion DBP1_4_4. Each of the corresponding first iteration level digital beam parts DBP1 may correspond to the sum of the lowest level digital beam parts LDBP associated with each antenna element of each proper subset (e.g., number 4) of antenna elements. In addition, similar to the above, a relative delay between each lowest level digital beam part LDBP may be applied, and each first iteration level digital beam part DBP1 may be assigned a relative delay relative to other first iteration level digital beam parts DBP1.

[0067] In a second iteration level corresponding to the next iteration level of the iterative process, some of the first iteration level digital beam parts are added together to generate a second iteration level digital beam part. Fig. 9In the example of , digital beamforming processors 406, 408, and 410 are communicatively coupled to digital beamforming processor 404. Therefore, first iteration-level digital beam portions DBP1_1_2, DBP1_1_3, and DBP1_1_4 are provided to digital beamforming processor 404 from digital beamforming processors 406, 408, and 410, respectively. Therefore, digital beamforming processor 404 is configured to generate second iteration-level digital beam portion DBP2_1, which corresponds to the sum of first iteration-level digital beam portions DBP1_1_1, DBP1_1_2, DBP1_1_3, and DBP1_1_4. Similarly, digital beamforming processors 416, 418, and 420 are communicatively coupled to digital beamforming processor 414. Therefore, the first iteration level digital beam portions DBP1_2_2, DBP1_2_3 and DBP1_2_4 are provided from the digital beamforming processors 416, 418 and 420 to the digital beamforming processor 414, respectively. Therefore, the digital beamforming processor 414 is configured to generate the second iteration level digital beam portion DBP2_2, which corresponds to the sum of the first iteration level digital beam portions DBP1_2_1, DBP1_2_2, DBP1_2_3 and DBP1_2_4. Similarly, the digital beamforming processors 426, 428 and 430 are communicatively coupled to the digital beamforming processor 424. Thus, the first iteration level digital beam portions DBP1_3_2, DBP1_3_3 and DBP1_3_4 are provided from the digital beamforming processors 426, 428 and 430 to the digital beamforming processor 424, respectively. Therefore, the digital beamforming processor 424 is configured to generate a second iteration level digital beam portion DBP2_3, which corresponds to the sum of the first iteration level digital beam portions DBP1_3_1, DBP1_3_2, DBP1_3_3 and DBP1_3_4. Similarly, the digital beamforming processors 436, 438 and 440 are communicatively coupled to the digital beamforming processor 434. Therefore, the first iteration level digital beam portions DBP1_4_2, DBP1_4_3 and DBP1_4_4 are provided to the digital beamforming processor 434 from the digital beamforming processors 436, 438 and 440, respectively. Therefore, the digital beamforming processor 434 is configured to generate a second iteration level digital beam portion DBP2_4 corresponding to the sum of the first iteration level digital beam portions DBP1_4_1, DBP1_4_2, DBP1_4_3 and DBP1_4_4.Furthermore, similar to the above description, a relative delay between each first iteration level digital beam portion DBP1 may be applied, and each second iteration level digital beam portion DBP2 may be assigned a relative delay relative to other second iteration level digital beam portions DBP2.

[0068] In a third iteration level corresponding to the next iteration level of the iterative process, some of the second iteration level digital beam parts are added together to generate a third iteration level digital beam part. Fig. 9 In the example of , the digital beamforming processors 404, 414, 424 and 434 are communicatively coupled to the digital beamforming processor 406. Therefore, the second iteration level digital beam portions DBP2_1, DBP2_2, DBP2_3 and DBP2_4 are provided to the digital beamforming processor 406 by the digital beamforming processors 404, 414, 424 and 434, respectively. Therefore, the digital beamforming processor 406 is configured to generate a third iteration level digital beam portion DBP3_1, which corresponds to the sum of the second iteration level digital beam portions DBP2_1, DBP2_2, DBP2_3 and DBP2_4. In addition, similar to the above, the relative delay between each second iteration level digital beam portion DBP2 can be applied, and each third iteration level digital beam portion DBP3 can be assigned a relative delay relative to other third iteration level digital beam portions DBP3.

[0069] In a fourth iteration level corresponding to the next iteration level of the iterative process, some of the digital beam parts of the third iteration level are added together to generate a digital beam part of the fourth iteration level. Fig. 9 In the example of FIG. 4 , the digital beamforming processor 406 is communicatively coupled to the digital beamforming processor 408, Fig. 9 The same is true for other (e.g., other three) digital beamforming processors not demonstrated in the example. Therefore, the third iteration level digital beam portion DBP3_1 is provided from the digital beamforming processor 406 to the digital beamforming processor 408, and other third iteration level digital beam portions DBP3 are provided from the other digital beamforming processors to the digital beamforming processor 408. Therefore, the digital beamforming processor 408 is configured to generate a fourth iteration level digital beam portion DBP4_1, which corresponds to the sum of the third iteration level digital beam portion DBP3_1 and the other third iteration level digital beam portions DBP3. As an example, in Figure 3-Figure 7In the example of FIG. 1 , based on the arrangement of the RF front end, the fourth iteration level digital beam part DBP4_1 can be one of the four fourth iteration level digital beam parts. In addition, similar to the above, the relative delay between each third iteration level digital beam part DBP3 can be applied, and each fourth iteration level digital beam part DBP4 can be assigned a relative delay relative to other fourth iteration level digital beam parts DBP4.

[0070] In a fifth iteration level corresponding to the next iteration level of the iterative process, some of the fourth iteration level digital beam parts are added together to generate a fifth iteration level digital beam part. Fig. 9 In the example of FIG. 4 , the digital beamforming processor 408 is communicatively coupled to the digital beamforming processor 410, Fig. 9 The same is true for other (e.g., other three) digital beamforming processors not demonstrated in the example. Therefore, the fourth iteration-level digital beam portion DBP4_1 is provided from the digital beamforming processor 408 to the digital beamforming processor 410, and other fourth iteration-level digital beam portions DBP4 are provided from other digital beamforming processors to the digital beamforming processor 410. Therefore, the digital beamforming processor 410 is configured to generate a fifth iteration-level digital beam portion DBP5, which corresponds to the sum of the fourth iteration-level digital beam portion DBP4_1 and other fourth iteration-level digital beam portions DBP4. For example, Figure 3-Figure 7 In the example, based on the arrangement of the RF front end, the fifth iteration-level digital beam part DBP5 may be the highest iteration-level digital beam part, and thus may be represented as Figure 3-Figure 7 The sum of all lowest-level digital beam parts LDBP of all corresponding antenna elements 102 in the example. In addition, similar to the above, the relative delay between each fourth iteration-level digital beam part DBP4 can be applied to generate the fifth iteration-level digital beam part DBP5.

[0071] therefore, Fig. 9 The example demonstrates the interaction between the digital beamforming processors to perform the iterative process of digital beamforming. Fig. 9In the example of , no digital beamforming processor is configured to process more than two iteration levels, thereby distributing the processing of beamforming between the digital beamforming processors. Therefore, by shifting the processing burden of the digital beam DB to the digital beamforming processor, rather than providing all processing of the digital beam DB at the digital beamforming system 16, the operation of the digital beamforming processor provides a more efficient way to process the digital beam DB to transmit or receive the wireless beam WB. Therefore, the processing of the digital beam DB by the digital beamforming processor can significantly alleviate the potential processing bottleneck provided by the digital beamforming system 16. In addition, by implementing the distribution of the digital beamforming processor on the RF front end 12 relative to the antenna element 102, as provided by a typical phased array antenna system, the phased array antenna system 10 can have a significantly more efficient design by reducing the interconnection between the digital beamforming system 16 and each individual antenna element 102. Therefore, for the reasons described herein, the phased array antenna system 10 can provide a more efficient and more effective design for beamforming of the wireless beam WB.

[0072] In view of the above structural and functional characteristics, reference Fig.10 and Fig.11 The example methods may be better understood. Although the methods are shown and described as executing serially for ease of explanation, it should be understood and appreciated that the methods are not limited to the order shown, as portions of the methods may occur in a different order and / or simultaneously than those shown and described herein. Methods such as these may be executed by various components configured in, for example, an integrated circuit, a processor, or a controller.

[0073] Fig.10An example of a method 450 for receiving a wireless beam (e.g., wireless beam WB) by a phased array antenna system (e.g., phased array antenna system 10) is shown. At 452, a portion of the wireless beam is received at each of a plurality of antenna elements (e.g., antenna element 14) disposed in an array and associated with a radio frequency front end (e.g., RF front end 12). At 454, the wireless beam portion (e.g., wireless beam portion WBP) associated with each antenna element is converted into a respective lowest level digital beam portion (e.g., lowest level digital beam portion LDBP) by respective plurality of ADCs (e.g., DAC / ADC 20). At 456, the lowest level digital beam portions associated with a plurality of proper subsets of antenna elements (e.g., proper subset 152) are added by each of a plurality of digital beamforming processors (e.g., digital beamforming processor 22) to generate a plurality of digital beam portions (e.g., digital beam portions DBP) at the lowest iteration level of the wireless beam iteration process. At 458, the digital beam portions are iteratively added by the digital beamforming processor in a plurality of iteration stages including a lowest iteration stage and a highest iteration stage. Each digital beam portion associated with a given iteration stage comprises the sum of smaller and relatively delayed digital beam portions from the next lower iteration stage of the iterative process. At 460, the digital beam portions associated with the highest iteration stage are added to generate a digital beam corresponding to a wireless beam (e.g., digital beam DB).

[0074] Fig.11An example of a method 500 for transmitting a wireless beam (e.g., wireless beam WB) by a phased array antenna system (e.g., phased array antenna system 10) is shown. At 502, a digital beam (e.g., digital beam DB) corresponding to a wireless beam to be transmitted from the phased array antenna system is generated. At 504, a digital beam portion (e.g., digital beam portion DBP) is allocated from a digital beam at a highest iteration level among multiple iteration levels of a digital beam iterative process by a plurality of digital beamforming processors (e.g., digital beamforming processor 22). At 506, the digital beam portion is iteratively allocated by the digital beamforming processors in a plurality of iteration levels including a highest iteration level and a lowest iteration level. Each digital beam portion associated with a given iteration level is allocated from the given iteration level to a next lower iteration level of the iterative process as a plurality of smaller digital beam portions having relatively different delays, the smaller digital beam portions being equal to the respective digital beam portions in general. At 508, the plurality of digital beam portions are allocated to generate a plurality of lowest-level digital beam portions (e.g., lowest-level digital beam portions LDBP) associated with each of the plurality of antenna elements (e.g., antenna element 14) by each of the plurality of digital beamforming processors, which are the lowest iteration level of the digital beam iteration process. At 510, the lowest-level digital beam portions are converted into wireless beam portions (e.g., wireless beam portions WB) associated with each of the respective antenna elements by respective plurality of DACs (e.g., DAC / ADC 20). At 512, the wireless beam portions are transmitted as wireless beams from each of the respective plurality of antenna elements.

[0075] What has been described above are some examples. Of course, it is impossible to describe every conceivable combination of components or methods, but those of ordinary skill in the art will recognize that many further combinations and arrangements are possible. Therefore, the present disclosure is intended to include all such changes, modifications and variations within the scope of the present application, including the appended claims. As used herein, the term "includes" means including but not limited to, and the term "including" means including but not limited to. The term "based on" means at least partially based on. In addition, when the present disclosure or claims list "a", "an", "afirst" or "another" element, or its equivalent, it should be interpreted as including one or more such elements, neither requiring nor excluding two or more such elements.

Claims

1. A phased array antenna system, comprising: A radio frequency (RF) front end configured to transmit or receive a wireless beam, the RF front end comprising a plurality of antenna elements arranged in an array, each of the plurality of antenna elements being configured to propagate a respective one of the wireless beam portions with a respective time delay and amplitude; a digital beamforming system configured to generate a digital beam corresponding to the wireless beam; as well as A digital signal conditioner system between the RF front end and the digital beamforming system, the digital signal conditioner system comprising a plurality of digital beamforming processors, each of the plurality of digital beamforming processors being associated with a proper subset of the plurality of antenna elements, the plurality of digital beamforming processors being collectively configured to perform iterative processing on digital beam portions of the digital beam in a plurality of iteration stages, the plurality of iteration stages comprising a lowest iteration stage associated with a lowest level digital beam portion corresponding to each wireless beam portion at each antenna element and a highest iteration stage associated with the digital beam, wherein each digital beam portion associated with a given iteration stage comprises a sum of relatively delayed digital beam portions from a next lower iteration stage.

2. The system according to claim 1, wherein: Each digital beam portion is associated with a plurality of lowest level digital beam portions corresponding to a subset of the plurality of antenna elements, such that the digital beam portions associated with the given iteration level are associated with a corresponding subset of the plurality of antenna elements, the subset of the plurality of antenna elements being larger than a subset of the plurality of antenna elements associated with a next lower iteration level of the iterative process.

3. The system according to claim 1, wherein: Each digital beam portion in each given iteration level is associated with the sum of the radio beam portions of consecutive antenna element groups, wherein the number of consecutive antenna element groups increases from the lowest iteration level to the highest iteration level.

4. The system according to claim 3, wherein: The first digital beamforming processor is configured to process a sum of lowest level digital beam portions associated with a respective consecutive group of antenna elements in a given iteration level of the iterative processing, wherein the second digital beamforming processor is configured to process a sum of lowest level digital beam portions associated with a respective consecutive group of antenna elements and at least one adjacent and equally sized consecutive group of antenna elements in a next higher iteration level of the iterative processing.

5. The system according to claim 1, wherein: Each proper subset of the digital beamforming processors is configured to process digital beam portions associated with the lowest iteration stage and to process digital beam portions associated with higher iteration stages of the plurality of iteration stages.

6. The system according to claim 1, wherein: Each digital beamforming processor is configured to process, at a lowest iteration level of the iterative processing, a sum of lowest level digital beam portions associated with a respective proper subset of the plurality of antenna elements.

7. The system according to claim 1, wherein: The set of multiple digital beamforming processors is associated with corresponding adjacent proper subsets of the antenna elements such that a corresponding one of the set of digital beamforming processors is communicatively coupled to each remaining digital beamforming processor in the set of digital beamforming processors to process a lowest level digital beam portion of each digital beamforming processor in the set of digital beamforming processors into a first iteration level digital beam portion.

8. The system according to claim 7, wherein: A second digital beamforming processor in the set of digital beamforming processors is communicatively coupled to another digital beamforming processor outside the set of digital beamforming processors, so that the other digital beamforming processor is configured to process a second iteration level digital beam portion in a second iteration level based on the first iteration level digital beam portion and at least one other first iteration level digital beam portion associated with another set of multiple digital beamforming processors.

9. The system according to claim 1, wherein: The digital signal conditioner system includes a plurality of frequency channels, each of the frequency channels being associated with a separate frequency, wherein each frequency channel is coupled to each of the plurality of digital beamforming processors.

10. The system according to claim 1, wherein: The RF front end is configured to transmit and receive the wireless beam, wherein the digital beamforming processor is collectively configured to: in response to receiving the wireless beam, iteratively adding the digital beam portion of the digital beam to the plurality of iteration stages from the lowest iteration stage to the highest iteration stage, and The digital beam parts of the digital beam are iteratively allocated in the plurality of iteration levels from the highest iteration level to the lowest iteration level to transmit the wireless beam.

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