Signal sampling method, device and equipment of digital PET and storage medium

Abstract

The application discloses a signal sampling method, device and equipment of digital PET, and a storage medium. The signal sampling method of the application comprises the following steps: performing delay processing on pulse signals input to multiple channels, and obtaining multiple delay pulse signals; switching the multiple channels based on the multiple delay pulse signals, and obtaining comparison signals; and performing time-to-digital conversion processing on the comparison signals to extract time information. According to the scheme of the embodiment of the application, the multiplexing of time-to-digital converters among multiple channels can be realized in the FPGA, information loss is not caused, the resource usage of the FPGA is reduced, and the time measurement precision and system integration are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of positron emission computed tomography (PET), in particular to a signal sampling method, device and equipment of digital PET and a storage medium. BACKGROUND

[0002] Positron emission tomography (PET) is a high-end nuclear medical imaging equipment, which is widely used in cancer diagnosis and treatment, brain science research, cardiology research, heavy ion radiotherapy monitoring and other fields, and a large number of gamma ray detectors are used for signal sampling. The multi-voltage threshold sampling (Multi-Voltage Threshold, hereinafter referred to as MVT) method proposed by Xie Qingguo team completes the digitization of scintillation pulse by sampling the time point of scintillation pulse over threshold voltage. The MVT method can directly digitize the scintillation pulse signal when the detector samples, so as to make the detector modular and bring PET into the digital PET era.

[0003] The key of MVT method is to obtain the time information of input waveform over the set threshold through TDC (time-to-digital conversion) technology, so as to inverse the waveform information. Usually, threshold comparison of multiple channels and subsequent time measurement are needed, which needs to consume certain logic resources inside FPGA to realize. The processing circuit of waveform output by a single SIPM detector is usually as shown in Figure 1 The waveform of a single channel corresponds to 4 channel comparators (LVDS Comparator), which needs to consume 8 input pins of FPGA chip and 8 channel TDC measurement modules. A FPGA usually needs to process the signals of dozens to hundreds of channels. The FPGA chip used in PET can provide 115K logic resources and about 500 available LVDS pin numbers. Neither the pin nor the logic resource can process the data of numerous channels. The logic resource is limited, and the measurement accuracy of TDC module is also restricted.

[0004] In summary, the high FPGA resource consumption and the number of input pins have become a bottleneck of system design. It is urgent to provide a signal sampling method, device and equipment of digital PET and a storage medium to solve at least one of the above technical problems.

[0005] The content described in the background technology is only for the convenience of understanding the related technology in the art, and is not regarded as the recognition of the prior art. SUMMARY

[0006] Therefore, the present application provides a signal sampling method, device and equipment of digital PET and a storage medium, which can solve at least one problem existing in the prior art.

[0007] In a first aspect, the application provides a signal sampling method for digital PET, comprising: delaying pulse signals input to multiple channels to obtain multiple delayed pulse signals; switching the multiple channels based on the multiple delayed pulse signals to obtain comparison signals; and performing time-to-digital conversion on the comparison signals to extract time information.

[0008] According to an embodiment of the application, before the step of delaying pulse signals input to multiple channels to obtain multiple delayed pulse signals, the method further comprises the step of: simultaneously inputting the pulse signals of a single channel collected to corresponding multiple channels to form multiple pulse signals.

[0009] According to an embodiment of the application, the step of delaying pulse signals input to multiple channels to obtain multiple delayed pulse signals comprises: through the way of delay lines, staggering the rising edges of the pulse signals input to the multiple channels simultaneously to obtain multiple delayed pulse signals.

[0010] According to an embodiment of the application, the time interval between the rising edges of the multiple delayed pulse signals and / or the time interval between the staggered falling edges is greater than the minimum time interval of the time-to-digital conversion.

[0011] According to an embodiment of the application, the minimum time interval of the time-to-digital conversion is 10 ns.

[0012] According to an embodiment of the application, the step of switching the multiple channels based on the multiple delayed pulse signals to obtain comparison signals comprises: sequentially performing waveform acquisition processing on the multiple delayed pulse signals, switching channels based on a preset order and comparing with a preset threshold to obtain corresponding comparison signals.

[0013] According to an embodiment of the application, the step of sequentially performing waveform acquisition processing on the multiple delayed pulse signals to obtain comparison signals comprises: obtaining feedback output signals based on the multiple delayed pulse signals.

[0014] According to an embodiment of the application, the step of sequentially performing waveform acquisition processing on the multiple delayed pulse signals to obtain comparison signals further comprises: sequentially performing rising edge waveform acquisition processing and falling edge waveform acquisition processing on the multiple delayed pulse signals to obtain feedback output signals.

[0015] According to an embodiment of the application, the step of sequentially performing rising edge waveform acquisition processing and falling edge waveform acquisition processing on the multiple delayed pulse signals comprises: sequentially performing rising edge waveform acquisition processing according to the order of arrival of the rising edges of the multiple delayed pulse signals, and sequentially performing falling edge waveform acquisition processing according to the order of arrival of the falling edges of the multiple delayed pulse signals.

[0016] According to one embodiment of the present application, the time-to-digital conversion process is implemented by a single-channel time-to-digital converter.

[0017] In a second aspect, the present application provides a signal sampling device for digital PET, comprising: a delay module configured to delay the pulse signals input to multiple channels, and obtain multiple delayed pulse signals; a routing switching module configured to switch the multiple channels based on the multiple delayed pulse signals, and obtain comparison signals; and perform time-to-digital conversion processing on the comparison signals to extract time information.

[0018] According to one embodiment of the present application, the multiple channels are provided with comparators, and the input end of the delay module is connected to the input end of the pulse signals.

[0019] According to one embodiment of the present application, the multiple channels are provided with comparators, and the output end of the delay module is connected to the input end of the comparators.

[0020] According to one embodiment of the present application, the delay module comprises a delay line structure.

[0021] According to one embodiment of the present application, the delay module comprises a plurality of delay line structure units, and the delay line structure units are located outside the module where the comparators are located.

[0022] According to one embodiment of the present application, the routing switching module comprises a channel selection module and a time-to-digital conversion module, wherein the channel selection module is configured to receive the delayed pulse signals of the channels selected by the channel selection module, and convert the delayed pulse signals into comparison signals and transmit the comparison signals to the time-to-digital conversion module; and the time-to-digital conversion module is configured to perform rising edge waveform acquisition processing and falling edge waveform acquisition processing on the comparison signals of the channels switched to, and perform time-to-digital conversion to obtain the time corresponding to the rising edge and the falling edge, respectively.

[0023] According to one embodiment of the present application, the routing switching module comprises a channel selection module, a time-to-digital conversion module, and a channel control module, wherein the channel selection module is configured to receive the delayed pulse signals of the channels selected by the channel selection module, and convert the delayed pulse signals into comparison signals and transmit the comparison signals to the time-to-digital conversion module; the time-to-digital conversion module is configured to perform rising edge waveform acquisition processing and falling edge waveform acquisition processing on the comparison signals of the channels switched to, output a feedback output signal to the channel control module, and receive a synchronous switching pulse signal output by the channel control module, and perform time-to-digital conversion processing on the synchronous switching pulse signal to measure the time of the rising edge and the falling edge, respectively; and the channel control module is configured to control the switching to the corresponding channels based on the feedback output signal received by the channel control module, and output a synchronous switching pulse signal to the time-to-digital conversion module for time measurement.

[0024] According to an embodiment of the present application, the route switching module comprises a channel selection module, a time-to-digital conversion module and a channel control module, wherein the channel selection module is configured to receive the delay pulse signal of the channel selected by the channel selection module and convert the delay pulse signal into a comparison signal and transmit the comparison signal to the time-to-digital conversion module and transmit the comparison signal as a feedback output signal to the channel control module; the time-to-digital conversion module is configured to perform rising edge waveform acquisition processing and falling edge waveform acquisition processing on the comparison signal of the channel switched to, respectively, and perform time-to-digital conversion to measure the time of the rising edge and the falling edge, respectively; the channel control module is configured to control switching to the corresponding channel based on the feedback output signal received by the channel control module and output a synchronous switching pulse signal to the time-to-digital conversion module for time measurement.

[0025] According to an embodiment of the present application, the time interval between the rising edges and / or the time interval between the falling edges is greater than the minimum time interval processed by the time-to-digital conversion module.

[0026] According to an embodiment of the present application, the minimum time interval processed by the time-to-digital conversion module is 10 ns.

[0027] According to an embodiment of the present application, the time-to-digital conversion module comprises a time-to-digital converter, and the time-to-digital converter comprises: a carry chain configured to perform time acquisition of the rising edge and the falling edge of the pulse signal and output a sampling clock data signal; a D flip-flop configured to receive the sampling clock data signal and output a feedback output signal to the channel control module based on the sampling clock data signal; and a processing unit configured to receive the synchronous switching pulse signal output by the channel control module and extract time information.

[0028] In a third aspect, the present application provides a detector device, the detector device comprising: a detector and the signal sampling device of the digital PET according to any one of the preceding items, wherein the detector is configured to detect a ray and output a pulse signal to the signal sampling device for digital processing.

[0029] In a fourth aspect, the present application provides a computer device, the computer device comprising: a memory configured to store a computing program; and a processor configured to execute the computing program to perform the signal sampling method of the digital PET according to any one of the preceding items.

[0030] In a fifth aspect, the present application provides a computer readable storage medium, the computer readable storage medium being configured to store a computing program, the computing program being executed to perform the signal sampling method of the digital PET according to any one of the preceding items.

[0031] As can be seen from the technical solutions provided by the embodiments of the present application, the present application has the following beneficial effects:

[0032] The multi-channel delay pulse signals are obtained by delaying the pulse signals input to the multiple channels, the rising edges and the falling edges of the multi-channel delay pulse signals are staggered, which facilitates subsequent complete extraction of time information; based on the multi-channel delay pulse signals, the multiple channels can be switched, so that the same time-to-digital converter can be used to realize the collection of the time information of the multi-channel pulse signals input to the FPGA chip, the multiplexing of the time-to-digital converters between the multiple channels can be realized in the FPGA, and no information loss is caused. Compared with the existing MVT sampling circuit, the resource usage of the FPGA is reduced, the resources are saved, and the time measurement precision and the system integration are improved.

[0033] The rising edges of the pulse signals are staggered by the delay lines, so that the rising edges of the signals in the FPGA are staggered by the threshold time in a simple and low-cost manner, which facilitates subsequent processing.

[0034] The time interval between the rising edges and / or the time interval between the falling edges of the multi-channel delay pulse signals is greater than the minimum time interval of the time-to-digital conversion processing, so as to avoid the phenomenon of information loss or inaccuracy caused by the close rising edges of the signals, thereby ensuring that the digital information sampling processing of the rising edges and the falling edges can be accurately completed in the case that the multiple channel pulse signals use the same TDC, and the data information is accurate.

[0035] Some optional features and other effects of the embodiments of the present application are described below, and some can be understood by reading this document. BRIEF DESCRIPTION OF DRAWINGS

[0036] The present application will be further illustrated in the form of exemplary embodiments, which will be described in detail with reference to the accompanying drawings. These embodiments are not limiting, and in these embodiments, the same reference numbers represent the same structures, wherein:

[0037] Figure 1 A digital processing circuit diagram used in the MVT method in the prior art is shown;

[0038] Figure 2 An application environment diagram of the signal sampling method of the digital PET according to the embodiments of the present application is shown;

[0039] Figure 3 A flowchart of the signal sampling method of the digital PET according to the embodiments of the present application is shown;

[0040] Figure 4 A pulse signal waveform diagram of the input of the digital PET according to the embodiments of the present application is shown;

[0041] Figure 5A waveform diagram of a multi-path delay pulse signal input according to an embodiment of the present application is shown.

[0042] Figure 6 A waveform diagram of a comparison signal according to an embodiment of the present application is shown.

[0043] Figure 7 A flow chart of waveform acquisition based on a four-path delay pulse signal according to an embodiment of the present application is shown.

[0044] Figure 8 A module diagram of a signal sampling device of a digital PET according to an embodiment of the present application is shown.

[0045] Figures 9A-9D A structure diagram of a signal sampling device of a digital PET according to an embodiment of the present application is shown.

[0046] Figure 10 A structure diagram of a detector device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only used to explain and describe a part of the embodiments of the present application, but not all the embodiments of the present application, and are not intended to limit the scope or the claims of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work should be within the scope of protection of the present application.

[0048] It should be noted that when an element is referred to as being "on" another element, it can be directly on the other element or there can be an intervening element. When an element is referred to as being "connected / coupled" to another element, it can be directly connected / coupled to the other element or there can be an intervening element. The term "connected / coupled" as used herein can include electrically and / or mechanically physically connected / coupled. The term "comprises / comprising" as used herein specifies the presence of stated features, steps or elements, but does not preclude the presence or addition of one or more other features, steps or elements. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the present application.

[0050] In addition, in the description of the present application, the terms "first", "second", and the like are only used for descriptive purposes and to distinguish similar objects, and there is no prior and posterior order between them, nor can it be understood as indicating or implying relative importance. In addition, in the description of the present application, unless otherwise specified, the meaning of "multiple" is two or more.

[0051] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0052] Figure 2 The application environment diagram of the signal sampling method of the digital PET in an embodiment. Referring to Figure 2 The method can be applied to a digital PET device. The digital PET device includes a terminal 100 and a detector 200 connected through a network. The method can be executed in the terminal 100 or the detector 200, for example, the terminal 100 can directly obtain the pulse signal from the detector 200 and execute the above method on the terminal side; or the detector 200 can directly execute the above method to obtain the digital signal when detecting, and then send the digital signal to the terminal 100 for data processing. The terminal 100 can be a desktop terminal (for example, a desktop computer) or a mobile terminal (for example, a notebook computer). The detector 200 can be realized by an independent detector or a detector integrated with a sampling chip.

[0053] Figure 3 The signal sampling method of the digital PET according to the embodiment of the present application is shown. The signal sampling method can include the following steps S1, S2, S3 and S4.

[0054] Step S1: The acquired single-channel pulse signal is subjected to delay processing to obtain multiple delay pulse signals.

[0055] In the embodiment of the present application, the single-channel pulse signal is a scintillation pulse signal output by the detector, and the multiple channels are channels in which multiple LVDS of the FPGA chip are located.

[0056] In an embodiment of the present application, the detector includes a scintillation crystal and a photoelectric conversion device.

[0057] The photoelectric conversion device can be a photomultiplier tube (PMT), a silicon photomultiplier (SiPM), a multi-pixel photon counter, or a Geiger-mode avalanche diode, but is not limited thereto.

[0058] The scintillation crystal is often combined with a photoelectric conversion device to form a detector pair to detect gamma rays. The scintillation crystal absorbs the energy of the gamma rays and generates a certain number of visible light photons corresponding to the energy. The photoelectric conversion device is used to receive the batch of photons and convert them into pulse signals, which are further sampled and output via a matching electronic readout system / circuit. The pulse signals are preferably in the form of electrical pulse signals, including but not limited to voltage pulse signals, current pulse signals, etc.

[0059] In an optional embodiment of the present application, the detector uses a silicon photomultiplier (SiPM) as the photoelectric conversion device, and the pulse signals generated by the detector are sampled using a four-channel voltage threshold. Specifically, the pulse signals output by a single channel of the detector are input to four channels of LVDS of an FPGA chip, thereby being divided into four pulse signals. The input pulse signal waveform is shown in Figure 4 The input pulse signal waveform consists of a fast-rising rising edge and a slow-falling falling edge. The rising speed of the rising edge is determined by the scintillation crystal and the photoelectric conversion device; the decay speed of the falling edge is determined by the characteristics of the scintillation crystal. The rising edge of the input pulse signal waveform is usually less than 10 ns, the falling edge is usually greater than 100 ns, and the pulse amplitude varies from a few hundred millivolts to a few volts. The pulse signal waveform is simultaneously input to the 4 p terminals of the LVDS pins of the FPGA chip. A reference voltage threshold is generated by a digital-to-analog converter (DAC) controlled by the FPGA chip and input to the 4 n terminals of the LVDS pins. Specifically, the first threshold, the second threshold, the third threshold, and the fourth threshold are input by DAC1-4, respectively, to facilitate the threshold comparison process.

[0060] After obtaining the multiple pulse signals, the pulse signals input to the multiple channels are subjected to delay processing to delay the pulse signals for a period of time to obtain delayed multiple delay pulse signals. The specific delay time for delay processing can be pre-set according to actual needs or controlled in real time according to received instructions.

[0061] In an embodiment of the present application, after the pulse signals output by a single channel of the detector are divided into multiple channels, the pulse signals are subjected to delay processing, which can be performed independently outside the FPGA or inside the FPGA.

[0062] In an embodiment of the present application, the pulse signals input to the multiple channels are subjected to delay processing, which can be performed by delaying the rising edges of the pulse signals to obtain delay pulse signals.

[0063] The delay pulse signal waveform input to the four channels of the FPGA is also shown in Figure 4As shown, the rising edge of the pulse signal is very steep, and the rising edge and the falling edge of the pulse signals of the multiple channels are staggered after the delay processing, facilitating the collection of complete data information and the smooth operation of the subsequent operation of extracting the time information of the pulse signal, facilitating subsequent processing. In an example of the present application, the pulse signals in the channels of each LVDS input into the FPGA chip are subjected to delay wiring processing, and the transmission time length of the pulse signals in the longer delay line is greater than the transmission time length in the shorter delay line. Specifically, the delay time of the pulse signals of each channel can be preset by setting the line length of the corresponding delay wiring, so that the rising edge and the falling edge of the multiple channels are staggered by a predetermined time to obtain multiple delay pulse signals. The specific implementation form of the delay wiring can refer to the prior art, which will not be described here. The delay processing mode of the present application is not limited to delay wiring, but can also be other delay elements or circuit structures.

[0064] The pulse signals of the multiple channels follow a certain delay output principle, that is, the time interval between the rising edges and / or the falling edges of the multiple delay pulse signals is greater than the minimum time interval of the subsequent time-to-digital conversion processing measurement time. Since the process of time-to-digital conversion processing measurement time of the pulse signal needs at least 10 ns, the time difference is usually greater than 10 ns to meet the requirements. Preferably, the time interval of the rising edge and the falling edge of the pulse signals of the multiple channels is greater than 10 ns.

[0065] In an embodiment, the time interval is fixed. For example, when sampling is performed in a four-channel voltage threshold sampling mode, the reference delay unit of the line delay of the delay wiring can be accurately set to 11 ns. Then, when the pulse waveform generated by the detector is input into the FPGA and divided into four, the second channel is output with a delay of 11 ns compared to the first channel, the third channel is output with a delay of 11 ns compared to the second channel, and the fourth channel is output with a delay of 11 ns compared to the third channel, thereby obtaining four delay pulse signals.

[0066] In another embodiment, the time interval is not fixed. For example, when sampling is performed in a four-channel voltage threshold sampling mode, the pulse waveform generated by the detector is input into the FPGA and divided into four, the second channel is output with a delay of 11 ns compared to the first channel, the third channel is output with a delay of 12 ns compared to the second channel, and the fourth channel is output with a delay of 13 ns compared to the third channel, thereby obtaining four delay pulse signals.

[0067] Step S2: comparing the multiple delay pulse signals with the set threshold in the multiple channels respectively to obtain comparison signals.

[0068] In the embodiments of the present application, the multiple delay pulse signals are respectively input into corresponding LVDS channels to compare with preset threshold values. In an embodiment, when the voltage of the delay pulse signal at the P terminal of the input LVDS is higher than the voltage threshold value at the N terminal, a corresponding high level signal is output, which is a rising edge. At this time, the delay pulse signal output is a digital signal 1 representing a high level signal. When the voltage of the pulse signal at the P terminal of the input LVDS is lower than the voltage threshold value at the N terminal, a corresponding low level signal is output, which is a falling edge. At this time, the delay pulse signal output is a digital signal 0 representing a low level signal.

[0069] Taking the sampling by using a four-channel voltage threshold sampling mode as an example, the four delay pulse signals are respectively compared with preset threshold waveforms in four channels as shown in FIG. 4. Figure 5 Figure 4 For the first threshold to the fourth threshold in FIG. 4, since the time of the pulse rising edge is extremely short, the four rising edges will simultaneously cross the preset threshold values when the rising edge sampling is performed, so it is difficult to determine the accurate time when each threshold is crossed. Therefore, after the delay processing of step S1, the delay pulse signals in each channel will be staggered, and the time when the corresponding preset threshold value is crossed in each channel will also be staggered, that is, Figure 5 ​As shown in the figure, the first channel corresponds to the first threshold value, when the delay pulse signal crosses the first threshold value at the rising edge, the LVDS outputs a high level signal, the position of the first rising edge is the time when the delay pulse signal crosses the first threshold value at the rising edge, when the delay flicker pulse signal crosses the first threshold value at the falling edge, the LVDS outputs a corresponding low level signal, the position of the first falling edge is the time when the delay pulse signal crosses the first threshold value at the falling edge; the second channel corresponds to the second threshold value, when the delay pulse signal crosses the second threshold value at the rising edge, the LVDS outputs a high level signal, the position of the second rising edge is the time when the delay pulse signal crosses the second threshold value at the rising edge, when the delay flicker pulse signal crosses the second threshold value at the falling edge, the LVDS outputs a corresponding low level signal, the position of the second falling edge is the time when the delay pulse signal crosses the second threshold value at the falling edge; the third channel corresponds to the third threshold value, when the delay pulse signal crosses the third threshold value at the rising edge, the LVDS outputs a high level signal, the position of the third rising edge is the time when the delay pulse signal crosses the third threshold value at the rising edge, when the delay flicker pulse signal crosses the third threshold value at the falling edge, the LVDS outputs a corresponding low level signal, the position of the third falling edge is the time when the delay pulse signal crosses the third threshold value at the falling edge; the fourth channel corresponds to the fourth threshold value, when the delay pulse signal crosses the fourth threshold value at the rising edge, the LVDS outputs a high level signal, the position of the fourth rising edge is the time when the delay pulse signal crosses the fourth threshold value at the rising edge, when the delay flicker pulse signal crosses the fourth threshold value at the falling edge, the LVDS outputs a corresponding low level signal, the position of the fourth falling edge is the time when the delay pulse signal crosses the fourth threshold value at the falling edge. After comparison, the rising edge or falling edge time of the comparison signal corresponding to each channel is staggered, which is convenient for subsequent time sampling.

[0070] Step S3: switching the multiple channels based on the multiple comparison signals, and sequentially performing time-to-digital conversion processing on the switched comparison signals to extract time information.

[0071] After obtaining the multiple comparison signals, the multiple channels can be switched using the multiple comparison signals to realize waveform acquisition, and the switched comparison signals are sequentially subjected to time-to-digital conversion processing to extract time information.

[0072] In Figure 3 the embodiment, step S3 can specifically include sequentially switching the multiple comparison signals according to a preset algorithm or a preset order, and then sequentially extracting time information from the comparison signals of the current channel.

[0073] The preset algorithm can be an "and" or "or" logical operation, or sequentially switching according to the number of threshold values, etc., and the purpose is to enable different rising edges or falling edges to be identified in the subsequent time-to-digital conversion processing process.

[0074] In Figure 3 In the embodiment, the step S3 can specifically include: sequentially performing waveform acquisition processing on the multiple comparison signals, obtaining a feedback output signal, and switching to a corresponding channel based on the feedback output signal; and performing waveform acquisition based on the channel switching, and obtaining corresponding time information.

[0075] In the embodiment, after the multiple comparison signals are obtained, the rising edge waveform acquisition processing and the falling edge waveform acquisition processing are sequentially performed on the multiple comparison signals to obtain the feedback output signal. Specifically, after the multiple comparison signals are obtained, the rising edge waveform acquisition processing is sequentially performed according to the order of arrival of the rising edges of the multiple comparison signals, and the falling edge waveform acquisition processing is sequentially performed according to the order of arrival of the falling edges of the multiple comparison signals.

[0076] After the feedback output signal is obtained, the switching to the corresponding channel is controlled based on the feedback output signal to realize the gating of the channel; and the rising edge waveform acquisition and the falling edge waveform acquisition are sequentially performed on the comparison signals of the multiple channels based on the channel switching to complete the waveform acquisition. The specific implementation form of the control system for controlling the channel switching can adopt any suitable controller and selector in the prior art, and will not be described here.

[0077] In an embodiment, the step of sequentially performing waveform acquisition processing on the multiple comparison signals further includes: performing time-to-digital conversion preprocessing on the multiple comparison signals to obtain the feedback output signal. Specifically, the comparison signal output by the switched channel is preprocessed by time-to-digital conversion to obtain the feedback output signal. That is, the comparison signal is processed by time-to-digital conversion, specifically, only the first level of signal processing is performed, and the corresponding signal is output. Preferably, the time-to-digital conversion preprocessing only performs the first level of processing on the multiple comparison signals, and outputs the first level of signal as the feedback output signal. In a preferred embodiment, the time-to-digital conversion processing is implemented by a time-to-digital converter TDC of an FPGA chip. The TDC uses a carry chain to realize the time acquisition of the rising edge or the falling edge of a pulse, and usually each level of the carry chain has a tap to a D flip-flop (DFF) to complete clock sampling. The data on the carry chain when the sampling clock arrives is 0 or 1. Preferably, the output of the DFF of the first level of the TDC is used as the feedback output signal, that is, whether the digital signal output by the first level DFF of the TDC is 0 or 1 is used as the feedback output signal, which is used as the criterion for controlling the channel switching. Using the output of the DFF of the first level of the TDC as the feedback output signal can avoid adding an extra tap on the input signal link, and improves the final time measurement accuracy. The specific implementation form of the TDC can refer to the prior art, and will not be described here.

[0078] In another embodiment, the waveform acquisition processing is sequentially performed on the multiplexed comparison signals, and the step of obtaining the feedback output signal further comprises: obtaining the feedback output signal based on the multiplexed comparison signals. Specifically, the comparison signal output by the switched channel is the feedback output signal. Specifically, the comparison signal output by the switched channel is directly transmitted to the control system for controlling the switching channel as the feedback output signal, and the control system directly identifies whether the comparison signal output by the switched channel is digital 0 or digital 1 to control the subsequent switching channel operation.

[0079] In an embodiment of the application, four-channel voltage threshold sampling is used, four channels are processed for delay to obtain four delay pulse signals, the four channels are channel 1, channel 2, channel 3 and channel 4, based on the four comparison signals, the feedback output signal is obtained as a criterion for switching the four channels, and the four channels are switched based on the obtained feedback output signal to realize waveform acquisition and obtain the corresponding complete pulse time of crossing each threshold. Figure 7 As shown in the figure, the specific steps of realizing waveform acquisition based on four comparison signals include:

[0080] S310: sequentially performing rising edge waveform acquisition on the four delay pulse signals.

[0081] S3101: Channel 1 is gated, the feedback output signal is obtained, and it is determined whether the feedback output signal is 1, if not, channel 1 continues to be gated, and if yes, step S3102 is executed;

[0082] S3102: Channel 2 is gated, the feedback output signal is obtained, and it is determined whether the feedback output signal is 1, if not, channel 2 continues to be gated, and if yes, step S3103 is executed;

[0083] S3103: Channel 3 is gated, the feedback output signal is obtained, and it is determined whether the feedback output signal is 1, if not, channel 3 continues to be gated, and if yes, step S3104 is executed;

[0084] S3104: Channel 4 is gated, the feedback output signal is obtained, and it is determined whether the feedback output signal is 1, if not, channel 4 continues to be gated, and if yes, the rising edge waveform acquisition is completed, and the falling edge waveform acquisition step is executed, i.e., step S320 is executed.

[0085] S320: sequentially performing falling edge waveform acquisition on the four delay pulse signals.

[0086] S3201: Channel 4 is gated, the feedback output signal is obtained, and it is determined whether the feedback output signal is 0, if not, channel 4 continues to be gated, and if yes, step S3202 is executed;

[0087] S3202: Channel 3 is gated, the feedback output signal is acquired, and it is judged whether the feedback output signal is 0. No, channel 3 continues to be gated. Yes, step S3203 is executed.

[0088] S3203: Channel 2 is gated, the feedback output signal is acquired, and it is judged whether the feedback output signal is 0. No, channel 2 continues to be gated. Yes, step S3204 is executed.

[0089] S3204: Channel 1 is gated, the feedback output signal is acquired, and it is judged whether the feedback output signal is 0. No, channel 1 continues to be gated. Yes, it is ended, the complete synchronization switching pulse signal is acquired, and the next start is waited.

[0090] After step S3204 is ended, that is, the waveform acquisition and processing of the comparison signals of the four channels are sequentially completed, the time measurement of the rising and falling edges of the comparison signals is performed, and the corresponding complete pulse time of crossing each threshold value is acquired.

[0091] The specific form of the time-to-digital conversion processing can refer to the prior art, and will not be repeated here.

[0092] It can be seen from the above description that, by performing delay processing on the pulse signals of multiple channels, the rising edges of the pulse signals are staggered to obtain the delay pulse signals, which avoids the problem that the time when the pulse signal reaches the corresponding voltage threshold value cannot be accurately obtained when the time-to-digital conversion processing is performed on the pulse signals, resulting in information loss or inaccuracy. Based on the delay pulse signals obtained through the delay processing, the same logic unit of the FPGA can be used to control the switching of multiple channels. Based on the switching of the channels, the same time-to-digital converter (TDC) of the FPGA can be used to perform time-to-digital conversion processing, and the time information of the rising and falling edges of the pulse signals can be extracted, so that the digital processing of the multi-channel pulse signals can be completed by using one time-to-digital conversion component. Compared with the prior art in which a time-to-digital converter TDC is configured for each channel to measure the pulse signal time information, the resource usage of the FPGA is reduced, and the time measurement precision and system integration are improved.

[0093] Figure 8 A signal sampling device of a digital PET is shown, and the multi-channel signal digital processing device is arranged in an FPGA chip and used to process the single-channel pulse signals output by a detector. Figure 8As shown, the signal sampling device of the digital PET includes: a delay module configured to delay the pulse signals input to the multiple channels, obtain multiple delayed pulse signals; a routing switching module configured to switch the multiple channels based on the multiple delayed pulse signals, obtain comparison signals; and perform time-to-digital conversion processing on the comparison signals to extract time information. The multiple channels are multiple channels corresponding to each LVDS of the FPGA, and the LVDS simultaneously serves as a comparator. The single-channel pulse signals output by the detector are divided into multiple delayed pulse signals entering the multiple channels of the FPGA chip, and the switching channel waveform acquisition and the processing of measuring the time information of the pulse signals are performed.

[0094] The embodiment of the present application avoids the problem that the time when the pulse signal reaches the corresponding voltage threshold cannot be accurately obtained during the time-to-digital conversion processing of the pulse signal, resulting in information loss or inaccuracy, by delaying the pulse signals of the multiple channels to obtain delayed pulse signals whose rising edges are staggered with each other. Based on the delayed pulse signals obtained through the delay processing, the same logic unit of the FPGA can be used to control the switching of the multiple channels, and based on the switching of the channels, the same time-to-digital converter (TDC) of the FPGA can be used for time-to-digital conversion processing to extract the time information of the rising edge and the falling edge of the pulse signal, so that the digital processing of the multiple-channel pulse signals can be completed using one time-to-digital conversion component. Compared with the prior art method of configuring a time-to-digital converter TDC for each channel to measure the time information of the pulse signal, the resource usage of the FPGA is reduced, and the time measurement accuracy and system integration are improved.

[0095] In an embodiment, the multiple channels are each provided with a delay module. Specifically, the channel where each LVDS of the FPGA is located is provided with a delay module.

[0096] The delay module comprises a plurality of delay units. Preferably, the delay units adopt a delay line structure, and specifically, the delay units comprise a plurality of delay line structures. In an example, a plurality of delay line structures connected with LVDS are arranged in each channel of the FPGA, and the rising edge and the falling edge of the pulse signals of the plurality of channels are staggered by means of the delay line structures, so as to facilitate the collection of complete data information and to make the subsequent operation of extracting the time information of the pulse signals smoothly. The transmission time of the pulse signals in a longer delay line is longer than that in a shorter delay line, and the delay time of the pulse signals of each channel can be preset by setting the length of the delay line, for example, one delay line structure can be arranged in each channel, but the delay time of each delay line structure is set according to the requirement; a plurality of delay line structure units can also be arranged in each channel, and the length of the delay line of each delay line structure unit is fixed, that is, the lengthening time is fixed, and the number of the delay line structure units arranged in each channel is adjusted according to the specific requirement; the delay line structure and a plurality of delay line structure units can also be used in combination. By means of the above delay line structure, the rising edges of the pulse signals of the plurality of channels are staggered by a predetermined time to obtain a plurality of delay pulse signals. The specific implementation form of the delay line structure can refer to the prior art, and will not be described here.

[0097] The pulse signals of the plurality of channels follow a certain delay output principle, and specifically, the time interval between the rising edge and the falling edge of the plurality of delay pulse signals is greater than the minimum time interval of the time digital conversion processing and measurement time of the subsequent routing switching module. Since the time required by the routing switching module for the time digital conversion processing and measurement of the pulse signals is at least 10 ns, the time difference is usually greater than 10 ns, which can meet the requirement. Preferably, the interval time between the rising edge and the falling edge of the delay pulse signals output by the plurality of channels after being delayed by the delay units is greater than 10 ns. For example, when a four-channel voltage threshold sampling method is used for sampling, the line delay reference unit of the delay line can be accurately set to 11 ns, and then after the pulse waveform generated by the detector is input into the FPGA chip, the second channel is output by delaying the first channel by 11 ns, the third channel is output by delaying the second channel by 11 ns, and the fourth channel is output by delaying the third channel by 11 ns, so as to obtain four delay pulse signals.

[0098] In an embodiment, the delay pulse signals output by the plurality of channels are sequentially spaced apart by the same time interval. For example, the rising edge or falling edge of the delay pulse signal output by the second channel can be offset by 13 ns from the rising edge or falling edge of the delay pulse signal output by the first channel, the rising edge or falling edge of the delay pulse signal output by the third channel can be offset by 13 ns from the rising edge or falling edge of the delay pulse signal output by the second channel, and so on. Specifically, the delay unit of the first channel can be configured to include a delay line structure with a delay of 13 ns, the delay unit of the second channel can be configured to include a delay line structure with a delay of 26 ns, the delay unit of the third channel can be configured to include a delay line structure with a delay of 39 ns, and so on, as long as the delay line structure of the next channel has a delay that is 13 ns longer than the delay of the delay line structure of the previous channel. Alternatively, the delay unit of the first channel can be configured to include a delay line structure with a delay of 13 ns, the delay unit of the second channel can be configured to include two delay line structures with a delay of 13 ns, the delay unit of the third channel can be configured to include three delay line structures with a delay of 13 ns, and so on. The same time interval is not limited to 13 ns, and can be greater than 10 ns.

[0099] In another alternative embodiment, the delay pulse signals output by the plurality of channels are sequentially spaced apart by different time intervals. For example, the rising edge and falling edge of the delay pulse signal output by the second channel can be offset by 14 ns from the rising edge and falling edge of the delay pulse signal output by the first channel, the rising edge and falling edge of the delay pulse signal output by the third channel can be offset by 15 ns from the rising edge and falling edge of the delay pulse signal output by the second channel, and the rising edge and falling edge of the delay pulse signal output by the fourth channel can be offset by 16 ns from the rising edge and falling edge of the delay pulse signal output by the third channel. The time interval can be greater than 10 ns. The specific delay unit can also be configured to include a single delay line structure, for example, the delay line structure of the first channel has a delay of 14 ns, the delay line structure of the second channel has a delay of 28 ns, the delay line structure of the third channel has a delay of 43 ns, and the delay line structure of the fourth channel has a delay of 59 ns. Alternatively, a combination of a plurality of delay line structures can also be used.

[0100] The delay unit of the present application is not limited to a delay line structure. In some embodiments, other delay elements or circuit structures can also be used.

[0101] In an example, the plurality of channels of the FPGA chip are provided with an LVDS comparator, the input end of each delay module is connected to a signal, and the output end of the delay module is connected to the input end of the LVDS comparator. The pulse signals input by the plurality of channels are input to the LVDS comparator after delay processing, and the voltage threshold is output. For example, Figure 9BIn the example shown in FIG. 9C, taking four channels as an example, the FPGA chip is provided with four channels, namely channel 1, channel 2, channel 3 and channel 4, and the channel 1 to channel 4 are respectively provided with delay module 1 to delay module 4 and comparator 1 to comparator 4. The delay module specifically adopts delay line 1 to delay line 4. The pulse signals of the input channel 1 to input channel 4 are input into the comparator 1 to comparator 4 for voltage threshold comparison after passing through the delay module, and the comparison signals are output.

[0102] Specifically, referring to the method embodiment, when the pulse signal voltage of the p terminal of the input LVDS is higher than the voltage threshold of the n terminal, the comparison signal output is a digital signal 1 representing a high-level signal, and when the pulse signal voltage of the p terminal of the input LVDS is lower than the voltage threshold of the n terminal, the comparison signal output is a digital signal 0 representing a low-level signal.

[0103] In an embodiment, the route switching module includes a channel selection module, a time-to-digital conversion module and a channel control module.

[0104] The channel selection module is configured to receive the comparison signals of the channels selected by the channel selection module and transmit the comparison signals to the time-to-digital conversion module. The time interval between the rising edges and the time interval between the falling edges of the comparison signals are greater than the minimum time interval processed by the time-to-digital conversion module. The channel selection module includes a channel selector, which includes but is not limited to a multiplexer (MUX) and can also be implemented in any appropriate manner, which will not be described here. In an embodiment of the present application, in the embodiment shown in FIG. 9A, the channel selector is a multiplexer (MUX). The multiplexer (MUX) is configured to receive the comparison signals of the channels selected by the channel selection module and transmit the comparison signals to the time-to-digital conversion module. The time interval between the rising edges and the time interval between the falling edges of the comparison signals are greater than the minimum time interval processed by the time-to-digital conversion module. Figure 9B 、 Figure 9C or Figure 9D In the embodiment shown in FIG. 9C, the comparison signals output by the channels switched to by the channel selector are feedback output signals. Specifically, the comparison signals output by the channels switched to are directly transmitted to the channel control module as feedback output signals, and the channel control module directly identifies whether the comparison signals output by the channels switched to are digital 0 or digital 1 to control the switching channel operation of the channel selector.

[0105] The time-to-digital conversion module is configured to perform rising edge waveform acquisition processing and falling edge waveform acquisition processing on the comparison signals of the channels switched to, and output feedback output signals to the channel control module. The time-to-digital conversion module processes the comparison signals to measure the time of the rising edge and the falling edge, respectively. The minimum time interval processed by the time-to-digital conversion module is 10 ns to ensure that accurate time information can be extracted. In another embodiment, as shown in the embodiment of FIG. 9C, the feedback output signal is the output signal of the first flip-flop of the time-to-digital conversion module to avoid long signal links affecting the time measurement accuracy. Figure 9D

[0106] ​The channel control module is configured to control the switching of the corresponding channel based on the feedback output signal received thereby and output a synchronous switching pulse signal to the time-to-digital conversion module for time measurement. The channel control module comprises a channel controller, which can be implemented in any appropriate manner and will not be described here.

[0107] In an embodiment, the time-to-digital conversion module comprises a time-to-digital converter (TDC) provided in the FPGA chip. Figures 9A-9D In the embodiment shown, only one time-to-digital converter (TDC) is provided. The time-to-digital converter (TDC) comprises a carry chain, a D flip-flop (DFF) and a processing unit.

[0108] The carry chain is configured to collect the time of the rising and falling edges of the pulse signal and output a sampling clock data signal. Specifically, each stage of the carry chain has a tap to the D flip-flop (DFF) to complete clock sampling and obtain the data on the carry chain at the time when the sampling clock arrives, which is either 0 or 1. The carry chain can be implemented in any appropriate manner and will not be described here.

[0109] The D flip-flop (DFF) is configured to receive the sampling clock data signal and output a feedback output signal to the channel control module based on the sampling clock data signal. Preferably, the output of the flip-flop of the first stage of the TDC is used as the feedback output signal and is connected to the channel controller to obtain the digital 0 and 1 signals output thereby as the criterion for channel switching, so as to avoid adding additional taps to the input signal link and affecting the final time measurement accuracy. The D flip-flop can be implemented in any appropriate manner and will not be described here.

[0110] The processing unit is configured to receive the synchronous switching pulse signal output by the channel control module and extract time information. The processing unit can be implemented in any appropriate manner and will not be described here.

[0111] The working principle of the signal sampling device of the digital PET of the present application is as follows:

[0112] In the embodiment shown in FIG. 1, the signal sampling device of the digital PET of the present application can be used in the following manner: Figure 9A In the embodiment shown in FIG. 1, the signal sampling device of the digital PET of the present application can be used in the following manner:

[0113] In the embodiment shown in FIG. 1, the signal sampling device of the digital PET of the present application can be used in the following manner: Figure 9B

[0114] ​Firstly, the single-channel pulse signal output by the probe is divided into four pulse signals, which are input into comparators 1-4 of four FPGA chips (input into LVDS pins p) at the same time. The comparison threshold is generated by DAC and input into the comparators 1-4 (input into LVDS pins n), so as to complete the threshold comparison process.

[0115] Then, the rising edge waveform of each channel is collected in turn:

[0116] The pulse signal output by the comparator 1 in channel 1 is delayed by a preset time, for example, 12 ns, through the delay line structure 1 of the delay unit, and a first delayed pulse signal waveform is output. The first delayed pulse signal waveform enters the signal routing control module for rising edge waveform collection and processing. Firstly, the digital signal 0, 1 output by the first-stage D flip-flop of the TDC is taken as a feedback output signal, which is taken as a criterion for channel switching. The feedback output signal is transmitted to the channel controller. The channel controller generates a control signal for switching to the corresponding channel according to the signal, and transmits the control signal to the channel selector to select the corresponding channel for continuing the rising edge waveform collection. Specifically, if the TDC outputs the digital signal 0, the controller continues to collect the rising edge signal of channel 1, and the channel selector continues to select channel 1 at this time. If the TDC outputs the digital signal 1, the rising edge waveform collection of channel 1 is completed. The channel controller generates a control signal for switching to channel 2. Based on the control signal, the channel selector selects channel 2 for continuing the rising edge waveform collection of the pulse signal.

[0117] The pulse signal output by the comparator 2 in channel 2 is delayed by a preset time, for example, 24 ns, through the delay line structure 2 of the delay unit, and a second delayed pulse signal waveform is output. The second delayed pulse signal waveform enters the signal routing control module for rising edge waveform collection and processing. If the TDC outputs the digital signal 1, the rising edge waveform collection of channel 2 is completed. The channel controller generates a control signal for switching to channel 3. Based on the control signal, the channel selector selects channel 3 for continuing the rising edge waveform collection of the pulse signal.

[0118] The pulse signal output by the comparator 3 in channel 3 is delayed by a preset time, for example, 36 ns, through the delay line structure 3 of the delay unit, and a third delayed pulse signal waveform is output. The third delayed pulse signal waveform enters the signal routing control module for rising edge waveform collection and processing. If the TDC outputs the digital signal 1, the rising edge waveform collection of channel 3 is completed. The controller generates a control signal for switching to channel 4. Based on the control signal, the channel selector selects channel 4 for continuing the rising edge waveform collection of the pulse signal.

[0119] The pulse signal output by the comparator 4 in the channel 4 is delayed by a delay line structure 4 of the delay unit for a preset time, such as 48 ns, to output a fourth delay pulse signal waveform, which enters the signal routing control module for rising edge waveform acquisition processing; when the TDC outputs a digital signal 1, the rising edge waveform acquisition of the channel 4 ends;

[0120] Up to now, the rising edge waveform acquisition of the channels 1-4 ends.

[0121] Next, the channels 4-1 are sequentially subjected to falling edge waveform acquisition:

[0122] After the rising edge waveform acquisition of the channel 4 ends, the channel 4 continues to be selected, and the fourth delay pulse signal waveform of the channel 4 enters the signal routing control module for falling edge waveform acquisition processing. First, the waveform acquisition of the falling edge of the pulse is transmitted to the TDC, and the digital signals 0, 1 output by the first stage D flip-flop of the TDC are taken as feedback output signals as the criterion for channel switching, which are transmitted to the channel controller. The channel controller generates a control signal for switching to the corresponding channel according to the signal, which is transmitted to the channel selector to select the corresponding channel to continue the falling edge waveform acquisition. Specifically, if the TDC outputs a digital signal 1, the controller generates a signal for controlling the falling edge acquisition of the channel 4 to continue, and the channel selector continues to select the channel 4.

[0123] The third delay pulse signal waveform in the channel 3 enters the signal routing control module for falling edge waveform acquisition processing. When the TDC outputs a digital signal 0, the falling edge waveform acquisition of the channel 3 ends. The controller generates a control signal for switching to the channel 2, and based on this control signal, the channel selector selects the channel 2 to continue the falling edge waveform acquisition of the pulse signal.

[0124] The second delay pulse signal waveform in the channel 2 enters the signal routing control module for falling edge waveform acquisition processing. When the TDC outputs a digital signal 0, the falling edge waveform acquisition of the channel 2 ends. The controller generates a control signal for switching to the channel 1, and based on this control signal, the channel selector selects the channel 1 to continue the falling edge waveform acquisition of the pulse signal.

[0125] The first delay pulse signal waveform in the channel 1 enters the signal routing control module for falling edge waveform acquisition processing. When the TDC outputs a digital signal 0, the falling edge waveform acquisition of the channel 1 ends.

[0126] Up to now, this time of waveform acquisition ends, and a complete synchronous switching pulse waveform is obtained, waiting for the next start.

[0127] Finally, the channel controller transmits the synchronous switching pulse waveform obtained by controlling the channel switching to the TDC to extract the time information, so as to obtain the time information of the multi-channel pulse signal.

[0128] In the embodiment, the working mode of the signal sampling device of the digital PET of the present application can be used, which is different from the working mode in the embodiment. Figure 9C In the embodiment, the working mode of the signal sampling device of the digital PET of the present application can be used, which is different from the working mode in the embodiment. Figure 9B In the embodiment, the working mode of the signal sampling device of the digital PET of the present application can be used, which is different from the working mode in the embodiment.

[0129] In the embodiment, the working mode of the signal sampling device of the digital PET of the present application can be used, which is different from the working mode in the embodiment. Figure 9D In the embodiment, the working mode of the signal sampling device of the digital PET of the present application can be used, which is different from the working mode in the embodiment. Figure 9B In the embodiment, the working mode of the signal sampling device of the digital PET of the present application can be used, which is different from the working mode in the embodiment.

[0130] The embodiment of the present application avoids the problem that the time when the pulse signal reaches the corresponding voltage threshold cannot be accurately obtained during the subsequent time-to-digital conversion processing of the pulse signal, resulting in information loss or inaccuracy, by performing delay processing on the pulse signals of multiple channels to obtain delay pulse signals whose rising edges are staggered with each other. Based on the delay pulse signals obtained through the delay processing, the same logic unit of the FPGA can be used to control the switching of multiple channels, and based on the switching of the channels, the same time-to-digital converter (TDC) of the FPGA can be used for time-to-digital conversion processing to extract the time information of the rising edge and the falling edge of the pulse signal, so that a single time-to-digital conversion component can complete the digital processing of the multi-channel pulse signal. Compared with the prior art of configuring a time-to-digital converter TDC for each channel to measure the pulse signal time information, the resource usage of the FPGA is reduced, and the time measurement accuracy and system integration are improved.

[0131] Figure 10An embodiment of the present application provides a detector device, which comprises a detector and the signal sampling device of the digital PET of any of the above embodiments, wherein the detector is configured to detect rays and output pulse signals to the signal sampling device of the digital PET for digital processing. The detector refers to the detector in the method embodiments.

[0132] An embodiment of the present application provides a computer device, which can be a terminal or a server in the computer device Figure 2 The computer device comprises a memory configured to store a computing program, and a processor configured to execute the computing program to perform the signal sampling method of the digital PET of any of the embodiments.

[0133] The apparatus, circuit, device described in the embodiments of the present application can be combined with the method features described in the embodiments of the present application, and vice versa.

[0134] Although not shown, in some embodiments, a computer readable storage medium is also provided, which stores a computer program configured to be executed to perform the method of any of the embodiments of the present application. The computer program comprises various program modules / units constituting the apparatus according to the embodiments of the present application, and the computer program executed by the various program modules / units can realize the functions corresponding to the various steps in the method described in the above embodiments. The computer program can also be executed on the computer device as described in the embodiments of the present application.

[0135] The storage medium of the embodiments of the present application includes non-volatile and / or volatile information storage articles that can be realized by any method or technology. The non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. The volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0136] Those skilled in the art should understand that the embodiments of the present specification can be implemented in various forms such as a method, a system or a computer program product. Therefore, those skilled in the art can think that the implementation of the functional modules / units or controllers and the related method steps illustrated by the above-described embodiments can be implemented in software, hardware and a combination of software and hardware.

[0137] Unless explicitly stated, the actions or steps of the methods, programs described in the embodiments of the present application do not have to be performed in a specific order and still achieve the desired results. In some embodiments, multi-task processing and parallel processing are possible or can be advantageous.

[0138] In this document, descriptions of multiple embodiments have been presented for the purpose of providing those skilled in the art with a thorough understanding of the application. Accordingly, the descriptions of the embodiments are not intended to limit the scope of the application. Various embodiments can omit, substitute, or add various procedures or components as appropriate. For instance, it should be understood that the methods, procedures, steps, and / or components described herein can be performed in an arbitrary sequence. As such, the descriptions of the various embodiments have been presented for the purpose of illustration and description only and not by way of limitation. Furthermore, the purposes of the embodiments have been set forth above, and the descriptions of the embodiments have been presented in order to provide those skilled in the art with a thorough understanding of the application.

[0139] The exemplary systems and methods of this application have been described with reference to the specific implementations as set forth above. This description is merely illustrative of the best mode of practicing the systems and methods of this application. Numerous variations and modifications will become apparent to those skilled in the art once the principles of the present application have been articulated above. The applications described herein are intended to achieve the spirit of the application, which is defined in the appended claims.

Claims

1. A signal sampling method for digital PET, characterized in that, include: The pulse signal from a single channel is simultaneously input into multiple corresponding channels to form a multi-channel pulse signal. The multi-channel pulse signal is then delayed to stagger the rising edges of the pulse signals, thus obtaining a multi-channel delayed pulse signal. The multiple channels are switched based on the multi-channel delayed pulse signal to obtain a comparison signal; The comparison signal is processed by a time-to-digital converter to extract time information; Wherein, the time interval between the rising edges and / or the time interval between the falling edges of the multi-channel delayed pulse signal are greater than the minimum time interval for time-to-digital conversion processing.

2. The signal sampling method according to claim 1, characterized in that, The steps for delaying pulse signals input to multiple channels to obtain multiple delayed pulse signals include: For pulse signals input from multiple channels simultaneously, the rising edges of the pulse signals are staggered by delay routing to obtain multiple delayed pulse signals.

3. The signal sampling method according to claim 1, characterized in that, The minimum time interval for the time-to-digital conversion process is 10 ns.

4. The signal sampling method according to claim 1, characterized in that, The step of switching the multiple channels based on the multi-channel delayed pulse signal to obtain the comparison signal includes: The multi-channel delayed pulse signals are sequentially processed by waveform acquisition, and the channels are switched according to a preset order and compared with a preset threshold to obtain the corresponding comparison signals.

5. The signal sampling method according to claim 4, characterized in that, The step of sequentially acquiring and processing the waveforms of the multi-channel delayed pulse signals to obtain the comparison signal includes: obtaining the feedback output signal based on the multi-channel delayed pulse signals.

6. The signal sampling method according to claim 5, characterized in that, The step of sequentially acquiring and processing the waveforms of the multiple delayed pulse signals to obtain the comparison signal further includes: The multi-channel delayed pulse signals are sequentially processed by acquiring rising edge waveforms and falling edge waveforms to obtain feedback output signals.

7. The signal sampling method according to claim 6, characterized in that, The steps of sequentially performing rising edge waveform acquisition processing and falling edge waveform acquisition processing on the multi-channel delayed pulse signals include: The rising edge waveforms of the multiple delayed pulse signals are acquired and processed sequentially according to the order in which the rising edges arrive, and the falling edge waveforms are acquired and processed sequentially according to the order in which the falling edges arrive.

8. The signal sampling method according to claim 1, characterized in that, The time-to-digital conversion process is implemented using a single-channel time-to-digital converter.

9. A signal sampling device for digital PET, characterized in that, include: The delay module is configured to delay the input multi-channel pulse signals by staggering the rising edges of the pulse signals to obtain multi-channel delayed pulse signals. The multi-channel pulse signals are formed by simultaneously inputting the pulse signals of a single channel to the corresponding multiple channels. The routing switching module is configured to switch the multiple channels based on the multi-channel delay pulse signal and obtain a comparison signal; The comparison signal is processed by the same time-to-digital conversion module to extract time information. Wherein, the time interval between the rising edges and / or the time interval between the falling edges of the multi-channel delayed pulse signal are greater than the minimum time interval for time-to-digital conversion processing.

10. The signal sampling device according to claim 9, characterized in that, Each of the multiple channels is equipped with a comparator, and the output of the delay module is connected to the input of the comparator.

11. The signal sampling device according to any one of claims 9-10, characterized in that, The delay module includes a delay line structure.

12. The signal sampling device according to any one of claims 9-10, characterized in that, The delay module includes several delay line structure units, which are located outside the module containing the comparator.

13. The signal sampling device according to claim 9, characterized in that, The routing switching module includes a channel selection module and a time-to-digital conversion module, wherein, The channel selection module is configured to receive the delayed pulse signal of the channel it selects and convert the delayed pulse signal into a comparison signal and transmit it to the time-to-digital converter module. The time-to-digital conversion module is configured to perform rising edge waveform acquisition and falling edge waveform acquisition processing on the comparison signal of the switched channel, and perform time-to-digital conversion to obtain the time corresponding to the rising edge and falling edge respectively.

14. The signal sampling device according to claim 9, characterized in that, The routing switching module includes a channel selection module, a time-to-digital conversion module, and a channel control module, wherein... The channel selection module is configured to receive the delayed pulse signal of the channel it selects and convert the delayed pulse signal into a comparison signal and transmit it to the time-to-digital converter module. The time-to-digital conversion module is configured to perform rising edge waveform acquisition processing and falling edge waveform acquisition processing on the comparison signal of the switched channel, respectively, output a feedback output signal to the channel control module, and receive the synchronous switching pulse signal output by the channel control module, and perform time-to-digital conversion processing on the synchronous switching pulse signal to measure the rising edge and falling edge time respectively. The channel control module is configured to control the switching to the corresponding channel based on the feedback output signal it receives, and to output a synchronous switching pulse signal to the time-to-digital converter module for time measurement.

15. The signal sampling device according to claim 9, characterized in that, The routing switching module includes a channel selection module, a time-to-digital conversion module, and a channel control module, wherein... The channel selection module is configured to receive the delayed pulse signal of the channel it selects, convert the delayed pulse signal into a comparison signal and transmit it to the time-to-digital converter module, and transmit the comparison signal as a feedback output signal to the channel control module. The time-to-digital conversion module is configured to perform rising edge waveform acquisition and falling edge waveform acquisition processing on the comparison signal of the switched channel, and perform time-to-digital conversion to measure the time of the rising edge and falling edge respectively. The channel control module is configured to control the switching to the corresponding channel based on the feedback output signal it receives, and to output a synchronous switching pulse signal to the time-to-digital converter module for time measurement.

16. The signal sampling device according to claim 9, characterized in that, The minimum time interval processed by the time-to-digital conversion module is 10 ns.

17. The signal sampling device according to claim 9, characterized in that, The time-to-digital conversion module includes a time-to-digital converter, which includes: The carry chain is configured to acquire the timing of the rising and falling edges of the pulse signal and output the sampled clock data signal. A D flip-flop is configured to receive the sampling clock data signal and output a feedback output signal to the channel control module based on the sampling clock data signal. The processing unit is configured to receive the synchronization switching pulse signal output by the channel control module and extract time information.

18. A detector device, characterized in that, The detector device includes: The detector and the signal sampling device for the digital PET as described in any one of claims 9-17, wherein the detector is configured to detect rays and output pulse signals to the signal sampling device for digital processing.

19. A computer device, characterized in that, The computer device includes: The memory is configured to store computational programs; The processor is configured to execute the computational program to perform the signal sampling method of digital PET as described in any one of claims 1-8.

20. A computer-readable storage medium, characterized in that, The computer-readable storage medium is configured to store a computing program, which, when run, performs the signal sampling method of digital PET as described in any one of claims 1-8.

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