First-In-First-Out Buffer and Control Method Thereof

Abstract

The present application discloses a first-in-first-out buffer and a control method therefor. The first-in-first-out buffer includes: an input processing module, a register bank, an output processing module, and a status generation module. The status generation module determines status information; the input processing module receives requests for input multiplexed data and determines the valid data to be written among the multiplexed data; determines the valid number of data that can be written according to the number of valid data to be written and the number of remaining data that can be received, generates an increment of the write pointer based on the valid number of data that can be written, and sends the valid data to be written to the register bank; the output processing module receives requests for output data, generates an increment of the read pointer and sends it to the register bank; the register bank writes the valid data to be written into the register according to the write pointer and updates the write pointer according to the increment of the write pointer, and / or reads the data to be output from the register according to the read pointer and updates the read pointer according to the increment of the read pointer. The solution provided by the present application uses a register bank as a storage unit, which can avoid the problem of waste of resources when the depth is small.

Description

Technical Field

[0001] This application relates to the technical field of data caching, and particularly to a first-in-first-out buffer and a control method for the first-in-first-out buffer. Background Art

[0002] A first-in-first-out buffer (First Input First Output, abbreviated as FIFO) is a commonly used data caching device in modern digital integrated circuit design, mainly for realizing data queue caching, caching and outputting data in the order of data input. Traditional FIFO can only achieve single input and single output, that is, only one data can be output or input at a time. For the situation where multiple input data need to be cached and output in order, multiple FIFOs have to be used for caching, and an arbiter is used at the FIFO exit to select one for output. This method requires the use of multiple FIFOs and an arbiter, resulting in relatively large resource waste.

[0003] Existing multi-input FIFOs are mainly for scenarios with a relatively large storage depth, usually implemented using a random access memory (Random Access Memory, RAM) in a multi-level caching form. For example, in the solution disclosed in the patent with the patent number CN104778025A and the name "Circuit Structure of First-in-First-Out Memory Based on Random Access Memory", a RAM is used to implement a multi-input single-output FIFO. However, in this solution, N + 1 blocks of RAM are required for N-way inputs. If the depth of each block of RAM is M, the effective data storage capacity of this FIFO is only N * M, not (N + 1) * M, which will cause resource waste when the storage depth is relatively small.

[0004] In view of this, the present application aims to provide a multi-way first-in-first-out buffer solution that can avoid resource waste when the FIFO depth is small.

[0005] It should be understood that the above-listed technical problems are only examples and not limitations to the present invention. The present invention is not limited to the technical solutions that can solve all the above technical problems simultaneously. The technical solutions of the present invention can be implemented to solve one or more of the above or other technical problems. Summary of the Invention

[0006] To solve the above and other problems, the present application provides a first-in-first-out buffer, including: an input processing module, a register bank, an output processing module, and a status generation module; the register bank includes a plurality of registers serving as storage units;

[0007] Wherein, the status generation module communicates with the register bank and is configured to determine status information, and the status information at least includes the number of remaining data that can be received by the register bank;

[0008] The input processing module communicates with the state generation module, and is configured to receive a request for inputting multiplexed data, and determine valid data to be written in the multiplexed data; determine the valid quantity of writable data according to the quantity of the valid data to be written and the quantity of the remaining receivable data, generate an increment of the write pointer based on the valid quantity of the writable data, and send the valid data to be written to the register bank;

[0009] The output processing module communicates with the state generation module, and is configured to receive a request for outputting data, and generate an increment of the read pointer and send it to the register bank;

[0010] The register bank communicates with the input processing module and the output processing module respectively, and is configured to write the valid data to be written into the register according to the write pointer and update the write pointer according to the increment of the write pointer, and / or read data to be output from the register according to the read pointer and update the read pointer according to the increment of the read pointer.

[0011] Optionally, the register bank is configured to determine a start position for writing into the register according to the write pointer, input the valid data to be written from the start position, and the quantity of the input data is the same as the valid quantity of the writable data.

[0012] Optionally, the input processing module is further configured to: input the valid data to be written from the start position in a preset order.

[0013] Optionally, the preset order is to start from the least significant bit or the most significant bit of the valid data to be written, and arrange in ascending or descending order according to the channel number.

[0014] Optionally, the first-in first-out buffer supports synchronization or asynchronization of read and write clocks. In the asynchronous case, cross-clock domain processing is required for read and write clocks, and in the synchronous case, cross-clock domain processing is not required for read and write clocks.

[0015] Optionally, the register bank is a two-dimensional register matrix.

[0016] Optionally, the write pointer is represented in binary, and the width of the write pointer is represented as log2(K)+1 bits, where K is the depth of the register bank, log2(K) bits represent the position of the write data with a depth of K, and an additional 1-bit most significant bit is used to determine whether the write pointer loops back at the boundary K. Whenever the write pointer crosses the boundary of K, the most significant bit of the write pointer is flipped.

[0017] Optionally, the write pointer is updated when the valid quantity of the writable data is greater than zero, and the value increased each time is the valid quantity of the writable data.

[0018] Optionally, the read pointer is represented in binary, and the width of the read pointer is represented as log2(K)+1 bits, where K is the depth of the register file, log2(K) bits represent the position of the read data with a depth of K, and an additional 1-bit highest bit is used to determine whether the read pointer loops back at the boundary K. Whenever the read pointer crosses the boundary of K, the highest bit of the read pointer is flipped.

[0019] Optionally, the read pointer is updated when the number of remaining receivable data is greater than zero and a data output request is received, and the value increased each time is 1.

[0020] Optionally, the status generation module is configured to determine the number of remaining receivable data based on the write pointer, the read pointer, and the depth K of the register file:

[0021] When the highest bits of the write pointer and the read pointer are the same, the number of remaining receivable data is K - (WPTR - RPTR); where WPTR represents the value of the write pointer and RPTR represents the value of the read pointer;

[0022] When the highest bits of the write pointer and the read pointer are different, the number of remaining receivable data is RPTR_LSB - WPTR_LSB; where WPTR_LSB represents the value of WPTR after removing the highest bit, and RPTR_LSB represents the value of RPTR after removing the highest bit.

[0023] Optionally, the status generation module is further configured to convert the binary read pointer and write pointer into Gray code for representation when the first-in-first-out buffer implements asynchronous input, and perform two-stage register synchronization using the Gray code, and convert the synchronized Gray code into binary.

[0024] Optionally, the status generation module is further configured to generate an empty status information, a nearly-empty status information, a nearly-full status information, and a full status information;

[0025] Among them, when the number of received data is 0, the empty status information is generated;

[0026] When the number of received data is less than or equal to a preset nearly-empty threshold, the nearly-empty status information is generated;

[0027] When the number of received data is greater than or equal to a preset nearly-full threshold, the nearly-full status information is generated;

[0028] When the number of received data is equal to the depth of the register file, the full status information is generated.

[0029] The present application also provides a control method for a first-in-first-out buffer, which is applied to any of the above-mentioned first-in-first-out buffers, and the method includes:

[0030] The input processing module receives a request for input multiplexed data;

[0031] The input processing module compares the number of valid data to be written with the number of remaining receivable data determined by the status generation module; if the number of valid data to be written is greater than the number of remaining receivable data, the valid number of writable data is the number of remaining receivable data; if the number of valid data to be written is not greater than the number of remaining receivable data, the valid number of writable data is the number of valid data to be written;

[0032] The input processing module generates an increment of the write pointer based on the valid number of writable data, and sends the valid data to be written to the register bank;

[0033] The register bank writes the valid data to be written into the register according to the write pointer and updates the write pointer according to the increment of the write pointer.

[0034] Optionally, it further includes:

[0035] The output processing module receives a request for output data, generates an increment of the read pointer and sends it to the register bank;

[0036] The register bank reads the data to be output from the register according to the read pointer and updates the read pointer according to the increment of the read pointer.

[0037] The FIFO buffer and its control method provided by this application. The FIFO buffer includes: an input processing module, a register bank, an output processing module, and a status generation module; the register bank includes multiple registers serving as storage units; wherein, the status generation module communicates with the register bank and is configured to determine status information, which at least includes the number of remaining data that can be received by the register bank; the input processing module communicates with the status generation module and is configured to receive a request for input multiplexed data, and determine the valid data to be written in the multiplexed data; determine the valid number of data that can be written according to the number of valid data to be written and the number of remaining data that can be received, generate an increment of the write pointer based on the valid number of data that can be written, and send the valid data to be written to the register bank; the output processing module communicates with the status generation module and is configured to receive a request for output data, generate an increment of the read pointer and send it to the register bank; the register bank communicates with the input processing module and the output processing module respectively, and is configured to write the valid data to be written into the register according to the write pointer and update the write pointer according to the increment of the write pointer, and / or read the data to be output from the register according to the read pointer and update the read pointer according to the increment of the read pointer.

[0038] It can be seen that the solution provided by this application uses a register bank as a storage unit. By controlling the write pointer, the valid data in the input data can be stored in the register bank in sequence. Since the area of a register is smaller than that of a multi-level storage unit using RAM, in the case of a small depth, the FIFO buffering of multi-channel input data can be completed with very little hardware overhead, and it can avoid the problem of resource waste in the existing solution using multi-level storage units when the depth is small. Description of the Drawings

[0039] Hereinafter, this application will be further explained with reference to the drawings based on the embodiments.

[0040] Figure 1 Schematically showing the structural block diagram of a specific embodiment of the FIFO buffer provided by this application;

[0041] Figure 2 Schematically showing the structural diagram of another specific embodiment of the FIFO buffer provided by this application;

[0042] Figure 3 Schematically showing the flowchart of the control method of the FIFO buffer provided by this application;

[0043] Figure 4 Schematically showing the data path diagram of a FIFO buffer with 4-channel input data and a depth of 10. Detailed Embodiments

[0044] The method and apparatus of the present application will be described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the embodiments shown in the drawings and described below are merely illustrative and not limiting to the present application.

[0045] A structural block diagram of a specific embodiment of the first-in, first-out buffer provided by the present application is as Figure 1 shown. The first-in, first-out buffer specifically includes: an input processing module 11, a register bank 12, an output processing module 13, and a status generation module 14; the register bank 12 includes a plurality of registers as storage units.

[0046] Among them, the status generation module 14 communicates with the register bank 12 and is configured to determine status information, where the status information at least includes the number of remaining data that can be received by the register bank.

[0047] The input processing module 11 communicates with the status generation module 14 and is configured to receive a request for input multiplexed data and determine the valid data to be written in the multiplexed data; determine the valid number of data that can be written according to the number of valid data to be written and the number of remaining data that can be received, generate an increment of the write pointer based on the valid number of data that can be written, and send the valid data to be written to the register bank 12.

[0048] The output processing module 13 communicates with the status generation module 14 and is configured to receive a request for output data and generate an increment of the read pointer and send it to the register bank 12.

[0049] The register bank 12 communicates with the input processing module 11 and the output processing module 13 respectively, and is configured to write the valid data to be written into the register according to the write pointer and update the write pointer according to the increment of the write pointer, and / or read the data to be output from the register according to the read pointer and update the read pointer according to the increment of the read pointer.

[0050] The provided first-in, first-out buffer and its control method. The first-in, first-out buffer includes: an input processing module, a register bank, an output processing module, and a status generation module; the register bank includes multiple registers serving as storage units; wherein, the status generation module communicates with the register bank and is configured to determine status information, which at least includes the number of remaining data that can be received by the register bank; the input processing module communicates with the status generation module and is configured to receive a request for input multiplexed data, and determine the valid data to be written in the multiplexed data; determine the valid number of data that can be written according to the number of valid data to be written and the number of remaining data that can be received, generate an increment of the write pointer based on the valid number of data that can be written, and send the valid data to be written to the register bank; the output processing module communicates with the status generation module and is configured to receive a request for output data, generate an increment of the read pointer and send it to the register bank; the register bank communicates with the input processing module and the output processing module respectively, and is configured to write the valid data to be written into the register according to the write pointer and update the write pointer according to the increment of the write pointer, and / or read the data to be output from the register according to the read pointer and update the read pointer according to the increment of the read pointer.

[0051] It can be seen that the solution provided in this application uses a register bank as a storage unit. By controlling the write pointer, the valid data in the input data can be stored in the register bank in sequence. Since the area of a register is smaller than that of a multi-level storage unit using RAM, in the case of a smaller depth, the first-in, first-out of multiplexed input data can be completed with very little hardware overhead, and it can avoid the problem of waste of hardware storage resources in the existing solution using multi-level storage units when the depth is small.

[0052] The structural schematic diagram of another specific implementation manner of the first-in, first-out buffer provided in this application is as Figure 2 shown.

[0053] Among them, the input processing module 11 is configured to receive a request for input multiplexed data. In this embodiment, N-way input data is taken as an example. The input processing module 11 receives a request for input N-way data, and receives the N-way data, and determines the number VALID_REQ_NUM of valid data to be written in the N-way data. Specifically, when the input request signal flag is 1, it indicates that this input request is valid; when the input request signal flag is 0, it indicates that this input signal is invalid. Among the requests for N-way data, the number VALID_REQ_NUM of valid data to be written can be determined by counting the number of input requests with valid flags.

[0054] The input processing module 11 obtains the number of remaining receivable data ENTRY_LEFT in the register bank 12 from the status generation module 14. Further, according to the number of valid data to be written VALID_REQ_NUM and the number of remaining receivable data ENTRY_LEFT in the register bank, the valid number of data that can be written VALID_WNUM can be determined. The specific determination process is as follows: If the number of valid data to be written VALID_REQ_NUM is greater than the number of remaining receivable data ENTRY_LEFT in the register bank, it can be determined that the valid number of data that can be written VALID_WNUM is the number of remaining receivable data ENTRY_LEFT. Otherwise, when the number of valid data to be written VALID_REQ_NUM is not greater than the number of remaining receivable data ENTRY_LEFT in the register bank, the valid number of data that can be written VALID_WNUM is the number of valid data to be written VALID_REQ_NUM.

[0055] The input processing module inputs the valid data to be written starting from the lowest bit or the highest bit of the write data, and inputs the valid data to be written from the starting position in a preset order. The register bank determines the starting position for writing to the register according to the write pointer, and inputs the valid data to be written from the starting position, and the number of input data is the same as the valid number of data that can be written.

[0056] It can be understood that the preset order is the position in the write data to the register bank when there are multiple input data arriving simultaneously, and its arrangement method can be pre-specified. For example, it can be arranged in ascending or descending order according to the channel number. As a preferred implementation manner, the data can be arranged in a preset order and tightly arranged into the write data of the register bank. It can be understood that tight arrangement means that there is no invalid data between every two valid data.

[0057] The input processing module is further configured to generate an increment Δ of the write pointer based on the valid number of data that can be written WPTR , and the write pointer WPTR is updated according to the increment Δ of the write pointer when the valid number of data that can be written VALID_WNUM > 0 WPTR The write pointer WPTR and the increment Δ are updated WPTRAfter removing the highest bit and adding them, if the addition result exceeds the boundary, the highest bit of the write pointer WPTR is flipped. Those skilled in the art can understand that the value increased by the write pointer WPTR each time can be 1. In some embodiments, as needed, the value increased by the write pointer WPTR each time (i.e., the increment of the write pointer) can also be greater than 1. Specifically, the write pointer WPTR is represented in binary, and the width of the write pointer is represented as log2(K)+1 bits, where K is the depth of the register bank, log2(K) bits represent the position of the write data with a depth of K, and an additional 1 bit of the highest bit is used to determine whether the write pointer loops back at the boundary K. Whenever the write pointer crosses the boundary of K, the highest bit of the write pointer is flipped. Taking the depth of the register bank as 8 as an example, the width of the write pointer is represented by a 4-bit binary number of log2(K)+1 bits, and the additional highest bit is used to determine whether the write pointer loops back at the boundary K. The write pointer at the starting position is 0000. When 8 data have been written, the highest bit of the write pointer is flipped, changing from 0 to 1. That is, at this time, the write pointer WPTR is represented as: 1000.

[0058] The register bank 12 communicates with the input processing module 11 and the output processing module 13 respectively, and is configured to write the to-be-written valid data into the register according to the write pointer and update the write pointer according to the increment of the write pointer, and / or read the to-be-output data from the register according to the read pointer and update the read pointer according to the increment of the read pointer.

[0059] As a specific implementation manner, the register bank 12 is configured to determine the starting position for writing into the register according to the write pointer, and input the to-be-written valid data from the starting position, and the number of input data is the same as the valid number of writable data.

[0060] In this embodiment, the register bank 12 is a two-dimensional register matrix. If each of the N input data is M bits, then the width of the register bank is M. When the depth of the register bank is K, the depth K of the register bank and the number of input channels N should satisfy: K>=N, otherwise it is easy to lose data due to the FIFO being full.

[0061] The output processing module 13 is configured to receive a request for output data, generate an increment of the read pointer and send it to the register bank 12. The register bank 12 reads the to-be-output data from the register according to the read pointer and updates the read pointer according to the increment of the read pointer.

[0062] The output processing module 13 generates an increment Δ of the read pointer RPTR , and the read pointer RPTR is updated according to the increment Δ of the read pointer when the number of remaining receivable data ENTRY_LEFT is greater than zero and a data output request is received RPTR , specifically, adding the read pointer RPTR and the increment Δ RPTRAfter removing the highest bit and adding them, if the addition result exceeds the boundary, the highest bit of the read pointer RPTR is flipped. In this embodiment, the value that the read pointer RPTR increases each time is 1. Specifically, the read pointer can be represented in binary, and the width of the read pointer is represented as log2(K)+1 bits, where K is the depth of the register file, log2(K) bits represent the position of the read data with a depth of K, and an additional 1 bit of the highest bit is used to determine whether the read pointer loops back at the boundary K. Whenever the read pointer crosses the boundary of K, the highest bit of the read pointer is flipped. Similarly, taking the depth of the register file as 8 as an example, the width of the read pointer is represented by a 4-bit binary number of log2(K)+1 bits, and the additional highest bit is used to determine whether the read pointer loops back at the boundary K. The read pointer at the starting position is 0000. When 8 data have been read, the highest bit of the read pointer is flipped, changing from 0 to 1. That is, at this time, the read pointer RPTR is represented as: 1000; if 2 data have been read, the highest bit of the read pointer does not flip, and at this time, the read pointer RPTR is represented as: 0010.

[0063] The status generation module 14 is configured to determine the remaining number of data ENTRY_LEFT that can be received and the number of data ENTRY_USED that have been received based on the write pointer, the read pointer, and the depth K of the register file.

[0064] When the highest bits of the write pointer and the read pointer are the same, the remaining number of data ENTRY_LEFT that can be received is K - (WPTR - RPTR); the number of data ENTRY_USED that have been received is WPTR – RPTR. Where WPTR represents the value of the write pointer and RPTR represents the value of the read pointer.

[0065] When the highest bits of the write pointer and the read pointer are different, the remaining number of data ENTRY_LEFT that can be received is RPTR_LSB - WPTR_LSB; the number of data ENTRY_USED that have been received is K - (RPTR_LSB - WPTR_LSB). Where WPTR_LSB represents the value after removing the highest bit of WPTR, and RPTR_LSB represents the value after removing the highest bit of RPTR.

[0066] For example, the depth of the register file K = 8, the read and write pointers are each 4 bits, and the starting data are both 0000. If 8 data are written, the highest bit is flipped and the write pointer is 1000. If 2 data are read, the read pointer is 0010. Then the remaining number of data ENTRY_LEFT that can be received = RPTR_LSB - WPTR_LSB = 010 - 000 (represented in binary) = 2 (represented in decimal).

[0067] The FIFO buffer provided by this application supports multiple simultaneous inputs and single output, and can support synchronous or asynchronous read and write clocks. When asynchronous, the read and write clocks need to handle cross-clock domain, and when synchronous, the read and write clocks do not need to handle cross-clock domain.

[0068] The status generation module 14 is further configured to convert the binary read pointer and write pointer into Gray code for representation when the FIFO buffer implements asynchronous input, and use the Gray code for two-stage register synchronization, and convert the synchronized Gray code into binary to implement cross-clock domain processing of the read and write pointers. When implementing a synchronous FIFO, there is no need for cross-clock domain processing of the read and write pointers.

[0069] The status generation module 14 is further configured to generate empty status information, the about-to-be-empty status information, full status information, and the about-to-be-full status information.

[0070] Among them, when the number of received data ENTRY_USED is 0, the empty status information is generated.

[0071] When the number of received data ENTRY_USED is less than or equal to the preset about-to-be-empty threshold AEMPTY_THRES, the about-to-be-empty status information is generated.

[0072] When the number of received data ENTRY_USED is greater than or equal to the preset about-to-be-full threshold AFULL_THRES, the about-to-be-full status information is generated.

[0073] When the number of received data ENTRY_USED is equal to the depth of the register bank, the full status information is generated.

[0074] In addition, this application also provides a control method for a FIFO buffer, which can be applied to the FIFO buffer described above. Refer to Figure 3 The flowchart of the control method for the FIFO buffer provided by this application, and this method specifically includes:

[0075] S101: The input processing module receives a request for inputting multiple-channel data.

[0076] S102: The input processing module compares the number of valid data to be written VALID_REQ_NUM with the number of remaining receivable data determined by the status generation module ENTRY_LEFT; if the number of valid data to be written VALID_REQ_NUM is greater than the number of remaining receivable data ENTRY_LEFT, the valid number of writable data VALID_WNUM is the number of remaining receivable data ENTRY_LEFT; if the number of valid data to be written VALID_REQ_NUM is not greater than the number of remaining receivable data ENTRY_LEFT, the valid number of writable data VALID_WNUM is the number of valid data to be written VALID_REQ_NUM.

[0077] S103: The input processing module generates an increment of the write pointer based on the valid number of writable data, and sends the valid data to be written to the register bank.

[0078] S104: The register bank writes the valid data to be written into the register according to the write pointer and updates the write pointer according to the increment of the write pointer.

[0079] The register bank obtains the position of the updated register according to the write pointer, and judges how many registers to update backward from the position starting from the write pointer according to the valid number of writable data VALID_WNUM.

[0080] Based on the above embodiments, the method provided by this application may further include: The output processing module receives a request for output data, generates an increment of the read pointer and sends it to the register bank; the register bank reads the data to be output from the register according to the read pointer and updates the read pointer according to the increment of the read pointer.

[0081] The output processing module generates an increment of the read pointer according to the request for output data. The register bank feeds back the value of the register at the corresponding position to the output processing module according to the read pointer as the data to be output.

[0082] In this process, the status generation module 14 is used to generate status information, provide information for the first-in-first-out buffer, and perform control.

[0083] Figure 4 Shows a data path diagram of a 4-way input data, 10-depth first-in-first-out buffer. As Figure 4 shown, the specific working process of this first-in-first-out buffer will be introduced below with reference to the accompanying drawings.

[0084] In this embodiment, sorting is performed in the order of increasing input channel number, and the input channel with a smaller number is ranked at the lowest position. Correspondingly, its position in the register bank will be closest to the exit, so it will be output first.

[0085] For simplicity of explanation, when only considering the case where data only goes in and not out:

[0086] In the first clock cycle, there is valid data on the second, third, and fourth paths. VALID_REQ_NUM is 3. At this time, there is no data in the register file, so ENTRY_LEFT is 10. Since ENTRY_LEFT > VALID_REQ_NUM, VALID_WNUM = VALID_REQ_NUM = 3. All the valid data to be written is written into the register file, and the write pointer is incremented by 3.

[0087] In the second clock cycle, there is valid data on the first and third paths. VALID_REQ_NUM is 2. At this time, there are already 3 data in the register file, so ENTRY_LEFT is 10 - 3 = 7. Since ENTRY_LEFT > VALID_REQ_NUM, VALID_WNUM = VALID_REQ_NUM = 2. All the valid data to be written is written into the register file, and the write pointer is incremented by 2.

[0088] In the third clock cycle, there is valid data on the first, second, and fourth paths. VALID_REQ_NUM is 3. At this time, there are already 5 data in the register file, so ENTRY_LEFT is 10 - 5 = 5. Since ENTRY_LEFT > VALID_REQ_NUM, VALID_WNUM = VALID_REQ_NUM = 3. All the valid data to be written is written into the register file, and the write pointer is incremented by 3.

[0089] In the fourth clock cycle, there is valid data on the first, second, and fourth paths. VALID_REQ_NUM is 3. At this time, there are already 8 data in the register file, so ENTRY_LEFT is 10 - 8 = 2. Since ENTRY_LEFT < VALID_REQ_NUM, VALID_WNUM = ENTRY_LEFT = 2. Only the input data on the first and second paths is written into the register file, and the data on the fourth path is lost. The write pointer is incremented by 2.

[0090] In the fifth clock cycle, since there is only input and no output, the FIFO is full at this time, ENTRY_LEFT = 0. All the data to be written that comes in will be lost.

[0091] When considering the case with output:

[0092] If there is exactly an output request in the above-mentioned fourth cycle, the write pointer is incremented by 1, and at the same time ENTRY_LEFT is also incremented by 1. At this time, ENTRY_LEFT = VALID_REQ_NUM = 3, and the three-way valid input data will all be written into the register file, and at the same time the write pointer is incremented by 3.

[0093] In the fifth cycle, ENTRY_LEFT is still 0, the FIFO is full, and if there is no output request, all inputs will be discarded.

[0094] The control method of the first-in first-out buffer provided in this application corresponds to the first-in first-out buffer described above. The specific implementation content can be referred to each other and will not be elaborated here.

[0095] Although various embodiments of aspects of this application have been described for the purposes of this disclosure, the teachings of this disclosure should not be construed as being limited to these embodiments. The features disclosed in a particular embodiment are not limited to that embodiment, but can be combined with the features disclosed in different embodiments. For example, one or more features and / or operations of the method according to this application described in one embodiment can also be applied alone, in combination, or as a whole in another embodiment. Those skilled in the art should understand that there are also possible more alternative embodiments and variations, and various changes and modifications can be made to the above system without departing from the scope defined by the claims of this application.

Claims

1. A multi-input first-in first-out buffer, characterized in that, it includes: an input processing module, a register bank, an output processing module, and a status generation module; the register bank includes a plurality of registers as storage units; wherein, the status generation module communicates with the register bank and is configured to determine status information, and the status information at least includes the number of remaining data that can be received by the register bank; the input processing module communicates with the status generation module, and is configured to receive a request for input multiplexed data, and determine the valid data to be written in the multiplexed data; determine the valid number of writable data according to the number of valid data to be written and the number of remaining data that can be received, generate an increment of the write pointer based on the valid number of writable data, and send the valid data to be written to the register bank; the output processing module communicates with the status generation module, and is configured to receive a request for output data, generate an increment of the read pointer and send it to the register bank; the register bank communicates with the input processing module and the output processing module respectively, and is configured to write the valid data to be written into the register according to the write pointer and update the write pointer according to the increment of the write pointer, and / or read the data to be output from the register according to the read pointer and update the read pointer according to the increment of the read pointer.

2. The multi-input first-in first-out buffer according to claim 1, characterized in that, the register bank is configured to determine the start position of writing into the register according to the write pointer, input the valid data to be written from the start position, and the number of input data is the same as the valid number of writable data.

3. The multi-input first-in first-out buffer according to claim 2, characterized in that, the input processing module is further configured to: input the valid data to be written from the start position in a preset order.

4. The multi-input first-in first-out buffer according to claim 3, characterized in that, the preset order is to start from the lowest bit or the highest bit of the valid data to be written, and arrange in ascending or descending order according to the channel number.

5. The multi-input first-in first-out buffer according to claim 1, characterized in that, the multi-input first-in first-out buffer supports synchronization or asynchronization of read and write clocks. When asynchronous, the read and write clocks need to be processed across clock domains, and when synchronous, the read and write clocks do not need to be processed across clock domains.

6. The multi-input first-in first-out buffer according to claim 1, characterized in that, the register bank is a two-dimensional register matrix.

7. The multi-input first-in first-out buffer according to claim 6, characterized in that, the write pointer is represented in binary, and the width of the write pointer is represented as log2(K)+1 bits, where K is the depth of the register bank, log2(K) bits represent the position of the write data with a depth of K, and an additional 1-bit highest bit is used to determine whether the write pointer loops back at the boundary K. Whenever the write pointer crosses the boundary of K, the highest bit of the write pointer is flipped.

8. The multi-input first-in first-out buffer according to claim 7, characterized in that, The write pointer is updated when the effective number of writable data is greater than zero, and the value increased each time is the effective number of writable data.

9. The multi-input first-in first-out buffer according to claim 8, wherein, the read pointer is represented in binary, and the width of the read pointer is represented as log2(K)+1 bits, where K is the depth of the register file, log2(K) bits represent the position of the read data with a depth of K, and an additional 1-bit highest bit is used to determine whether the read pointer loops back at the boundary K. Whenever the read pointer crosses the boundary of K, the highest bit of the read pointer is flipped.

10. The multi-input first-in first-out buffer according to claim 9, wherein, the read pointer is updated when the remaining number of data that can be received is greater than zero and a data output request is received, and the value increased each time is 1.

11. The multi-input first-in first-out buffer according to claim 10, wherein, the status generation module is configured to determine the remaining number of data that can be received based on the write pointer, the read pointer, and the depth K of the register file: when the highest bits of the write pointer and the read pointer are the same, the remaining number of data that can be received is K - (WPTR - RPTR); where WPTR represents the value of the write pointer and RPTR represents the value of the read pointer; when the highest bits of the write pointer and the read pointer are different, the remaining number of data that can be received is RPTR_LSB - WPTR_LSB; where WPTR_LSB represents the value after removing the highest bit of WPTR, and RPTR_LSB represents the value after removing the highest bit of RPTR.

12. The multi-input first-in first-out buffer according to any one of claims 7 to 11, wherein, the status generation module is further configured to, when the multi-input first-in first-out buffer implements asynchronous input, convert the binary read pointer and write pointer into Gray code for representation, and use the Gray code for two-stage register synchronization, and convert the synchronized Gray code into binary.

13. The multi-input first-in first-out buffer according to any one of claims 1 to 11, wherein, the status generation module is further configured to generate an empty status information, a nearly-empty status information, a nearly-full status information, and a full status information; wherein, the empty status information is generated when the number of received data is 0; the nearly-empty status information is generated when the number of received data is less than or equal to a preset nearly-empty threshold; the nearly-full status information is generated when the number of received data is greater than or equal to a preset nearly-full threshold; the full status information is generated when the number of received data is equal to the depth of the register file.

14. A control method for a multi-input first-in first-out buffer, wherein, applied to the multi-input first-in first-out buffer according to any one of claims 1 to 13, the method includes: an input processing module receives a request for input multiplexed data; The input processing module compares the number of valid data to be written with the number of remaining receivable data determined by the status generation module; if the number of valid data to be written is greater than the number of remaining receivable data, the valid number of writable data is the number of remaining receivable data; if the number of valid data to be written is not greater than the number of remaining receivable data, the valid number of writable data is the number of valid data to be written; The input processing module generates an increment of the write pointer based on the valid number of writable data, and sends the valid data to be written to the register bank; The register bank writes the valid data to be written into the register according to the write pointer.

15. The control method of the multi-input first-in first-out buffer according to claim 14, characterized in that, further comprising: The output processing module receives a request for output data, generates an increment of the read pointer and sends it to the register bank; The register bank reads the data to be output from the register according to the read pointer and updates the read pointer according to the increment of the read pointer.

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