Instruction retirement unit, instruction execution unit, and related apparatus and methods

Abstract

Embodiments of the present application provide an instruction retirement unit, an instruction execution unit, and related devices and methods. The present solution is applicable to various chips including CISC instruction set, RISC reduced instruction set (especially RISC-V instruction set), or VLIM instruction set architecture, such as Internet of Things chips, audio / video chips, etc. The instruction retirement unit includes a receiving subunit configured to receive a completion request signal; an arbitration subunit configured to, after determining that a to-be-completed instruction can be completed, send a completion permission signal to an instruction execution unit, and store instruction completion information of the to-be-completed instruction into an instruction buffer table item in a buffer; and a retirement subunit configured to, according to the instruction completion information stored in each instruction buffer table item, perform retirement processing on a to-be-retired instruction which has been completed but not retired, and delete the instruction completion information of the retired instruction from the instruction buffer table item. The present solution can reduce the hardware resource consumption of the processing unit for the instruction reordering part.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the chip technical field, and in particular, to an instruction retirement unit, an instruction execution unit, and related apparatus and method. BACKGROUND

[0002] In a processing unit of an out-of-order execution architecture, an execution order of instructions is rearranged by using a dynamic scheduling technique, which can reduce stalls while maintaining data flow, thereby improving performance of the processing unit. By using the dynamic scheduling technique, a correlation problem that cannot be predicted at compile time can be solved without performing targeted optimization on the processing unit architecture by software, and the processing unit can still not produce a bubble when encountering a large delay. After the execution order of instructions is rearranged by using the dynamic scheduling technique, the execution order of the instructions needs to be restored after the instructions are executed, so that the instructions are submitted in order and the correctness of the overall execution behavior is ensured.

[0003] Currently, for a processing unit of an out-of-order execution architecture, a re-order buffer (ROB) is used to temporarily store execution results of instructions, and the instructions are submitted in the original order.

[0004] However, when the re-order buffer is used to temporarily store the execution results of the instructions and restore the execution order, for one instruction, the instruction occupies an instruction buffer entry in the re-order buffer from the start of the instruction distribution to the retirement of the instruction, and therefore each instruction being executed in the processing unit needs to be allocated an instruction buffer entry. The number of instruction buffer entries is equal to the out-of-order degree allowed by the processing unit, and the processing unit needs to consume a large amount of resources to maintain the re-order buffer, thereby causing a large consumption of hardware resources for the instruction reordering part when the processing unit performs out-of-order processing. SUMMARY

[0005] Therefore, embodiments of the present application provide an instruction retirement unit, an instruction execution unit, and related apparatus and method to at least solve or alleviate the above problems.

[0006] According to a first aspect of the embodiments of the present application, an instruction retirement unit is provided, comprising: a receiving subunit configured to receive a completion request signal sent by an instruction execution unit for a to-be-completed instruction, wherein the completion request signal is used to request completion of the to-be-completed instruction; an arbitration subunit configured to send an allowed completion signal for the to-be-completed instruction to the instruction execution unit after determining that the to-be-completed instruction can be completed according to a new-old relationship between a retired instruction and the to-be-completed instruction, and receive instruction completion information of the to-be-completed instruction sent by the instruction execution unit, and store the instruction completion information of the to-be-completed instruction into an instruction buffer table item in a buffer area, wherein the number of instruction buffer table items in the buffer area is greater than 1 and less than an out-of-order degree allowed by a processing unit, and each instruction buffer table item can store instruction completion information of one instruction; a retirement subunit configured to retire a to-be-retired instruction that has been completed but not retired according to the instruction completion information stored in each instruction buffer table item, and delete instruction completion information of a retired instruction from the instruction buffer table item.

[0007] According to a second aspect of the embodiments of the present application, an instruction execution unit is provided, comprising: a requesting subunit configured to send a completion request signal to an instruction retirement unit, wherein the completion request signal is used to request completion of a to-be-completed instruction; a sending subunit configured to send instruction completion information of the to-be-completed instruction to the instruction retirement unit after receiving an allowed completion signal sent by the instruction retirement unit, store the instruction completion information into an instruction buffer table item in a buffer area by the instruction retirement unit, retire a to-be-retired instruction that has been completed but not retired according to the instruction completion information stored in each instruction buffer table item, and delete instruction completion information of a retired instruction from the instruction buffer table item, wherein the number of instruction buffer table items in the buffer area is greater than 1 and less than an out-of-order degree allowed by a processing unit, and each instruction buffer table item can store instruction completion information of one instruction.

[0008] According to a third aspect of the embodiments of the present application, a processing unit is provided, comprising: the instruction retirement unit of the first aspect described above; and at least one instruction execution unit of the second aspect described above.

[0009] According to a fourth aspect of the embodiments of the present application, a computing device is provided, comprising: the processing unit of the third aspect described above; and a memory coupled to the processing unit and configured to store instructions to be executed.

[0010] According to a fifth aspect of the embodiments of the present application, an instruction processing method is provided, which is applied to an instruction retirement unit. The instruction processing method comprises: receiving a completion request signal sent by an instruction execution unit for a to-be-completed instruction, wherein the completion request signal is used to request completion of the to-be-completed instruction; after determining that the to-be-completed instruction can be completed according to a new-old relationship between a retired instruction and the to-be-completed instruction, sending an allowed completion signal for the to-be-completed instruction to the instruction execution unit, receiving instruction completion information of the to-be-completed instruction sent by the instruction execution unit, and storing the instruction completion information of the to-be-completed instruction into an instruction buffer table item in a buffer area, wherein the number of instruction buffer table items in the buffer area is greater than 1 and less than an out-of-order degree allowed by a processing unit, and each instruction buffer table item can store instruction completion information of one instruction; and according to the instruction completion information stored in each instruction buffer table item, performing retirement processing on a to-be-retired instruction which has been completed and not retired, and deleting instruction completion information of a retired instruction from the instruction buffer table item.

[0011] According to a sixth aspect of the embodiments of the present application, an instruction processing method is provided, which is applied to an instruction execution unit. The instruction processing method comprises: sending a completion request signal to an instruction retirement unit, wherein the completion request signal is used to request completion of a to-be-completed instruction; after receiving an allowed completion signal sent by the instruction retirement unit, sending instruction completion information of the to-be-completed instruction to the instruction retirement unit, storing the instruction completion information into an instruction buffer table item in a buffer area by the instruction retirement unit, and according to the instruction completion information stored in each instruction buffer table item, performing retirement processing on a to-be-retired instruction which has been completed and not retired, and deleting instruction completion information of a retired instruction from the instruction buffer table item, wherein the number of instruction buffer table items in the buffer area is greater than 1 and less than an out-of-order degree allowed by a processing unit, and each instruction buffer table item can store instruction completion information of one instruction.

[0012] According to the instruction execution order recovery scheme provided by the embodiments of the present application, the number of instruction buffer table items in the buffer area is less than the out-of-order degree of the processing unit, the instruction is completed in order, the instruction completion information of the completed instruction is stored into the instruction buffer table item, the to-be-retired instruction is processed according to the instruction completion information in the instruction buffer table item, and the instruction completion information of the retired instruction is deleted from the instruction buffer table item. Since the instruction completion information of the instruction which has been completed and not retired or is being retired is stored in the instruction buffer table item, the instruction only occupies the instruction buffer table item in the completion and retirement stages, and therefore the buffer area only needs to include a small number of instruction buffer table items to meet the out-of-order execution of the processing unit, and maintaining a small number of instruction buffer table items can reduce the hardware resource consumption of the instruction reordering part when the processing unit performs out-of-order processing. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art based on these drawings.

[0014] Figure 1 is a schematic diagram of a computing device to which an embodiment of the present application is applied;

[0015] Figure 2 is a schematic diagram of a processing unit of an embodiment of the present application;

[0016] Figure 3 is a schematic diagram of an instruction execution stage of an embodiment of the present application;

[0017] Figure 4 is a schematic diagram of an instruction retirement unit of an embodiment of the present application;

[0018] Figure 5 is a schematic diagram of an acceptable complete instruction of an embodiment of the present application;

[0019] Figure 6 is a schematic diagram of an instruction retirement unit of another embodiment of the present application;

[0020] Figure 7 is a schematic diagram of a current submittable instruction of an embodiment of the present application;

[0021] Figure 8 is a schematic diagram of an instruction execution unit of an embodiment of the present application;

[0022] Figure 9 is a schematic diagram of an instruction execution unit of another embodiment of the present application;

[0023] Figure 10 is a schematic diagram of an instruction execution unit of yet another embodiment of the present application;

[0024] Figure 11 is a flowchart of an instruction processing method of an embodiment of the present application;

[0025] Figure 12 is a flowchart of an instruction processing method of another embodiment of the present application. DETAILED DESCRIPTION

[0026] The present application is described in detail below based on examples, but the present application is not limited to these examples. In the following detailed description of the present application, some specific details are described in detail. The present application can also be fully understood without the description of these details. In order to avoid confusion of the essence of the present application, the well-known methods, processes and procedures are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0027] First, some of the nouns or terms appearing in the description of the embodiments of the present application are applicable to the following explanations.

[0028] Speculative execution: Speculative execution is a kind of optimization technology. The processor using speculative execution technology can predict the program flow and branch direction according to the existing information, and execute the subsequent instructions in the program flow in advance using the idle time according to the prediction result. The instructions executed in advance may or may not be used subsequently.

[0029] Correct path: The path that the program flow will execute when a speculation failure occurs. The speculative instructions located on the correct path need to produce execution effects. The speculative instructions located on the correct path are older than the speculation failure instruction that causes the speculation failure.

[0030] Error path: The path that the program flow will not execute when a speculation failure occurs. The speculative instructions located on the error path do not need to produce execution effects. The speculative instructions located on the error path are newer than the speculation failure instruction that causes the speculation failure.

[0031] Speculation failure instruction: The speculative instruction that causes the speculation failure. The speculative instruction that is newer than the speculation failure instruction does not need to complete the execution effect, and the speculative instruction that is older than the speculation failure instruction needs to complete the execution effect.

[0032] Pipeline flush: The behavior of the processor to clear the speculative instructions located on the error path in the internal pipeline when a speculation failure occurs.

[0033] Dynamic scheduling: Re-arranging the execution order of instructions to reduce the stall of processing units while maintaining data flow.

[0034] Out-of-order execution: The processing unit dynamically schedules the instruction stream so that a instruction can start executing as soon as its operands and instruction execution unit are available, without waiting for the previous instructions to be executed.

[0035] Dispatch: In the processing unit of the out-of-order execution architecture, the process of making the instruction enter the out-of-order state from the in-order state, which is usually implemented by the instruction issue unit in the processing unit. In general implementation, instruction decoding, dispatching and issuing can be implemented by the instruction decoding unit.

[0036] Issuance: The process of sending instructions to the instruction execution unit to begin the execution of the instructions, which is usually implemented by the instruction issuing unit in the processing unit.

[0037] Commit: Indicates that an instruction is allowed to modify the processor state to produce an execution effect visible in the programming model, typically implemented by the instruction execution unit within the processing unit.

[0038] Write-back: The instruction execution unit performs processor state modifications visible to the programming model, including register values, which is usually implemented by the instruction retirement unit in the processing unit.

[0039] Completion: The instruction execution unit returns the execution result (instruction completion information) excluding the destination register value. Instruction completion means that the instruction execution unit determines that the instruction can be executed. Instruction completion is achieved by the instruction retirement unit in the processing unit.

[0040] Retirement: The execution of instructions by the processing unit is completed, which is usually achieved by the instruction retirement unit in the processing unit.

[0041] Computing device

[0042] Figure 1 A schematic block diagram of a computing device 10 is shown. The computing device 10 can be built based on various types of processing units and driven by any operating system such as Windows, UNIX, or Linux. Furthermore, the computing device 10 can be implemented in hardware and / or software such as PCs, desktops, laptops, servers, and mobile communication devices.

[0043] like Figure 1 As shown, the computing device 10 may include one or more processing units 12 and a memory 14. The memory 14 in the computing device 10 may serve as main memory (or simply main memory or RAM) for storing instruction information and / or data information represented by data signals. For example, the memory 14 may store data provided by the processing unit 12 (e.g., budget results) and may also be used to realize data exchange between the processing unit 12 and the external storage device 16 (or auxiliary memory or external memory).

[0044] In some cases, processing unit 12 needs to access memory 14 through bus 11 to fetch data in memory 14 or to modify data in memory 14. Since memory 14 has a slower access speed, to alleviate the speed gap between processing unit 12 and memory 14, computing device 10 further includes a cache memory 18 communicatively connected with bus 11, which is configured to cache some program data or packet data in memory 14 that can be repeatedly invoked. Cache memory 18 can be implemented by a type of storage device such as static random access memory (SRAM). Cache memory 18 can be a multi-level structure, for example, a three-level cache structure with a level one cache (L1 cache), a level two cache (L2 cache), and a level three cache (L3 cache), or a cache structure with more than three levels or other types of cache structures. In some embodiments, a portion of cache memory 18 (e.g., the L1 cache, or both the L1 cache and the L2 cache) can be integrated inside processing unit 12 or integrated in the same system on chip as processing unit 12.

[0045] Based on this, processing unit 12 can include an instruction execution unit 121 and a memory management unit 122, etc. Instruction execution unit 121 initiates a write access request when executing some instructions that need to modify memory, the write access request specifies write data to be written into memory and a corresponding physical address. Memory management unit 122 is configured to translate the virtual address specified by these instructions into the physical address mapped by the virtual address, and the physical address specified by the write access request can be consistent with the physical address specified by the corresponding instructions.

[0046] The information interaction between memory 14 and cache memory 18 can be organized in data blocks. In some embodiments, cache memory 18 and memory 14 can be divided into data blocks according to the same spatial size, and the data blocks can be the smallest unit (including one or more data of a preset length) of data exchange between cache memory 18 and memory 14. For the sake of brevity and clarity of expression, each data block in cache memory 18 will be referred to as a cache block (or can be referred to as a cacheline or cache line) below, and different cache blocks have different cache block addresses. Each data block in memory 14 will be referred to as a memory block, and different memory blocks have different memory block addresses. The cache block address and / or the memory block address can include a physical address tag for locating the data block.

[0047] Due to the limitation of space and resources, the cache memory 18 cannot cache all the contents in the memory 14, i.e., the storage capacity of the cache memory 18 is usually less than that of the memory 14, and the cache memory 18 cannot provide all the memory block addresses provided by the memory 14. When the processing unit 12 needs to access the memory, it first accesses the cache memory 18 through the bus 11 to determine whether the contents to be accessed have been stored in the cache memory 18. If the contents to be accessed have been stored in the cache memory 18, the cache memory 18 hits, and the processing unit 12 directly calls the contents to be accessed from the cache memory 18. If the contents to be accessed have not been stored in the cache memory 18, the cache memory 18 and the processing unit 12 need to access the memory 14 through the bus 11 to find the corresponding information in the memory 14. Since the access rate of the cache memory 18 is very fast, the efficiency of the processing unit 12 can be significantly improved when the cache memory 18 hits, and thus the performance and efficiency of the entire computing device 10 are improved.

[0048] In addition, the computing device 10 can further include a storage device 16, a display device, an audio device, a mouse / keyboard, and the like input / output devices. The storage device 16 can be a hard disk, an optical disk, a flash memory, and the like device for information access coupled with the bus 11 through a corresponding interface. The display device can be coupled with the bus 11 through a corresponding display card, and is used for display according to the display signal provided by the bus 11.

[0049] The computing device 10 can further include a communication device 17, and thus the computing device 10 can communicate with a network or other devices in various ways. The communication device 17 can include one or more communication modules, and the communication device 17 can include a wireless communication module suitable for a specific wireless communication protocol. For example, the communication device 17 can include a WLAN module for implementing WiFi communication conforming to the 802.11 standard formulated by the Institute of Electrical and Electronics Engineers (IEEE). The communication device 17 can include a WWAN module for implementing wireless wide area communication conforming to a cellular or other wireless wide area protocol. The communication device 17 can further include a Bluetooth module or other communication module using other protocols, or other custom type communication module. The communication device 17 can also be a port for serial transmission of data.

[0050] It should be noted that the structure of the computing device 10 can vary according to the mainboard, operating system, and instruction set architecture of the computing device 10. For example, many current computing devices are provided with an input / output control center connected between the bus 11 and the various input / output devices, and the input / output control center can be integrated into the processing unit 12 or independent of the processing unit 12.

[0051] Processing unit

[0052] Figure 2 This is a schematic block diagram of a processing unit 12 according to one embodiment of this application. Figure 2 As shown, each processing unit 12 may include one or more processor cores 120 for processing instructions. The processing and execution of instructions can be controlled by a user (e.g., through an application program) and / or the system platform. Each processor core 120 can be used to process a specific instruction set, which can support Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or Very Long Instruction Word (VLIW) based computation. Specifically, processor core 120 is suitable for processing the RISC-V instruction set. Different processor cores 120 can each process different or the same instruction sets. Processor core 120 may also include other processing modules, such as a Digital Signal Processor (DSP). As an example, Figure 2 The diagram shows processor cores 1 through m, where m is a positive integer.

[0053] Figure 1 The cache memory 18 shown can be wholly or partially integrated into the processing unit 12. Depending on the architecture, the cache memory 18 can be a single or multi-level internal cache memory located within and / or outside each processor core 120 (e.g., ...). Figure 2 The three-level cache memory L1 to L3 are shown. Figure 2 The cache memory (referred to as 18 in the original text) may include instruction-oriented cache and instruction cache, as well as data cache. The components in processing unit 12 may share at least a portion of the cache memory; for example, processor cores 1 to m may share the third-level cache L3. Processing unit 12 may also include an external cache (not shown), and other cache structures may also serve as external caches for processing unit 12.

[0054] like Figure 2As shown, the processing unit 12 can include a register file 126, which can include a plurality of registers for storing different types of data and / or instructions, which can be of different types, such as integer registers, floating point registers, status registers, instruction registers, and pointer registers, etc. The registers in the register file 126 can be implemented as general purpose registers or can be designed according to the actual needs of the processing unit 12.

[0055] The processing unit 12 can include a memory management unit (MMU) 122 for implementing translation of virtual addresses to physical addresses. The memory management unit 122 caches a portion of the entries of a page table, and can retrieve entries not cached in the memory management unit 122 from the memory. One or more memory management units 122 can be provided in each processor core 120, and the memory management units 122 in different processor cores 120 can be synchronized with the memory management units 122 in other processing units or processor cores, so that each processing unit or processor core can share a unified virtual memory system.

[0056] The processing unit 12 is configured to execute a sequence of instructions (i.e., a program). The process of executing each instruction by the processing unit 12 includes the steps of fetching the instruction from a memory storing the instructions, decoding the fetched instruction, executing the decoded instruction, and saving the result of the instruction execution, and so on, until all instructions in the instruction sequence are executed or a halt instruction is encountered.

[0057] To implement the above process, the processing unit 12 can include an instruction fetch unit 124, an instruction decode unit 125, an instruction issue unit (not shown), an instruction execution unit 121, and a retirement unit 123, etc.

[0058] The instruction fetch unit 124 serves as the initiation engine of the processing unit 12, and is configured to fetch instructions from the memory 14 to an instruction register (which can be a register in the register file 126 shown) and to receive the next fetch address or to calculate the next fetch address according to a fetch algorithm, which can be an incrementing address or a decrementing address according to the length of the instruction. Figure 2

[0059] After the instruction is fetched, the processing unit 12 enters the instruction decode stage, and the instruction decode unit 125 decodes the fetched instruction according to a predetermined instruction format to obtain the operand fetch information required by the fetched instruction, so as to prepare for the operation of the instruction execution unit 121. The operand fetch information can include immediate numbers, registers, or other software / hardware capable of providing source operands.

[0060] ​An instruction issue unit is usually present in a high performance processing unit 12 between the instruction decode unit 125 and the instruction execution units 121 for scheduling and control of instructions to be dispatched to the different instruction execution units 121 for efficient execution of the instructions in parallel. After an instruction is fetched, decoded and dispatched to a corresponding instruction execution unit 121, the corresponding instruction execution unit 121 starts to execute the instruction, i.e. performs the operation indicated by the instruction, i.e. the corresponding function.

[0061] A retirement unit 123 (also referred to as an instruction retirement unit or an instruction write back unit) is mainly used to write back the execution result generated by the instruction execution units 121 to a corresponding storage location (e.g. a register within the processing unit 12) so that the execution result can be quickly obtained by a subsequent instruction from the storage location.

[0062] Different instruction execution units 121 can be provided in the processing unit 12 for different categories of instructions. The instruction execution units 121 can be arithmetic units (e.g. including an arithmetic logic unit, an integer processing unit, a vector arithmetic unit, etc. for performing operations on operands and outputting the operation result), memory execution units (e.g. for accessing the memory 14 to read data from the memory 14 or write data to the memory 14, etc.), coprocessors, etc. In the processing unit 12, the different instruction execution units 121 can operate in parallel and output the corresponding execution results.

[0063] When an instruction execution unit 121 executes an instruction of a certain category (e.g. a memory access instruction), the instruction execution unit 121 needs to access the memory 14 to obtain information stored in the memory 14 or provide data to be written into the memory 14. It is noted that the instruction execution unit 121 for executing a memory access instruction can also be referred to as a memory execution unit, which can be a load store unit (LSU) and / or other units for memory access.

[0064] After a memory access instruction is fetched by the instruction fetch unit 124, the instruction decode unit 125 can decode the memory access instruction so that the source operand of the memory access instruction can be obtained. The decoded memory access instruction is provided to a corresponding instruction execution unit 121, which can perform a corresponding operation (e.g. an operation on the source operand stored in a register by an arithmetic logic unit) on the source operand of the memory access instruction to obtain address information corresponding to the memory access instruction, and initiate a corresponding request (e.g. an address translation request, a write access request, etc.) according to the address information.

[0065] The source operand of a memory access instruction usually includes an address operand, which is operated by the instruction execution unit 121 to obtain a virtual address or a physical address corresponding to the memory access instruction. When the memory management unit 122 is disabled, the instruction execution unit 121 can directly obtain the physical address of the memory access instruction through logical operation. When the memory management unit 121 is enabled, the corresponding instruction execution unit 121 initiates an address translation request according to the virtual address corresponding to the memory access instruction, the address translation request including the virtual address corresponding to the address operand of the memory access instruction; the memory management unit 122 responds to the address translation request and converts the virtual address in the address translation request into a physical address according to the table item matched with the virtual address, so that the instruction execution unit 121 can access the cache 18 and / or the memory 14 according to the translated physical address.

[0066] According to different functions, the memory access instruction can include a load instruction and a store instruction. The execution process of the load instruction usually does not need to modify the information in the memory 14 or the cache 18, and the instruction execution unit 121 only needs to read the data stored in the memory 14, the cache 18 or an external storage device according to the address operand of the load instruction. Unlike the load instruction, the source operand of the store instruction includes not only the address operand but also the data information, and the execution process of the store instruction usually needs to modify the information in the memory 14 and / or the cache 18. The data information of the store instruction can point to write data, which can come from the execution result of an operation instruction, a load instruction or the like, or can come from the data provided by a register or other storage unit in the processing unit 12, or can come from an immediate number.

[0067] The processing unit 12 can implement a micro-out-of-order mechanism. When the instructions are out-of-order emitted, only the table items in the reordering buffer are occupied in the completion and retirement stages of the instructions, and the table items in the reordering buffer do not need to be occupied in the entire execution life cycle of the instructions, so that a complete reordering buffer does not need to be maintained, thereby reducing the resources consumed for maintaining the reordering buffer and reducing the resource consumption of the processing unit 12. In addition, since the instructions only occupy the table items in the reordering buffer in the completion and retirement stages, the number of table items in the reordering buffer can be reduced, a smaller reordering buffer can meet the demand, and the reduction of the reordering buffer can reduce the cost of the processing unit 12.

[0068] For the processing unit 12 of the out-of-order execution architecture, the processing unit 12 can further include an instruction dispatch unit, which can convert instructions from an in-order state to an out-of-order state, and assign an instruction identification (instruction ID) to the instructions, so that the instruction execution unit 121 and the instruction retirement unit 123 can determine the new-old relationship of the instructions according to the instruction identification. After the instruction dispatch unit converts the instructions to the out-of-order state, the instruction issue unit can issue the out-of-order instructions to the instruction execution unit 121, and then the instruction execution unit 121 executes the instructions out of order.

[0069] The embodiments of the present application mainly focus on the instruction completion and retirement process of the instruction retirement unit 123, and the instruction submission process of the instruction execution unit 121, which will be described in detail below.

[0070] Instruction retirement unit

[0071] Dynamic scheduling can rearrange the execution order of functions to reduce the pause in the execution process of the instruction sequence, thereby improving the performance of the processing unit. However, after the instructions are executed out of order, the execution order of the instructions needs to be restored to submit the executed instructions in order, so as to ensure the correctness of the overall execution behavior.

[0072] At present, the instruction retirement unit 123 maintains a reorder buffer, which temporarily stores the execution results of the instructions and restores the execution order of the instructions. As shown in Figure 3 For the processing unit 12 of the out-of-order execution architecture, the execution life cycle of each instruction needs to go through multiple stages such as dispatch, issue, execution, completion, submission, write-back, and retirement. The instruction occupies an instruction buffer entry in the reorder buffer from the beginning of the dispatch to the retirement, that is, the instruction buffer entry in the reorder buffer needs to be occupied during the entire execution life cycle of the instruction. Therefore, the number of instruction buffer entries is equal to the out-of-order degree allowed by the processing unit 12. Since the reorder buffer includes a large number of instruction buffer entries, the instruction retirement unit 123 needs to consume a large amount of resources to maintain the reorder buffer, which causes a large resource consumption of the processing unit 12.

[0073] The embodiments of the present application are generated to solve the problem that a large amount of resources are consumed to maintain the reorder buffer, which are mainly implemented by the instruction execution unit 121 and the instruction retirement unit 123. The internal structure of the instruction retirement unit 123 and the implementation process of the embodiments of the present application will be discussed in detail below.

[0074] Figure 4 is a schematic diagram of the internal structure of the instruction retirement unit according to an embodiment of the present application. As shown in Figure 4As shown, the instruction retirement unit 123 includes a receiving subunit 1231, an arbitration subunit 1232, and a retirement subunit 1233. The receiving subunit 1231 can receive a completion request signal sent by the instruction execution unit 121 for a to-be-completed instruction. The arbitration subunit 1232 can send an allowed completion signal for the to-be-completed instruction to the instruction execution unit 121 in response to the completion request signal received by the receiving subunit 1231, and determine that the to-be-completed instruction can be completed according to the new-old relationship between the retired instruction and the to-be-completed instruction, receive the instruction completion information of the to-be-completed instruction sent by the instruction execution unit 121, and store the instruction completion information of the to-be-completed instruction into the instruction buffer table item in the buffer. The retirement subunit 1233 can perform retirement processing on the to-be-retired instruction that has been completed and not retired according to the instruction completion information stored in each instruction buffer table item, and delete the instruction completion information of the retired instruction from the instruction buffer table item. The number of instruction buffer table items in the buffer is greater than 1 and less than the out-of-order degree allowed by the processing unit 12, and each instruction buffer table item can store the instruction completion information of one instruction.

[0075] Whether an instruction can be completed is determined by the instruction execution unit 121. When the instruction execution unit 121 determines that one instruction executed by it can be completed, the instruction is a to-be-completed instruction, and the instruction execution unit 121 sends a completion request signal for the instruction to the instruction retirement unit 123. The arbitration subunit 1232 sends an allowed completion signal to the instruction execution unit 121 after determining that the to-be-completed instruction can be completed. The instruction execution unit 121 sends the instruction completion information of the to-be-completed instruction to the instruction retirement unit 123 after receiving the allowed completion signal, and the completion of the instruction is realized.

[0076] The completion of an instruction is a stage after the execution of the instruction, and a completed instruction is an instruction that can be normally executed to obtain a result. The instruction execution unit 121 can initiate a completion request for an instruction when it determines that the instruction can be normally executed. Therefore, the to-be-completed instruction is not necessarily an instruction that has been executed. The instruction execution unit 121 can determine whether a to-be-executed instruction can be normally executed after the instruction is started, and initiate a completion request for the instruction if it is determined that the instruction can be normally executed.

[0077] After the to-be-completed instruction is allowed to be completed, the instruction execution unit 121 sends the instruction completion information of the to-be-completed instruction to the instruction retirement unit 123, and the arbitration subunit 1232 stores the instruction completion information into the instruction buffer table item for use by the retirement subunit 1233 when performing retirement processing on the instruction. The instruction completion information includes the length of the instruction, whether the instruction will update the identification bit, whether the instruction will generate an exception, and the like.

[0078] The buffer is located in the instruction retirement unit 123, the number of instruction buffer entries in the buffer is greater than 1 and less than the out-of-order degree allowed by the processing unit 12, and each instruction buffer entry can store the instruction completion information of one instruction at the same time. The out-of-order degree of the processing unit 12 is equal to the upper limit of the number of instructions allowed in the instruction execution unit 121, that is, the upper limit of the number of instructions in the instruction execution unit 121 in the distribution stage to the retirement stage. For example, the out-of-order degree of the instruction execution unit 121 is 64, the upper limit of the number of unretired instructions in the instruction execution unit 121 is 64, the number of instruction buffer entries in the buffer is greater than 1 and less than 64, for example, the number of instruction buffer entries is 4.

[0079] It should be understood that the number of instruction buffer entries in the buffer will affect the number of completed but not retired instructions, thereby affecting the performance of the processing unit 12, and the number of instruction buffer entries will also affect the resource consumption for maintaining the buffer. By setting a reasonable number of instruction buffer entries, the performance of the processing unit 12 and the resource consumption can be balanced.

[0080] The arbitration sub-unit 1232 determines whether the to-be-completed instruction can be completed according to the new-old relationship between the retired instruction and the to-be-completed instruction, and stores the instruction completion information of the to-be-completed instruction into the instruction buffer entry after determining that the to-be-completed instruction can be completed. Since the number of instruction buffer entries is less than the out-of-order degree allowed by the processing unit 12, the arbitration sub-unit 1232 controls the instructions to be completed in order and stores the instruction completion information of the completed instruction in the instruction buffer entry, avoiding the situation that the completed instruction cannot be retired and continuously occupies the instruction buffer entry, causing other instructions to be unable to be completed, and thus the pipeline is blocked.

[0081] In the embodiment of the present application, the number of instruction buffer entries in the buffer is less than the out-of-order degree of the processing unit 12, the arbitration sub-unit 1232 makes the instructions to be completed in order and stores the instruction completion information of the completed instruction into the instruction buffer entry, and the retirement sub-unit 1233 performs the retirement processing on the to-be-retired instruction according to the instruction completion information in the instruction buffer entry, and deletes the instruction completion information of the retired instruction from the instruction buffer entry. Since the instruction completion information of the completed and not retired or retired instruction is stored in the instruction buffer entry, the instruction only occupies the instruction buffer entry in the completion and retirement stages, and therefore the buffer only needs to include a small number of instruction buffer entries to meet the out-of-order execution of the processing unit 12, and maintaining a small number of instruction buffer entries can reduce the hardware resource consumption of the instruction reordering part when the processing unit 12 performs the out-of-order processing.

[0082] In a possible implementation, the buffer includes N instruction buffer entries, N being a positive integer greater than or equal to 2. In order to avoid the sending pipeline from being blocked, the buffer stores the instruction completion information of the N oldest instructions except the retired instructions, and each instruction buffer entry stores the instruction completion information of one instruction. After the receiving sub-unit 1231 receives the completion request signal for a to-be-completed instruction, the arbitration sub-unit 1232 determines whether the to-be-completed instruction is included in the N oldest instructions except the retired instructions, and if so, allows the to-be-completed instruction to complete, and further sends the completion permission signal to the instruction execution unit 121, so that the instruction execution unit 121 sends the instruction completion information of the to-be-completed instruction and stores the instruction completion information of the to-be-completed instruction into the instruction buffer entry.

[0083] Figure 5 Figure 1 is a schematic diagram of acceptable completion instructions according to an embodiment of the present application. As shown in Figure 1, instructions X-1 to X+N+1 are sequential instructions in an instruction packet, and instructions X and the preceding instructions are retired instructions. When the number of instruction buffer entries is N, the acceptable completion instructions are instructions X+1 to X+N, i.e., the N oldest instructions except the retired instructions 1 to X. Any instruction among instructions X+1 to X+N that initiates a completion request will be accepted by the arbitration sub-unit 1232, while any instruction outside instructions X+1 to X+N that initiates a completion request will not be accepted by the arbitration sub-unit 1232. Figure 5 Figure 5 For example, when the number of instruction buffer entries is 4, and the instruction packet includes instructions 1 to 64 according to the instruction sequence (the new-old relationship of the instructions), instructions 1 and 2 are retired instructions, and the 4 oldest instructions except instructions 1 and 2 are instructions 3 to 6. If any instruction among instructions 3 to 6 initiates a completion request, the arbitration sub-unit 1232 will allow the instruction to complete, and if any instruction outside instructions 3 to 6 initiates a completion request, e.g., instruction 7 initiates a completion request, the arbitration sub-unit 1232 will not allow the instruction to complete.

[0084] For example, when the number of instruction buffer entries is 4, and the instruction packet includes instructions 1 to 64 according to the instruction sequence (the new-old relationship of the instructions), instructions 1 and 2 are retired instructions, and the 4 oldest instructions except instructions 1 and 2 are instructions 3 to 6. If any instruction among instructions 3 to 6 initiates a completion request, the arbitration sub-unit 1232 will allow the instruction to complete, and if any instruction outside instructions 3 to 6 initiates a completion request, e.g., instruction 7 initiates a completion request, the arbitration sub-unit 1232 will not allow the instruction to complete.

[0085] It should be understood that when any instruction among the N oldest instructions except the retired instructions initiates a completion request, the arbitration sub-unit 1232 will run the instruction to complete, i.e., the N instructions do not need to be completed according to the new-old relationship, and part or all of the N instructions can simultaneously initiate a completion request. For example, when the N oldest instructions except the retired instructions are instructions 3 to 6, there is no requirement for the completion order of instructions 3 to 6.

[0086] ​In the embodiment of the present application, since the instructions need to retire in order, the arbitration sub-unit 1232 allows the N instructions older than the retired instruction to retire according to the retired instruction, that is, the buffer can store the instruction completion information of the N instructions older than the retired instruction, so as to avoid that the subsequent instruction occupies the instruction buffer entry while the previous instruction cannot be completed, the previous instruction cannot be completed to cause the completed instruction to be unable to retire and the instruction buffer entry to be emptied, and the cycle causes the pipeline to be blocked, thereby reducing the resource consumption of the processing unit 12 while ensuring the performance and reliability of the processing unit 12.

[0087] In a possible implementation, the N instruction buffer entries included in the buffer are used to store the instruction completion information of different instructions, and the i th instruction buffer entry in the N instruction buffer entries is used to store the instruction completion information of the i+kN th instruction in the instruction sequence, k is a non-negative integer.

[0088] For example, when the buffer includes 4 instruction buffer entries in total, that is, N is equal to 4, instruction buffer entry 1 is used to store the instruction completion information of instruction 1+4k, instruction buffer entry 2 is used to store the instruction completion information of instruction 2+4k, instruction buffer entry 3 is used to store the instruction completion information of instruction 3+4k, and instruction buffer entry 4 is used to store the instruction completion information of instruction 4+4k, where k is a non-negative integer such as 0, 1, 2, and the like. When the out-of-order degree allowed by the processing unit 12 is 64, the instructions corresponding to the instruction completion information stored in instruction buffer entry 1 to instruction buffer entry 4 are as shown in Table 1.

[0089] Table 1

[0090]

[0091] It should be noted that each instruction buffer entry can only store the instruction completion information of one instruction at the same time, and the instruction completion information of the next instruction can be stored in the instruction buffer entry only after the instruction completion information of the previous instruction is deleted from the instruction buffer entry. For example, for instruction buffer entry 1 in Table 1, when the instruction completion information of instruction 1 is in instruction buffer entry 1, the instruction completion information of instruction 5 cannot be stored in instruction buffer entry 1, and at this time, the completion request of instruction 5 will not be accepted by the arbitration sub-unit 1232, and after instruction 1 retires, the instruction completion information of instruction 1 is deleted from instruction buffer entry 1, and then the instruction completion information of instruction 5 can be stored in instruction buffer entry 1, and at this time, the completion request of instruction 5 will be accepted by the arbitration sub-unit 1232.

[0092] For the i-th instruction buffer table entry of the instruction buffer table entries, if the i-th instruction buffer table entry stores the instruction completion information of the i+kN-th instruction, after the instruction completion information of the i+kN-th instruction retires, the arbitration sub-unit 1232 matches the instruction identifier of the i+(k+1)N-th instruction to the i-th instruction buffer table entry to indicate that the i-th instruction buffer table entry can currently store the instruction completion information of the i+(k+1)N-th instruction, and thus the completion request of the i+(k+1)N-th instruction can be accepted by the arbitration sub-unit 1232.

[0093] In the embodiment of the present application, the N instruction buffer table entries included in the buffer store the instruction completion information of different instructions, and each instruction buffer table entry stores the instruction completion information of each instruction separated by N-1 instructions in the instruction sequence. The instruction completion information of adjacent instructions in the instruction sequence is stored in different instruction buffer table entries, which can shorten the completion waiting time of the instructions, improve the efficiency of instruction completion and retirement, and guarantee the performance of the processing unit 12 while reducing the resource consumption of the processing unit 12.

[0094] In a possible implementation, for each completed and unretired instruction to be retired, the retirement sub-unit 1233 can determine whether the precedent instructions of the instruction to be retired have all retired or have all been completed and will not cause a speculation failure according to the instruction completion information of the instruction to be retired in the instruction buffer table entry. If the precedent instructions of the instruction to be retired have all retired or have all been completed and will not cause a speculation failure, the retirement sub-unit 1233 performs retirement processing on the instruction to be retired and the unretired precedent instructions in sequence, and deletes the instruction completion information of the retired instructions from the instruction buffer table entry.

[0095] For example, after the instruction completion information of the instruction 5 is stored in the instruction buffer table entry, the retirement sub-unit 1233 determines whether the precedent instructions of the instruction 5 have all retired or have all been completed and will not cause a speculation failure. If the precedent instructions of the instruction 5 have all retired or have all been completed and will not cause a speculation failure, the retirement sub-unit 1233 retires the instruction 5. If the precedent instructions of the instruction 5 include an unretired instruction that has been completed and will not cause a speculation failure, the retirement sub-unit 1233 simultaneously retires the unretired instruction that has been completed and will not cause a speculation failure in the precedent of the instruction 5. For example, the instructions 1 to 3 in the precedent of the instruction 5 have all retired, and the instruction 4 has been completed and will not cause a speculation failure. Therefore, the retirement sub-unit 1233 retires the instructions 4 and 5 in sequence.

[0096] For any instruction to be retired, if the precedent of the instruction to be retired includes an uncompleted instruction, the instruction to be retired needs to wait until the precedent instructions of the instruction to be retired are all completed, and then determines whether the instruction to be retired can be normally retired according to whether the precedent instructions will cause a speculation failure.

[0097] In the embodiment of the present application, the retirement subunit 1233 retires the completed instructions that do not cause the speculative failure in sequence, and deletes the instruction completion information of the retired instructions from the instruction buffer table item, so that the instruction completion information of the subsequent instructions can be stored in the instruction buffer table item, to enable the subsequent instructions to be completed in sequence, to ensure the correctness of the overall execution behavior while restoring the instruction execution sequence.

[0098] In a possible implementation, for each completed and unretired instruction to be retired, the retirement subunit 1233 can determine, according to the instruction completion information of the instruction to be retired in the instruction buffer table item, whether the precedent of the instruction to be retired has a completed instruction that causes the speculative failure. If the precedent of the instruction to be retired has a completed instruction that causes the speculative failure, the retirement subunit 1233 performs the retirement processing on the completed instruction that causes the speculative failure, generates a flush pipeline operation, sends a pipeline flush request to the instruction execution unit 121, and deletes the instruction completion information of the retired instruction and the completed instruction on the error path from the instruction buffer table item.

[0099] For example, when the retirement subunit 1233 performs the retirement processing on instruction 5, it determines whether each completed instruction in the precedent of instruction 5 causes the speculative failure. After instruction 3 that causes the speculative failure is completed, the retirement subunit 1233 performs the retirement processing on instruction 3, generates a flush pipeline operation, and sends a pipeline flush request to the instruction execution unit 121, so that the speculative instruction on the error path does not have an execution effect. If the speculative instruction on the error path is completed, the instruction completion information of the speculative instruction on the error path is deleted from the instruction buffer table item.

[0100] In the embodiment of the present application, when the precedent of the completed instruction has a completed instruction that causes the speculative failure, the retirement subunit 1233 retires to the speculative failure instruction that causes the speculative failure, generates a flush pipeline operation, and sends a pipeline flush request to the instruction execution unit 121, so that the speculative instruction on the error path does not have an execution effect. If the speculative instruction on the error path is completed, the instruction completion information of the speculative instruction on the error path is deleted from the instruction buffer table item, so that the retired instruction is an instruction on the correct path, and the correctness of the overall execution behavior is ensured.

[0101] Figure 6 FIG. 12 is a schematic diagram of the internal structure of the instruction retirement unit 123 according to another embodiment of the present application. As shown in FIG. 12, the instruction retirement unit 123 includes a retirement subunit 1233 and a flush subunit 1231. Figure 6As shown, the instruction retirement unit 123 further includes a determining sub-unit 1234. The determining sub-unit 1234 can determine the current submittable instruction according to the instruction completion information stored in each instruction buffer table entry, wherein the in-order instructions of the current submittable instruction have all been retired or not retired but completed and will not cause a speculation failure. After determining the current submittable instruction, the determining sub-unit 1234 sends an instruction submission signal to the instruction execution unit 121 based on the current submittable instruction, and the instruction execution unit 121 receiving the instruction submission signal can submit the current submittable instruction and its in-order instructions according to the instruction submission signal.

[0102] The determining sub-unit 1234 can determine the instruction whose in-order instructions have all been retired or not retired but completed and will not cause a speculation failure as the current submittable instruction according to the instruction completion information stored in each instruction buffer table entry, and the current submittable instruction can be an uncompleted instruction. Since the submittable instruction is the instruction whose in-order instructions have all been retired or not retired but completed and will not cause a speculation failure, the current submittable instruction is the next instruction of the last submittable instruction.

[0103] Figure 7 is a schematic diagram of the current submittable instruction of an embodiment of the present application. As shown, Figure 7 Instruction X is the last submittable instruction, and instruction X+1 is the current submittable instruction. Figure 7 In the figure, the instructions shown in the oblique hatched rectangular frame are completed instructions, and the instructions not shown in the oblique hatched rectangular frame are uncompleted instructions, i.e., instruction X-2, instruction X-1, instruction X, and instruction X+2 are completed instructions, and instruction X+1 is an uncompleted instruction.

[0104] In the embodiment of the present application, the determining sub-unit 1234 determines the current submittable instruction according to the instruction completion information stored in each instruction buffer table entry, and after sending the instruction submission signal to the instruction execution unit 121 based on the current submittable instruction, the instruction execution unit 121 can submit the current submittable instruction and its in-order instructions. Since the in-order instructions of the current submittable instruction have all been retired or not retired but completed and will not cause a speculation failure, it is ensured that the submitted instructions are all on the correct path, thereby ensuring the correctness of the overall execution behavior.

[0105] Instruction execution unit

[0106] Figure 8 is a schematic diagram of the internal structure of the instruction execution unit of an embodiment of the present application. As shown, Figure 8As shown, the instruction execution unit 121 includes a request subunit 1211 and a sending subunit 1212. When determining that one instruction executed by the instruction execution unit 121 can be completed, the request subunit 1211 can send a completion request signal for the to-be-completed instruction to the instruction retirement unit 123 to request completion of the to-be-completed instruction. When determining that the to-be-completed instruction can be completed, the instruction retirement unit 123 sends an allowed completion signal to the instruction execution unit 121, and the sending subunit 1212 receives the allowed completion signal and sends instruction completion information of the to-be-completed instruction to the instruction retirement unit 123. The instruction retirement unit 123 stores the instruction completion information in an instruction buffer table item in the buffer area, and then the instruction retirement unit 123 can perform retirement processing on the to-be-retired instruction that has been completed and not retired according to the instruction completion information stored in each instruction buffer table item, and delete the instruction completion information of the retired instruction from the instruction buffer table item. The number of instruction buffer table items in the buffer area is greater than 1 and less than the out-of-order degree allowed by the processing unit 12, and each instruction buffer table item can store the instruction completion information of one instruction.

[0107] After the instruction execution unit 121 starts executing one instruction, the request subunit 1211 can determine whether the instruction can be completed. If it is determined that the instruction can be completed, the request subunit 1211 sends a completion request signal for the instruction to the instruction retirement unit 123. If it is determined that the instruction cannot be completed temporarily, the request subunit 1211 waits until the instruction can be completed, and then sends a completion request signal for the instruction to the instruction retirement unit 123. After the request subunit 1211 sends the completion request signal to the instruction retirement unit 123, if no allowed completion signal sent by the instruction retirement unit 123 is received, it indicates that the instruction retirement unit 123 determines that the to-be-completed request cannot be completed yet, and the request subunit 1211 needs to re-perform completion of the to-be-completed instruction subsequently.

[0108] In the embodiment of the present application, the number of instruction buffer table items in the buffer area is less than the out-of-order degree of the processing unit 12. The request subunit 1211 sends instruction completion information to the instruction retirement unit 123, and the instruction retirement unit 123 stores the instruction completion information in the instruction buffer table item to complete the instruction. Then, the instruction retirement unit 123 can perform retirement processing on the to-be-retired instruction according to the instruction completion information in the instruction buffer table item, and delete the instruction completion information of the retired instruction from the instruction buffer table item. Since the instruction buffer table item stores the instruction completion information of the instruction that has been completed and not retired or is being retired, the instruction only occupies the instruction buffer table item in the completion and retirement stages, and therefore the buffer area only needs to include a small number of instruction buffer table items to meet the out-of-order execution of the processing unit 12, and maintaining a small number of instruction buffer table items can reduce the resource consumption of the processing unit 12.

[0109] Figure 9is a schematic diagram of an internal structure of an instruction execution unit according to another embodiment of the present application. As shown in Figure 9 The instruction execution unit 121 further includes a commit subunit 1213. The commit subunit 1213 can receive an instruction commit signal from the instruction retirement unit 123, and commit the current commitable instruction and its predecessor instructions corresponding to the instruction commit signal. The predecessor instructions of the current commitable instruction have all been retired or not retired but completed and will not cause a speculation failure.

[0110] The instruction retirement unit 123 can determine the current commitable instruction according to the instruction completion information stored in each instruction buffer entry, and broadcast an instruction commit signal to the instruction execution unit 121 based on the current commitable instruction. After the instruction execution unit 121 receives the instruction commit signal, the instruction execution unit 121 commits the current commitable instruction and its predecessor instructions.

[0111] In the embodiments of the present application, since the current commitable instruction is determined according to the instruction completion information in each instruction buffer entry, the predecessor instructions of the current commitable instruction have all been retired or not retired but completed and will not cause a speculation failure, so the current commitable instruction and its predecessor instructions are all instructions on the correct path, thereby ensuring the correctness of the overall execution behavior.

[0112] In a possible implementation, the instruction commit signal includes an instruction identifier of the current commitable instruction, the instruction identifier of the instruction is obtained when the instruction is dispatched, and the instruction identifier can indicate the timing relationship of the instruction, i.e., the new-old relationship of the instruction can be determined according to the instruction identifier. The commit subunit 1213 can obtain the instruction identifier of the to-be-committed instruction generating the commit request, compare the instruction identifier of the to-be-committed instruction with the instruction identifier of the current commitable instruction, commit the to-be-committed instruction if the instruction identifier of the to-be-committed instruction is older than or equal to the instruction identifier of the current commitable instruction, and do not commit the to-be-committed instruction if the instruction identifier of the to-be-committed instruction is newer than the instruction identifier of the current commitable instruction.

[0113] The instruction dispatch unit assigns an instruction identifier to each instruction when the instruction enters the out-of-order state from the in-order state, the instruction identifier is a unique identifier of the instruction in the pipeline, and the new-old relationship of different instructions can be determined by comparing the instruction identifiers. The instruction identifier can be incremented or decremented according to the instruction sequence. When the instruction identifier is incremented according to the instruction sequence, the instruction with a larger instruction identifier is newer than the instruction with a smaller instruction identifier. When the instruction identifier is decremented according to the instruction sequence, the instruction with a larger instruction identifier is older than the instruction with a smaller instruction identifier.

[0114] In the embodiment of the present application, the submitting subunit 1213 determines the new-old relationship of the instructions according to the instruction identifiers. If one instruction is older than the current submitting instruction, the instruction is submitted. If one instruction has the same instruction identifier as the current submitting instruction, it is the current submitting instruction, and then the instruction is submitted. If one instruction is newer than the current submitting instruction, the instruction is not submitted. The new-old relationship of the instructions is determined according to the instruction identifiers, and then the instructions that can be submitted are determined, so that the submitted instructions are on the correct path, and the overall execution behavior is correct.

[0115] Figure 10 FIG. 12 is a schematic diagram of an internal structure of an instruction execution unit according to another embodiment of the present application. As shown in FIG. 12, the instruction execution unit 121 further includes a flushing subunit 1214. The flushing subunit 1214 can flush the instruction execution unit 121 according to the execution delay and architecture of the instruction execution unit 121 by a first flushing mode and / or a second flushing mode in response to a pipeline flushing request from the instruction retirement unit 123, wherein the first flushing mode clears the speculative instructions on the incorrect path before the instructions are executed, and the second flushing mode makes the speculative instructions on the incorrect path have no execution effect. Figure 10

[0116] The first flushing mode clears the speculative instructions on the incorrect path before the instructions are executed, so that the pipeline flushing can be performed without waiting for all the instructions in the instruction execution unit 121 to be executed, thereby shortening the time required for each pipeline flushing. However, the first flushing mode needs to determine the new-old relationship of the instructions before the instructions are executed, and therefore has a hard requirement for the architecture of the instruction execution unit 121. For example, the instruction execution unit 121 that processes the instructions in order can perform the pipeline flushing by the first flushing mode, while the instruction execution unit 121 that processes the instructions out of order cannot perform the pipeline flushing by the first flushing mode.

[0117] The second flushing mode can make the speculative instructions on the incorrect path have no execution effect, and the new-old relationship of the instructions can be determined according to the execution results after all the instructions in the instruction execution unit 121 are executed, so that the second flushing mode can be applied to the instruction execution unit 121 of various architectures. However, the second flushing mode needs to determine the new-old relationship of the instructions after the instructions are executed. If there is a long-delay instruction in the instruction execution unit 121, the instruction execution unit 121 needs a long time to execute the long-delay instruction, and a long time is required to complete the pipeline flushing. During the pipeline flushing, the previous stage cannot send new instructions to the instruction execution unit 121, resulting in execution bubbles of the processing unit 12 and affecting the performance of the processing unit 12.

[0118] ​In the embodiment of the present application, when speculation failure occurs, the instruction retirement unit 123 sends a pipeline flush request to the instruction execution unit 121, and the flush subunit 1214 flushes the pipeline of the instruction execution unit 121 according to the execution delay and architecture of the instruction execution unit 121 by the first flush mode and / or the second flush mode in response to the pipeline flush request. Since the first flush mode clears the speculative instructions on the error path before the instructions are executed, the pipeline flush speed is faster, but it is only applicable to the instruction execution unit of some architecture types. The second flush mode can make the speculative instructions on the error path not produce execution effect, and is applicable to the instruction execution unit of various architecture types. Therefore, the flush subunit 1214 can flush the pipeline of the instruction execution unit 121 according to the execution delay and architecture of the instruction execution unit 121 by the first flush mode and / or the second flush mode, which can improve the pipeline flush speed and thus improve the pipeline flush efficiency on the basis of being able to flush the pipeline of the instruction execution unit of different architectures.

[0119] Instruction processing method

[0120] Figure 11 is a flowchart of an instruction processing method of an embodiment of the present application, which can be executed by the instruction retirement unit 123 in the above embodiment. As shown in Figure 11 , the instruction execution method comprises the following steps:

[0121] Step 1101, receiving a completion request signal sent by the instruction execution unit for the to-be-completed instruction, wherein the completion request signal is used to request completion of the to-be-completed instruction.

[0122] Step 1102, after determining that the to-be-completed instruction can be completed according to the new-old relationship between the retired instruction and the to-be-completed instruction, sending an allowed completion signal for the to-be-completed instruction to the instruction execution unit, and receiving the instruction completion information of the to-be-completed instruction sent by the instruction execution unit, and storing the instruction completion information of the to-be-completed instruction into the instruction buffer table item in the buffer area.

[0123] , the number of instruction buffer table items in the buffer area is greater than 1 and less than the out-of-order degree allowed by the processing unit, and each instruction buffer table item can store the instruction completion information of one instruction;

[0124] Step 1103, performing retirement processing on the to-be-retired instruction which has been completed and not retired according to the instruction completion information stored in each instruction buffer table item, and deleting the instruction completion information of the retired instruction from the instruction buffer table item.

[0125] In the embodiment of the present application, the number of instruction buffer entries in the buffer is less than the out-of-order degree of the processing unit, the instruction completion information of the completed instruction is stored in the instruction buffer entry by completing the instruction in order, the retirement processing is performed on the to-be-retired instruction according to the instruction completion information in the instruction buffer entry, and the instruction completion information of the retired instruction is deleted from the instruction buffer entry. Since the instruction completion information of the completed and unretired or retired instruction is stored in the instruction buffer entry, the instruction only occupies the instruction buffer entry in the completion and retirement stages, and therefore the buffer only needs to include a small number of instruction buffer entries to meet the out-of-order execution of the processing unit, and maintaining a small number of instruction buffer entries can reduce the resource consumption of the processing unit.

[0126] In a possible implementation, the buffer includes N instruction buffer entries, when completing an instruction, it can be determined whether the to-be-completed instruction is included in the N older instructions except the retired instruction, if the to-be-completed instruction is included in the N older instructions except the retired instruction, a completion permission signal for the to-be-completed instruction is sent to the instruction execution unit, the instruction completion information of the to-be-completed instruction sent by the instruction execution unit is received, and the instruction completion information of the to-be-completed instruction is stored in the instruction buffer entry in the buffer.

[0127] In a possible implementation, the N instruction buffer entries are used to store the instruction completion information of different instructions, and the i th instruction buffer entry in the N instruction buffer entries is used to store the instruction completion information of the i+kN instruction in the instruction sequence, k is a non-negative integer.

[0128] In a possible implementation, when performing the retirement processing on the instruction, for each to-be-retired instruction, if it is determined according to the instruction completion information of the to-be-retired instruction in the instruction buffer entry that the antecedent instruction of the to-be-retired instruction has been retired or completed and will not cause a speculation failure, the retirement processing is sequentially performed on the to-be-retired instruction and the unretired antecedent instruction, and the instruction completion information of the retired instruction is deleted from the instruction buffer entry.

[0129] In a possible implementation, when performing the retirement processing on the instruction, for each to-be-retired instruction, if it is determined according to the instruction completion information of the to-be-retired instruction in the instruction buffer entry that the antecedent instruction of the to-be-retired instruction is the completed instruction causing the speculation failure, the retirement processing is performed on the completed instruction causing the speculation failure, a pipeline flush request is sent to the instruction execution unit, and the instruction completion information of the retired instruction and the completed instruction on the error path is deleted from the instruction buffer entry.

[0130] In one possible implementation, the instruction processing method further includes: determining the currently committable instruction based on the instruction completion information stored in each instruction cache entry, and sending an instruction commit signal to the instruction execution unit based on the currently committable instruction, so that the instruction execution unit commits the currently committable instruction and its preceding instructions according to the instruction commit signal, wherein the preceding instructions of the currently committable instruction have all been retired or completed and will not cause speculation failure.

[0131] Figure 12 This is a flowchart of an instruction processing method according to another embodiment of this application, which can be executed by the instruction execution unit 121 in the above embodiment. Figure 12 As shown, the instruction execution method includes the following steps:

[0132] Step 1201: Send a completion request signal to the instruction retirement unit, wherein the completion request signal is used to request the completion of the instruction to be completed.

[0133] Step 1202: After receiving the completion permission signal sent by the instruction retirement unit, the instruction completion information of the instruction to be completed is sent to the instruction retirement unit. The instruction retirement unit stores the instruction completion information in the instruction buffer table in the buffer, and performs retirement processing on the completed but not retired instructions according to the instruction completion information stored in each instruction buffer table, and deletes the instruction completion information of retired instructions from the instruction buffer table.

[0134] The number of instruction cache entries in the buffer is greater than 1 and less than the out-of-order limit allowed by the processing unit. Each instruction cache entry can store the instruction completion information of one instruction.

[0135] In this embodiment, the number of instruction buffer entries in the buffer is less than the out-of-order execution capability of the processing unit. By completing instructions in sequence, the instruction completion information of completed instructions is stored in the instruction buffer entries. Based on the instruction completion information in the instruction buffer entries, retirement processing is performed on instructions awaiting retirement, and the instruction completion information of retired instructions is deleted from the instruction buffer entries. Since the instruction buffer entries store the instruction completion information of completed instructions that are not yet retired or are in the process of retirement, instructions only occupy instruction buffer entries during the completion and retirement phases. Therefore, the buffer only needs to include a small number of instruction buffer entries to satisfy the out-of-order execution capability of the processing unit, and maintaining fewer instruction buffer entries reduces the resource consumption of the processing unit.

[0136] In one possible implementation, the instruction processing method further includes: receiving an instruction commit signal from the instruction retirement unit, and committing the currently committable instruction and the preceding instructions of the currently committable instruction corresponding to the instruction commit signal, wherein the preceding instructions of the currently committable instruction have all been retired or completed and will not cause speculation failure.

[0137] In a possible implementation, the instruction submission signal includes an instruction identifier of a current submittable instruction, the instruction identifier of the instruction being obtained when the instruction is dispatched, the instruction identifier being used to indicate the timing relationship of the instruction; when the instruction is submitted, the instruction identifier of a to-be-submitted instruction generating the submission request can be obtained, and if the instruction identifier of the to-be-submitted instruction is older than or equal to the instruction identifier of the current submittable instruction, the to-be-submitted instruction is submitted.

[0138] In a possible implementation, the instruction processing method further includes: in response to a pipeline flushing request from the instruction retirement unit, flushing the instruction execution unit according to the execution delay of the instruction execution unit and the architecture by using a first flushing mode and / or a second flushing mode, wherein the first flushing mode clears the speculative instructions on the error path before the instructions are executed, and the second flushing mode makes the speculative instructions on the error path have no execution effect.

[0139] It should be noted that, since the details of the instruction processing method are described in the instruction retirement unit and the instruction execution unit of the above-mentioned embodiments, the specific process can be referred to the description in the foregoing instruction retirement unit embodiments and instruction execution unit embodiments, which will not be described herein again.

[0140] Computer storage medium

[0141] The application also provides a computer-readable storage medium storing instructions for causing a machine to perform the instruction processing method as described herein. Specifically, a system or apparatus equipped with a storage medium can be provided, the storage medium storing software program codes for implementing the functions of any of the above-mentioned embodiments, and causing the computer (or CPU or MPU) of the system or apparatus to read and execute the program codes stored in the storage medium.

[0142] In this case, the program codes read from the storage medium can implement the functions of any of the above-mentioned embodiments, and thus the program codes and the storage medium storing the program codes constitute a part of the application.

[0143] The storage medium for providing the program codes includes floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, the program codes can be downloaded from a server computer via a communication network.

[0144] Computer program product

[0145] The embodiment of the present application further provides a computer program product comprising computer instructions for instructing a computing device to perform any corresponding operation in the above method embodiments.

[0146] Commercial value of embodiments of the present application

[0147] The embodiment of the present application solves the problem of large resource consumption when the processing unit restores the instruction execution sequence. The number of instruction buffer table entries in the buffer is less than the out-of-order degree of the processing unit, the instructions are executed in order, the instruction completion information of the completed instructions is stored in the instruction buffer table entries, the instructions to be retired are processed according to the instruction completion information in the instruction buffer table entries, and the instruction completion information of the retired instructions is deleted from the instruction buffer table entries. Since the instruction completion information of the completed and unretired or retired instructions is stored in the instruction buffer table entries, the instructions only occupy the instruction buffer table entries in the completion and retirement stages, and therefore the buffer only needs to include a small number of instruction buffer table entries to meet the out-of-order execution of the processing unit, and maintaining a small number of instruction buffer table entries can reduce the resource consumption of the processing unit.

[0148] It should be understood that each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment mainly describes the difference from other embodiments. Especially, for the method embodiments, since the method is basically similar to the method described in the device and system embodiments, the description is relatively simple, and the relevant parts can refer to the part of the description of other embodiments.

[0149] It should be understood that the above describes specific embodiments of the specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multi-task processing and parallel processing are possible or can be advantageous.

[0150] It should be understood that the element described in the singular form or only shown in the drawings in the singular form does not mean that the number of the element is limited to one. In addition, the modules or elements described or shown as separate in the specification can be combined into a single module or element, and the modules or elements described or shown as single in the specification can be split into multiple modules or elements.

[0151] It is also to be understood that the terminology and phraseology employed herein is for the purpose of description and the specification one or more embodiments of the present application should not be limited to the terms used. The use of such terms and expressions does not therefore admit of any limitation on the scope of the application, it being recognized that the various modifications are possible to the embodiments in view of the teachings and adversities made and that modifications are to be included within the scope of the present application. Other modifications, variations, and alternatives are also possible. Accordingly, the claims should be regarded as encompassing all such equivalents.

Claims

1. An instruction retirement unit, comprising: a receiving subunit configured to receive a completion request signal sent by an instruction execution unit for a to-be-completed instruction, wherein the completion request signal is configured to request completion of the to-be-completed instruction; an arbitration subunit configured to send an allowed completion signal for the to-be-completed instruction to the instruction execution unit after determining that the to-be-completed instruction can be completed according to a new-older relationship between a retired instruction and the to-be-completed instruction, and receive instruction completion information of the to-be-completed instruction sent by the instruction execution unit, and store the instruction completion information of the to-be-completed instruction into an instruction buffer entry in a buffer, wherein a number of instruction buffer entries in the buffer is greater than 1 and less than an out-of-order degree allowed by a processing unit, and each instruction buffer entry can store instruction completion information of one instruction; and a retirement subunit configured to perform retirement processing on a to-be-retired instruction that has been completed and not retired according to the instruction completion information stored in each instruction buffer entry, and delete instruction completion information of the retired instruction from the instruction buffer entry. The buffer comprises N instruction buffer entries. The arbitration subunit is configured to determine whether the to-be-completed instruction is included in N instructions that are older than the retired instruction, and if the to-be-completed instruction is included in the N instructions that are older than the retired instruction, send the allowed completion signal for the to-be-completed instruction to the instruction execution unit, and receive the instruction completion information of the to-be-completed instruction sent by the instruction execution unit, and store the instruction completion information of the to-be-completed instruction into the instruction buffer entry in the buffer. The N instruction buffer entries are configured to store instruction completion information of different instructions, and an i-th instruction buffer entry in the N instruction buffer entries is configured to store instruction completion information of an i+kN-th instruction in an instruction sequence, wherein k is a non-negative integer.

2. The instruction retirement unit of claim 1, wherein, 4. The instruction retirement unit of claim 1, wherein The retirement subunit is configured to, for each to-be-retired instruction, if it is determined according to the instruction completion information of the to-be-retired instruction in the instruction buffer entry that all of the in-order instructions of the to-be-retired instruction have been retired or have been completed and will not cause a speculation failure, perform retirement processing on the to-be-retired instruction and the in-order instructions that have not been retired in sequence, and delete instruction completion information of the retired instructions from the instruction buffer entry.

3. The instruction retirement unit of claim 2, wherein, 5. The instruction retirement unit of claim 4, wherein The retirement subunit is configured to, for each to-be-retired instruction, if it is determined according to the instruction completion information of the to-be-retired instruction in the instruction buffer entry that there is a completed instruction of the in-order instructions that causes a speculation failure, perform retirement processing on the completed instruction that causes the speculation failure, send a pipeline flush request to the instruction execution unit, and delete instruction completion information of the retired instructions and the completed instructions on an error path from the instruction buffer entry. The instruction retirement unit further comprises: ​ ​ 6. The instruction retirement unit of any one of claims 1-5, wherein, ​ determining sub-unit, configured to determine a current submittable instruction according to instruction completion information stored in each of the instruction cache table entries, and send an instruction submission signal to the instruction execution unit based on the current submittable instruction, so that the instruction execution unit submits the current submittable instruction and in-sequence instructions of the current submittable instruction according to the instruction submission signal, wherein the in-sequence instructions of the current submittable instruction have all been retired or completed and will not cause a speculation failure.

7. An instruction execution unit, comprising: a request sub-unit, configured to send a completion request signal to an instruction retirement unit, wherein the completion request signal is used to request completion of a to-be-completed instruction; a sending sub-unit, configured to send instruction completion information of the to-be-completed instruction to the instruction retirement unit after receiving an allowed completion signal sent by the instruction retirement unit, store the instruction completion information in an instruction cache table entry in a buffer by the instruction retirement unit, retire a to-be-retired instruction that has been completed and not retired according to instruction completion information stored in each of the instruction cache table entries, and delete instruction completion information of a retired instruction from the instruction cache table entry, wherein a number of instruction cache table entries in the buffer is greater than 1 and less than an out-of-order degree allowed by a processing unit, and each instruction cache table entry can store instruction completion information of one instruction.

8. The instruction execution unit of claim 7, wherein, The instruction execution unit further comprises: a submission sub-unit, configured to receive an instruction submission signal from the instruction retirement unit, and submit a current submittable instruction corresponding to the instruction submission signal and in-sequence instructions of the current submittable instruction, wherein the in-sequence instructions of the current submittable instruction have all been retired or completed and will not cause a speculation failure.

9. The instruction execution unit of claim 8, wherein, The instruction submission signal comprises an instruction identifier of the current submittable instruction, and the instruction identifier of the instruction is obtained when the instruction is dispatched, and the instruction identifier is used to indicate a timing relationship of the instruction; The submission sub-unit is configured to obtain an instruction identifier of a to-be-submitted instruction generating a submission request, and if the instruction identifier of the to-be-submitted instruction is older than or equal to the instruction identifier of the current submittable instruction, the to-be-submitted instruction is submitted.

10. A processing unit, comprising: the instruction retirement unit according to any one of claims 1-6; at least one instruction execution unit according to any one of claims 7-9.

11. The processing unit of claim 10, wherein, The processing unit further comprises: an instruction dispatch unit, configured to convert an instruction from an in-sequence state to an out-of-order state, and assign an instruction identifier to the instruction, wherein the instruction identifier is used to indicate an old-new relationship of the instruction; an instruction launching unit, configured to launch the instruction in the out-of-order state to the instruction execution unit.

12. A computing device, comprising: the processing unit according to claim 10 or 11; a memory, coupled to the processing unit, and storing instructions to be executed.

13. An instruction processing method applied to an instruction retirement unit, the instruction processing method comprising: receiving a completion request signal sent by an instruction execution unit for a to-be-completed instruction, wherein the completion request signal is used to request completion of the to-be-completed instruction; sending a completion request signal to the instruction retirement unit, wherein the completion request signal is used to request completion of the to-be-completed instruction; after receiving the completion permission signal sent by the instruction retirement unit, sending the instruction completion information of the to-be-completed instruction to the instruction retirement unit, storing the instruction completion information of the to-be-completed instruction into instruction buffer entries in a buffer, wherein the number of instruction buffer entries in the buffer is greater than 1 and less than the out-of-order degree allowed by the processing unit, each instruction buffer entry can store the instruction completion information of one instruction; retiring the to-be-retired instruction that has been completed but not retired according to the instruction completion information stored in each instruction buffer entry, and deleting the instruction completion information of the retired instruction from the instruction buffer entry.

14. An instruction processing method applied to an instruction execution unit, the instruction processing method comprising: sending a completion request signal to the instruction retirement unit, wherein the completion request signal is used to request completion of the to-be-completed instruction; after receiving the completion permission signal sent by the instruction retirement unit, sending the instruction completion information of the to-be-completed instruction to the instruction retirement unit, storing the instruction completion information of the to-be-completed instruction into instruction buffer entries in a buffer, wherein the number of instruction buffer entries in the buffer is greater than 1 and less than the out-of-order degree allowed by the processing unit, each instruction buffer entry can store the instruction completion information of one instruction; retiring the to-be-retired instruction that has been completed but not retired according to the instruction completion information stored in each instruction buffer entry, and deleting the instruction completion information of the retired instruction from the instruction buffer entry.

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