Data receiving method, device and processor readable storage medium

Abstract

The application provides a data receiving method, device and processor readable storage medium. When a processor core is in an interrupt enabled state, the processor core enters interrupt processing in response to an interrupt processing request initiated by any network card receiving queue; the interrupt enabled state is switched to an interrupt disabled state, data received by each network card receiving queue is processed in a polling NAPI manner; the interrupt disabled state is switched to the interrupt enabled state again, and if the processor core does not receive an interrupt processing request initiated by any network card receiving queue within a preset time period, a real-time guarantee processing procedure is executed, and the real-time guarantee processing procedure is used to ensure that there is no data to be processed in a plurality of network card receiving queues bound to the processor core. Through such a receiving manner, data in the network card can be received by the processor core and sent to a network protocol stack within a specified time, the probability of data receiving delay is reduced, and the real-time performance of data communication is effectively improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method and device for receiving data and a processor-readable storage medium. Background Art

[0002] In 5G-based communication business scenarios, different communication business scenarios have different requirements for data throughput and data response speed.

[0003] In the prior art, in order to ensure that the processor's reception of network card data can meet the business requirements of different scenarios, a processing method of interrupting and polling NAPI data reception is generally adopted.

[0004] However, due to the peculiarities of how the network card triggers the processor core's interrupt handling in this method, when the network data flow to be processed is low, the time when the processor core triggers the next interrupt handling is uncontrollable. This also makes the reception of network data prone to delays, and the real-time performance of data communication is insufficient. Summary of the Invention

[0005] The present application provides a data receiving method, device, and processor-readable storage medium for implementing data reception and processing.

[0006] In one aspect, the present application provides a method for receiving data, the method being applicable to any one processor core in a multi-core processor, the processor core being bound to multiple network card receive queues; the method comprising:

[0007] When the processor core is in an interrupt-enabled state, the processor core responds to an interrupt processing request initiated by any network card receiving queue and enters interrupt processing;

[0008] Switch the interrupt enable state to the interrupt disable state, and process the data received by each network card receiving queue based on the polling NAPI method;

[0009] The interrupt disable state is switched back to the interrupt enable state. Within a preset time period, if the processor core does not receive an interrupt processing request initiated by any network card receive queue, a real-time guarantee processing flow is executed. The real-time guarantee processing flow is used to ensure that there is no data to be processed in the multiple network card receive queues bound to the processor core.

[0010] Optionally, the method further includes:

[0011] Within a preset time period, if the processor core receives an interrupt processing request initiated by any network card receiving queue, the processor core executes the step of returning to the step of entering the interrupt processing.

[0012] Optionally, the method further includes:

[0013] When the processor core switches the interrupt disabled state back to the interrupt enabled state, the processor core synchronously calls and controls the current timer to start;

[0014] The current timer continues timing until the timing duration is equal to the duration of the preset time period, and the processor core executes the real-time guarantee processing flow, or the processor core executes the step of returning to the interrupt processing step.

[0015] Optionally, the method further includes:

[0016] During the process of the current timer continuously timing, if a timing cancellation request sent by a next timer is received, the current timer is reset and controlled to start timing again.

[0017] Optionally, before the processor core synchronously calls and controls the start of the current timer, the method further includes:

[0018] Determine whether there is a previous timer in a continuous timing state;

[0019] If so, a timing cancellation request is sent to the previous timer.

[0020] Optionally, if the processor core does not receive an interrupt processing request initiated by any network card receiving queue, executing the real-time guarantee processing flow includes:

[0021] Scan the receiving queues of each network card in turn;

[0022] When it is determined that there is data to be processed in any network card receive queue among multiple network card receive queues, the processor core actively triggers an interrupt to perform interrupt processing, switches the interrupt enable state to an interrupt disable state, and returns to the step of processing the data received by each network card receive queue based on the polling NAPI method.

[0023] Optionally, when determining that any of the multiple network card receive queues has data to be processed, the method further includes:

[0024] monitoring whether the processor core responds to an interrupt processing request initiated by any network card receiving queue;

[0025] If so, the processor core stops executing the real-time guarantee processing flow and performs interrupt processing according to the received interrupt processing request.

[0026] On the other hand, the present application provides a data receiving device, comprising: a memory, a transceiver, and a processor:

[0027] A memory for storing a computer program; a transceiver for transmitting and receiving data under the control of the processor; and a processor for reading the computer program in the memory and performing the following operations:

[0028] When the processor core is in an interrupt-enabled state, it responds to an interrupt processing request initiated by any network card receiving queue and enters interrupt processing;

[0029] Switch the interrupt enable state to the interrupt disable state, and process the data received by each network card receiving queue based on the polling NAPI method;

[0030] The interrupt disable state is switched back to the interrupt enable state. Within a preset time period, if no interrupt processing request is received from any network card receive queue, a real-time guarantee processing flow is executed. The real-time guarantee processing flow is used to ensure that there is no data to be processed in the multiple network card receive queues bound to the processor core.

[0031] Optionally, the processor is also used to:

[0032] If no interrupt processing request is received from any network card receiving queue within the preset time period, the process returns to the step of entering the interrupt processing.

[0033] Optionally, the processor is also used to:

[0034] When the interrupt disabled state is switched back to the interrupt enabled state, synchronously calling and controlling the current timer to start;

[0035] When the current timer continues to count until the timing duration is equal to the duration of the preset time period, the real-time guarantee processing flow is executed, or the processor core returns to the step of entering the interrupt processing.

[0036] Optionally, the processor is also used to:

[0037] During the process of the current timer continuously timing, if a timing cancellation request sent by a next timer is received, the current timer is reset and controlled to start timing again.

[0038] Optionally, the processor is also used to:

[0039] Determine whether there is a previous timer in a continuous timing state;

[0040] If so, a timing cancellation request is sent to the previous timer.

[0041] Optionally, the processor is also used to:

[0042] Scan the receiving queues of each network card in turn;

[0043] When it is determined that there is data to be processed in any network card receive queue among multiple network card receive queues, the interrupt of the processor core is actively triggered to perform interrupt processing, and the interrupt enable state is switched to the interrupt disable state, and the step of processing the data received by each network card receive queue in a polling NAPI-based manner is returned.

[0044] Optionally, the processor is further configured to:

[0045] When determining that any network card receiving queue among the plurality of network card receiving queues has data to be processed, monitoring whether the processor core responds to an interrupt processing request initiated by any network card receiving queue;

[0046] If so, the real-time guarantee processing flow is stopped, and interrupt processing is performed according to the received interrupt processing request.

[0047] On the other hand, the present application provides a data receiving device, wherein the receiving device is installed in any one processor core of a multi-core processor, and the processor core is bound to multiple network card receiving queues;

[0048] The device comprises:

[0049] An interrupt triggering unit, configured to respond to an interrupt processing request initiated by any network card receiving queue when the processor core is in an interrupt-enabled state;

[0050] A processing unit is configured to enter interrupt processing; and to switch the interrupt enable state to an interrupt disable state, processing data received by each network card receive queue based on a polling NAPI method; and further configured to switch the interrupt disable state back to an interrupt enable state, and within a preset time period, if the processor core does not receive an interrupt processing request initiated by any network card receive queue, execute a real-time guarantee processing flow, wherein the real-time guarantee processing flow is configured to ensure that there is no data to be processed in the multiple network card receive queues bound to the processor core.

[0051] On the other hand, the present application provides a processor-readable storage medium, wherein the processor-readable storage medium stores a computer program, and the computer program is used to enable the processor to execute any of the methods described above.

[0052] In a final aspect, the present application provides a computer program product, comprising a computer program, characterized in that when the computer program is executed by a processor, the steps of executing any one of the methods described above are implemented.

[0053] The present application provides a data receiving method, device and processor-readable storage medium. First, when the processor core is in an interrupt-enabled state, the processor core responds to an interrupt processing request initiated by any network card receiving queue and enters interrupt processing; the interrupt-enabled state is switched to an interrupt-disabled state, and the data received by each network card receiving queue is processed based on the polling NAPI method; the interrupt-disabled state is switched back to an interrupt-enabled state. Within a preset time period, if the processor core does not receive an interrupt processing request initiated by any network card receiving queue, a real-time guarantee processing flow is executed. The real-time guarantee processing flow is used to ensure that there is no data to be processed in the multiple network card receiving queues bound to the processor core. Through such a receiving method, it can be ensured that the data in the network card is received by the processor core within the specified time and sent to the network protocol stack. Compared with the existing technology, the probability of data reception delay is reduced, and the real-time performance of data communication is effectively improved.

[0054] It should be understood that the contents described in the above summary of the invention are not intended to limit the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in this application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0056] Figure 1 It is a network architecture provided by this application;

[0057] Figure 2 A flowchart of a method for receiving data of a processor core in the prior art is shown;

[0058] Figure 3 This is a flow chart of a data receiving method provided by this application;

[0059] Figure 4 This is a process flow diagram of a real-time guarantee process provided by this application;

[0060] Figure 5 This is a process flow diagram of another real-time assurance process provided by this application;

[0061] Figure 6 This is a flowchart of another data receiving method provided by the present application;

[0062] Figure 7A schematic diagram of the structure of a data receiving device provided in this application;

[0063] Figure 8 This is a structural diagram of another data receiving device provided by this application. DETAILED DESCRIPTION

[0064] The following description of exemplary embodiments of the present application is made in conjunction with the accompanying drawings, including various details of the embodiments of the present application to facilitate understanding. These details should be considered as merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present application. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0065] In response to the problem that in 5G network communications, when the data traffic is not large but low-latency signaling business processes are required, data reception is prone to delays and the real-time performance of communication is not high, the present application provides a data receiving method that can ensure that the data in the network card is received by the processor core within the specified time and sent to the network protocol stack, thereby reducing the probability of data reception delays and effectively improving the real-time performance of data reception.

[0066] Among them, the method and the device are based on the same application concept. Since the principles of solving problems by the method and the device are similar, the implementation of the device and the method can refer to each other, and the repeated parts will not be repeated.

[0067] It should be noted that the technical solutions provided in the embodiments of the present application can be applied to a variety of wireless communication systems.

[0068] For example, the applicable system can be a global system of mobile communication (GSM) system, a code division multiple access (CDMA) system, a wideband code division multiple access (WCDMA) general packet radio service (GPRS) system, a long term evolution (LTE) system, an LTE frequency division duplex (FDD) system, an LTE time division duplex (TDD) system, a long term evolution advanced (LTE-A) system, a universal mobile system (UMTS), a worldwide interoperability for microwave access (WiMAX) system, a 5G new radio (NR) system, etc. The various systems include terminal devices and network devices. The system can also include a core network part, such as an evolved packet system (EPS), a 5G system (5GS), etc.

[0069] In order to clearly understand the technical solutions of the present application, the prior art solutions are first described in detail.

[0070] Figure 1 A network architecture provided by the present application, as shown in Figure 1 The network architecture includes a terminal and a network device.

[0071] Among them, Figure 1 The terminal in the network architecture, also known as a terminal device, can be a device that provides voice and / or data connectivity to users, a handheld device with wireless connection function, or other processing devices connected to a wireless modem, etc.

[0072] In different systems, the name of the terminal device may also be different. For example, in the 5G system, the terminal device can be called User Equipment (UE). Wireless terminal devices can communicate with one or more core networks (CN) via the Radio Access Network (RAN). Wireless terminal devices can be mobile terminal devices, such as mobile phones (or "cellular" phones) and computers with mobile terminal devices, for example, portable, pocket-sized, handheld, computer-built-in, or vehicle-mounted mobile devices, which exchange voice and / or data with the radio access network.

[0073] For example, Personal Communication Service (PCS) phones, cordless phones, Session Initiated Protocol (SIP) phones, Wireless Local Loop (WLL) stations, Personal Digital Assistants (PDAs), etc. Wireless terminal devices may also be referred to as systems, subscriber units, subscriber stations, mobile stations, mobile stations, remote stations, access points, remote terminal devices, access terminal devices, user terminal devices, user agents, and user devices, but are not limited in the embodiments of the present application.

[0074] and Figure 1 The network devices in the network may specifically include base stations and servers. A base station may include multiple cells that provide services to terminals. Depending on the specific application scenario, a base station may also be called an access point, or may be a device in the access network that communicates with wireless terminal devices over the air interface through one or more sectors, or may be called something else. The network device may be used to interchange received air frames with Internet Protocol (IP) packets, acting as a router between the wireless terminal device and the rest of the access network, which may include an Internet Protocol (IP) communication network. The positioning server in the network device may also coordinate attribute management of the air interface.

[0075] In such Figure 1In the wireless communication system shown, when the terminal and the base station conduct 5G-based network communication, the network card of the terminal receives data sent by the base station, and the processor core of the terminal processes the data in the network card based on the interrupt plus polling NAPI method to send the data to the network protocol stack.

[0076] The data receiving method of NAPI based on processor interruption and polling is a commonly used data receiving method. Figure 2 FIG is a flow chart of a method for receiving data of a processor core in the prior art. It is known that, in actual situations, a terminal may include one or more processor cores, i.e., a single-core processor or a multi-core processor. In a multi-core processor, for example Figure 2 The process shown is multi-core parallel. For the convenience of representation, the figure only shows the processing flow of one processor core.

[0077] exist Figure 2 In the illustrated process, a processor core is bound to multiple network interface card (NIC) receive queues (i.e., NIC receive queue 1, NIC receive queue 2, ..., NIC receive queue n). The interrupt-enabled state means that the processor core's interrupt can be triggered, i.e., when the processor core receives an interrupt signal, it will enter the interrupt processing state. The interrupt-disabled state means that the processor core's interrupt cannot be triggered, i.e., when the processor core receives an interrupt signal, it will not enter the interrupt processing state.

[0078] like Figure 2 As shown, when the processor core is in the interrupt-enabled state, the network card receive queue 1 will initiate an interrupt request to the processor core after receiving data to trigger the processor core to enter interrupt processing; the processor core will switch from the interrupt-enabled state to the interrupt-disabled state and enter the soft interrupt processing.

[0079] At this point, the processor core begins polling and scanning each NIC receive queue. Specifically, the processor core scans each NIC receive queue in the order of NIC receive queue 1 to NIC receive queue n to determine whether any of them have pending data. If a NIC receive queue has pending data, the processor core receives the data and reports it to the network protocol stack. After processing all NIC data queues, the processor core re-enables interrupts and waits for the next interrupt to be triggered.

[0080] Among them, when the processor core is performing polling and scanning processing on each network card receiving queue, the processor core is continuously in an interrupt disabled state. That is to say, when the processor core is performing polling and scanning processing, if it receives an interrupt request initiated by a network card receiving queue, it will not respond to the interrupt request.

[0081] In addition, see further Figure 2When the processor core performs polling scanning, the processing round is 1 round, that is, for each network card receiving queue, the processor core will only determine once whether there is data to be processed in the network card receiving queue.

[0082] This leads to a problem: when the processor core scans NIC receive queue n, NIC receive queue 1 receives data. Because the processor core is in the interrupt-disabled state, NIC receive queue 1 cannot trigger the processor core to respond to its interrupt request. Moreover, because the processor core has already completed scanning NIC receive queue 1, the data currently received by NIC receive queue 1 cannot be processed while the processor core is processing this interrupt.

[0083] When the processor core is in the interrupt-enabled state and any network card receiving queue (such as Figure 2 After the network card receive queue 2 shown receives new data again, the processor core will respond to the interrupt request again. At this time, the data in the network card receive queue 1 that was not processed in the previous round of polling scanning will be processed in this round of polling scanning.

[0084] Obviously, since each processor core interrupt is triggered only when the NIC receive queue receives new data, if any NIC receive queue (such as NIC receive queue 1 mentioned above) contains data that was not processed during the current round of polling scanning, the time it takes for the processor core to trigger the interrupt again will be determined by the time it takes for the processor core to trigger the interrupt again. When data is sparse or network traffic is low, the processor core will not trigger an interrupt for a long time, and the reception time for this unprocessed data will be longer, causing data delay.

[0085] This phenomenon not only occurs on single-core processors, but also has more obvious delays on multi-core processors: because multi-core processors use the load-balanced data processing principle when receiving data from the network card receive queue, that is, each processor core works as evenly as possible. When the data is relatively sparse or the network traffic is small, the time it takes to receive the unprocessed data increases exponentially compared to a single-core processor, greatly reducing the real-time communication and not conducive to meeting the diverse needs of the business.

[0086] Based on this, the present application came into being. In order to improve the efficiency of data reception, the inventor considered that on the basis of the existing interrupt polling NAPI method, within a preset time period, if the processor core does not receive an interrupt processing request initiated by any network card receiving queue, a real-time guarantee processing process will be executed so that before the processor core enters a new round of interrupt triggering, there is no data to be processed in the multiple network card receiving queues bound to the processor core.

[0087] By setting up a real-time guarantee processing flow, it can be ensured that the data in the network card is received by the processor core and sent to the network protocol stack within the specified time. Compared with the existing technology, the probability of delay in data reception is reduced, and the real-time performance of data communication is effectively improved.

[0088] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0089] Example 1

[0090] In the first embodiment, a method for receiving data based on the inventive concept of the present application is provided. In this method, Figure 1 The terminal in the network device serves as the execution subject to perform data reception processing. The receiving method is applicable to any processor core in a multi-core processor, wherein the processor core is bound to multiple network card receiving queues.

[0091] Specifically, Figure 3 This is a flow chart of a data receiving method provided by this application, combined with Figure 3 The data receiving method provided in this embodiment includes the following steps:

[0092] Step 101: When the processor core is in an interrupt-enabled state, the processor core responds to an interrupt processing request initiated by any network card receiving queue and enters interrupt processing.

[0093] Step 102: Switch the interrupt enable state to the interrupt disable state, and process the data received by each network card receiving queue based on the polling NAPI method.

[0094] Specifically, similar to the prior art, when any network interface card receive queue bound to a processor core receives data, the processor core's current state must first be determined. If the processor core is interrupt-enabled, the network interface card receive queue initiates an interrupt request to the processor core, which responds to the received interrupt request. At this point, the processor core initiates interrupt processing, specifically, entering the interrupt service routine.

[0095] Subsequently, the state of the processor core will be switched from the interrupt enabled state to the interrupt disabled state, and enter the soft interrupt processing. In the soft interrupt processing, the processor core will scan each network card receiving queue in turn based on the polling NAPI mode, and check whether each network card receiving queue has data to be processed to be received based on the arrangement order of the network card receiving queues. When there is data to be processed in a network card receiving queue, the processor core will receive the data and report it to the network protocol stack until the scanning of all network card data queues is completed. Of course, in this process, the processing round of the processor core is 1 round when performing the polling scanning processing, that is, for each network card receiving queue, the processor core will only determine once whether the network card receiving queue has data to be processed.

[0096] Step 103, re-switch the interrupt disabled state to the interrupt enabled state, and if the processor core does not receive an interrupt processing request initiated from any network card receiving queue within a preset time period, execute the real-time guarantee processing procedure, which is used to make the processor core bound to multiple network card receiving queues not have data to be processed.

[0097] Because in actual situations, it is easy to appear that a network card receiving queue receives data to be processed after completing the polling of the current round, and the newly received data cannot be processed in this polling.

[0098] When facing this situation, unlike the prior art, the real-time guarantee processing procedure is further provided in the scheme to make the processor core receive the data to be processed of the multiple network card receiving queues bound thereto if the processor core does not receive an interrupt processing request initiated from any network card receiving queue within a preset time period.

[0099] Specifically, when executing the real-time guarantee processing procedure, the processor core can include the following steps: scanning each network card receiving queue in turn; when determining that there is data to be processed in any network card receiving queue of the multiple network card receiving queues, the processor core actively triggers an interrupt to perform interrupt processing, and switches the interrupt enabled state to the interrupt disabled state, and returns to the step of processing the data received by each network card receiving queue based on the polling NAPI mode.

[0100] That is, the essence of the real-time guarantee processing procedure is that when determining that there is data to be processed in any network card receiving queue of the multiple network card receiving queues, the processor core actively performs an interrupt processing and a polling processing procedure once.

[0101] This approach allows newly received data to be processed and reported to the network protocol stack during the polling process within the processor core's real-time assurance process. The processing time for newly received data no longer depends on the next interrupt triggered by the processor core, significantly improving processing efficiency and reducing latency.

[0102] The startup and execution of the real-time guarantee processing flow can be understood as the processor core calling and executing functions, components, or processes that can achieve real-time guarantee processing. By running the functions, components, or processes, the functions of scanning, determining, and setting various status flags of the processor core status can be realized.

[0103] Figure 4 This is a process flow diagram of a real-time guarantee process provided by this application, such as Figure 4 As shown, when the real-time guarantee process is started, the first relevant status bit of the processor core is first set to the "entering process" flag bit to indicate that the processor core is executing the real-time guarantee process.

[0104] Then, starting with NIC data queue 1 bound to the processor core, NIC data queue 1 is scanned to determine whether there is any data to be received in NIC data queue 1. After completing the scan and determination of NIC data queue 1, the same data scan and determination of data to be received are performed on NIC data queue 2 bound to it. This process is repeated until all NIC data queues are scanned and the data to be received is determined.

[0105] Of course, in this process, when it is determined that there is data to be received in a certain network card data queue, the second relevant status bit of the processor core will be set to the "active trigger interrupt" flag bit to indicate that the data to be processed needs to be received and processed at this time.

[0106] After completing the data scan of all network card data queues and determining the data to be received, the processor core's first status bit is set to the "exit processing" flag, indicating that the processor core is no longer executing the real-time guarantee process. Simultaneously, a check is performed to determine whether the second status bit is set to the "actively triggered interrupt" flag. If so, the processor core's hardware actively triggers an interrupt, and the processor core responds to the actively triggered interrupt and performs interrupt processing. If not, the real-time guarantee process can be directly exited.

[0107] Because a real-time guaranteed processing flow is adopted to determine whether there is data to be processed in the current network card receiving queue, and the relevant flag bit is used to indicate the determination result, the processor core can directly execute the active triggering or exit processing process according to the status indicated by the flag bit, thereby improving data processing efficiency.

[0108] Because the processor core is interrupt-enabled while executing the real-time guarantee process, it is possible for the processor core to receive an interrupt request from any network card receive queue while executing the real-time guarantee process. In this case, the processor core will exit the real-time guarantee process and choose to respond to the interrupt request from any network card receive queue. That is, in an optional embodiment, if the processor core receives an interrupt request from any network card receive queue within a preset time period, the processor core returns to the interrupt processing step.

[0109] Specifically, when it is determined that there is data to be processed in any network card receive queue among multiple network card receive queues, it will also monitor whether the processor core responds to the interrupt processing request initiated by any network card receive queue; if so, the processor core stops executing the real-time guarantee processing flow and performs interrupt processing according to the received interrupt processing request.

[0110] exist Figure 4 On the basis of Figure 5 This is a schematic diagram of another process flow of real-time guarantee processing provided by the present application. As previously mentioned, when the processor core is in the real-time guarantee processing process, if it receives an interrupt request sent by any network card receive queue, the process will monitor the change of the processor core interrupt enable state. At this time, the first relevant status bit of the processor core will be set to the "exit processing" flag bit to indicate that the processor core is no longer executing the real-time guarantee processing process. At the same time, it is determined whether the second relevant status bit is set to the "actively triggered interrupt" flag bit. If so, the second relevant status bit is set to the "non-actively triggered interrupt" flag bit. If not, it exits directly.

[0111] exist Figure 5 In the illustrated approach, the addition of a corresponding monitoring process ensures that if a processor core is executing the real-time guarantee process while simultaneously responding to an interrupt request initiated by any network card receive queue, the real-time guarantee process will exit and cease execution. At this point, the newly received data will be processed along with the currently responding interrupt, further improving processing efficiency and avoiding the additional system overhead associated with processing the newly received data simultaneously by the real-time guarantee process and the currently responding interrupt.

[0112] Figure 6This is a flow chart of another data receiving method provided by this application, such as Figure 6 As shown, based on the above embodiments, the method includes:

[0113] Step 201: When the processor core is in an interrupt-enabled state, the processor core responds to an interrupt processing request initiated by any network card receiving queue and enters interrupt processing;

[0114] Step 202: Switch the interrupt enable state to the interrupt disable state, and process the data received by each network card receiving queue based on the polling NAPI method;

[0115] Step 203: Switch the interrupt disabled state back to the interrupt enabled state, and the processor core synchronously calls and controls the current timer to start;

[0116] Step 204: the current timer continues timing until the timing duration is equal to the duration of the preset time period, and determines whether the processor core receives an interrupt processing request initiated by any network card receiving queue;

[0117] If yes, return to step 201; if no, execute step 205.

[0118] Step 205: Execute a real-time guarantee processing flow, wherein the real-time guarantee processing flow is used to ensure that there is no data to be processed in the receiving queues of the multiple network cards bound to the processor core.

[0119] Step 201 and step 202 in this embodiment are similar to step 101 and step 102 in the aforementioned embodiment, and this embodiment does not limit this.

[0120] Different from the above embodiments, based on the above embodiments, in order to ensure that the data is processed and received within a preset time period, a timer is also provided in the present application to ensure that the data processing time is fixed within the preset time period.

[0121] Specifically, when the processor core switches the interrupt disable state back to the interrupt enable state, the processor core synchronously calls and controls the start of the current timer; wherein, the current timer continues timing until the timing duration is equal to the duration of the preset time period, and the processor core executes the real-time guarantee processing flow, or the processor core executes the step of returning to the step of entering the interrupt processing.

[0122] The length of the preset time period can be determined based on actual conditions, for example, 100 μs. For example, when the interrupt disable state is switched back to the interrupt enable state, the current timer is controlled to start, so that the current timer begins timing. Once the current timer reaches 100 μs, the processor core will begin executing the aforementioned real-time performance guarantee process.

[0123] For timers, their number is indefinite. That is to say, at the same moment, there may be multiple timers timing. In order to avoid redundant data processing, in an optional implementation, before the processor core synchronously calls and controls the start of the current timer, it will also determine whether there is a previous timer in a continuous timing state; if so, a timing cancellation request is sent to the previous timer so that the previous timer no longer times (that is, the real-time guarantee processing flow after reaching the corresponding timing duration will not be executed). In this way, the real-time guarantee processing flow that has not yet been executed can be canceled in advance, thereby saving the operating overhead of the processor core.

[0124] If the processor core may receive a new interrupt request while the current timer is timing, the processor core will respond to the new interrupt request and execute a NAPI process of interrupt polling to perform timing, and start a new timer (i.e., the next timer) after processing. At this time, the data that should have been processed by the real-time guarantee processing flow after this timing will be processed during the NAPI processing of the new interrupt polling, that is, the real-time guarantee processing flow after this timing will not process data. At this time, in order to save the operating overhead of the processor core, the current timer will receive a timing cancellation request sent by the next timer, and then reset the current timer and control the current timer to re-time. In this way, the operating overhead can be reduced and the data processing efficiency of the processor core can be further improved.

[0125] The present application provides a data receiving method. First, when the processor core is in an interrupt-enabled state, the processor core responds to an interrupt processing request initiated by any network card receiving queue and enters interrupt processing; the interrupt-enabled state is switched to an interrupt-disabled state, and the data received by each network card receiving queue is processed based on a polling NAPI method; the interrupt-disabled state is switched back to an interrupt-enabled state. Within a preset time period, if the processor core does not receive an interrupt processing request initiated by any network card receiving queue, a real-time guarantee processing flow is executed. The real-time guarantee processing flow is used to ensure that there is no data to be processed in the multiple network card receiving queues bound to the processor core. Through such a receiving method, it can be ensured that the data in the network card is received by the processor core within the specified time and sent to the network protocol stack. Compared with the existing technology, the probability of data reception delay is reduced, and the real-time performance of data communication is effectively improved.

[0126] Example 2

[0127] Figure 7 This is a schematic diagram of the structure of a data receiving device provided by this application. Figure 7 As shown, the data receiving device includes:

[0128] The system includes a memory 820, a transceiver 800, and a processor 810.

[0129] Memory 820, for storing computer programs;

[0130] The transceiver 800 is configured to transmit and receive data under the control of the processor 810;

[0131] The processor 810 is configured to read the computer program in the memory 820 and perform the following operations:

[0132] When the processor core is in an interrupt-enabled state, it responds to an interrupt processing request initiated by any network card receiving queue and enters interrupt processing;

[0133] Switch the interrupt enable state to the interrupt disable state, and process the data received by each network card receiving queue based on the polling NAPI method;

[0134] The interrupt disable state is switched back to the interrupt enable state. Within a preset time period, if no interrupt processing request is received from any network card receive queue, a real-time guarantee processing flow is executed. The real-time guarantee processing flow is used to ensure that there is no data to be processed in the multiple network card receive queues bound to the processor core.

[0135] Optionally, the processor 810 is further configured to:

[0136] If no interrupt processing request is received from any network card receiving queue within the preset time period, the process returns to the step of entering the interrupt processing.

[0137] Optionally, the processor 810 is further configured to:

[0138] When the interrupt disable state is switched back to the interrupt enable state, the current timer is synchronously called and controlled to start; when the current timer continues timing until the timing duration is equal to the duration of the preset time period, the real-time guarantee processing flow is executed, or the processor core executes the step of returning to the interrupt processing entry.

[0139] Optionally, the processor 810 is further configured to:

[0140] During the process of the current timer continuously timing, if a timing cancellation request sent by a next timer is received, the current timer is reset and controlled to start timing again.

[0141] Optionally, the processor 810 is further configured to:

[0142] Determine whether there is a previous timer in a continuous timing state; if so, send a timing cancellation request to the previous timer.

[0143] Optionally, the processor 810 is further configured to:

[0144] Scan each network card receiving queue in turn; when it is determined that there is data to be processed in any network card receiving queue among multiple network card receiving queues, actively trigger the interrupt of the processor core to perform interrupt processing, and switch the interrupt enable state to the interrupt disable state, and return to the step of processing the data received by each network card receiving queue in a polling NAPI-based manner.

[0145] Optionally, the processor 810 is further configured to:

[0146] When it is determined that there is data to be processed in any network card receiving queue among multiple network card receiving queues, monitor whether the processor core responds to the interrupt processing request initiated by any network card receiving queue; if so, stop executing the real-time guarantee processing flow and perform interrupt processing according to the received interrupt processing request.

[0147] Specifically, the transceiver 800 is configured to receive and transmit data under the control of the processor 810 .

[0148] Among them, Figure 7 In the embodiment, the bus architecture may include any number of interconnected buses and bridges, specifically various circuits of one or more processors represented by processor 810 and memory represented by memory 820, which are linked together. The bus architecture may also link together various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and are therefore not further described herein. The bus interface provides an interface. The transceiver 800 may be a plurality of components, namely a transmitter and a receiver, providing a unit for communicating with various other devices on a transmission medium, such as a wireless channel, a wired channel, an optical cable, and the like. For different user devices, the user interface z30 may also be an interface capable of connecting external or internal devices as required, and the connected devices include but are not limited to a keypad, a display, a speaker, a microphone, a joystick, and the like.

[0149] The processor 810 is responsible for managing the bus architecture and general processing, and the memory 820 can store data used by the processor 600 when performing operations.

[0150] Optionally, the processor 810 may be a CPU (central processing unit), an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array) or a CPLD (Complex Programmable Logic Device), and the processor may also adopt a multi-core architecture.

[0151] The processor 810 is configured to execute any of the methods provided in the embodiments of the present application according to the obtained executable instructions by calling the computer program stored in the memory. The processor and the memory may also be physically separated.

[0152] It should be noted here that the above-mentioned device provided in this application can implement all the method steps implemented in the above-mentioned method embodiment 1, and can achieve the same technical effects. The parts and beneficial effects of this embodiment that are the same as those of the method embodiment will not be described in detail here.

[0153] Example 3

[0154] Figure 8 This is a structural diagram of another data receiving device provided by this application. The data receiving device is installed in any processor core in a multi-core processor, and the processor core is bound to multiple network card receiving queues, such as Figure 8 As shown, the receiving device includes:

[0155] An interrupt triggering unit 11 is configured to respond to an interrupt processing request initiated by any network card receiving queue when the processor core is in an interrupt-enabled state;

[0156] The processing unit 12 is used to enter interrupt processing; and switch the interrupt enable state to the interrupt disable state, and process the data received by each network card receive queue based on the polling NAPI method; and is also used to switch the interrupt disable state back to the interrupt enable state. Within a preset time period, if the processor core does not receive an interrupt processing request initiated by any network card receive queue, a real-time guarantee processing flow is executed, and the real-time guarantee processing flow is used to ensure that there is no data to be processed in the multiple network card receive queues bound to the processor core.

[0157] Optionally, within a preset time period, if the interrupt triggering unit 11 does not receive an interrupt processing request initiated by any network card receiving queue, the processing unit 12 returns to execute the step of entering the interrupt processing.

[0158] Optionally, the processing unit 12 is used to synchronously call and control the start of the current timer when the interrupt disable state is switched back to the interrupt enable state; when the current timer continues to time until the timing duration is equal to the duration of the preset time period, the real-time guarantee processing flow is executed, or the processor core executes the step of returning to the interrupt processing entry.

[0159] Optionally, the processing unit 12 is configured to reset the current timer and control the current timer to re-time if a timing cancellation request is received from a next timer during the process of the current timer continuing to time.

[0160] Optionally, the processing unit 12 is further configured to: determine whether there is a previous timer in a continuous timing state; if so, send a timing cancellation request to the previous timer.

[0161] Optionally, the processing unit 12 is also used to: scan each network card receiving queue in sequence; when it is determined that there is data to be processed in any network card receiving queue among the multiple network card receiving queues, actively trigger the interrupt of the processor core to perform interrupt processing, and switch the interrupt enable state to the interrupt disable state, and return to execute the step of processing the data received by each network card receiving queue in a polling NAPI-based manner.

[0162] Optionally, when it is determined that there is data to be processed in any network card receiving queue among multiple network card receiving queues, the interrupt triggering unit 11 is used to monitor whether the processor core responds to the interrupt processing request initiated by any network card receiving queue; if so, the processing unit 12 is used to stop executing the real-time guarantee processing process and perform interrupt processing according to the received interrupt processing request.

[0163] It should be noted that the division of units in the embodiments of the present application is schematic and is merely a logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0164] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a processor-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0165] Example 4

[0166] The present application also provides a processor-readable storage medium, wherein the processor-readable storage medium stores a computer program, and the computer program is used to enable the processor to execute the method of the aforementioned embodiment 1 of claim 1.

[0167] The processor-readable storage medium can be any available medium or data storage device that can be accessed by the processor, including but not limited to magnetic storage (such as floppy disks, hard disks, magnetic tapes, magneto-optical disks (MO)), optical storage (such as CDs, DVDs, BDs, HVDs, etc.), and semiconductor storage (such as ROMs, EPROMs, EEPROMs, non-volatile memories (NANDFLASH), solid-state drives (SSDs)), etc.

[0168] In addition, the present application provides a computer program product, including a computer program, characterized in that when the computer program is executed by a processor, the steps of the method described in the above embodiment 1 are implemented.

[0169] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage and optical storage, etc.) that contain computer-usable program code.

[0170] The computer executable instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operations steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart Figure 1 one or more flows and / or functions specified in the flowchart Figure 1 one or more blocks or steps in the flowchart

[0171] These processor-executable instructions can also be stored in a processor-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the processor-readable memory produce an article of manufacture including instructions which implement the functions specified in the flowchart Figure 1 one or more flows and / or functions specified in the flowchart Figure 1 one or more blocks or steps in the flowchart

[0172] These processor-executable instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operations steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart Figure 1 one or more flows and / or functions specified in the flowchart Figure 1 one or more blocks or steps in the flowchart

Claims

1. A method for receiving data, characterized in that: The method is applicable to any processor core in a multi-core processor, wherein the processor core is bound to multiple network card receiving queues; The method includes: When the processor core is in an interrupt-enabled state, the processor core responds to an interrupt processing request initiated by any network card receiving queue and enters interrupt processing; Switch the interrupt enable state to the interrupt disable state, and process the data received by each network card receiving queue based on the polling NAPI method; The interrupt disable state is switched back to the interrupt enable state. Within a preset time period, if the processor core does not receive an interrupt processing request initiated by any network card receive queue, a real-time guarantee processing flow is executed. The real-time guarantee processing flow is used for, when it is determined that there is data to be processed in any network card receive queue among multiple network card receive queues, the processor core actively executes an interrupt processing and polling processing flow, so that there is no data to be processed in the multiple network card receive queues bound to the processor core.

2. The receiving method according to claim 1, wherein: Also includes: Within a preset time period, if the processor core receives an interrupt processing request initiated by any network card receiving queue, the processor core executes the step of returning to the step of entering the interrupt processing.

3. The receiving method according to claim 1 or 2, characterized in that Also includes: When the processor core switches the interrupt disabled state back to the interrupt enabled state, the processor core synchronously calls and controls the current timer to start; The current timer continues timing until the timing duration is equal to the duration of the preset time period, and the processor core executes the real-time guarantee processing flow, or the processor core executes the step of returning to the interrupt processing step.

4. The receiving method according to claim 3, wherein: Also includes: During the process of the current timer continuously timing, if a timing cancellation request sent by a next timer is received, the current timer is reset and controlled to start timing again.

5. The receiving method according to claim 3, wherein: Before the processor core synchronously calls and controls the start of the current timer, the process further includes: Determine whether there is a previous timer in a continuous timing state; If so, a timing cancellation request is sent to the previous timer. The receiving method according to claim 1 , wherein: If the processor core does not receive an interrupt processing request initiated by any network card receiving queue, the real-time guarantee processing flow is executed, including: Scan the receiving queues of each network card in turn; When it is determined that there is data to be processed in any network card receive queue among multiple network card receive queues, the processor core actively triggers an interrupt to perform interrupt processing, switches the interrupt enable state to an interrupt disable state, and returns to the step of processing the data received by each network card receive queue based on the polling NAPI method.

7. The receiving method according to claim 6, wherein: When it is determined that any network card receiving queue among the multiple network card receiving queues has data to be processed, the method further includes: monitoring whether the processor core responds to an interrupt processing request initiated by any network card receiving queue; If so, the processor core stops executing the real-time guarantee processing flow and performs interrupt processing according to the received interrupt processing request.

8. A data receiving device, characterized in that: Including memory, transceiver, processor: A memory for storing a computer program; a transceiver for transmitting and receiving data under the control of the processor; and a processor for reading the computer program in the memory and performing the following operations: When the processor core is in an interrupt-enabled state, it responds to an interrupt processing request initiated by any network card receiving queue and enters interrupt processing; Switch the interrupt enable state to the interrupt disable state, and process the data received by each network card receiving queue based on the polling NAPI method; The interrupt disable state is switched back to the interrupt enable state. Within a preset time period, if no interrupt processing request is received from any network card receive queue, a real-time guarantee processing flow is executed. The real-time guarantee processing flow is used for, when it is determined that there is data to be processed in any network card receive queue among the multiple network card receive queues, the processor core actively executes an interrupt processing and polling processing flow, so that there is no data to be processed in the multiple network card receive queues bound to the processor core.

9. The receiving device according to claim 8, wherein Processor, also used for: If no interrupt processing request is received from any network card receiving queue within the preset time period, the process returns to the step of entering the interrupt processing.

10. The receiving device according to claim 8 or 9, characterized in that Processor, also used for: When the interrupt disabled state is switched back to the interrupt enabled state, synchronously calling and controlling the current timer to start; When the current timer continues to count until the timing duration is equal to the duration of the preset time period, the real-time guarantee processing flow is executed, or the processor core returns to the step of entering the interrupt processing.

11. The receiving device according to claim 10, wherein: Processor, also used for: During the process of the current timer continuously timing, if a timing cancellation request sent by a next timer is received, the current timer is reset and controlled to start timing again.

12. The receiving device according to claim 10, wherein: Processor, also used for: Determine whether there is a previous timer in a continuous timing state; If so, a timing cancellation request is sent to the previous timer.

13. The receiving device according to claim 9, wherein: Processor, also used for: Scan the receiving queues of each network card in turn; When it is determined that there is data to be processed in any network card receive queue among multiple network card receive queues, the interrupt of the processor core is actively triggered to perform interrupt processing, and the interrupt enable state is switched to the interrupt disable state, and the step of processing the data received by each network card receive queue in a polling NAPI-based manner is returned.

14. The receiving device according to claim 13, wherein: The processor is further configured to: When determining that any network card receiving queue among the plurality of network card receiving queues has data to be processed, monitoring whether the processor core responds to an interrupt processing request initiated by any network card receiving queue; If so, the real-time guarantee processing flow is stopped, and interrupt processing is performed according to the received interrupt processing request.

15. A data receiving device, characterized in that: The receiving device is installed in any one processor core of a multi-core processor, and the processor core is bound to multiple network card receiving queues; The device comprises: An interrupt triggering unit, configured to respond to an interrupt processing request initiated by any network card receiving queue when the processor core is in an interrupt-enabled state; A processing unit is used to enter interrupt processing; and switch the interrupt enable state to an interrupt disable state, and process the data received by each network card receive queue based on the polling NAPI method; and is also used to switch the interrupt disable state back to the interrupt enable state. Within a preset time period, if the processor core does not receive an interrupt processing request initiated by any network card receive queue, a real-time guarantee processing flow is executed. The real-time guarantee processing flow is used for, when it is determined that there is data to be processed in any network card receive queue among multiple network card receive queues, the processor core actively executes an interrupt processing and polling processing flow, so that there is no data to be processed in the multiple network card receive queues bound to the processor core.

16. A processor-readable storage medium, characterized in that: The processor-readable storage medium stores a computer program, and the computer program is configured to cause the processor to execute the method according to any one of claims 1 to 7.

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