A system and method for hot plug protection of an FPGA system peripheral expansion device

Abstract

The application provides a hot plug protection system of a peripheral expansion device of an FPGA prototype verification system, comprising a hot plug processing device and a processing module; the hot plug processing device comprises a judgment module and a protection module; the judgment module and the protection module are electrically connected with the peripheral expansion device; the processing module is arranged in the FPGA prototype verification system; wherein the judgment module judges the power connection state of the FPGA prototype verification system and sends to the protection module and the processing module; according to a first authentication strategy, the peripheral expansion device of the FPGA prototype verification system can be released or locked in the power-off state; according to a second authentication strategy, the peripheral expansion device of the FPGA prototype verification system is subjected to power-off processing or early warning processing in the power-on state. The application also provides a hot plug protection method of the peripheral expansion device of the FPGA prototype verification system. The application provides a real intervention sub-card hot plug mode.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuits, and particularly relates to a protection system and method for hot removal of a peripheral expansion device of an FPGA system. BACKGROUND

[0002] Generally, in the prototype verification of a chip design in an FPGA prototype verification system, that is, when an FPGA chip is debugged and programmed, an FPGA board needs to be used, and the FPGA board is a PCB printed circuit board with as many as ten layers.

[0003] In the PCB printed circuit board, the communication mode of the FPGA logic system and the peripheral circuit is mainly achieved through the on-board connector. The connected channels are mainly divided into two categories: daughter cards and cables. The male connector of the daughter card / cable and the female connector of the FPGA mainboard are closely combined to realize the communication on the circuit and the interaction in the function.

[0004] At present, the FPGA system itself does not have the support for hot plug performance. Therefore, under the condition of power-on, due to the hot plug under the misoperation or unknown condition, the IO pin of the FPGA is easily damaged. From the electrical characteristics, such damage is irreversible, that is, it cannot be repaired. When the damaged pin reaches a certain scale, the debug IO interface of the FPGA system will be greatly reduced; for the design that needs a large number of debug IO, the work will be greatly affected. At present, the only way to repair is to replace the FPGA main chip. Because the cost of a middle and high-end FPGA chip is very expensive, several ten thousand or even several hundred thousand yuan per chip; therefore, such a method will bring very expensive repair cost. From the current FPGA prototype verification market, no manufacturer has really provided an intervention mode for the hot plug of the daughter card.

[0005] In addition, the number of interconnection interfaces in the prior art FPGA prototype verification system is relatively small, and it is difficult to additionally design the functions without affecting the main functions of the FPGA prototype verification system, thereby increasing the technical difficulty.

[0006] Based on the above, the present application provides a technical solution to solve the above technical problems. SUMMARY

[0007] The first object of the present application is to obtain a FPGA system peripheral expansion device removal early warning system.

[0008] The second object of the present application is to obtain a prototype verification system with a FPGA system peripheral expansion device removal early warning system.

[0009] The third object of the present application is to obtain a FPGA system peripheral expansion device removal early warning method.

[0010] The first aspect of the present application provides a hot plug protection system of a peripheral expansion device of a FPGA prototype verification system, the hot plug processing system comprising a hot plug processing device and a processing module;

[0011] The hot plug processing device comprises a judgment module and a protection module, and the hot plug processing device is arranged near the peripheral expansion device of the peripheral FPGA prototype verification system; the judgment module and the protection module are electrically connected with the peripheral expansion device of the FPGA prototype verification system;

[0012] The processing module is arranged in the FPGA prototype verification system;

[0013] Among them,

[0014] According to a preset judgment strategy, the judgment module is configured to judge the power connection state of the FPGA prototype verification system, obtain power connection state information that the FPGA prototype verification system is in a power-on state or a power-off state, and send the power connection state information to the protection module and the processing module;

[0015] According to a preset first authentication strategy, the protection module is configured to release or lock the peripheral expansion device of the FPGA prototype verification system when the FPGA prototype verification system is in a power-off state,

[0016] According to a preset second authentication strategy, when the FPGA prototype verification system is in a power-on state, the processing module is configured to perform power-off processing or early warning processing on the peripheral expansion device of the FPGA prototype verification system.

[0017] In one specific embodiment of the present application, after the processing module performs power-off processing on the peripheral expansion device of the FPGA prototype verification system, according to a preset first authentication strategy, the peripheral expansion device of the FPGA prototype verification system can be released or locked.

[0018] The judgment module comprises a voltage decision module or a current decision module;

[0019] The protection module comprises a fixing device for releasing or locking the peripheral expansion device of the FPGA prototype verification system; and / or

[0020] The processing module comprises a system on chip.

[0021] In one embodiment, the fixing device is a screw fixing device.

[0022] Preferably, the judging module is a voltage judging module. Specifically, when not powered, the connector is 0V, and when powered, it is 1.8V or 3.3V.

[0023] Alternatively, the judging module is a current judging module. In terms of current, it can also be judged that the FPGA system has no current when not powered, and has current when powered.

[0024] In one embodiment of the present application, the hot-plug protection device further comprises an authentication unit, the authentication unit comprising a biological information recognition module, a first storage unit;

[0025] The first storage unit is configured to store a biological information database of legitimate users, and the biological information recognition unit identifies illegal users and legitimate users according to the biological information of the legitimate users.

[0026] The biological information can be fingerprint, iris, or a combination thereof. Preferably, fingerprint is used.

[0027] In one embodiment, the fixing device releases or locks the peripheral expansion device of the FPGA prototype verification system according to the authentication result fed back by the authentication unit and according to a preset first authentication strategy.

[0028] In one embodiment, the processing module releases or performs early warning processing on the peripheral expansion device of the FPGA prototype verification system according to the authentication result fed back by the authentication unit and according to a preset second authentication strategy.

[0029] In one embodiment of the present application, the FPGA prototype verification system comprises an FPGA mainboard unit and a power supply control unit, characterized in that the peripheral expansion device of the FPGA prototype verification is electrically connected to the FPGA mainboard unit, and the processing module is arranged in the power supply control unit.

[0030] In one embodiment of the present application, the FPGA mainboard unit is a plurality of FPGA mainboard units.

[0031] In one embodiment of the present application, the power supply control unit comprises a system on chip (SOC chip).

[0032] The processing module arranged in the power supply control unit comprises: the processing module is arranged in the system on chip (SOC chip).

[0033] In one embodiment of the present application, the system on chip (SOC chip) can control the power-on or power-off operation of the upper FPGA board.

[0034] In one embodiment of the present application, the FPGA prototype verification system further comprises a second storage unit for storing or recording a database of biological information of legitimate users and / or the prompt information.

[0035] In one embodiment, the record is stored in a second Flash chip. More specifically, the Flash chip is arranged on a PCM board on a power control board.

[0036] Preferably, the first storage unit stores biological information, and the second storage unit stores or records a database of biological information of legitimate users and the prompt information.

[0037] Preferably, the biological information is a fingerprint. Alternatively, an iris or other biological information that can identify legitimate users can be used, or a combination thereof can be used.

[0038] The second aspect of the present application provides an FPGA prototype verification system comprising the hot-plug protection system of the present application.

[0039] The third aspect of the present application provides a hot-plug protection method for a peripheral expansion device of an FPGA prototype verification system, which is applicable to the hot-plug protection system of the present application and the FPGA prototype verification system of the present application. The hot-plug protection method comprises:

[0040] According to a predetermined judgment strategy, the judgment module judges the power connection state of the FPGA prototype verification system to obtain power connection state information that the FPGA prototype verification system is in a power-on state or a power-off state, and sends the power connection state information to the protection module and the processing module;

[0041] According to a predetermined first authentication strategy, the protection module releases or locks the peripheral expansion device of the FPGA prototype verification system when the FPGA prototype verification system is in a power-off state,

[0042] According to a predetermined second authentication strategy, the processing module performs release processing or early warning processing on the peripheral expansion device of the FPGA prototype verification system when the FPGA prototype verification system is in a power-on state.

[0043] In one embodiment of the present application, the processing module performs a power-off operation on the peripheral expansion device of the FPGA prototype verification system.

[0044] In one embodiment of the present application, the early warning processing comprises providing prompt information.

[0045] The prompt information includes first prompt information and second prompt information, the first prompt information includes information prompted by an LED lamp, and the second prompt information includes information prompted by a buzzer.

[0046] The present application can bring at least one of the following benefits:

[0047] 1. Not only can effectively reduce the damage of IO interface caused by misoperation hot pullout, but also can actively intervene in the hot plug phenomenon;

[0048] 2. The existing resources on the existing FPGA system are utilized, and no additional module or circuit is needed to realize the early warning function, so that the effective early warning function is realized without increasing additional cost.

[0049] 3. The problem of hot plug of the daughter card which is difficult to solve for a long time can be actively intervened. BRIEF DESCRIPTION OF DRAWINGS

[0050] The above characteristics, technical features, advantages and implementation modes will be further described in the following preferred embodiments in a clear and understandable manner combined with the drawings.

[0051] Figure 1 A plurality of FPGA board systems are shown;

[0052] Figure 2 The overall structure of a commonly used FPGA system is shown;

[0053] Figure 3 The connector and fixing screw hole of the daughter card are shown;

[0054] Figure 4 The FPGA system part structure diagram with daughter card protection lock is shown;

[0055] Figure 5 The FPGA system element distribution structure diagram is shown;

[0056] Figure 6 The body structure diagram of the daughter card protection device (lock) is shown;

[0057] Figure 7 The fingerprint set data acquisition flowchart is shown;

[0058] Figure 8 The flowchart of software control power-off and pullout of the daughter card is shown. DETAILED DESCRIPTION

[0059] In the present application, the inventor has found through extensive and in-depth experiments that, as long as the IO interface damage caused by hot removal due to misoperation is effectively reduced, the working efficiency and design accuracy during FPGA system debugging can be greatly improved; more importantly, hot removal is prevented through an authentication strategy. In addition, the technical solution provided by the present application utilizes various existing resources on the existing FPGA system, without the need to add additional modules or circuits to realize the early warning function, thereby realizing effective protection function without increasing additional costs.

[0060] Unless otherwise defined and limited, the "or" in the present application contains the "and" relationship. The "and" corresponds to the Boolean logic operator "AND", the "or" corresponds to the Boolean logic operator "OR", and the "AND" is a subset of the "OR".

[0061] Unless otherwise defined and limited, the terms "connected", "communicated", "connected" in the present application should be understood in a broad sense, for example, it can be fixedly connected, or connected through an intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0062] Herein, terms such as "top", "bottom", "above", "below", "on", "under" and the like are used to describe the relationship of one element, layer or region relative to another element, layer or region as shown in the drawings. It can be understood that, in addition to the orientation described in the drawings, these terms should also include other orientations of the device.

[0063] It can be understood that, although the terms "first", "second" and the like can be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, the first element can be called the second element without departing from the teachings of the present inventive concept.

[0064] The various aspects of the present application are described below:

[0065] Hot removal protection system

[0066] The hot plug protection system of the peripheral expansion device of the FPGA prototype verification system, a hot plug protection system of a peripheral expansion device of a FPGA prototype verification system, the hot plug processing system comprises a hot plug processing device and a processing module; the hot plug processing device comprises a judgment module and a protection module, and the hot plug processing device is arranged near the peripheral expansion device of the peripheral FPGA prototype verification system; the judgment module and the protection module are electrically connected with the peripheral expansion device of the FPGA prototype verification system; the processing module is arranged in the FPGA prototype verification system; wherein, according to a preset judgment strategy, the judgment module is configured to judge the power connection state of the FPGA prototype verification system, obtain power connection state information that the FPGA prototype verification system is in a power-on state or a power-off state, and send the power connection state information to the protection module and the processing module; according to a preset first authentication strategy, the protection module is configured to release or lock the peripheral expansion device of the FPGA prototype verification system when the FPGA prototype verification system is in a power-off state, and according to a preset second authentication strategy, the processing module is configured to perform power-off processing or warning processing on the peripheral expansion device of the FPGA prototype verification system when the FPGA prototype verification system is in a power-on state.

[0067] The inventor utilizes various existing resources on the existing FPGA prototype verification system, without adding additional modules or circuits to realize the warning function, realizes effective protection function without increasing additional cost, especially using hardware approach to the peripheral expansion device, thereby greatly prolonging the service life of the main chip in the FPGA prototype verification system.

[0068] In this context, the "external object close to the FPGA prototype verification system" includes but is not limited to hands, fingers, or other objects.

[0069] In one specific embodiment, the peripheral expansion device of the FPGA prototype verification system includes two types: daughter cards and cables.

[0070] The peripheral expansion device of the FPGA prototype verification system is the hot plug protection object of the present application, preferably for hot plug protection of daughter cards, which can protect one daughter card or multiple daughter cards.

[0071] In one embodiment, the FPGA prototype verification system communicates with the peripheral circuit (for connecting peripheral expansion devices) mainly through connectors. The connectors generally have two specifications, which are installed in two places: the first specification is arranged on the FPGA board, which is mostly a female connector, connecting most of the available IO of the FPGA chip; the second specification is arranged on the peripheral expansion device, which is mostly a male connector, used to connect components such as functional chips, discrete components, etc. on the daughter card. For example, the male connector arranged on the daughter card or cable and the female connector arranged on the FPGA system are tightly combined to realize the communication on the circuit and the interaction in the function.

[0072] In one embodiment, the daughter card provides various protocol support, storage media, and data paths between external devices and the FPGA system. The various protocol support includes but is not limited to PCIe, DDR4, MIPI protocol, or a combination thereof.

[0073] In one embodiment of the present application, the FPGA prototype verification system includes an FPGA mainboard unit and a power control unit, wherein the peripheral expansion device of the FPGA prototype verification is electrically connected to the FPGA mainboard unit, and the monitoring module is arranged in the power control unit.

[0074] In one embodiment, the FPGA mainboard unit includes an FPGA main chip (FPGA chip to be debugged), a plurality of connectors to lead out the IO (input / output) pins of the FPGA chip, a user debugging pin header, an LED display lamp, a button switch, a JTAG interface, and various devices and modules. The above-mentioned parts constitute an FPGA system for chip function development and interaction.

[0075] In one embodiment of the present application, the FPGA mainboard unit is a plurality of FPGA mainboard units.

[0076] In one embodiment, the FPGA prototype verification system also has other optional peripheral components of the SOC, such as: a FLASH chip, a fingerprint recognition chip, a capacitive sensing button, an LED light tube, a Beep buzzer, or a combination thereof.

[0077] In one embodiment, the PCM power control unit (full name: Power and Control Module) is used to connect the FPGA board and the power supply. Generally, the PCM power control unit also has certain external interfaces to realize the interconnection function of the FPGA system and external devices, such as USB, Ethernet, global reset button, or a combination thereof.

[0078] Thermal extraction protection device

[0079] In one embodiment of the present application, the hot-plug protection device comprises a card protection lock.

[0080] In one embodiment of the present application, the hot-plug protection device further comprises an authentication unit, which comprises a biological information recognition module and a first storage unit.

[0081] The first storage unit is configured to store a database of biological information of legitimate users, and the biological information recognition unit recognizes legitimate users and illegal users according to the biological information of the legitimate users.

[0082] The authentication unit comprises a fingerprint recognition unit and a first storage unit; the first storage unit stores a database of fingerprint information of legitimate users, the fingerprint recognition unit performs fingerprint recognition according to the fingerprint information of the legitimate users, and sends the fingerprint recognition signal to the judgment module; and the fixing device releases or locks the peripheral expansion device of the FPGA prototype verification system according to the feedback of the judgment module; so that the protection module releases or locks the peripheral expansion device of the FPGA prototype verification system.

[0083] The biological information can be fingerprint, iris or a combination thereof. Preferably, fingerprint is used.

[0084] In one embodiment of the present application, a power supply module is provided in the hot-plug protection device. More specifically, the power supply module is a battery. For example, when a battery is provided in the hot-plug protection device, the battery provides power for work, so whether the FPGA system is powered on or not will not affect the work of the voltage judgment module. However, it should be understood that the power supply module can also be provided outside the hot-plug protection device, as long as it does not affect the judgment module.

[0085] In one embodiment of the present application, the FPGA prototype verification system further comprises a second storage unit, which is used to store or record a database of biological information of legitimate users and / or the prompt information.

[0086] In one embodiment, the record is stored in a second Flash chip. More specifically, the Flash chip is provided on a PCM board on a power control board.

[0087] Preferably, the first storage unit stores biological information, and the second storage unit stores or records a database of biological information of legitimate users and the prompt information.

[0088] Preferably, the biological information is a fingerprint. Alternatively, an iris or other biological information that can identify a legitimate user can be used, or a combination thereof can be used.

[0089] Judgment module of a thermal extraction treatment device

[0090] The judging module includes a voltage judging module or a current judging module.

[0091] Preferably, the judging module is a voltage judging module.

[0092] In one embodiment of the present application, when the judging module (specifically, the voltage judging module) judges the power connection state of the FPGA prototype verification system, the state of whether the FPGA prototype verification system has been powered on can be judged according to the interface voltage value (specifically, the interface voltage value of the power line).

[0093] Protection module of a thermal extraction treatment device

[0094] The protection module includes a fixing device.

[0095] The fixing device of the protection module is used to release or lock the peripheral expansion device of the FPGA prototype verification system.

[0096] In one embodiment, the fixing device is a screw fixing device.

[0097] The "release or lock" is a physical release or lock. When released, the peripheral expansion device can be used. When locked, the peripheral expansion device cannot be used.

[0098] In one embodiment, the fixing device releases or locks the peripheral expansion device of the FPGA prototype verification system according to a preset first authentication strategy according to the authentication result fed back by the authentication unit.

[0099] Treatment module

[0100] In one embodiment of the present application, the power control unit includes a system on chip.

[0101] In one embodiment of the present application, the system on chip (SOC chip) can control the power-on or power-off operation of the upper FPGA board.

[0102] In one embodiment of the present application, the FPGA prototype verification system comprises an FPGA mainboard unit and a power control unit, and the peripheral expansion device of the FPGA prototype verification system is electrically connected to the FPGA mainboard unit, and in particular, the processing module is arranged in the power control unit.

[0103] Preferably, the processing module arranged in the power control unit comprises that the processing module is arranged in the system on chip.

[0104] In one embodiment, the processing module performs release processing or early warning processing on the peripheral expansion device of the FPGA prototype verification system according to the preset second authentication strategy according to the authentication result fed back by the authentication unit.

[0105] In one embodiment of the present application, the processing module is driven by the output pin of the SOC monitoring module; and the PCM power monitoring module is further provided with a Flash memory chip (second storage unit) connected to the SOC control chip through an SPI4 bus.

[0106] In one embodiment, the SOC control chip contains an ARM module. Preferably, the SOC control chip is a Zynq of Xilinx or a Cyclone chip of Intel.

[0107] In one embodiment, the early warning mode of the processing module is set to adopt a polling mode to detect whether the sensing signal sent by the protection module is received.

[0108] In one embodiment, when the sensing signal is a fingerprint identification signal, the SOC chip adopts a polling mode to detect whether the following condition is met: whether a finger touches the sub-card is identified through a capacitive fingerprint identification module.

[0109] In one embodiment, the polling period can be set to be not greater than 10 seconds. Specifically, it includes but is not limited to 0.5-10 seconds, such as 0.5 seconds, 1 second, 2 seconds, 3 seconds, 4 seconds, or 5 seconds, or any interval in the above values.

[0110] In one embodiment, the early warning mode includes an alarm buzzer, an LED alarm lamp or a combination thereof.

[0111] Hot plug protection method

[0112] The present application provides a hot plug protection method for the peripheral expansion device of the FPGA prototype verification system, which is applicable to the hot plug protection system and the FPGA prototype verification system of the present application, and the hot plug protection method comprises the following steps.

[0113] According to a preset judgment strategy, the judgment module judges the power connection state of the FPGA prototype verification system, obtains power connection state information that the FPGA prototype verification system is in a power-on state or a power-off state, and sends the power connection state information to the protection module and the processing module;

[0114] According to a preset first authentication strategy, the protection module releases or locks the peripheral expansion device of the FPGA prototype verification system when the FPGA prototype verification system is in a power-off state.

[0115] According to a preset second authentication strategy, the processing module performs release processing or early warning processing on the peripheral expansion device of the FPGA prototype verification system when the FPGA prototype verification system is in a power-on state.

[0116] In one specific embodiment of the present application, the processing module performs a power-off operation on the peripheral expansion device of the FPGA prototype verification system.

[0117] In one specific embodiment of the present application, the early warning processing includes providing prompt information.

[0118] The prompt information includes first prompt information and second prompt information, the first prompt information includes information for prompting by an LED lamp, and the second prompt information includes information for prompting by a buzzer.

[0119] Based on the present application, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, the devices and / or methods can be implemented using any number and / or combination of the aspects set forth herein. In addition, this device and / or method can be implemented using other structures and / or functionality in addition to or other than one or more of the aspects set forth herein.

[0120] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the specific embodiments of the present application will be described below with reference to the drawings. Obviously, the drawings described below are only some of the embodiments of the present application, and those skilled in the art can obtain other drawings and other embodiments from these drawings without creative labor.

[0121] It is also need to be explained that the following embodiments provided in the drawings only illustrate the basic idea of the present application in a schematic way, and only the components related to the present application are shown in the drawings, not the number, shape and size of the components when actually implemented, and the actual implementation of each component type, number and proportion can be a voluntary change, and its component layout type can be more complex.

[0122] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, one skilled in the art will understand that the described aspects can be practiced without these specific details. The terms "first", "second", etc. are used only to describe the purpose and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features described with "first", "second", etc. can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0123] It should be noted that the words "front", "back", "left", "right", "up" and "down" used in the following description refer to the directions in the drawings. The words "inwardly" and "outwardly" are used to refer to the direction towards or away from the geometric center of a particular component.

[0124] Examples and comparative examples

[0125] The terms of the present embodiment are explained as follows:

[0126] FPGA chip: FPGA (Field Programmable Gate Array) is a kind of semi-custom circuit in the field of ASIC (Application Specific Integrated Circuit), which solves the shortcomings of custom circuit and overcomes the limitation of the number of gate circuits of the original programmable device. The basic structure of FPGA includes configurable logic block, digital clock management module, embedded block RAM, wiring resource, embedded special hard core, bottom embedded function unit and programmable input and output unit. Because FPGA has the characteristics of rich wiring resources, repeated programming and high integration, low investment, it has been widely used in the field of digital circuit design. The design process of FPGA includes algorithm design, code simulation and design, board debugging. The designer and the actual demand establish the algorithm architecture, use EDA to establish the design scheme or HDL to write the design code, through code simulation to ensure that the design scheme meets the actual requirements, and finally perform board level debugging. The configuration circuit downloads the related files to the FPGA chip to verify the actual running effect.

[0127] FPGA board is connected with the PCM board through the connector under the board, and the daughter card is connected with the FPGA board connector through the connector on the card. In the structure of the general connector, because it contains several hundred pins, it can transmit 'power line' and 'data bus' at the same time to achieve the connection of the entire data link.

[0128] FPGA IO: that is, the input / output pin. It is the main way of interaction between the FPGA verification system and the external circuit; usually the IO of FPGA is divided into two kinds: ordinary IO and high-speed IO. The transmission rate of ordinary IO can generally reach several hundred Mhz; and the high-speed IO can currently reach several tens of Gbit per channel.

[0129] FPGA board: a PCB printed circuit board with less than ten layers and up to dozens of layers; it serves as the carrier of the FPGA chip. The FPGA chip main body and various peripheral components are soldered on the FPGA board to ensure that the FPGA chip can normally start and run subsequent functions. At the same time, multiple connectors (to be described later) are installed on the FPGA board to lead out the IO pins of the FPGA. The FPGA board also has user debugging pin headers, LED display lights, button switches, JTAG debugging ports, USB debugging ports, Ethernet ports, and various debugging interfaces.

[0130] Connector: the IO connection body of FPGA and the main interconnection method with peripheral circuits; usually a connector contains dozens to hundreds of metal pins. Correspondingly, the external connection board or daughter card also has connector elements that match the FPGA board connectors. Therefore, the FPGA board has mostly female connectors that connect most of the available IO of the FPGA; on the daughter card, mostly male connectors; connect components such as functional chips and discrete components on the daughter card. Through the tight fitting of the connectors on the FPGA board and the connectors on the daughter card, the data path and interaction are realized, and the design function is realized.

[0131] PCM: Power and Control Module (Power and Control Module), in a complete FPGA system, PCM is generally in the middle layer position; it serves as a connection between the FPGA board and the power supply. At the same time, the PCM board usually also has certain external interfaces such as USB, Ethernet, global reset button, etc.; to realize the interconnection function of the FPGA system and external devices.

[0132] Sub card: The peripheral expansion board of FPGA system, small size. The chips with different functions are welded on the sub card to provide various protocol support (such as PCIe, DDR4, Ethernet, MIPI, etc.), storage media and data path between external devices and FPGA board. In most cases, the IO of each chip on the sub card is also connected to the connector of the sub card and connected to the FPGA system through the connector.

[0133] SOC chip: Each functional module such as storage, processing, logic and interface is realized in one chip, instead of using several different physical chips as in the board system. Compared with the board system, the SoC solution is lower in cost, faster and safer in data transmission between different system units, higher in overall system speed, lower in power consumption, smaller in physical size and better in reliability. Taking the VU series logic system of Sillicon Labs as an example, a SOC control chip is installed on its PCM board to control the power on / off of the whole system, monitor the hardware environment in real time, etc., like the human brain.

[0134] Multi-FPGA system: Usually one FPGA board is installed on one PCM board, which is called single-FPGA system. Multi-FPGA system, as the name implies, means that more than one FPGA board is installed on one PCM board. Such a system can run large-capacity designs and can have multiple users simultaneously and independently use different FPGA boards for functional testing without affecting each other. In addition, each FPGA board can be independently powered on and off.

[0135] Hot plug: Hot plug (hot-plugging or Hot Swap) means plugging in with power on. The hot plug function allows users to remove and replace damaged hard drives, power supplies or board cards without shutting down the system and cutting off the power supply, thereby improving the system's ability to recover from disasters in a timely manner, scalability and flexibility, etc. For example, some disk mirroring systems for high-end applications can provide hot plug function for disks. However, for the FPGAs currently sold on the market, only a small number of high-speed channel IOs of FPGAs support hot plug; most FPGAs do not support hot plug. Hot plug operation can be divided into two parts after subdivision: hot insertion and hot removal; hot insertion means that the FPGA mainboard is in the power-on state and the sub card is inserted into the system connector; the meaning of hot removal is to remove the inserted sub card from the system in the power-on state. Usually in the case of hot insertion / hot removal, the IO of the FPGA is easily damaged and difficult to repair. Therefore, the use of hot plug should be strictly prohibited. Considering the present solution, the occurrence of hot removal can be prohibited.

[0136] As Figure 1As shown in the figure, a multi-FPGA board system is shown.

[0137] As shown in the figure, the overall structure of a common FPGA system is shown; as for the FPGA currently sold on the market, only a small part of the high-speed channel IO supports hot plug; the common IO does not support it. Figure 2 As shown in the figure, the overall structure of a common FPGA system is shown; as for the FPGA currently sold on the market, only a small part of the high-speed channel IO supports hot plug; the common IO does not support it. Figure 1 As shown in the figure, the overall structure of a common FPGA system is shown; as for the FPGA currently sold on the market, only a small part of the high-speed channel IO supports hot plug; the common IO does not support it.

[0138] As shown in the figure, the overall structure of a common FPGA system is shown; as for the FPGA currently sold on the market, only a small part of the high-speed channel IO supports hot plug; the common IO does not support it. Figure 1 In the FPGA system, the FPGA board is connected with the PCM board through a connector, and the daughter card is connected with the FPGA board through another connector. The FPGA system is used for prototype verification.

[0139] The FPGA board is usually a PCB printed circuit board with up to ten layers; it is the carrier of the FPGA chip. Generally, the FPGA chip main body is welded on the FPGA board, and a plurality of connectors are installed to lead out the IO pins of the FPGA chip. User debugging pin headers, LED display lamps, button switches, JTAG ports and the like are also left on the FPGA board.

[0140] The present application is applicable to various FPGA chips in the field, especially the FPGA chips of the prototype verification system. Specifically, the basic structure of the FPGA chip can include a programmable input and output unit, a configurable logic block, a digital clock management module, an embedded block RAM, a wiring resource, an embedded special hard core, a bottom embedded functional unit or a combination thereof. However, the scope of the FPGA is not limited thereto.

[0141] Figure 3 It is a schematic view of the connector and fixing screw hole of the daughter card;

[0142] Figure 3 It is an enlarged view of the daughter card connector: the middle part is the connector body, as described in the first part, the male connector is installed on the daughter card in most cases. There is a round hole on each side of the daughter card, and the fixing screw passes through the hole, is screwed into the nut on the mainboard and is fastened.

[0143] Figure 4 It is a partial structure diagram of the FPGA system with a daughter card protection lock; after adding the plug-in protection device (or daughter card protection lock) of the daughter card, the structure of the whole system changes little. The daughter card protection lock is installed above the daughter card, and the daughter card protection lock also has two holes with the same spacing and size as the daughter card, which can be fixed by the fixing screw.

[0144] That is, the present application can make small changes to the FPGA prototype verification system, which is beneficial to the upgrading and modification of the existing FPGA prototype verification system.

[0145] Figure 5 The distribution structure diagram of the FPGA system components; referring to the detailed component distribution diagram, in order to describe clearly, the three-dimensional level is converted into the flat form as shown in Figure 3 Figure 5

[0146] Figure 6 The body structure diagram of the subcard protection device (lock).

[0147] It should be understood that the subcard protection device of the present application can be one or more.

[0148] The body structure of the subcard protection device (lock) is described in detail as follows:

[0149] For convenience of use, the subcard protection lock uses fingerprint identification as the authentication method; the lock contains a fingerprint identification unit, a storage chip (storing fingerprint information and unlocking log), a voltage judgment module and a micro battery. From the physical structure, the subcard protection lock also has a pair of screw fixing devices to fix the two fixing screws described above. When the FPGA system is in the power-off state, and the fingerprint identification authentication is passed, the screw fixing device releases the action, and the screw can be removed by rotating; when the FPGA system connector is in the power-on state, the screw fixing device is always fastened and cannot be rotated. Therefore, the mechanical structure plays a role in fixing and protecting the subcard.

[0150] Figure 7 The fingerprint set data collection flowchart is shown.

[0151] Before using the fingerprint identification function of the subcard protection lock, the authorized fingerprint must be recorded first. The method described in this paper is to use computer software to connect the PCM board, the fingerprint identification unit to collect and verify the sample integrity, and then store the fingerprint set in the subcard protection lock and the Flash storage chip on the PCM board. The specific process is shown in Figure 7 , first, connect the USB data line to the PCM board, the subcard protection lock and the subcard to the connector of the FPGA board. Then, start the hardware system, after starting, the software sends a fingerprint collection command to the SOC chip, and then the SOC chip sends an instruction to the fingerprint collection module. After receiving the instruction, the collection module returns a ready feedback signal, and the LED indicator light is on, indicating that the fingerprint collection is ready. Next, perform the fingerprint collection action, and after the collection is completed, the data will not be lost in the Flash storage chip. Repeat this process until all fingerprint collection work is completed.

[0152] Figure 8 The flowchart of software control power-off and removal of the subcard is shown. ​​

[0153] The sub-card protection device of the present application operates as follows:

[0154] In view of the working effect of the sub-card protection lock, to achieve intervention protection for hot removal of the sub-card, first, the preset condition for the removal event to occur is considered, i.e. the preset condition is established in the case of power-on of the entire FPGA system. If the plug-in is performed in the state of complete power-off of the system, it is cold plug-in, and there is no harmfulness as described above.

[0155] Secondly, the specific intervention protection method is considered. The present embodiment will mainly describe two input conditions and output results:

[0156] Input condition 1: whether the FPGA system has been in the power-on state?

[0157] Judgment method: it is mainly performed by the voltage judgment module on the protection lock. According to the interface voltage value of the power supply line, it can be judged whether the power-on state has been established. Since the battery provides power for work, whether the FPGA system is powered on or not, it will not affect the work of the voltage judgment module on the sub-card.

[0158] Input condition 2: whether the result of fingerprint recognition is legal? Before the protection device is formally enabled, fingerprint collection and storage work will be performed. If the recognition result is the fingerprint set stored in the Flash chip in advance, it is considered legal; otherwise, it is an illegal fingerprint.

[0159] The overall protection process is divided into two cases:

[0160] Case 1: the entire FPGA system is in the power-off state.

[0161] First, according to the judgment of input condition 1, the battery supply circuit on the protection lock continues to work, and at the same time, through the level judgment module, it is known that the system has been powered off. At this time, when the fingerprint recognition signal is generated, the identification result of input condition 2 is identified, if it conforms to the subset of the fingerprint database stored in the Flash chip, it is a legal unlocking, and the judgment module releases the screw fixing device; then the user removes the two fixing screws, removes the sub-card and the sub-card protection lock. The entire sub-card removal operation process is completed; if the fingerprint is illegal, the process is ended. Whether the identification is successful or failed, the log will be stored in the Flash chip of the sub-card protection lock for record.

[0162] Scenario 2: If the FPGA board is powered on, the protection lock's level judgment module, connected via the power line, can determine that the FPGA board is powered on. Therefore, the enable signal for the fingerprint recognition module will be turned off, the fingerprint recognition module will not work, and it will output a recognition failure signal by default. The screw fixing device will also remain closed, thus protecting and locking the daughter card. On the other hand, since the system is powered on, the control SOC, through the fingerprint feedback signal input via the connector, detects that a user has touched the daughter card. At this time, the SOC will issue a warning on the board through LED flashing and a buzzer sounding.

[0163] Furthermore, in this state, if the user wants to remove the daughter card, they have two options:

[0164] A- From a physical perspective, powering down the entire FPGA system, i.e., by pressing the power button, will completely disconnect power to the power supply, the PCM board, and all components on the FPGA board. This returns the system to the state described in scenario 1; the user then performs fingerprint authentication, and once successful, the daughter card can be removed.

[0165] B-as Figure 8 As shown, the user controls the FPGA board to power down via software, and then can remove and insert daughter cards. This is especially convenient in systems with multiple FPGA boards, as one daughter board can be powered down and its daughter card removed without affecting the continued operation of the remaining FPGA boards.

[0166] in conclusion

[0167] The specific embodiments of the present invention achieve the following effects:

[0168] First, the present invention proposes a hardware device to prevent damage to FPGA I / O caused by hot-swapping; more specifically, for example, a daughter card protection lock device as described in the embodiments;

[0169] Secondly, the control SOC and software in the FPGA system can control the FPGA board to power down and remove the daughter card; it is convenient to use and the control effect is reliable.

[0170] Secondly, the sub-card protection lock has its own battery, flash memory, and fingerprint recognition for independent authentication;

[0171] In addition, user behavior can be analyzed by reading the Flash operation logs on a computer.

[0172] Compared with conventional prototype verification systems, this invention effectively reduces the damage to the I / O interface caused by accidental hot-plugging, without increasing additional costs.

[0173] It should be understood that the detailed description illustrates implementations of the subcard protection lock.

[0174] It should be noted that the above-mentioned embodiments can be freely combined according to requirements. The above merely constitutes preferred embodiments of the present application, and it should be pointed out that, for those skilled in the art, several improvements and refinements can be made without departing from the principles of the present application, and these improvements and refinements should also be considered as falling within the scope of protection of the present application.

[0175] All documents mentioned in the present application are incorporated herein by reference as if individually incorporated by reference. In addition, it should be understood that various changes and modifications to the preferred embodiments described herein will be apparent to those skilled in the art and can be made without departing from the spirit and scope of the application.

Claims

1. A hot-swap protection system for peripheral expansion devices of an FPGA prototyping system, characterized in that, The hot stripping protection system includes a hot stripping processing device and a processing module; The hot-stripping device includes a judgment module and a protection module, and the hot-stripping device is located near the peripheral expansion device of the peripheral FPGA prototype verification system; the judgment module and the protection module are electrically connected to the peripheral expansion device of the FPGA prototype verification system. The processing module is located within the FPGA prototype verification system; in, -According to the preset judgment strategy, the judgment module is configured to judge the power connection status of the FPGA prototype verification system, obtain the power connection status information of whether the FPGA prototype verification system is in the power-on state or the power-off state, and send the power connection status information to the protection module and the processing module. According to a preset first authentication strategy, the protection module is configured to release or lock the peripheral expansion devices of the FPGA prototype verification system when the FPGA prototype verification system is powered down. -According to the preset second authentication strategy, when the FPGA prototype verification system is powered on, the processing module is configured to power off or issue a warning to the peripheral expansion devices of the FPGA prototype verification system.

2. The hot-stripping protection system as described in claim 1, characterized in that, The judgment module includes a voltage judgment module, a current judgment module, or a combination thereof; The protection module includes a fixing device for releasing or locking peripheral expansion devices of the FPGA prototype verification system; and / or The processing module includes a system-on-a-chip.

3. The hot-stripping protection system as described in claim 1, characterized in that, The hot stripping protection device also includes an authentication unit, which includes a biometric identification module and a first storage unit. The first storage unit is configured to store a database of biometric information of legitimate users, and the biometric identification unit identifies illegal users and legitimate users based on the biometric information of the legitimate users.

4. The hot-swap protection system as described in any one of claims 1 to 3, wherein the FPGA prototype verification system comprises an FPGA motherboard unit and a power control unit, characterized in that, The peripheral expansion device for FPGA prototype verification is electrically connected to the FPGA motherboard unit, and the processing module is located within the power control unit.

5. The hot-stripping protection system as described in claim 4, characterized in that, The power control unit includes a system-on-a-chip; The processing module is located within the power control unit, meaning the processing module is located within the system-on-a-chip.

6. The hot-stripping protection system as described in claim 5, characterized in that, The FPGA prototype verification system also includes a second storage unit, which is used to record the biometric information database and / or prompt information of legitimate users.

7. An FPGA prototype verification system comprising the hot-swap protection system as described in any one of claims 1 to 6.

8. A method for hot-swapping protection of peripheral expansion devices in an FPGA prototyping system, characterized in that, The hot-swap protection method, applicable to the hot-swap protection system as described in any one of claims 1-6 and the FPGA prototyping system as described in claim 7, comprises: According to the preset judgment strategy, the judgment module judges the power connection status of the FPGA prototype verification system, obtains the power connection status information of whether the FPGA prototype verification system is in the power-on state or the power-off state, and sends the power connection status information to the protection module and the processing module. According to the preset first authentication strategy, when the FPGA prototype verification system is powered off, the protection module releases or locks the peripheral expansion devices of the FPGA prototype verification system. -According to the preset second authentication strategy, when the FPGA prototype verification system is powered on, the processing module performs release processing or warning processing on the peripheral expansion devices of the FPGA prototype verification system.

9. The hot-pull-out protection method as described in claim 8, characterized in that, The processing module powers down the peripheral expansion devices of the FPGA prototype verification system.

10. The thermal stripping protection method as described in claim 8, characterized in that, The aforementioned early warning processing includes providing alert information; The prompt information includes a first prompt information and a second prompt information. The first prompt information includes information indicated by an LED light, and the second prompt information includes information indicated by a buzzer.

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