A hot-plug processing system and method for peripheral expansion device of FPGA prototype verification system

Abstract

The application provides a hot plug processing system of a peripheral expansion device of an FPGA prototype verification system, a sensing module of the system is electrically connected with the system, and a monitoring module is arranged in the system; the sensing module senses an external object close to the system according to a sensing strategy, and generates a sensing signal and sends the sensing signal to the system when the distance is less than or equal to a threshold value; the monitoring module is configured to judge whether the sensing signal is received according to a judgment strategy, and output a prompt information to prompt that the external object will perform a hot plug operation on the peripheral expansion device when it is judged that the sensing signal is received. The application also provides an FPGA prototype verification system and a hot plug processing method. The application can effectively reduce the IO interface damage caused by the misoperation of the hot plug and has no influence on the main function of the FPGA system.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuits, and particularly relates to a hot-plug processing system and a hot-plug processing method of an FPGA system. BACKGROUND

[0002] FPGA chips belong to a kind of semi-customized circuits in application-specific integrated circuits (ASIC), are programmable logic arrays, and can effectively solve the problem of less original device gate circuits, and are therefore often used for prototype verification in chip design, that is, one or more FPGA devices are used as the core chip of the prototype verification system, and a large number of external expansion devices are used to jointly constitute the FPGA prototype verification system.

[0003] Generally, in the prototype verification of chip design in the FPGA prototype verification system, that is, when the FPGA chip is debugged and programmed, an FPGA board needs to be used. The FPGA board is a PCB printed circuit board with as many as ten layers. The FPGA board is provided with an FPGA main chip, a plurality of connectors and the like, and also leads out the IO (input / output) pins of the FPGA chip, the user debugging pin pinout and a plurality of peripheral expansion devices such as LED display lamps, button switches, JTAG interfaces and various devices and modules outside the FPGA chip through the connectors, connection lines and the like. These peripheral expansion devices are used to assist the prototype verification of the chip design of the FPGA chip, and are convenient for function development and interaction in the prototype verification of chip design.

[0004] At present, the service life of the main chip in the FPGA prototype verification system is often terminated in advance. The existing solution can only simply replace the FPGA main chip. However, the FPGA main chip used in the FPGA prototype system is a medium-high-end FPGA chip, and the cost is very expensive, and the repair cost is very expensive.

[0005] This is because the number of interconnection interfaces in the FPGA prototype verification system of the prior art is relatively small, and it is difficult to additionally design functions without affecting the main functions of the FPGA prototype verification system.

[0006] Based on the above, there is an urgent need in the art to provide a technical solution to solve the above technical problems. SUMMARY

[0007] The first object of the present application is to obtain a hot-plug processing system of peripheral expansion devices of an FPGA prototype verification system.

[0008] The second object of the present application is to obtain an FPGA prototype verification system containing the hot-plug processing system.

[0009] The third object of the present application is to obtain a hot-plug processing method of a peripheral expansion device of an FPGA prototype verification system.

[0010] The first aspect of the present application provides a hot-plug processing system of a peripheral expansion device of an FPGA prototype verification system, the hot-plug processing system comprising a sensing module and a monitoring module, the sensing module being electrically connected to the FPGA prototype verification system, and the monitoring module being arranged in the FPGA prototype verification system.

[0011] The sensing module is configured to:

[0012] According to a preset sensing strategy, the external object close to the FPGA prototype verification system is sensed, and when the distance between the external object and the peripheral expansion device is less than or equal to a preset distance threshold, a sensing signal is generated and sent to the FPGA prototype verification system, wherein the peripheral expansion device is a peripheral expansion device used by the FPGA prototype verification system when performing FPGA prototype verification.

[0013] The monitoring module is configured to:

[0014] According to a preset judgment strategy, it is judged whether the sensing signal sent by the sensing module is received, and when it is judged that the sensing signal is received, a prompt information is outputted to prompt the external object to perform a hot-plug operation on the peripheral expansion device through the prompt information.

[0015] In a preferred embodiment of the present application, the sensing module is arranged on the peripheral expansion device.

[0016] The electrical connection between the sensing module and the FPGA prototype verification system comprises an electrical connection between the sensing module and the FPGA prototype verification system through the peripheral expansion device.

[0017] In a preferred embodiment of the present application, the sensing module comprises at least one of the following modules: an infrared sensing module, a fingerprint recognition module.

[0018] Preferably, when the sensing module comprises a fingerprint recognition module, the fingerprint recognition module comprises a capacitive sensing button arranged on the peripheral expansion device.

[0019] In a preferred embodiment of the present application, the FPGA prototype verification system comprises an FPGA mainboard unit and a power control unit, the peripheral expansion device is electrically connected to the FPGA mainboard unit, and the monitoring module is arranged in the power control unit.

[0020] In a preferred embodiment of the present application, the power control unit comprises a system on chip.

[0021] The monitoring module is arranged in the power control unit, and the monitoring module is arranged in the system on chip.

[0022] In a preferred embodiment of the present application, the FPGA prototype verification system further comprises a storage unit configured to record the sensing signal and / or the prompt information.

[0023] The second aspect of the present application provides an FPGA prototype verification system comprising the hot-plug processing system.

[0024] The third aspect of the present application provides a hot-plug processing method for an FPGA prototype verification system peripheral expansion device, the hot-plug processing method comprising:

[0025] According to a preset sensing strategy, the external object close to the FPGA prototype verification system is sensed by the sensing module, and when the distance between the external object and the peripheral expansion device is less than or equal to a preset distance threshold, a sensing signal is generated and sent to the FPGA prototype verification system, wherein the peripheral expansion device is a peripheral expansion device used by the FPGA prototype verification system when performing FPGA prototype verification.

[0026] According to a preset judgment strategy, it is judged whether the sensing signal sent by the sensing module is received, and when it is judged that the sensing signal is received, a prompt information is outputted to prompt the external object to perform a hot-plug operation on the peripheral expansion device through the prompt information.

[0027] In a preferred embodiment of the present application, the sensing strategy comprises a first sensing strategy and a second sensing strategy, and the prompt information comprises a first prompt information and a second prompt information, wherein the first sensing strategy comprises a sensing and identification strategy using an infrared sensor, the second sensing strategy comprises a sensing and identification strategy using a fingerprint identifier, the first prompt information comprises information using an LED lamp for prompting, and the second prompt information comprises information using a buzzer for prompting.

[0028] According to a preset sensing strategy, the external object close to the FPGA prototype verification system is sensed, comprising:

[0029] According to the first sensing strategy, the hand close to the FPGA prototype verification system is sensed and identified by the infrared sensor, and according to the second sensing strategy, the hand contacting the peripheral expansion device is identified by the fingerprint identifier.

[0030] It is judged whether the sensing signal sent by the sensing module is received, and when it is judged that the sensing signal is received, a prompt information is outputted, comprising:

[0031] If it is judged that the sensing signal sent by the infrared sensor is received, the first prompt information is output through the LED lamp;

[0032] If it is judged that the sensing signal sent by the fingerprint recognizer is received, the second prompt information is output through the buzzer;

[0033] If it is judged that the sensing signal sent by the sensing module is not received, the next judgment period is entered.

[0034] In a preferred embodiment of the present application, the hot-plug processing method further comprises: recording the occurrence time of the output prompt information.

[0035] The present application can bring at least one of the following beneficial effects:

[0036] 1. effectively reducing the IO interface damage caused by the hot-plug of misoperation.

[0037] 2. using the existing resources on the existing FPGA system, without adding additional modules or circuits to realize the early warning function, realizing effective early warning function without increasing additional cost. BRIEF DESCRIPTION OF DRAWINGS

[0038] The above features, technical characteristics, advantages and their implementation will be further described in a clear and understandable manner in combination with the preferred embodiments and the accompanying drawings.

[0039] Figure 1 It is a schematic diagram of the existing FPGA system connection structure;

[0040] Figure 2 It is a FPGA system element distribution structure diagram of the present application;

[0041] Figure 3 It is a FPGA system control flow chart of the present application. DETAILED DESCRIPTION

[0042] In the present application, the inventor has found that only by effectively reducing the IO interface damage caused by the hot-plug of misoperation, the work efficiency during the debugging of the FPGA system can be greatly improved through extensive and in-depth experiments. In addition, the technical solution provided by the present application utilizes the existing resources on the existing FPGA system, without adding additional modules or circuits to realize the early warning function, realizing effective early warning function without increasing additional cost.

[0043] The technical concept of the present application is mainly based on the following discovery: the inventors have found that, for the currently marketed FPGA system, only a small part of the high-speed channel IO supports hot plugging, and the ordinary IO does not support hot plugging. Therefore, in the case of power-on, due to misoperation or hot plugging under unknown circumstances, the IO pin of the FPGA main chip is easily damaged, thereby reducing the available interconnection IO or debugging IO. From the electrical characteristics, such damage is irreversible and cannot be repaired.

[0044] The technical problem caused thereby is that, when the damaged pins reach a certain scale, the debugging IO interface of the FPGA system will be greatly reduced, and for circuit designs that need to use a large number of debugging IO interfaces, using such a large number of damaged FPGA systems for debugging will greatly affect the work efficiency and design accuracy. It is especially suitable for FPGA systems with ordinary IO channels (non-high-speed channels).

[0045] Therefore, the concept of the present application is as follows: to provide an alarm system method for intervening in the hot plugging of the FPGA system subcard.

[0046] Secondly, the time information of the alarm is also saved to the Flash memory chip of the FPGA system, which can be queried and analyzed subsequently.

[0047] Thirdly, the ordinary alarm system is difficult to realize due to the occupation of FPGA system resources, for example, it may cause the problem of slow verification system synthesis speed. However, the present application, preferably, is realized by a specific way of trying to occupy as few resources as possible: for example, the subcard and the FPGA board, the PCM board are connected through the inter-board connector; the sensing unit is arranged on the subcard, if an object or a hand approaches or contacts the subcard, an interrupt output will be sent to the SOC chip on the FPGA PCM, the SOC chip will judge the type of the interrupt, and then control the alarm system in the FPGA system to send warning information, thereby intervening in the behavior of hot plugging of the subcard. The present application utilizes various existing resources on the existing FPGA system, without adding additional modules or circuits to realize the early warning function, and realizes the effective early warning function without increasing additional costs. It is suitable for FPGA systems with ordinary IO channels (non-high-speed channels). The time required for the device to complete all functions is within an acceptable range.

[0048] In the present application, "or" includes "and". The "and" corresponds to the Boolean logic operator "AND", and the "or" corresponds to the Boolean logic operator "OR", and "AND" is a subset of "OR".

[0049] The various aspects of the present application are described in detail as follows:

[0050] Hot pull processing system

[0051] The FPGA prototype verification system peripheral expansion device hot-plug processing system provided by the application comprises a sensing module and a monitoring module, the sensing module is electrically connected with the FPGA prototype verification system, and the monitoring module is arranged in the FPGA prototype verification system; the sensing module is configured to sense an external object close to the FPGA prototype verification system according to a preset sensing strategy, and generate a sensing signal and send the sensing signal to the FPGA prototype verification system when the distance between the external object and the peripheral expansion device is less than or equal to a preset distance threshold, wherein the peripheral expansion device is a peripheral expansion device used by the FPGA prototype verification system when FPGA prototype verification is performed; and the monitoring module is configured to judge whether the sensing signal sent by the sensing module is received according to a preset judgment strategy, and output prompt information when it is judged that the sensing signal is received, so as to prompt the external object to perform a hot-plug operation on the peripheral expansion device.

[0052] The inventor utilizes various existing resources on the FPGA prototype verification system, does not need to add an additional module or circuit to realize the early warning function, realizes effective early warning function without increasing additional cost, and greatly prolongs the service life of the main chip in the FPGA prototype verification system.

[0053] In this context, the "external object close to the FPGA prototype verification system" includes but is not limited to a hand, a finger, or other objects.

[0054] Induction module

[0055] The sensing module of the application is electrically connected with the FPGA prototype verification system. The sensing module is configured to sense an external object close to the FPGA prototype verification system according to a preset sensing strategy, and generate a sensing signal and send the sensing signal to the FPGA prototype verification system when the distance between the external object and the peripheral expansion device is less than or equal to a preset distance threshold, wherein the peripheral expansion device is a peripheral expansion device used by the FPGA prototype verification system when FPGA prototype verification is performed.

[0056] In a preferred embodiment of the application, the sensing module is arranged on the peripheral expansion device.

[0057] The electrical connection between the sensing module and the FPGA prototype verification system comprises that the sensing module is electrically connected with the FPGA prototype verification system through the peripheral expansion device.

[0058] In one embodiment, the peripheral expansion device of the FPGA system includes two types: daughter cards and cables. For example, the male connector on the daughter card or cable and the female connector on the FPGA system are tightly coupled to achieve circuit connection and functional interaction.

[0059] In one embodiment, the peripheral expansion device includes a daughter card. The daughter card can be provided with one or more sensing modules. The sensing module is preferably an infrared sensing module, a fingerprint recognition module or a combination thereof. More preferably, the fingerprint recognition module is a capacitive fingerprint recognition module.

[0060] In one embodiment, the daughter card provides various protocol support, storage media and data paths between external devices and the FPGA system. The various protocol support includes but is not limited to PCIe, DDR4, MIPI protocol or a combination thereof.

[0061] In one preferred embodiment of the application, the sensing module includes at least one of the following modules: an infrared sensing module, a fingerprint recognition module.

[0062] In one preferred embodiment of the application, when the sensing module includes a fingerprint recognition module, the fingerprint recognition module includes a capacitive sensing button provided on the peripheral expansion device.

[0063] Monitoring module

[0064] The monitoring module of the application is provided in the FPGA prototype verification system. The monitoring module is configured to determine whether the sensing signal sent by the sensing module is received according to a predetermined determination strategy, and output a prompt information when it is determined that the sensing signal is received, so as to prompt the external object to perform a hot plug operation on the peripheral expansion device through the prompt information.

[0065] In one embodiment of the application, the monitoring module is a SOC control chip, and its control structure includes input pins and output pins; the SOC control chip receives the sensing signal sent by the sensing module of the application through the input pins; and the output result is controlled through the output pins.

[0066] In one embodiment, the SOC control chip contains an ARM module. Preferably, it is a Zynq of Xilinx or a Cyclone chip of Intel.

[0067] In one embodiment, the control mode of the monitoring module is set to use a polling mode to detect whether the sensing signal sent by the sensing module is received.

[0068] In one embodiment, when the sensing module is an infrared sensing module and a fingerprint identification module, the SOC chip adopts a polling mode to detect whether the following conditions are met: whether an object including a finger is close to the card by the infrared sensor; and / or whether a finger touches the card by the capacitive fingerprint identification module.

[0069] In one embodiment, the polling period can be set to no more than 10 seconds. Specifically, it includes but is not limited to 0.5-10 seconds, such as 0.5 seconds, 1 second, 2 seconds, 3 seconds, 4 seconds, or 5 seconds, or any interval in the above values.

[0070] In one embodiment, the pre-warning mode includes using an alarm buzzer, an LED alarm lamp, or a combination thereof.

[0071] FPGA prototyping system

[0072] The FPGA prototype verification system includes an FPGA mainboard unit and a power control unit, the peripheral expansion device is electrically connected with the FPGA mainboard unit, and the monitoring module is arranged in the power control unit.

[0073] In a preferred embodiment of the present application, the power control unit includes a system on chip, and the monitoring module arranged in the power control unit includes that the monitoring module is arranged in the system on chip.

[0074] In a preferred embodiment of the present application, the FPGA prototype verification system further includes a storage unit for recording the sensing signal and / or the prompt information.

[0075] In one embodiment of the present application, the FPGA prototype verification system includes: an FPGA mainboard unit; the FPGA mainboard unit is connected with a peripheral expansion device through a connection line; a PCM power control unit is connected with the FPGA mainboard unit through a connector; and the SOC control chip is arranged on the PCM power control unit.

[0076] In one embodiment, the FPGA prototype verification system is further provided with other optional peripheral components of SOC, such as: a FLASH chip, a fingerprint identification chip, a capacitive sensing button, an LED light tube, a Beep buzzer, or a combination thereof.

[0077] In one embodiment, the PCM power control unit (full name: Power and Control Module) is used to connect the FPGA board and the power supply. Generally, the PCM power control unit also has certain external interfaces to realize the interconnection function of the FPGA system and external devices, such as USB, Ethernet, global reset button, or a combination thereof.

[0078] In one embodiment, the communication between the FPGA system and the peripheral circuit (for connecting peripheral expansion devices) is mainly realized through a connector. The connector generally has two specifications, which are installed in two places: the first specification is arranged on the FPGA board, which is mostly a female connector, and connects most of the available IO of the FPGA chip; the second specification is arranged on the peripheral expansion device, which is mostly a male connector, and is used to connect components such as functional chips, discrete components, etc. on the daughter card.

[0079] In one embodiment of the present application, the FPGA mainboard unit is provided with a processing module, which is driven by the output pin of the SOC monitoring module; the PCM power monitoring module is also provided with a Flash memory chip, which is connected with the SOC control chip through an SPI4 bus.

[0080] In one embodiment, the processing module includes an alarm buzzer, an LED alarm lamp, or a combination thereof.

[0081] In one embodiment, the sensing module (including a fingerprint identification module and an infrared sensor) is connected with the interrupt input pin of the SOC through PCB wiring, and the SOC drives the processing module (such as the LED alarm lamp and the alarm buzzer) through the output pin.

[0082] In one embodiment, the FPGA mainboard unit includes an FPGA main chip (FPGA chip to be debugged), a plurality of connectors to lead out the IO (input / output) pins of the FPGA chip, a user debugging pin header, an LED display lamp, a button switch, a JTAG interface, and various devices and modules, wherein the above-mentioned parts constitute an FPGA system for chip function development and interaction.

[0083] Hot pull processing method

[0084] The hot plug processing method of the FPGA prototype verification system peripheral expansion device of the present application comprises:

[0085] The external object close to the FPGA prototype verification system is sensed by the sensing module according to a preset sensing strategy, and when the distance between the external object and the peripheral expansion device is less than or equal to a preset distance threshold, a sensing signal is generated and sent to the FPGA prototype verification system, wherein the peripheral expansion device is a peripheral expansion device used by the FPGA prototype verification system when performing FPGA prototype verification.

[0086] According to a preset judgment strategy, it is judged whether the sensing signal sent by the sensing module is received, and when it is judged that the sensing signal is received, prompt information is outputted to prompt the external object to perform a hot removal operation on the peripheral expansion device through the prompt information.

[0087] In a preferred embodiment of the present application, the sensing strategy includes a first sensing strategy and a second sensing strategy, and the prompt information includes first prompt information and second prompt information, wherein the first sensing strategy includes a sensing and identification strategy using an infrared sensor, the second sensing strategy includes a sensing and identification strategy using a fingerprint identifier, the first prompt information includes information using an LED lamp for prompting, and the second prompt information includes information using a buzzer for prompting.

[0088] According to a preset sensing strategy, the external object close to the FPGA prototype verification system is sensed, including:

[0089] According to a first sensing strategy, the hand close to the FPGA prototype verification system is sensed and identified by an infrared sensor, and according to a second sensing strategy, the hand contacting the peripheral expansion device is identified by a fingerprint identifier.

[0090] It is judged whether the sensing signal sent by the sensing module is received, and when it is judged that the sensing signal is received, prompt information is outputted, including:

[0091] If it is judged that the sensing signal sent by the infrared sensor is received, the first prompt information is outputted by an LED lamp;

[0092] If it is judged that the sensing signal sent by the fingerprint identifier is received, the second prompt information is outputted by a buzzer;

[0093] If it is judged that the sensing signal sent by the sensing module is not received, the next judgment period is entered.

[0094] In a preferred embodiment of the present application, the hot removal processing method further includes: recording the occurrence time of the output prompt information.

[0095] In one embodiment of the present application, a hot plug processing method of a peripheral expansion device of an FPGA system is provided, which comprises the following steps: (i) setting the sensing module of the present application to identify the object close to it and send a sensing signal to the monitoring module of the FPGA system; (ii) the monitoring module of the FPGA system enters the polling mode; detects whether the sensing signal is received; and controls the execution of the output result.

[0096] In one embodiment, the sensing module provided on the peripheral expansion unit is an infrared sensing module and a fingerprint identification module; the monitoring module provided in the FPGA system is a SOC control chip, the control structure of which comprises input pins and output pins; wherein the SOC control chip accepts the sensing signal sent by the sensing module through the input pins; the input conditions of the input pins are set as follows: input condition (1): the infrared sensing module identifies the close of the object including the hand; input condition (2): the fingerprint identification module identifies the contact of the finger; the output pins of the SOC control chip control the execution of the output result according to the types of input conditions, and the output results of the output pins are set as follows: output result (1): if it is detected that the input condition (1) is established, the LED light alarm is executed for early warning; output result (2): if it is detected that the input condition (2) is established, the alarm buzzer is run for early warning; output result (3): if neither the input condition (1) nor the input condition (2) is established, the SOC control chip enters the next polling cycle.

[0097] More advantageously, the time of the alarm buzzer in the output result (2) is recorded.

[0098] In one embodiment, the recording is performed by the Flash provided in the PCM.

[0099] Based on the present application, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, the number and aspects set forth herein can be used to implement a device and / or practice a method. In addition, this device and / or method can be implemented using other structures and / or functionality in addition to or instead of one or more of the aspects set forth herein.

[0100] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, specific embodiments of the present application will be described below with reference to the drawings. Obviously, the drawings described below are only some of the embodiments of the present application, and those skilled in the art can obtain other drawings and other embodiments from these drawings without creative labor.

[0101] It is also necessary to note that the diagrams provided in the following embodiments only illustrate the basic concepts of the present application in a schematic manner, and only show the components related to the present application in the diagrams, not drawn according to the number, shape and size of the components in actual implementation, and the shape, number and proportion of each component in actual implementation can be arbitrarily changed, and the component layout pattern can be more complex.

[0102] In addition, in the following description, specific details are provided in order to facilitate a thorough understanding of the examples. However, one skilled in the art will understand that the aspects described can be practiced without these specific details. The terms "first", "second", and the like are used only to describe purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features described with "first", "second", etc. can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0103] Examples and comparative examples

[0104] Figure 1 The existing FPGA system connection structure schematic diagram is shown. At present, only a small part of high-speed channel IO of the FPGA sold on the market supports hot plugging; the general IO does not support it. Figure 1 The existing FPGA system connection structure schematic diagram is shown. It belongs to the general IO type that does not support hot plugging.

[0105] Reference Figure 1 In which the FPGA board in the FPGA system is connected with the PCM board through the connector, and the daughter card is connected with the FPGA board through another connector. The FPGA system is used for prototype verification.

[0106] The FPGA board is usually a PCB printed circuit board with up to dozens of layers; it is the carrier of the FPGA chip. Generally, the FPGA chip main body is soldered on the FPGA board, and multiple connectors are installed to lead out the IO pins of the FPGA chip. There are also user debugging pin headers, LED display lights, button switches, JTAG ports and other devices on the FPGA board.

[0107] The present application is applicable to various FPGA chips in the field, especially the FPGA chips of the prototype verification system. Specifically, the basic structure of the FPGA chip can include a programmable input and output unit, a configurable logic block, a digital clock management module, an embedded block RAM, a wiring resource, an embedded special hard core, a bottom embedded functional unit or a combination thereof. However, the scope of the FPGA is not limited to this.

[0108] IO pin of FPGA is input / output pin, which is the main way of interaction between FPGA verification system and external circuit. Generally, IO of FPGA is divided into two types: normal IO and high-speed IO. Transmission rate of normal IO can reach several hundred MHz; while high-speed IO can reach tens of Gbit per channel.

[0109] FPGA chip has been widely used in the field of digital circuit design due to its rich wiring resources, reprogrammable, high integration and low investment. The design process of FPGA chip includes algorithm design, code simulation and design, board debugging. Designers and actual requirements establish algorithm architecture, use EDA to establish design scheme or HDL to write design code, ensure that the design scheme meets the actual requirements through code simulation, and finally perform board-level debugging. The relevant files are downloaded to the FPGA chip through the configuration circuit to verify the actual running effect.

[0110] A connector (inter-board connector) usually contains hundreds of metal pins; there are generally two specifications, which are installed in two places: one is on the FPGA board, which is mostly a female connector, connecting most of the available IO of FPGA; the other is on the daughter card, which is mostly a male connector; connecting components on the daughter card such as functional chips, discrete components, etc. Through the close fitting of the connector on the daughter card and the connector on the FPGA board, the data path and interaction are realized, and the design function is realized.

[0111] The structure of the connector can transmit power and data lines at the same time to achieve the connection of the entire data link. The connection method of FPGA logic system and peripheral circuit is mainly realized through integrated connector (inter-board connector). The connection channel is mainly divided into two types: daughter card and cable. The male connector of the daughter card / cable and the female connector of the FPGA mainboard are closely combined to realize the connection of the circuit and the interaction of the function.

[0112] The daughter card is a peripheral expansion circuit board of the FPGA system, which is small in size. The daughter card provides various protocol support (such as PCIe, DDR4, MIPI, etc.), storage medium and data path between external devices and FPGA board. Generally, the daughter card is connected to the FPGA system through the connector.

[0113] PCM stands for Power and Control Module (Power and Control Module), which is usually located in the middle layer in a complete FPGA system; it connects the FPGA board and the power supply. At the same time, the PCM board usually has certain external interfaces such as USB, Ethernet, global reset button, etc.; to realize the interconnection function of FPGA system and external devices.

[0114] Currently, in FPGA prototyping systems, there is a SOC chip containing an ARM module (usually Xilinx's Zynq or Intel's Cyclone chip), which can run an on-chip Linux operating system, essentially acting as a small CPU; it can be used for the control of the entire system.

[0115] Taking the VU series logic system (commercially available) from Silergy as an example, a single SoC control chip is installed on its PCM board. This chip controls the power-on and power-off of the entire system and monitors the hardware environment in real time, much like the human brain. The SoC chip integrates storage, processing, logic, and interface modules into a single chip, unlike on-board systems which require several different physical chips. Compared to on-board systems, SoC solutions are lower in cost, enable faster and more secure data transmission between different system units, and offer higher overall system speed, lower power consumption, smaller physical size, and better reliability.

[0116] Currently Figure 1 The FPGA system itself does not yet support hot-swapping. When powered on, accidental or unauthorized hot-swapping can easily damage the FPGA's I / O pins; and from an electrical perspective, this damage is irreversible, meaning it cannot be repaired. When a significant number of pins are damaged, the number of debug I / O interfaces on the FPGA system will be greatly reduced, severely impacting designs requiring numerous debug I / Os. Currently, the only repair method is to replace the FPGA main chip. Because mid-to-high-end FPGA chips are very expensive, this method incurs extremely high repair costs.

[0117] like Figure 2 The diagram shows the component distribution structure of the FPGA system of the present invention:

[0118] The daughter card hot-swap intervention alarm method described in this invention uses an SOC chip as the main controller, and connects to peripheral components such as FLASH chips, fingerprint recognition chips, capacitive sensing buttons, LED light-emitting diodes and Beep buzzers.

[0119] From the circuit board's layering, the SOC main control chip and Flash memory chip are mounted on the PCM board, connected via an SPI4 bus; the alarm buzzer and LED alarm lights are mounted on the FPGA board; and the infrared detection and fingerprint recognition modules are mounted on the daughter card. The fingerprint recognition module and infrared detector are connected to the SOC's interrupt input pins via PCB traces, while the SOC also has output pins to drive the LED alarm lights and alarm buzzer.

[0120] like Figure 3The FPGA system control flow chart is shown.

[0121] To intervene and alarm for hot pullout, firstly, preset conditions for pullout event occurrence should be considered, which is easy to understand, and the preset conditions are established in the whole FPGA system power-on condition. If the plug-in is performed in the power-off state, it is cold plug-in, and there is no danger involved in the case. Secondly, the specific intervention and alarm method and means should be considered. Among them, it can be divided into input conditions and output results.

[0122] In the specific embodiment of the present application, two input conditions and three output results will be mainly involved:

[0123] Input condition 1: identify the approach of hands or other objects to the daughter card through an infrared detector; the effectiveness of this condition is not limited to the direct contact of hands or other objects to the daughter card. As long as a relatively close distance above the infrared detector is passed, the input condition 1 is established.

[0124] The direct result triggered by input condition 1: the infrared detector sends a notification enable to the interrupt input pin of the control SOC.

[0125] Input condition 2: identify the touch of fingers to the daughter card through a capacitive fingerprint recognition module; the fingerprint recognition module can be dispersedly arranged on the front and back of the daughter card, and is deployed in the area where the fingers are easy to touch during the common operation of taking the daughter card; once one of the recognizers recognizes successfully, the input condition 2 is established.

[0126] The direct result triggered by input condition 2: the fingerprint recognition module sends a notification enable to the interrupt input pin of the control SOC.

[0127] Output result 1: LED light alarm; the LED light selects a prominent red color, indicating a warning.

[0128] Output result 2: the buzzer continuously sends an alarm buzz.

[0129] Output result 3: the buzzer alarm time is recorded in the Flash chip of the PCM for subsequent review.

[0130] Then, all the input / output conditions are associated to obtain the overall control flow as follows (refer to the above flow chart)

[0131] The whole FPGA system is powered on and powered on.

[0132] After the FPGA system is started, the control SOC chip enters a polling mode; according to the frequency of daily operation, the polling period can be set to 1 to several seconds. When the period arrives, the control SOC immediately detects whether the input condition 1 and the input condition 2 are true, that is, the corresponding notification enables the interrupt input pin of the control SOC chip;

[0133] If neither the input condition 1 nor the input condition 2 is true, the control SOC does not perform any action and enters the next polling working period;

[0134] If one of the input conditions 1 or 2 occurs, the control SOC judges the type of the input enable; if it is the input condition 1, the output result 1 is immediately executed; if it is the input condition 2, the output result 2 is immediately executed;

[0135] If the input conditions 1 and 2 occur at the same time, the control SOC has multi-thread processing capability and simultaneously executes the output results 1 and 2.

[0136] After one polling period ends, the polling work described in the second step is repeated;

[0137] The above-described working process is effective until the entire FPGA system is powered off; at this time, the subcard pulling action has become a cold pull, and the FPGA system will not be damaged.

[0138] After that, the historical alarm information recorded in the Flash can be read out through the software tool on the computer, and once the subcard or FPGA mainboard is damaged, the historical record will greatly help analyze the damage reason.

[0139] As shown in the specific embodiments of the present application shown in Figure 2 and 3 , the following effects are obtained:

[0140] (1) The hot pull of the subcard can be intervened and alarmed;

[0141] (2) The control SOC in the FPGA system occupies the central position of the entire control process, and the control effect is reliable;

[0142] (3) The infrared sensing module and the fingerprint sensing unit are innovatively arranged on the subcard.

[0143] (4) The historical alarm information is read by the computer, which is helpful for analyzing the user operation behavior.

[0144] (5) The FPGA system of the present application is suitable for both high-speed channel IO and low-speed channel IO.

[0145] It should be noted that the above embodiments can be freely combined as needed. The above only describes the preferred embodiments of the present application, and it should be pointed out that for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, which should also be considered as the protection scope of the present application.

Claims

1. A hot-swap processing system for peripheral expansion devices of an FPGA prototyping system, characterized in that, The hot-plug processing system comprises a sensing module and a monitoring module, the sensing module is electrically connected with the FPGA prototype verification system, and the monitoring module is arranged in the FPGA prototype verification system; The sensing module is configured to: According to a preset sensing strategy, the external object close to the FPGA prototype verification system is sensed, and when the distance between the external object and the peripheral expansion device is less than or equal to a preset distance threshold, a sensing signal is generated and sent to the FPGA prototype verification system, wherein the peripheral expansion device is a peripheral expansion device used by the FPGA prototype verification system during FPGA prototype verification; The monitoring module is configured to: According to a preset judgment strategy, whether the sensing signal sent by the sensing module is received is judged in a polling mode, and when it is judged that the sensing signal is received, prompt information is outputted to prompt the external object to perform a hot-plug operation on the peripheral expansion device through the prompt information; The FPGA prototype verification system comprises an FPGA mainboard unit and a power control unit, the peripheral expansion device is electrically connected with the FPGA mainboard unit, and the peripheral expansion device comprises a daughter card; The sensing module is arranged on the peripheral expansion device; The monitoring module is arranged in the power control unit; the power control unit comprises a system on chip; and the monitoring module is arranged in the system on chip; The monitoring module is a SOC control chip, the control structure of which comprises input pins and output pins; the SOC control chip receives the sensing signal sent by the sensing module through the input pins and controls the execution of output results through the output pins.

2. The hot pull process system of claim 1, wherein, The electrical connection between the sensing module and the FPGA prototype verification system comprises electrical connection between the sensing module and the FPGA prototype verification system through the peripheral expansion device.

3. The hot pull process system of claim 1, wherein, The sensing module comprises at least one of the following modules: an infrared sensing module and a fingerprint identification module.

4. The hot pull-through treatment system of any one of claims 1-3, wherein, When the sensing module comprises a fingerprint identification module, the fingerprint identification module comprises a capacitive sensing button arranged on the peripheral expansion device.

5. The hot pull process system of claim 4, wherein, The polling cycle is 0.5-10 seconds.

6. The hot pull process system of claim 5, wherein, The FPGA prototype verification system further comprises a storage unit for recording the sensing signal and / or the prompt information.

7. An FPGA prototype verification system comprising the hot-plug processing system according to any one of claims 1-6.

8. A hot-plug processing method of a peripheral expansion device of an FPGA prototype verification system, applied to the FPGA prototype verification system of claim 7, characterized in that, The hot-plug processing method comprises: According to a preset sensing strategy, the external object close to the FPGA prototype verification system is sensed by the sensing module, and when the distance between the external object and the peripheral expansion device is less than or equal to a preset distance threshold, a sensing signal is generated and sent to the FPGA prototype verification system, wherein the peripheral expansion device is a peripheral expansion device used by the FPGA prototype verification system during FPGA prototype verification; According to a preset judgment strategy, it is judged whether the sensing signal sent by the sensing module is received, and when it is judged that the sensing signal is received, prompt information is outputted to prompt the external object to perform a hot plug operation on the peripheral expansion device through the prompt information.

9. The hot plugging method of claim 8, wherein The sensing strategy includes a first sensing strategy and a second sensing strategy, and the prompt information includes first prompt information and second prompt information. The first sensing strategy includes a strategy of sensing and identifying by using an infrared sensor, and the second sensing strategy includes a strategy of sensing and identifying by using a fingerprint recognizer. The first prompt information includes information of prompting by using an LED lamp, and the second prompt information includes information of prompting by using a buzzer. According to the preset sensing strategy, the external object close to the FPGA prototype verification system is sensed, including: According to the first sensing strategy, the hand close to the FPGA prototype verification system is sensed and identified by using an infrared sensor, and according to the second sensing strategy, the hand contacting the peripheral expansion device is identified by using a fingerprint recognizer. It is judged whether the sensing signal sent by the sensing module is received, and when it is judged that the sensing signal is received, prompt information is outputted, including: If it is judged that the sensing signal sent by the infrared sensor is received, the first prompt information is outputted by using an LED lamp. If it is judged that the sensing signal sent by the fingerprint recognizer is received, the second prompt information is outputted by using a buzzer. If it is judged that the sensing signal sent by the sensing module is not received, the next judgment period is entered.

10. The hot-plugging method of claim 8, wherein The hot plug processing method further includes recording the occurrence time of the outputted prompt information.

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