An FPGA prototype verification platform based on a vehicle-gauge-grade millimeter wave radar SOC chip

Abstract

The application discloses a kind of FPGA prototype verification platform based on vehicle gauge grade millimeter wave radar SOC chip, belong to chip verification technical field.It includes: data selection unit, data generation unit, data storage unit, data transmission unit, data processing unit, analysis and verification unit and result display unit.Different data is selected using signal selector, dial code switch is dialled to 0 to select the data of real acquisition of radio frequency front end, dial to 1 to select the test data in HBM, the overall function of millimeter wave radar SOC chip is verified by building verification platform using integrated radio frequency front end analog chip, ADC chip and FPGA minimum system, the function of real millimeter wave radar SOC chip can be restored as far as possible using the verification platform built by multiple discrete devices, greatly reduce the risk of tape-out failure, using the HBM high bandwidth memory integrated in FPGA can replace the external DDR grain, and higher transmission rate can be obtained, so as to reduce the development cost and power consumption of verification platform.

Description

TECHNICAL FIELD

[0001] The application relates to the chip verification technical field, in particular to an FPGA prototype verification platform based on a vehicle regulation level millimeter wave radar SOC chip. BACKGROUND

[0002] With the development of science and technology, millimeter wave radars are more and more widely applied in various fields, such as automatic driving, unmanned aerial vehicle navigation, industrial detection and the like. Because of high precision, strong anti-interference ability, long detection distance, wide-angle detection, wide detection range and the like, the millimeter wave radar is regarded as the first choice for long-distance detection in intelligent driving.

[0003] In order to fully verify the functions of the millimeter wave radar chip, ensure the reliability and stability of each functional module of the chip, and comprehensively cover the function points, before the SOC chip is taped out, the real use scene is restored as much as possible by using the FPGA verification platform, because the FPGA implementation is closest to the real chip, and the design of the control software outside the chip can also be verified in advance on the verification platform. Compared with the slow speed of VCS simulation verification, the FPGA prototype verification can find design problems faster. This FPGA-based verification method can not only find potential problems in the design early, but also support the verification needs of complex system-level integration, thereby reducing the risk of tape-out failure. The common FPGA prototype verification platform currently only has a minimum FPGA system and some extended GPIO, and can only meet the verification of some intermediate frequency signal processing chips. SUMMARY

[0004] The purpose of the application is to provide an FPGA prototype verification platform based on a vehicle regulation level millimeter wave radar SOC chip, which can solve the problem that the common FPGA prototype verification platform currently only has a minimum FPGA system and some extended GPIO, and can only meet the verification of some intermediate frequency signal processing chips.

[0005] Technical scheme: In order to solve the above technical problems, according to one aspect of the application, more specifically, an FPGA prototype verification platform based on a vehicle regulation level millimeter wave radar SOC chip comprises a data selection unit, a data generation unit, a data storage unit, a data transmission unit, a data processing unit, an analysis and verification unit and a result display unit.

[0006] The data selection unit is used for selecting data to be processed.

[0007] The data generation unit is used for generating various data required by the FPGA prototype verification platform.

[0008] The data storage unit is used for storing intermediate frequency test data of different configurations and different targets.

[0009] Data transmission unit: for transmitting data between units of the platform;

[0010] Data processing unit: for processing data to meet the requirements of use;

[0011] Analysis and verification unit: for receiving and analyzing and verifying data that need to be analyzed and verified, and determining the analysis results of the data;

[0012] Result display unit: for displaying the results obtained by the analysis and verification unit.

[0013] Further, the data generation unit comprises a test data generation module and a real data simulation module;

[0014] Test data generation module: for generating intermediate frequency test data of different configurations and different targets;

[0015] Real data simulation module: for setting up a simulator to simulate different targets to provide real target data.

[0016] Further, the analysis and verification unit comprises a data receiving module, a data analysis module and a result determination module;

[0017] Data receiving module: for receiving data that need to be analyzed and verified;

[0018] Data analysis module: for analyzing, calculating and comparing the data received by the data receiving module;

[0019] Result determination module: for determining the results of analysis, calculation and comparison of the data analysis module.

[0020] Further, it comprises a radio frequency transceiver simulation chip, an ADC chip and an FPGA.

[0021] Further, the FPGA adopts a stacked silicon interconnection (SSI) technology, integrates a high bandwidth memory (HBM), deploys all functions of the digital end of the SOC chip, integrates a 32-bit high-performance MCU processor, and integrates common peripheral interfaces, chip GPIO and radar algorithm systems.

[0022] Further, the data selection unit is a signal selector, which selects different data through the signal selector. The dial code switch is set to 0 to select the real data collected by the radio frequency front end, and set to 1 to select the test data in the HBM.

[0023] Further, the analysis and verification unit comprises a main verification test flow and an auxiliary verification test flow when performing analysis and verification;

[0024] The main verification test flow is a millimeter wave radar chip target recognition flow, and the auxiliary verification test flow is a verification of functions of each peripheral.

[0025] Further, the main verification test flow is as follows: according to different configurations, the radio frequency front end is controlled to emit FMCW signals through the transmitting antenna, and the radio frequency front end receives echo signals through the receiving antenna, converts the echo signals into intermediate frequency signals after mixing and filtering, collects corresponding 4-channel intermediate frequency signals through an ADC, receives LVDS serial data, performs serial-parallel conversion processing, selects a data source to be processed according to a data selection switch, wherein the radio frequency front end actually collected data is selected when the switch is set to 0, and test data in the HBM is selected when the switch is set to 1, millimeter wave radar algorithm processing is started after a frame of data is collected, the position, speed and azimuth angle of the target are calculated, and the calculated results are reported to the simulated MCU core, the MCU core reports the information to the upper computer through a network port, and the information is displayed in a graphical manner.

[0026] The auxiliary verification test flow is as follows: peripheral interfaces attached to the chip are tested, wherein the peripheral interfaces include SPI A / B / C, QSPI, DEBUG_SPI, UART A / B / C, CAN / CAN-FD, I2C0 / 1, and the like, the functions of the peripheral interfaces are verified by comparing the data sent and received in the MCU core, the comparison result is judged in the MCU core, if the comparison result is PASS, the system returns to the initialization state, and if the comparison result is FAIL, the verification test is repeated, and relevant problems are located and debugged.

[0027] Further, the radio frequency transceiver analog chip is a radio frequency transceiver analog chip with 4 transmitting and 4 receiving, and a frequency range of 76GHz-81GHz.

[0028] Beneficial effects: FPGA integrates high bandwidth memory (HBM) to provide terabit-level memory, integrates a 32-bit high-performance MCU processor to control the scheduling of the whole system, the FPGA integrates 8GB HBM, the host computer can download the echo intermediate frequency data under different configurations to the HBM through the optical port, and the function of the SOC chip can be tested offline without using the radio frequency front end. Due to the particularity of the application of the millimeter wave radar SOC chip, the final purpose is to identify the distance, speed and azimuth angle of the target. Normal test should be carried out in anechoic chamber with wave-absorbing material, and the target is placed at a specified position, or a simulator for simulating various targets is placed. However, in order to more accurately reproduce and locate the problem in the early stage, and without the need to build a complex test environment, the verification platform adds a data selection path, and the host computer can download the echo intermediate frequency data under different configurations to the HBM in the FPGA through the gigabit network optical port. Here, a signal selector is used to select different data. The dial switch is set to 0 to select the data collected by the radio frequency front end, and set to 1 to select the test data in the HBM. The integrated radio frequency front end simulation chip, ADC chip and FPGA minimum system are used to build a verification platform to verify the overall function of the millimeter wave radar SOC chip. The verification platform built by using multiple discrete devices can restore the function of the real millimeter wave radar SOC chip as much as possible, greatly reducing the risk of tape-out failure. The HBM high bandwidth memory integrated in the FPGA can replace the external DDR grain, and a higher transmission rate can be obtained, which can reduce the development cost and power consumption of the verification platform. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is the overall framework diagram of the FPGA prototype verification platform;

[0030] Figure 2 is a data flow diagram;

[0031] Figure 3 is a processing flow diagram of the verification platform;

[0032] Figure 4 is a schematic diagram of the principle of the verification platform. DETAILED DESCRIPTION

[0033] In order to make the technical scheme of the present application clearer, the present application will be further described in detail in combination with the drawings and specific embodiments.

[0034] Embodiment 1

[0035] In Figure 1The structure diagram of the overall verification platform is given in the middle, which uses a 4-transmit, 4-receive, frequency range of 76GHz~81GHz radio frequency transceiver analog chip and ADC chip for receiving intermediate frequency signals, which is used to simulate the analog part of the SOC chip. Since the data interface of the ADC chip is an LVDS interface, the FPGA needs to add an LVDS interface driver in addition to the functions of the SOC chip. The FPGA in the figure uses a stacked silicon interconnect (SSI) technology and integrates a high-bandwidth memory (HBM) that can provide terabit-level memory. Figure 1 As can be seen in the middle, the FPGA deploys all the functions of the digital end of the SOC chip, which integrates a 32-bit high-performance MCU processor to schedule and control the entire system. In addition, it also integrates common peripheral interfaces, chip GPIO, and radar algorithm systems. Since the FPGA integrates 8GB of HBM, the host computer can download echo intermediate frequency data under different configurations to the HBM through the optical port. The SOC chip can be tested offline without using the radio frequency front end. The verification platform built with multiple discrete devices can restore the functions of the real millimeter wave radar SOC chip as much as possible, greatly reducing the risk of tape-out failure. The HBM high-bandwidth memory integrated in the FPGA can replace the external DDR grain, and higher transmission rate can be achieved, which can reduce the development cost and power consumption of the verification platform.

[0036] In Figure 2 The verification platform data flow is given in the middle. Due to the particularity of the millimeter wave radar SOC chip, the final goal is to identify the distance, speed, and azimuth angle of the target. Normal testing is performed in a darkroom with wave-absorbing materials, and the target is placed at a specified position, or a simulator that simulates various targets is placed. However, in the early stage, in order to more accurately reproduce and locate the problem without building a complex test environment, the verification platform adds a data selection path. The host computer can download echo intermediate frequency data under different configurations to the HBM inside the FPGA through the 10G network optical port. Here, a signal selector is used to select different data. The dial switch is set to 0 to select the real data collected by the radio frequency front end, and set to 1 to select the test data in the HBM.

[0037] In Figure 3 The processing flow of the verification platform is given in the middle, including the main verification test flow and the auxiliary verification test flow. The main verification test flow is the millimeter wave radar chip target recognition flow, and the auxiliary verification test flow is the verification of various peripheral functions.

[0038] The main verification test flow is: according to different configurations, the radio frequency front end is controlled, the FMCW signal is transmitted by the transmitting antenna, the echo signal is received through the receiving antenna of the radio frequency front end, and the intermediate frequency signal is converted after mixing and filtering, the corresponding 4-channel intermediate frequency signal is collected through the ADC, the LVDS serial data is received, the serial-parallel conversion processing is performed, the data source to be processed is selected according to the data selection switch, wherein the data collected by the radio frequency front end is selected by dialing 0, and the test data in the HBM is selected by dialing 1, after a frame of data is collected, the millimeter wave radar algorithm processing is started, the position, speed and azimuth angle of the target are calculated, the calculated results are reported to the simulated MCU core, the MCU core reports the information to the upper computer through the network port, and the information is displayed in the form of graphics.

[0039] The auxiliary verification test flow is: the peripheral interface attached to the test chip, including SPI A / B / C, QSPI, DEBUG_SPI, UART A / B / C, CAN / CAN-FD, I2C0 / 1 and other peripheral interfaces, the functions of the peripheral interfaces are verified by comparing the sent and received data in the MCU core, the comparison result is judged in the MCU core, if the comparison result is PASS, it returns to the initialization state, if the comparison result is FAIL, the verification test is repeated, and the related problems are located and debugged.

[0040] The above-described embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it cannot be understood as limiting the scope of the patent of the present application. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. An FPGA prototype verification platform based on an automotive-grade millimeter wave radar SOC chip, characterized in that, Comprise: Data selection unit, data generation unit, data storage unit, data transmission unit, data processing unit, analysis verification unit and result display unit; Data selection unit: for selecting data that needs to be processed; Data generation unit: for generating various data required by FPGA prototype verification platform; Data storage unit: for storing generated intermediate frequency test data of different configurations and different targets; Data transmission unit: for transmitting data between platform units; Data processing unit: for processing data to meet the requirements of use; Analysis verification unit: for receiving and analyzing the data that needs to be analyzed and verified, and judging the analysis results of the data; The analysis verification unit comprises a main verification test process and an auxiliary verification test process when analyzing and verifying; The main verification test process is a millimeter wave radar chip target recognition process, and the auxiliary verification test process is a verification of various peripheral functions; The main verification test process is: according to different configurations, control the radio frequency front end, open the transmit antenna to emit FMCW signal, at the same time, receive the echo signal through the receiving antenna of the radio frequency front end, and convert it into intermediate frequency signal after mixing and filtering, collect the corresponding 4-channel intermediate frequency signal through ADC, receive LVDS serial data, do serial-parallel conversion processing, select the data source that needs to be processed according to the data selection switch, where dialing to 0 selects the real data collected by the radio frequency front end, and dialing to 1 selects the test data in HBM, after collecting a frame of data, start the millimeter wave radar algorithm processing, calculate the position, speed and azimuth angle of the target, and report the calculated results to the simulated MCU core, and the MCU core reports the information to the upper computer through the network port, and displays it in the form of graphics; The auxiliary verification test process is: test the peripheral interfaces attached to the chip, including SPIA / B / C, QSPI, DEBUG_SPI, UARTA / B / C, CAN / CAN-FD, I2C0 / 1 and other peripheral interfaces, compare the sent and received data in the MCU core to verify the function of the peripheral interface, and judge the comparison result in the MCU core, if the comparison result is PASS, return to the initialization state, if the comparison result is FAIL, repeat the verification test and debug the related problems; Result display unit: for displaying the results calculated by the analysis verification unit.

2. The FPGA prototyping platform based on the automotive-grade millimeter wave radar SOC chip according to claim 1, wherein: The data generation unit comprises a test data generation module and a real data simulation module; Test data generation module: for generating intermediate frequency test data of different configurations and different targets; Real data simulation module: for setting the simulator to simulate different targets to provide real target data.

3. The FPGA prototyping platform based on the automotive-grade millimeter wave radar SOC chip according to claim 1, wherein: The analysis verification unit comprises a data receiving module, a data analysis module and a result determination module; Data receiving module: for receiving data that needs to be analyzed and verified; Data analysis module: for analyzing, calculating and comparing the data received by the data receiving module; Result determination module: for determining the results of analysis, calculation and comparison of the data analysis module.

4. The FPGA prototyping platform based on the automotive-grade millimeter wave radar SOC chip according to claim 1, wherein: Comprise: Radio frequency transceiver analog chip, ADC chip, FPGA.

5. The FPGA prototyping platform based on the automotive-grade millimeter wave radar SOC chip according to claim 4, characterized in that: The FPGA adopts a stacked silicon interconnection (SSI) technology, integrates a high bandwidth memory (HBM), deploys all functions of a digital end of the SOC chip, integrates a 32-bit high-performance MCU processor, and integrates common peripheral interfaces, chip GPIO and a radar algorithm system.

6. The FPGA prototyping platform based on the automotive-grade millimeter wave radar SOC chip according to claim 1, wherein: The data selection unit is a signal selector, different data is selected through the signal selector, and the data dial switch is dialled to 0 to select the data actually collected by the radio frequency front end, and dialled to 1 to select the test data in the HBM.

7. The FPGA prototyping platform based on the automotive-grade millimeter wave radar SOC chip according to claim 1, wherein: The radio frequency transceiver analog chip is a radio frequency transceiver analog chip with 4 transmitters and 4 receivers, and a frequency range of 76GHz~81GHz.

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