Fpga prototype verification method and system based on incremental compilation

Abstract

The application provides an FPGA prototype verification method and system based on incremental compilation, which comprises the following steps: obtaining a current chip design and dividing the current chip design into multiple partitions; comparing the current chip design with a previous chip design to obtain partitions that have changed and partitions that have not changed in the current chip design; synthesizing the partitions that have changed to obtain a current netlist of the partitions that have changed, merging the current netlist of the partitions that have changed with a previous netlist of the partitions that have not changed to obtain a netlist of the current chip design; mapping the netlist of the current chip design to an FPGA chip to obtain a current placement and routing design; and verifying the current placement and routing design, if the current placement and routing design does not meet the requirements, modifying the chip design and repeating the above process, and if the current placement and routing design meets the requirements, performing board debugging according to the current placement and routing design. The application improves the efficiency of FPGA prototype verification and the development speed of chips.

Description

Technical Field

[0001] This invention relates to the field of chip verification technology, and more specifically, to a method and system for verifying FPGA (Field Programmable Gate Array) prototypes based on incremental compilation. Background Technology

[0002] Chip verification is integral to the entire chip design process and typically falls into two main categories: software verification and FPGA-based chip prototyping (FPGA prototyping). Software verification involves verifying the chip design through logic simulation, while FPGA prototyping involves porting RTL (Register Transfer Level) to an FPGA and assembling an effective flow to verify the chip design. FPGA prototyping is orders of magnitude faster than software verification, significantly reducing verification time. As chip designs become larger and verification times increase, FPGA prototyping is finding wider and wider applications.

[0003] Currently, FPGA prototyping typically uses a fully compiled approach, with the compilation process including the following stages: reading the RTL design, synthesis, partitioning, placement and routing, generating download files, and on-board debugging. This fully compiled FPGA prototyping approach has the following problems: as chip design size and complexity increase, the compilation time for FPGA prototyping also increases. Even minor modifications to the chip design require traversing the entire compilation process, which cannot converge quickly, thus affecting the speed of FPGA prototyping and consequently the chip development speed. Summary of the Invention

[0004] To overcome the problems existing in the prior art, one aspect of the present invention provides an FPGA prototype verification method based on incremental compilation, comprising: acquiring a current chip design and dividing the current chip design into multiple partitions; comparing the current chip design with a previous chip design to obtain partitions in the current chip design that have changed compared to the previous chip design and partitions that have not changed; synthesizing the partitions that have changed to obtain the current netlist of the partitions that have changed; merging the current netlist of the partitions that have changed with the previous netlist of the partitions that have not changed to obtain the netlist of the current chip design; mapping the netlist of the current chip design onto the FPGA chip to obtain the current placement and routing design; and verifying the current placement and routing design, if it does not meet predetermined requirements, modifying the chip design and repeating the above process, and if it meets predetermined requirements, performing board-mounted debugging according to the current placement and routing design.

[0005] In the above method, mapping the netlist of the current chip design onto the FPGA chip to obtain the current placement and routing design may include: comparing the netlist of the current chip design with the netlist of the previous chip design to obtain the parts of the netlist of the current chip design that have changed compared to the netlist of the previous chip design; modifying the corresponding parts in the previous placement and routing design based on the changed parts, and using the modified previous placement and routing design as the current placement and routing design.

[0006] In the above method, mapping the netlist of the current chip design onto the FPGA chip to obtain the current placement and routing design may include: comparing the netlist of the current chip design with the netlist of the previous chip design to obtain the parts of the netlist of the current chip design that have changed compared to the netlist of the previous chip design; determining whether the changed parts meet the conditions for incremental placement and routing; if the conditions for incremental placement and routing are met, modifying the corresponding parts in the previous placement and routing design according to the changed parts, and using the modified previous placement and routing design as the current placement and routing design.

[0007] In the above method, the conditions for incremental placement and routing include: in the netlist of the current chip design, the proportion of the changed parts is less than a predetermined proportion; or the number of FPGA blocks corresponding to the changed parts is less than a predetermined number.

[0008] The above method may further include: obtaining the unchanging parts of the netlist of the current chip design compared with the netlist of the previous chip design; and locking the corresponding parts in the previous placement and routing design based on the unchanging parts.

[0009] In the above method, dividing the current chip design into multiple partitions may include: obtaining the partitions that have changed in the previous chip design compared to the current chip design; and replacing the partitions that have changed in the previous chip design with the corresponding parts in the current chip design.

[0010] In the above method, dividing the current chip design into multiple partitions may include dividing the current chip design into multiple partitions according to function.

[0011] In the above method, if there are multiple changed partitions in the current chip design compared to the previous chip design, then synthesizing the multiple changed partitions includes: synthesizing the multiple changed partitions in parallel.

[0012] Another aspect of the present invention provides an FPGA prototyping system based on incremental compilation, the system comprising:

[0013] The design input unit is used to obtain the current chip design.

[0014] Partitioning units are used to divide the current chip design into multiple partitions;

[0015] The synthesis unit is used to compare the current chip design with the previous chip design to obtain the partitions that have changed and the partitions that have not changed in the current chip design compared with the previous chip design; it synthesizes the partitions that have changed to obtain the current netlist of the partitions that have changed; it merges the current netlist of the partitions that have changed with the previous netlist of the partitions that have not changed to obtain the netlist of the current chip design.

[0016] The place-and-route unit is used to map the netlist of the current chip design onto the FPGA chip, obtaining the current place-and-route design; and

[0017] The inspection unit is used to inspect the current layout and wiring design. If it meets the predetermined requirements, it will be used for board-down debugging according to the current layout and wiring design.

[0018] In the above system, the placement and routing unit is used to compare the netlist of the current chip design with the netlist of the previous chip design to obtain the parts of the netlist of the current chip design that have changed compared with the netlist of the previous chip design; based on the changed parts, the corresponding parts in the previous placement and routing design are modified, and the modified previous placement and routing design is used as the current placement and routing design.

[0019] The embodiments of the present invention can achieve the following beneficial effects:

[0020] On the one hand, a partitioned compilation approach was introduced into the synthesis stage of FPGA prototype verification. This approach divides the chip design into multiple micro-partitions and uses incremental compilation to re-synthesize only the modified micro-partitions, thereby shortening the compilation time in the synthesis stage. Furthermore, multiple micro-partitions can be synthesized in parallel, further reducing the compilation time in the synthesis stage.

[0021] On the other hand, the concept of incremental compilation was also introduced in the placement and routing stage of FPGA prototype verification. Incremental placement and routing was performed with reference to the previous placement and routing design, thereby shortening the compilation time in the placement and routing stage.

[0022] The FPGA prototype verification method and system based on incremental compilation provided in this invention improves the efficiency of FPGA prototype verification by shortening the compilation time and increases the chip development speed.

[0023] It should be understood that the above general description and the following detailed description are illustrative and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention, wherein:

[0025] Figure 1 A flowchart illustrating an FPGA prototyping method based on incremental compilation according to an embodiment of the present invention is shown schematically.

[0026] Figure 2 A flowchart illustrating a method for synthesizing a current chip design according to an embodiment of the present invention is shown schematically.

[0027] Figure 3 A flowchart illustrating a method for placement and routing based on a netlist of a current chip design according to an embodiment of the present invention is shown schematically.

[0028] Figure 4 A block diagram of an FPGA prototyping system based on incremental compilation according to an embodiment of the present invention is shown schematically. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the invention.

[0030] Current FPGA prototyping typically employs a full compilation approach, resulting in increasingly longer compilation times as the chip design grows larger. Furthermore, even minor changes to the chip design necessitate traversing the entire compilation process, significantly impacting the speed of FPGA prototyping. To address these issues, this invention provides an FPGA prototyping method and system based on incremental compilation. This method incorporates incremental compilation into the synthesis and placement / routing stages to shorten compilation time in these phases.

[0031] One aspect of this invention provides an FPGA prototyping method based on incremental compilation to address the problems of low efficiency and slow chip development speed in current FPGA prototyping. This method is suitable for FPGA prototyping of SOC chips (especially very large SOC chips). In summary, the method includes: obtaining a current chip design; dividing the current chip design into multiple partitions; comparing the current chip design with a previous chip design to obtain the partitions that have changed and those that have not changed compared to the previous chip design; performing incremental synthesis on the changed partitions to obtain the current netlist of the changed partitions; merging the current netlist of the changed partitions with the previous netlist of the unchanged partitions to obtain the netlist of the current chip design; comparing the netlist of the current chip design with the netlist of the previous chip design to obtain the parts of the netlist of the current chip design that have changed compared to the previous chip design; modifying the corresponding parts in the previous placement and routing design based on the changed parts, and using the modified previous placement and routing design as the current placement and routing design; and verifying the current placement and routing design. If it does not meet predetermined requirements, the chip design is modified and the above process is repeated; if it meets predetermined requirements, the chip design is unmounted and debugged based on the current placement and routing design.

[0032] Figure 1 A flowchart illustrating an FPGA prototyping method based on incremental compilation according to an embodiment of the present invention is shown schematically, and will be referred to below. Figure 1 Describe each step of the method.

[0033] Step S11. Obtain the current chip design.

[0034] Before acquiring the chip design, an initial version needs to be completed. Chip designers can describe the designed chip circuit by performing RTL modeling, including descriptions of the clock domain, sequential logic, and combinational logic. RTL modeling involves using HDL (Hardware Description Language) languages ​​such as Verilog, VHDL, and SystemVerilog to describe the logic functions between registers and the HDL hierarchy of the chip circuit. RTL modeling ultimately yields a chip design file in RTL code form (i.e., the chip design). After completing the initial version of the chip design, chip designers can modify it and make further modifications based on the modified versions. The current chip design refers to the latest version. To acquire the current chip design, the creation time of each version of the chip design can be determined first, and the chip design with the latest creation time can be read as the chip design to be compiled, i.e., the current chip design. After acquiring the current chip design, it can be stored locally for quick retrieval in subsequent programs.

[0035] It should be understood that obtaining chip design information is also called design input, and the design input described above belongs to HDL input methods. In addition to the HDL input methods mentioned above, design input can also be achieved through schematic diagram input, IP core input, gate-level netlist file input, or a combination of these input methods.

[0036] Step S12. Divide the current chip design into multiple partitions.

[0037] After obtaining the current chip design, it is divided into multiple functional modules, with each module corresponding to a partition. In practice, the obtained RTL code chip design file can be divided by function to obtain multiple RTL code segments, so that each RTL code segment corresponds to a functional module.

[0038] By dividing the current chip design, the design dependencies within each partition can be high, while the design dependencies between partitions can be low, thus achieving high cohesion and low coupling. For example, the current chip design can be divided into 10 different partitions according to function: PCIE partition, DDR partition, bus partition, DMA partition, CPU partition, accelerated core partition 1, accelerated core partition 2, accelerated core partition 3, accelerated core partition 4, and the remaining partitions. Four accelerated core partitions are chosen because the design scale of accelerated core modules in chip design is often large, while modifications to accelerated core modules may only involve a small part of that module. The more refined the partitioning, the more accurately the subsequent program can locate the incremental synthesis part in the chip design, thereby improving compilation efficiency. It should be understood that the four accelerated core partitions here are only for example; those skilled in the art can divide the chip into 1-3 accelerated core partitions, or even 5 or more, depending on actual needs. In addition to accelerated core partitions, other partitions can also be further subdivided according to the design scale of the corresponding functional modules.

[0039] Step S13. Perform incremental synthesis on the current chip design to obtain the netlist of the current chip design.

[0040] If a previous compilation exists and the current synthesis constraints remain unchanged compared to the previous compilation constraints (hereinafter referred to as the previous synthesis constraints), but some partitions of the current chip design have changed compared to the previous compilation chip design (hereinafter referred to as the previous chip design), then synthesis can be performed on the changed partitions, while the unchanged partitions are not synthesized; this is incremental synthesis. Synthesizing the changed partitions will yield the current netlist for those partitions. This current netlist is then merged with the netlist obtained from the previous compilation for the unchanged partitions (hereinafter referred to as the previous netlist) to obtain the netlist for the current chip design.

[0041] Figure 2 The sub-steps of step S13 are illustrated schematically as follows:

[0042] S131. Obtain the current synthesis constraints. These constraints include, but are not limited to, speed, power consumption, cost, and circuit type constraints.

[0043] When chip designers complete the initial version of a chip design, they typically set initial synthesis constraints for that initial version. Afterward, chip designers can modify these initial synthesis constraints and make further modifications based on the modified versions; the current synthesis constraints refer to the latest version's synthesis constraints.

[0044] After obtaining the current synthesis constraints, you can store them locally so that you can quickly find them in subsequent programs.

[0045] S132. Determine if a previous compilation exists. If it does, proceed to step S133. Otherwise, treat all partitions in the current chip design as incremental synthesis partitions and proceed to step S135.

[0046] S133. Compare the current synthesis constraints with the previous synthesis constraints. If the current synthesis constraints have not changed compared with the previous synthesis constraints, proceed to step S134. Otherwise, take all partitions in the current chip design as incremental synthesis partitions and then proceed to step S135.

[0047] It should be understood that if there is no previous compilation, then all partitions of the current chip design have not been synthesized, so all partitions need to be treated as incremental synthesis partitions and synthesized in subsequent steps. In addition, if there is a previous compilation, but the current synthesis constraints have changed compared to the previous synthesis constraints, then all partitions also need to be treated as incremental synthesis partitions and re-synthesized under the current synthesis constraints.

[0048] S134. Compare the current chip design with the previous chip design to obtain the partitions that have changed and the partitions that have not changed in the current chip design compared with the previous chip design. The partitions that have changed are used as incremental synthesis partitions.

[0049] In practice, the current chip design file in RTL code form can be compared with the previous chip design file to obtain the changed RTL code segments in the current chip design file. The functional modules corresponding to the changed RTL code segments in the current chip design can be determined, and then the incremental synthesis partition can be obtained based on the partition corresponding to the functional module in the current chip design.

[0050] S135. Under the current synthesis constraints, perform synthesis on the incremental synthesis partition to obtain the current netlist of the incremental synthesis partition.

[0051] During incremental synthesis, synthesis tools (such as Synplify / Synplify Pro software from Synplicity) can be used to synthesize the incremental synthesis partitions in the current chip design. Specifically, for each incremental synthesis partition, the RTL code segment in its corresponding chip design file is translated into a logic connection netlist composed of basic logic units such as AND, OR, and NOT gates. The translated logic connections are optimized according to the current synthesis constraints, and the current netlist for that incremental synthesis partition is output.

[0052] In current chip designs with multiple incremental synthesis partitions, these incremental synthesis partitions can be synthesized in parallel to shorten synthesis time and improve compilation efficiency.

[0053] S136. Merge the current netlist of the incremental synthesis partition with the previous netlist of other partitions in the current chip design to obtain the netlist of the current chip design.

[0054] Other partitions refer to the partitions in the current chip design that have not changed compared to the previous chip design. If the current synthesis constraints have not changed compared to the previous synthesis constraints, the netlist obtained by synthesizing these partitions will be no different from the previous netlist. Therefore, there is no need to synthesize these partitions again, and their previous netlists can be directly used as the current netlist.

[0055] After obtaining the netlist of the current chip design, the netlist can be stored locally so that it can be quickly found in subsequent programs.

[0056] It should be noted that when all partitions in the current chip design are used as incremental synthesis partitions (e.g., there is no previous compilation, the current synthesis constraints have changed compared to the previous synthesis constraints, or all partitions in the current chip design have changed compared to the previous chip design), since there are no other partitions besides the incremental synthesis partitions, the current netlists of all incremental synthesis partitions are merged to obtain the netlist of the current chip design. Conversely, when no partitions in the current chip design are used as incremental synthesis partitions (e.g., there is a previous compilation, but the current chip design has not changed compared to the previous chip design, and the current synthesis constraints have not changed compared to the previous synthesis constraints, only the current place-and-route constraints have changed compared to the place-and-route constraints of the previous compilation), the previous netlists of all other partitions are merged, or the netlist of the previous chip design obtained in the previous compilation (hereinafter referred to as the netlist of the previous chip design) is obtained as the netlist of the current chip design.

[0057] As can be seen from the above incremental synthesis process, only the partitions that have changed in the current chip design are synthesized, and synthesis is performed in parallel when there are multiple changed partitions, which can significantly shorten the synthesis time and improve the compilation efficiency.

[0058] Step S14. Perform incremental placement and routing based on the netlist of the current chip design to obtain the current placement and routing design.

[0059] If a previous compilation exists and the current placement and routing constraints remain unchanged compared to the previous compilation's constraints (hereinafter referred to as the previous placement and routing constraints), but the netlist of the current chip design has changed compared to the previous chip design's netlist and meets the conditions for incremental placement and routing, then incremental placement and routing can be performed based on the changed portions. Specifically, under the current placement and routing constraints, based on the changed portions of the current chip design's netlist, incremental placement and routing is performed on the placement and routing design obtained from the previous compilation (hereinafter referred to as the previous placement and routing design) to obtain the current placement and routing design.

[0060] Figure 3 The sub-steps of step S14 are illustrated schematically as follows:

[0061] S141. Obtain the current placement and routing constraints, which include, but are not limited to, location constraints and timing constraints. Location constraints refer to the placement strategy, including I / O constraints and physical boundaries. Based on physical boundaries, the FPGA can be divided into multiple small blocks, and the corresponding module for each small block can be defined, facilitating incremental placement and routing. Timing constraints include period constraints, input offset constraints, and output offset constraints.

[0062] When chip designers complete the initial version of a chip design, they also set the initial placement and routing constraints. Later, chip designers can modify these initial placement and routing constraints and make further modifications based on the modified versions. The current placement and routing constraints refer to the latest version of the placement and routing constraints.

[0063] After obtaining the current layout and routing constraints, you can store them locally so that you can quickly find them in subsequent programs.

[0064] S142. Determine if a previous compilation exists. If it exists, proceed to step S143; otherwise, proceed to step S147.

[0065] S143. Compare the current layout and routing constraints with the previous layout and routing constraints. If the current layout and routing constraints have not changed compared with the previous layout and routing constraints, proceed to step S144; otherwise, proceed to step S147.

[0066] It should be understood that if there is no previous compilation, the current chip design has not been placed and routed, so global placement and routing (see step S147) is required instead of incremental placement and routing. In addition, if there is a previous compilation, but the current placement and routing constraints have changed compared with the previous placement and routing constraints, global placement and routing is also required.

[0067] S144. Compare the netlist of the current chip design with the netlist of the previous chip design to obtain the parts of the netlist of the current chip design that have changed compared to the netlist of the previous chip design.

[0068] S145. Determine whether the parts of the netlist in the current chip design that have changed compared to the netlist in the previous chip design meet the conditions for incremental placement and routing. If they do, proceed to step S146; otherwise, proceed to step S147.

[0069] The conditions for incremental placement and routing may include: in the netlist of the current chip design, the proportion of the changed parts compared with the netlist of the previous chip design to the whole (i.e., the whole netlist of the current chip design) is less than a predetermined proportion (e.g., 20%); or, the number of FPGA blocks corresponding to the changed parts in the netlist of the current chip design is less than a predetermined number, etc.

[0070] S146. Incremental placement and routing, that is, under the current placement and routing constraints, based on the parts of the netlist of the current chip design that have changed compared with the netlist of the previous chip design, incremental placement and routing is performed in the previous placement and routing design to obtain the current placement and routing design.

[0071] Specifically, the incremental placement and routing process may include: identifying the unchanged parts in the netlist of the current chip design compared to the netlist of the previous chip design, and locking these unchanged parts in the previous placement and routing design; additionally, under the constraints of the current placement and routing, modifying the corresponding changed parts in the previous placement and routing design based on the changed parts in the netlist of the current chip design compared to the netlist of the previous chip design. The incremental placement and routing method can refer to the Vivado locking incremental compilation technique.

[0072] S147. Global Placement and Routing: Under the current placement and routing constraints, perform global placement and routing from the netlist of the current chip design to the FPGA chip to obtain the current placement and routing design.

[0073] As mentioned above, global placement and routing is required under at least one of the following conditions: no previous compilation exists; the current placement and routing constraints have changed compared to the previous ones; or the netlist of the current chip design has changed compared to the previous one but does not meet the conditions for incremental placement and routing. Global placement and routing refers to mapping the entire netlist of the chip design onto the FPGA chip under placement and routing constraints, thereby generating a placement and routing design file. Placement refers to the rational configuration of hardware primitives and low-level cells in the netlist onto the inherent hardware structure inside the FPGA chip; routing refers to the rational connection of various components based on the topology of the placement, utilizing the various interconnect resources inside the FPGA chip. Placement and routing can be performed using software tools provided by the FPGA chip manufacturer. After placement and routing are completed, the software tool can automatically generate a placement and routing design file (i.e., placement and routing design), including placement and routing information, delay files, placement and routing reports, etc.

[0074] After obtaining the current layout and routing design, you can store the current layout and routing design locally so that you can quickly find the layout and routing design in subsequent programs.

[0075] As can be seen from the above incremental placement and routing process, by utilizing the previous placement and routing design, incremental placement and routing is only performed on the parts of the netlist that have changed, which can significantly shorten the placement and routing time and further improve compilation efficiency.

[0076] Step S15. Check the current layout and wiring design to determine whether it meets the predetermined requirements. If it does not meet the predetermined requirements, proceed to step S16; otherwise, proceed to step S17.

[0077] The verification of the current layout and routing design includes performing timing analysis and timing simulation after layout and routing, and determining whether the timing relationship meets the predetermined requirements of the chip design, such as determining whether the setup time and hold time meet the predetermined requirements.

[0078] Step S16. Determine whether the chip design, synthesis constraints, and / or placement and routing constraints have been further modified (e.g., further modifications to the current chip design, current synthesis constraints, and / or current placement and routing constraints). If it is found that the chip design, synthesis constraints, and / or placement and routing constraints have been updated by the chip designer, return to step S11 to recompile; otherwise, wait until it is found that the chip design, synthesis constraints, and / or placement and routing constraints have been updated by the chip designer.

[0079] If the predetermined requirements are not met, the chip designer can further modify the chip design, synthesis constraints, and / or placement and routing constraints. After confirming that the chip designer has modified the chip design, synthesis constraints, and / or placement and routing constraints, return to step S11.

[0080] S17. Lower board debugging.

[0081] Offboard debugging involves downloading the current layout and routing design to the FPGA prototype verification platform for functional debugging.

[0082] The above embodiments provide an FPGA prototyping method based on incremental compilation, which improves the efficiency of FPGA prototyping by shortening compilation time and increasing chip development speed. On one hand, a partitioned compilation approach is introduced in the synthesis stage of FPGA prototyping. This involves dividing the chip design into multiple micro-partitions and using incremental compilation to re-synthesize only the modified micro-partitions, thereby shortening the compilation time in the synthesis stage. Furthermore, multiple micro-partitions can be synthesized in parallel, further reducing the compilation time in the synthesis stage. On the other hand, the incremental compilation approach is also introduced in the place-and-route stage of FPGA prototyping. Incremental place-and-route is performed based on the previous place-and-route design, thus shortening the compilation time in the place-and-route stage.

[0083] The inventors conducted a comparative experiment between the incremental compilation-based FPGA prototyping method provided in the above embodiments and the existing full compilation-based FPGA prototyping method. The experimental results show that the incremental compilation-based FPGA prototyping method provided by the present invention can save 70% of the compilation time compared with the prior art, thereby greatly improving the efficiency of FPGA prototyping and accelerating the chip development speed.

[0084] In the above embodiments, after obtaining the current chip design, it is necessary to partition the current chip design in step S12. However, if a previous compilation exists, it is not necessary to partition the current chip design before comparing it with the previous chip design. In a preferred embodiment, the initial version of the chip design can be divided into multiple different partitions according to function. After obtaining the current chip design (and current synthesis constraints), it is determined whether a previous compilation exists. If a previous compilation exists, the current synthesis constraints are compared with the previous synthesis constraints. If the current synthesis constraints have not changed compared to the previous synthesis constraints, the previous chip design is compared with the current chip design to obtain the partitions in the previous chip design that have changed compared to the current chip design. The partitions in the previous chip design that have changed are replaced with the corresponding parts in the current chip design, thereby realizing the partitioning of the current chip design. In this preferred embodiment, it is not necessary to perform partitioning after each acquisition of the current chip design, but to replace the partitions based on the multiple partitions of the previous chip design, thereby further improving compilation efficiency.

[0085] It should be noted that some exemplary methods are depicted as flowcharts. Although the flowcharts represent operations as being executed sequentially, it is understood that many of the operations may be executed in parallel, simultaneously, or synchronously, and the order of the operations may also be rearranged. Processing may terminate upon completion of an operation, and may also have additional steps not included in the figures or embodiments.

[0086] Another aspect of the present invention provides an FPGA prototyping system based on incremental compilation. Figure 4 A block diagram of the system is shown schematically.

[0087] like Figure 4 As shown, the FPGA prototype verification system based on incremental compilation includes: a design input unit, a partitioning unit, a synthesis unit, a place-and-route unit, and a verification unit. The design input unit is used to acquire the current chip design; for details, please refer to step S11 above. The partitioning unit is used to divide the current chip design into multiple partitions; for details, please refer to step S12 above. The synthesis unit is used to perform incremental synthesis on the current chip design to obtain the netlist of the current chip design; for details, please refer to step S13 above. The place-and-route unit is used to perform incremental place-and-route based on the netlist of the current chip design to obtain the current place-and-route design; for details, please refer to step S14 above. The verification unit is used to verify the current place-and-route design; if it meets the predetermined requirements, it is used for off-board debugging based on the current place-and-route design; for details, please refer to steps S15-S17 above.

[0088] It should be understood that although several modules or units of the system have been described above, the way modules and units are divided is not limited to this. In fact, the features and functions of two or more modules or units described above can also be implemented in one module or unit, and conversely, the features and functions of one module or unit described above can be further divided and implemented by multiple modules or units.

[0089] Another aspect of the present invention provides a computer system for implementing an electronic device according to embodiments of the present invention. The computer system may include a bus, and a processor, memory, input devices (such as keyboard, mouse, sensors, etc.), output devices (such as display, printer, speaker, etc.), communication interfaces (such as parallel port, serial port, modem, network card, etc.), and other devices (such as detachable devices, drive devices, etc.) coupled to the bus.

[0090] The memory (such as ROM, PROM, EEPROM, RAM, SRAM, etc.) is used to store data and computer instructions or programs, including computer instructions or programs for implementing the incremental compilation-based FPGA prototyping method described above. The processor is used to execute a series of actions specified by the computer instructions or programs, such as executing the computer instructions or programs stored in the memory. When the processor executes the computer instructions or programs stored in the memory, the computer system is able to implement the embodiments of the incremental compilation-based FPGA prototyping method described above, including... Figure 1-3 The steps are shown in the figure.

[0091] Another aspect of the present invention provides a computer-readable medium, including but not limited to: floppy disks, hard disks, magnetic tapes, other magnetic media, CD-ROMs, CDRWs, DVDs, other optical media, punched cards, other physical media, ROMs, PROMs, EEPROMs, RAMs, SRAMs, or other computer-readable media, as well as transmission media (such as coaxial cables, fiber optic cables, carrier waves, etc.). The computer-readable medium can be included in the aforementioned computer system or can be a separate, uninstalled medium. The computer-readable medium is used to carry computer instructions or programs, including computer instructions or programs for implementing the incremental compilation-based FPGA prototyping method described above. When the computer instructions or programs in the computer-readable medium are read and executed by a processor (e.g., a processor in the aforementioned computer system), they can implement (e.g., cause the aforementioned computer system to implement) the method embodiments described above, including... Figure 1-3 The steps are shown in the figure.

[0092] Although the present invention has been described through preferred embodiments, it should be understood that the present invention is not limited to the embodiments described above and shown in the accompanying drawings, and those skilled in the art can make various changes and modifications without departing from the scope of the present invention.

Claims

1. An FPGA prototype verification method based on incremental compilation, characterized in that, The method includes: Obtain the current chip design and divide the current chip design into multiple partitions; The current chip design is compared with the previous chip design to obtain the partitions in the current chip design that have changed and the partitions that have not changed compared with the previous chip design. Obtain the current synthesis constraints, determine if a previous compilation exists. If a previous compilation exists and the current synthesis constraints have not changed compared to the previous synthesis constraints, then synthesize the partitions that have changed under the current synthesis constraints to obtain the current netlist of the partitions that have changed. Merge the current netlist of the partitions that have changed with the previous netlist of the partitions that have not changed to obtain the netlist of the current chip design. If no previous compilation exists or the current synthesis constraints have changed compared to the previous synthesis constraints, then synthesize all partitions in the current chip design under the current synthesis constraints to obtain the netlist of the current chip design. Map the netlist of the current chip design onto the FPGA chip, obtain the current placement and routing constraints, and determine if a previous compilation exists. If the current placement and routing constraints have not changed compared to the previous placement and routing constraints in the previous compilation, the netlist of the current chip design is compared with the netlist of the previous chip design to obtain the parts of the netlist of the current chip design that have changed compared to the previous chip design. It is then determined whether the changed parts meet the conditions for incremental placement and routing. If the conditions for incremental placement and routing are met, the corresponding parts in the previous placement and routing design are modified according to the changed parts, and the modified previous placement and routing design is used as the current placement and routing design. If there is no previous compilation, or the current placement and routing constraints have changed compared to the previous placement and routing constraints, or the conditions for incremental placement and routing are not met, then global placement and routing is performed to obtain the current placement and routing design. The current layout and routing design is checked. If it does not meet the predetermined requirements, the chip design is modified and the above process is repeated. If it meets the predetermined requirements, the chip is unboarded and debugged according to the current layout and routing design.

2. The method according to claim 1, characterized in that, The conditions for incremental placement and routing include: In the netlist of the current chip design, the percentage of the changed portion is less than a predetermined percentage; or The number of FPGA blocks corresponding to the changed parts is less than a predetermined number.

3. The method according to any one of claims 1-2, characterized in that, The method further includes: The portion of the netlist of the current chip design that has not changed compared to the netlist of the previous chip design is obtained; Based on the unchanged parts, the corresponding parts in the previous layout and wiring design are locked.

4. The method according to any one of claims 1-2, characterized in that, Dividing the current chip design into multiple partitions includes: The partitions that have changed compared to the current chip design in the previous chip design are obtained; Replace the partitions that changed in the previous chip design with the corresponding parts in the current chip design.

5. The method according to any one of claims 1-2, characterized in that, Dividing the current chip design into multiple partitions includes: The current chip design is divided into multiple partitions according to its functions.

6. The method according to any one of claims 1-2, characterized in that, The current chip design has several changed partitions compared to the previous chip design; as well as The process of integrating the multiple changed partitions includes integrating the multiple changed partitions in parallel.

7. An FPGA prototyping system based on incremental compilation, characterized in that, The system includes: The design input unit is used to obtain the current chip design. A partitioning unit is used to divide the current chip design into multiple partitions; The synthesis unit is used to compare the current chip design with the previous chip design to obtain the partitions in the current chip design that have changed and the partitions that have not changed compared to the previous chip design; obtain the current synthesis constraints, determine whether there was a previous compilation, if there was a previous compilation and the current synthesis constraints have not changed compared to the previous synthesis constraints, then synthesize the partitions that have changed under the current synthesis constraints to obtain the current netlist of the partitions that have changed, and merge the current netlist of the partitions that have changed with the previous netlist of the partitions that have not changed to obtain the netlist of the current chip design; if there was no previous compilation or the current synthesis constraints have changed compared to the previous synthesis constraints, then synthesize all partitions in the current chip design under the current synthesis constraints to obtain the netlist of the current chip design. The placement and routing unit is used to map the netlist of the current chip design onto the FPGA chip, obtain the current placement and routing constraints, and determine whether there was a previous compilation. If there was a previous compilation and the current placement and routing constraints have not changed compared to the previous placement and routing constraints, the placement and routing unit is used to compare the netlist of the current chip design with the netlist of the previous chip design to obtain the part of the netlist of the current chip design that has changed compared to the previous chip design. It is then determined whether the changed part meets the conditions for incremental placement and routing. If the conditions for incremental placement and routing are met, the corresponding part in the previous placement and routing design is modified according to the changed part, and the modified previous placement and routing design is used as the current placement and routing design. If there was no previous compilation, or the current placement and routing constraints have changed compared to the previous placement and routing constraints, or the conditions for incremental placement and routing are not met, then global placement and routing is performed to obtain the current placement and routing design. The inspection unit is used to inspect the current layout wiring design. If the predetermined requirements are met, the board is unloaded and debugged according to the current layout wiring design.

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