Chip reset verification method, device and equipment supporting multiple spatial domains

Abstract

An embodiment of the present invention provides a chip reset verification method, device and equipment supporting multiple spatial domains. The method includes: in a verification platform, encapsulating an independent and reusable general verification component for a reset signal; during simulation, driving the reset signal to the reset signal input port of a design under test in the reset_phase stage to reset the design under test, and monitoring the state of the reset signal by using a verification component related to the reset signal; jumping back to the reset_phase stage when the simulation is about to end; using a factory overloading mechanism to overload and replace the verification platform, so that after jumping back to the reset_phase, restarting the execution of a random test sequence; obtaining the actual response of the design under test to the random test sequence, and comparing the actual response with a predicted response to verify the reset function of the design under test. The present invention solves the problem of reset scenario testing for multiple clocks and their corresponding reset spatial domains that may exist in a DUT.

Description

Technical Field

[0001] The present invention relates to the field of chip design, and in particular, to a chip reset verification method, device, equipment and medium supporting multiple spatial domains. Background Art

[0002] When verifying a design under test (DUT) during chip design, it is often necessary to consider the verification in the reset scenario, that is, during the normal simulation operation of the DUT, the reset signal is set to the effective state to reset the DUT. After a delay of a certain number of clock cycles, the reset signal is released to restart the DUT, and it is verified whether the restarted DUT can work properly.

[0003] Usually, designers reset the DUT at any time point during the simulation process, which is likely to disrupt the running state of the testbench and cause unexpected problems. At the same time, there may be multiple clocks and their corresponding reset spatial domains in the DUT. Therefore, testing the reset scenario of such a multi-spatial domain chip in the same testbench is a complex and difficult problem, and there is currently no existing solution that can perfectly solve this problem. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a chip reset verification method, device, equipment and medium supporting multiple spatial domains to improve the above problems.

[0005] An embodiment of the present invention provides a chip reset verification method supporting multiple spatial domains, which includes:

[0006] In the verification platform, encapsulate independent and reusable general verification components for the reset signal; wherein, in the verification platform, the mutually independent verification components are located in different spatial domains;

[0007] During simulation, drive the reset signal to the reset signal input port of the DUT through the general verification component in the reset_phase stage to reset the DUT, and monitor the state of the reset signal by using the verification component related to the reset signal;

[0008] Jump back to the reset_phase stage when the simulation is about to end;

[0009] Use the factory overloading mechanism to overload and replace the verification platform, so that after jumping back to the reset_phase, restart the execution of the random test sequence to complete the test of the reset scenario of the DUT with multiple clocks and their corresponding reset spatial domains;

[0010] Obtain the actual response of the design under test to the random test sequence, and compare the actual response with the predicted response to verify the reset function of the design under test.

[0011] Preferably, encapsulating an independent reusable general verification component for the reset signal specifically includes:

[0012] Create a reset interface model to transmit the reset signal to the design under test;

[0013] Create a transaction data type related to the reset signal. The transaction data type contains two data variable members, which are respectively used to represent the delay time before reset and the duration for which the reset signal is valid, and constrain the above two times to a reasonable expected range;

[0014] Create an excitation sequence for generating the reset signal;

[0015] Create a driver for the excitation sequence for driving the reset signal, and drive the reset signal according to the reset delay and duration information in the transaction data type related to the reset signal and apply it to the reset signal input port of the design under test;

[0016] Create a reset monitor to monitor the reset signal and encapsulate it into a corresponding transaction data type;

[0017] Create a reset sequencer to arbitrate the excitation sequence of the reset signal and send it to the driver;

[0018] Encapsulate the above components related to the reset signal into an agent to generate a reusable general verification component.

[0019] Preferably, encapsulating the above components related to the reset signal into an agent to generate a reusable general verification component specifically includes:

[0020] Declare and instantiate the driver, sequencer, monitor, and configuration object included in the agent encapsulation, where the configuration object is used to configure the number of effective resets of the reset signal for the design under test during the entire simulation process;

[0021] In the reset_phase of UVM, if it is determined that the agent is in the UVM_ACTIVE mode, then call and execute the excitation sequence of the reset signal, thereby completing the effective reset of the corresponding reset signal for the design under test;

[0022] In the phase callback function `phase_ready_to_end`, when it comes to the `uvm_shutdown_phase` which is about to end the simulation, it is judged whether the number of effective resets is less than the previously configured number. If so, the `jump` method of the phase is called to jump back to the `reset_phase` to perform reset again. Thus, after the reset, it resumes execution in the `main_phase` to start sending a random test sequence to test the reset function.

[0023] Preferably, monitoring the status of the reset signal by using a verification component related to the reset signal includes:

[0024] Providing interface methods in the reset interface model to monitor the synchronous hardware reset signal, which are respectively used to wait for the reset signal to be activated and wait for the reset signal to be released.

[0025] Preferably, monitoring the status of the reset signal by using a verification component related to the reset signal further includes:

[0026] Implementing two parallel threads in the monitor of the signals of the input and output ports of the design under test. One thread is used to monitor the data on the signals of the input and output ports of the design under test, encapsulate it into a transaction data type, and broadcast it to other components in the verification platform; the other thread is used to monitor and wait for the reset signal to be activated. When the reset signal is valid, it stops monitoring, encapsulating, and broadcasting the port signals of the design under test.

[0027] Preferably, monitoring the status of the reset signal by using a verification component related to the reset signal further includes:

[0028] Implementing two parallel threads in the driver for driving the input signal sequence. One thread is used to obtain the input excitation sequence of the design under test and drive it to the input port of the design under test, and the other thread is used to monitor and wait for the reset signal to be activated. When the reset signal is valid, it stops driving and resets the signals on the input interface bus.

[0029] Preferably, monitoring the status of the reset signal by using a verification component related to the reset signal further includes:

[0030] In the sequencer for arbitrating and transmitting the input excitation sequence, there is no need to monitor the reset valid signal. After a phase jump, all sequences that are arbitrating and running on the sequencer are automatically stopped, and the sequencer is reset to an idle state.

[0031] Preferably, obtain the actual response of the design under test to the random test sequence, and compare the actual response with the predicted response to verify the reset function of the design under test. Specifically, it includes:

[0032] Implement two parallel threads in the scoreboard component used to compare the output results of the design under test and the reference model. One thread is used to predict the response and compare it with the actual response output by the design under test, and the other thread is used to monitor and wait for the reset signal to be activated. When the reset signal is valid, clear the internal logic.

[0033] An embodiment of the present invention also provides a chip reset verification device supporting multiple spatial domains, which includes:

[0034] A packaging unit for encapsulating an independent and reusable general verification component for the reset signal in the verification platform; wherein, in the verification platform, the independent verification components are located in different spatial domains;

[0035] A reset unit for driving the reset signal to the reset signal input port of the design under test through the general verification component in the reset_phase stage during simulation to reset the design under test, and monitoring the state of the reset signal using the verification component related to the reset signal;

[0036] A jump unit for jumping back to the reset_phase stage when the simulation is about to end;

[0037] A reload unit for reloading and replacing the verification platform using the factory reload mechanism, so that after jumping back to the reset_phase, restart the execution of the random test sequence to complete the test of the reset scenario of the design under test with multiple clocks and their corresponding reset spatial domains;

[0038] A verification unit for obtaining the actual response of the design under test to the random test sequence, and comparing the actual response with the predicted response to verify the reset function of the design under test.

[0039] An embodiment of the present invention also provides a chip reset verification device supporting multiple spatial domains, which includes a memory and a processor. The memory stores a computer program that can be executed by the processor to implement the chip reset verification method supporting multiple spatial domains as described above.

[0040] The present invention provides a method using phase jumps as a supplement to the testing method for the design under test in the reset scenario. Combining the UVM factory override mechanism and the domain mechanism, it realizes the support for the chip reset test scenarios in multiple spatial domains, thus solving the problem of testing the reset scenarios of multiple clocks and their corresponding reset spatial domains that may exist in the DUT. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0042] Figure 1 is the verification platform structure for the reset scenario of the present invention.

[0043] Figure 2 is the detailed division and execution sequence diagram of the UVM phase mechanism.

[0044] Figure 3 is the schematic diagram of the composition of the single-clock domain digital logic circuit.

[0045] Figure 4 is the schematic diagram of the composition of the multi-clock domain digital logic circuit

[0046] Figure 5 is the flowchart of the chip reset verification method supporting multiple spatial domains provided by the first embodiment of the present invention.

[0047] Figure 6 is the schematic diagram of the structure of the chip reset verification device supporting multiple spatial domains provided by the second embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0048] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0049] For a better understanding of the technical solutions of the present invention, the embodiments of the present invention will be described in detail below with reference to the drawings.

[0050] It should be clear that the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0051] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms of "a", "the" and "said" used in the embodiments of the present invention and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0052] Multiple embodiments of the present invention provide a chip reset verification method, device and equipment supporting multiple spatial domains, which comprehensively apply the phase mechanism, factory override mechanism and domain mechanism of UVM. For the convenience of understanding the present invention, the mechanisms involved in the present invention are described below.

[0053] (1), phase mechanism

[0054] The emergence of the phase mechanism is to unify the execution order of the code in the simulation. As long as everyone follows this order, there will be no problem of difficult debugging caused by the disordered code order, thus helping to achieve the reusability of the code and providing a unified standard for code simulation execution control.

[0055] The phases of UVM are mainly divided into three parts, as follows:

[0056] Build phases: This phase is used to configure, construct and connect a hierarchical verification platform.

[0057] Run-time phases: This phase consumes simulation time and generates and runs test cases.

[0058] Clean up phases: This phase is used to collect and print simulation results.

[0059] The specific division is as Figure 2 shown.

[0060] These phases are some predefined functions or tasks and are automatically called and executed in a certain order. The commonly used phases mainly include build, connect, run and report, which respectively complete the establishment, connection, operation and reporting of components.

[0061] In the run_phase, if the user wants to complete the test, the following excitation sequence is usually required:

[0062] 1. Power on

[0063] 2. Reset

[0064] 3. Configure register

[0065] 4. Execute test stimulus to complete target test content

[0066] 5. Wait for DUT to complete the test

[0067] One simple way is for the user to complete all of the above stimulus sequences in the run_phase; another way is that if the above several typical sequences can be divided into different intervals and the corresponding stimuli are executed according to the intervals, it can also make the test more hierarchical and achieve more refined simulation control. Therefore, the run_phase can be further divided into Figure 2 12 parallel phases on the right, with the execution order from top to bottom.

[0068] For example, the above five steps were originally all completed in the run_phase, but now they can be dispersed to the following phases to complete:[[]]

[0069] 1. Power on → pre_reset_phase

[0070] 2. Reset → reset_phase

[0071] 3. Configure register → configure_phase

[0072] 4. Execute test stimulus to complete target test content → main_phase

[0073] 5. Wait for DUT to complete the test → shutdown_phase

[0074] (2) factory Overloading Mechanism

[0075] The most important feature of the UVM factory overloading mechanism is its overloading function, which can replace existing components or objects in the verification platform, thus facilitating the reuse of the verification platform.

[0076] To use the overloading function of the UVM factory mechanism, the following three points need to be achieved:[[]]

[0077] (1) Register the object or component to the factory using the macro `uvm_object_utils(T)` or `uvm_component_utils(T)`.

[0078] (2) Use type_name::type_id::create() instead of the new constructor to construct components or objects.

[0079] (3) The overloaded class needs to be the parent class of the overloaded class.

[0080] Two overload usage modes are supported:

[0081] 1. Replace all components or objects A in the verification platform with components or objects B

[0082] 2. Replace some components or objects A in the verification platform with components or objects B

[0083] (3) Domain mechanism

[0084] like Figure 3 As shown, a digital chip is composed of a bunch of digital logic circuits, which are divided into combinational logic circuits and sequential logic circuits.

[0085] Sequential logic circuits are composed of clocks ( Figure 3 The clk in the clock source is used for control, and the rising or falling edge is used to synchronize and store data like a heartbeat. The combinational logic is some logical operations, such as AND, OR, NOT, XOR, etc. The path delay of the combinational logic circuit is different according to the complexity of the operation, but it needs to meet the setup time and hold time of the sequential logic circuit.

[0086] Generally, there is a combinational logic circuit between two sets of triggers. Figure 3 The above operation process is roughly as follows:

[0087] Data Input( Figure 3 data_in) in, and then through the register ( Figure 3 The D, Q, and CLK blocks in the figure are then stored, and then the operation is performed through a combinational logic, and finally the operation result is stored and output through a group of registers ( Figure 3 data_out), and the entire digital circuit is synchronized by a clock clk, which is equivalent to completing the circuit signal processing and transmission according to the jump of clk. Therefore, it can be said that this circuit works based on the clk clock, so the area of the circuit based on the clk clock can be called the clk clock domain.

[0088] Figure 3 The DUT has only one clk clock domain. Let's look at the situation where there are multiple clock domains on a DUT. As shown in Figure 4:

[0089] At this time, there are two clock domains, based on Figure 4The clk1 and the circuit operating based on the clk2 clock are independent of each other.

[0090] In fact, when doing verification, it is often encountered that the design under test (DUT) is based on multiple clock domains. Then, how to perform reset, configuration, and startup on these two independent parts respectively?

[0091] By default, all components in the verification platform are in the same spatial domain. However, if it is necessary to perform reset, configuration, and startup on two independent clock domains of the same DUT respectively, then these two independent parts need to be in two different domains respectively.

[0092] Separate the two clock domains through these two domains, then the sub - phases of the Run - time that consume simulation time within the two clock domains can run asynchronously and are independent of each other.

[0093] Note, however, that here the domain can only isolate the sub - phases of the Run - time. For other phases, they are actually synchronous, that is, the run_phase of the two domains is still synchronous, and other function phases that do not consume simulation time are also synchronous.

[0094] The present invention will be described in more detail below in combination with the above - mentioned mechanism.

[0095] Please refer to Figure 5 , the first embodiment of the present invention provides a chip reset verification method supporting multiple spatial domains, which includes:

[0096] S101, in the verification platform, encapsulate an independent and reusable general verification component for the reset signal; wherein, in the verification platform, independent verification components are in different spatial domains.

[0097] In this embodiment, based on the above - mentioned domin mechanism, the independent verification components of the verification platform in this embodiment are respectively in two different domains. In this way, multiple clock domains can be separated through these independent domains, and then the sub - phases of the Run - time that consume simulation time within these multiple clock domains can run asynchronously and are independent of each other.

[0098] Specifically, in this embodiment, step S101 includes:

[0099] Create a reset interface model to transmit the reset signal to the design under test;

[0100] Create a transaction data type related to the reset signal. The transaction data type contains two data variable members, which are used to represent the delay time before reset and the duration for which the reset signal is valid, respectively, and constrain the above two times to a reasonable expected range;

[0101] Create an excitation sequence for generating the reset signal;

[0102] Create a driver for the excitation sequence that drives the reset signal, and drive the reset signal according to the reset delay and duration information in the transaction data type related to the reset signal and apply it to the reset signal input port of the design under test;

[0103] Create a reset monitor to monitor the reset signal and encapsulate it into a corresponding transaction data type;

[0104] Create a reset sequencer to arbitrate the excitation sequence of the reset signal and send it to the driver;

[0105] Package the above components related to the reset signal into an agent to generate a reusable general verification component.

[0106] Among them, specifically include:

[0107] Declare and instantiate the driver, sequencer, monitor, and configuration object included in the agent package. The configuration object is used to configure the number of effective resets of the reset signal for the design under test during the entire simulation process;

[0108] In the reset_phase of UVM, if it is determined that the agent is in the UVM_ACTIVE mode, then call and execute the excitation sequence of the reset signal, thereby completing the effective reset of the corresponding reset signal for the design under test;

[0109] In the phase callback function phase_ready_to_end, when it is determined that when it comes to the uvm_shutdown_phase which is about to end the simulation, check whether the number of effective resets is less than the previously configured number. If so, then call the jump method of the phase to jump back to the reset_phase to perform the reset again. Thus, after the reset, re-execute in the main_phase to start sending a random test sequence to test the reset function.

[0110] S102. During simulation, drive the reset signal to the reset signal input port of the design under test through the general verification component in the reset_phase to reset the design under test, and use the verification component related to the reset signal to monitor the status of the reset signal.

[0111] In this embodiment, after obtaining the general verification component, by declaring and instantiating a reset signal excitation sequence (reset_sequence), it can be started at the reset_phase stage during the simulation process to generate a reset signal to the reset signal input port of the design under test. Among them, the effective reset times in the reset configuration object corresponding to the independent spatial domain can be randomly constrained and configured in the configure_phase, so as to generate a random number of effective reset excitations and apply them to the corresponding reset signal port of the design under test, so as to complete the random functional test under multiple reset scenarios.

[0112] In this embodiment, using the verification component related to the reset signal to monitor the state of the reset signal includes:

[0113] Provide interface methods in the reset interface model to monitor the synchronous hardware reset signal, which are used to wait for the reset signal to be activated and wait for the reset signal to be released respectively.

[0114] Implement two parallel threads in the monitor of the input and output port signals of the design under test. One thread is used to monitor the data on the input and output port signals of the design under test, encapsulate it into a transaction data type, and then broadcast it to other components in the verification platform. The other thread is used to monitor and wait for the reset signal to be activated. When the reset signal is valid, stop monitoring, encapsulating, and broadcasting the port signals of the design under test. After that, wait for the reset signal to be released, and the design under test enters the normal working state, and then repeat the above process continuously.

[0115] Implement two parallel threads in the driver (driver) for driving the input signal sequence. One thread is used to obtain the input excitation sequence elements (sequence_item) of the design under test and drive them to the input port of the design under test. The other thread is used to monitor. Wait for the reset signal to be activated. When the reset signal is valid, stop driving and reset the signals on the input interface bus. After that, wait for the reset signal to be released, and the design under test enters the normal working state, and then repeat the above process continuously.

[0116] In the sequencer for arbitrating and transmitting the input excitation sequence, there is no need to monitor the reset valid signal. After the phase jump, all the sequences that are arbitrating and running on the sequencer are automatically stopped, and the sequencer is reset to an idle state.

[0117] S103, jump back to the reset_phase stage when the simulation is about to end.

[0118] Specifically, it is possible to jump back to the reset_phase near the end of the simulation. This is equivalent to resetting the design under test during the simulation and then re-executing the random test sequence in the main_phase. At this time, if a random test sequence with basic functions is used, it is equivalent to performing a basic function test on the design under test in the reset scenario.

[0119] S104. Use the factory overloading mechanism to perform overloading replacement on the verification platform, so that after jumping back to the reset_phase, the random test sequence is restarted and executed to complete the test of the reset scenario of multiple clocks and their corresponding reset spatial domains in the design under test.

[0120] Specifically, in this embodiment, the factory overloading mechanism is used to perform overloading replacement on the verification platform for multiple spatial domains, which is mainly used to restart and execute the random test sequence after the phase jump to complete the test of the reset scenario of multiple clocks and their corresponding reset spatial domains in the design under test.

[0121] Among them, in the build_phase, the factory mechanism is used to perform overloading replacement on the verification components, so that after the clock reset signal corresponding to the independent spatial domain is effectively reset, the corresponding random test sequence is resented to apply the input stimulus to the design under test.

[0122] S105. Obtain the actual response of the design under test to the random test sequence, and compare the actual response with the predicted response to verify the reset function of the design under test.

[0123] In this embodiment, after the random test sequence is applied to the design under test, wait for the design under test to complete the operation and return the corresponding actual response.

[0124] Then, two parallel threads are implemented in the scoreboard component used to compare the output results of the design under test and the reference model. One thread is used to predict the response and compare it with the actual response output by the design under test, and the other thread is used to monitor and wait for the reset signal to be activated. When the reset signal is valid, the internal logic is cleared.

[0125] In summary, the present invention provides a method using phase jump as a supplement to the method for testing the design under test in the reset scenario, and at the same time combines the factory overloading mechanism and the domain mechanism of UVM to support the reset test scenario of chips with multiple spatial domains, thus solving the reset scenario test problem of multiple clocks and their corresponding reset spatial domains that may exist in the DUT.

[0126] Please refer to Figure 6, the second embodiment of the present invention also provides a chip reset verification device supporting multiple spatial domains, which includes:

[0127] An encapsulation unit 210, configured to encapsulate a separate and reusable general verification component for the reset signal in the verification platform; wherein, in the verification platform, independent verification components are located in different spatial domains;

[0128] A reset unit 220, configured to drive the reset signal to the reset signal input port of the design under test through the general verification component in the reset_phase stage during simulation to reset the design under test, and monitor the state of the reset signal by using the verification component related to the reset signal;

[0129] A jump unit 230, configured to jump back to the reset_phase stage when the simulation is about to end;

[0130] A reload unit 240, configured to reload and replace the verification platform by using the factory reload mechanism, so that after jumping back to the reset_phase, the random test sequence is restarted to execute to complete the test of the reset scenario of multiple clocks and their corresponding reset spatial domains in the design under test;

[0131] A verification unit 250, configured to obtain the actual response of the design under test to the random test sequence, and compare the actual response with the predicted response to verify the reset function of the design under test.

[0132] The third embodiment of the present invention also provides a chip reset verification device supporting multiple spatial domains, which includes a memory and a processor. The memory stores a computer program, and the computer program can be executed by the processor to implement the chip reset verification method supporting multiple spatial domains as described above.

[0133] The fourth embodiment of the present invention also provides a computer-readable storage medium, which stores a computer program, and the computer program can be executed by the processor of the device where the computer-readable storage medium is located to implement the chip reset verification method supporting multiple spatial domains as described above.

[0134] In several embodiments provided by the embodiments of the present invention, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device and method embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of devices, methods, and computer program products according to multiple embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, as well as the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0135] In addition, each functional module in various embodiments of the present invention can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part.

[0136] If the described functions are implemented in the form of software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, an electronic device, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes. It should be noted that in this article, the term "including", "comprising", or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article, or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article, or device. Without further limitations, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article, or device including the said element.

[0137] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A chip reset verification method supporting multiple spatial domains, characterized in that Including: In a verification platform, encapsulate an independent and reusable general verification component for the reset signal; wherein, in the verification platform, the mutually independent verification components are located in different spatial domains; During simulation, drive the reset signal to the reset signal input port of the design under test through the general verification component in the reset_phase stage to reset the design under test, and use the verification component related to the reset signal to monitor the state of the reset signal; Jump back to the reset_phase stage when the simulation is about to end; Use the factory override mechanism to override and replace the verification platform, so that after jumping back to the reset_phase, restart the execution of the random test sequence to complete the test of the reset scenario for multiple clocks and their corresponding reset spatial domains in the design under test; Obtain the actual response of the design under test to the random test sequence, and compare the actual response with the predicted response to verify the reset function of the design under test.

2. The chip reset verification method supporting multiple spatial domains according to claim 1, wherein Encapsulating an independent and reusable general verification component for the reset signal specifically includes: Create a reset interface model to transmit the reset signal to the design under test; Create a transaction data type related to the reset signal, and the transaction data type contains two data variable members, which are respectively used to represent the delay time before reset and the duration of the effective reset signal, and constrain the above two times to a reasonable expected range; Create an excitation sequence for generating the reset signal; Create a driver for the excitation sequence for driving the reset signal, and drive the reset signal according to the reset delay and duration information in the transaction data type related to the reset signal and apply it to the reset signal input port of the design under test; Create a reset monitor to monitor the reset signal and encapsulate it into a corresponding transaction data type; Create a reset sequencer to arbitrate the excitation sequence of the reset signal and send it to the driver; Encapsulate each of the above components related to the reset signal into an agent to generate a reusable general verification component.

3. The chip reset verification method supporting multiple spatial domains according to claim 2, characterized in that, Encapsulating each of the above components related to the reset signal into an agent to generate a reusable general verification component specifically includes: Declare and instantiate the driver, sequencer, monitor, and configuration object included in the agent encapsulation, where the configuration object is used to configure the number of times to effectively reset the reset signal of the design under test during the entire simulation process; In the reset_phase of UVM, if it is determined that the agent is in the UVM_ACTIVE mode, then call and execute the excitation sequence of the reset signal to complete the effective reset of the corresponding reset signal of the design under test; In the phase callback function `phase_ready_to_end`, when it comes to the `uvm_shutdown_phase` which is about to end the simulation, check if the number of effective resets is less than the previously configured number. If so, call the `jump` method of the phase to jump back to the `reset_phase` to perform reset again. Thus, after the reset, it will execute again in the `main_phase` to start sending a random test sequence to test the reset function.

4. The chip reset verification method supporting multiple spatial domains according to claim 1, wherein Monitoring the status of the reset signal using a verification component related to the reset signal includes: Providing interface methods in the reset interface model to monitor the synchronous hardware reset signal, respectively for waiting for the reset signal to be activated and waiting for the reset signal to be released.

5. The chip reset verification method supporting multiple spatial domains according to claim 4, wherein Monitoring the status of the reset signal using a verification component related to the reset signal also includes: Implementing two parallel threads in the monitor of the input / output port signals of the design under test. One thread is used to monitor the data on the input / output port signals of the design under test, encapsulate it into a transaction data type, and broadcast it to other components in the verification platform; the other thread is used to monitor and wait for the reset signal to be activated. When the reset signal is valid, stop monitoring, encapsulating, and broadcasting the port signals of the design under test.

6. The chip reset verification method supporting multiple spatial domains according to claim 5, wherein Monitoring the status of the reset signal using a verification component related to the reset signal also includes: Implementing two parallel threads in the driver for driving the input signal sequence. One thread is used to obtain the input excitation sequence of the design under test and drive it to the input port of the design under test; the other thread is used to monitor and wait for the reset signal to be activated. When the reset signal is valid, stop driving and reset the signals on the input interface bus.

7. The chip reset verification method supporting multiple spatial domains according to claim 6, characterized in that Monitoring the status of the reset signal using a verification component related to the reset signal also includes: In the sequencer for arbitrating and transmitting the input excitation sequence, there is no need to monitor the reset valid signal. After the phase jump, automatically stop all sequences that are arbitrating and running on the sequencer, and reset the sequencer to an idle state.

8. The chip reset verification method supporting multiple spatial domains according to claim 1, wherein Obtaining the actual response of the design under test to the random test sequence and comparing the actual response with the predicted response to verify the reset function of the design under test specifically includes: Implementing two parallel threads in the scoreboard component for comparing the output results of the design under test and the reference model. One thread is used to predict the response and compare it with the actual response output by the design under test; the other thread is used to monitor and wait for the reset signal to be activated. When the reset signal is valid, clear the internal logic.

9. A chip reset verification device supporting multiple spatial domains, characterized in that Including: An encapsulation unit for encapsulating an independent and reusable general verification component for the reset signal in the verification platform; among them, in the verification platform, the independent verification components are located in different spatial domains; A reset unit, which is used during simulation to drive a reset signal to the reset signal input port of the design under test through the general verification component in the reset_phase stage to reset the design under test, and monitor the status of the reset signal using a verification component related to the reset signal; A jump unit, which is used to jump back to the reset_phase stage when the simulation is about to end; A reload unit, which is used to reload and replace the verification platform using the factory reload mechanism, so that after jumping back to the reset_phase, the execution of the random test sequence is restarted to complete the test of the reset scenarios in the design under test with multiple clocks and their corresponding reset spatial domains; A verification unit, which is used to obtain the actual response of the design under test to the random test sequence and compare the actual response with the predicted response to verify the reset function of the design under test.

10. A chip reset verification device supporting multiple spatial domains, characterized in that, It includes a memory and a processor, and a computer program is stored in the memory, and the computer program can be executed by the processor to implement the multi-spatial-domain chip reset verification method according to any one of claims 1 to 8.

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