On-chip network task mapping method under resource-constrained conditions

Abstract

The present invention discloses a method for mapping network-on-chip tasks under resource-constrained conditions, wherein the key steps of the method include linear task mapping, nonlinear task mapping, and overall iteration, wherein the linear task is mapped when the impact of the nonlinear task is as small as possible, and then the nonlinear task is mapped to obtain a complete task mapping result, and the iteration is repeated several times to obtain different mapping schemes, and an evaluation function is used to calculate the evaluation value of each mapping scheme, and the mapping scheme with the largest evaluation value is selected as the final mapping scheme. The present invention comprehensively considers the delay of task processing, the power consumption on the processing platform, and the hardware resource limitation of each processing unit, so that the number of nonlinear tasks mapped to each processing unit is within an acceptable range, so that the mapping task can be normally executed in actual operation, so that the task mapping scheme obtained by the present invention is more reasonable and feasible, and the performance in terms of delay and power consumption is also very good.

Description

Technical Field

[0001] The present invention relates to the field of on-chip network task mapping, and in particular to an on-chip network task mapping method under resource-constrained conditions. Background Art

[0002] With the rapid development of integrated circuit technology, multi-processor system-on-chip (MPSoC) will integrate hundreds of cores in a single chip to provide high throughput, low latency and low energy consumption to meet various practical functional requirements. Due to the increase in bus load and the decrease in network communication performance of the traditional bus interconnection structure of MPSoC, the bus structure is no longer suitable for interaction between multiple cores. Therefore, drawing on the idea of ​​computer networks (see "Mapping and scheduling techniques in NoC: A survey of the state of the art," D. Belkebir and A. Zga, 2019 International Conference on Networking and Advanced Systems (ICNAS), 2019, pp. 1-6), as a new technology for high-speed communication between multiple cores, Network-on-Chip (NoC) was proposed to meet the growing communication needs of MP SoC. Each NoC connects the grids to each other with a special structure topology (typically 2D-Mesh structure, Torus structure, tree structure, etc.). Each grid consists of a processing element (PE), a router, a network interface (NI) and interconnection links (see "Research on Network-on-Chip Mapping for Power and Delay Optimization", H. Zhao, Beijing Industry University, MA thesis, 2019). Currently, NoC technology widely adopts an adjustable communication structure consisting of multiple PEs systems, in which routers and NIs constitute the underlying communication structure of the network topology, and the role of NI is to connect PEs to the network and extract access points for data conversion (see "Using SmartRouting for Secure and Dependable NoC-Based MPSoCs", Fernandes, C. Marcon, R. Cataldo and J. Sepúlveda, IEEE / ACM Transactions on Networking, vol. 28, no. 3, pp. 1158-1171, June 2020).NoC task mapping (TMP) is to find the appropriate location for a set of tasks with specific requirements, that is, to find the most suitable PE for each task. The result will greatly affect the network performance and system performance. Therefore, task mapping is a key step in NoC design (see "Calazans and F.G.Moraes, Dynamic Task Mapping for MPSoCs", ELD S Carvalho, NLV, IEEE Design & Test of Computers, vol. 27, no. 5, pp. 26-35, Sept.-Oct. 2010).

[0003] Currently, researchers consider multiple optimization indicators when solving TMP, including but not limited to: communication delay, power consumption, system utilization, real-time schedulability, and load balancing. For example, V. Tsoutsouras et al. proposed a real-time distributed task mapping method DRTRM based on local manager and controller strategies (see "A hierarchical distributed runtime resource management scheme for NoC-based many-cores", V. Tsoutsouras, I. Anagnosto poulos, D. Masouros, and D. Soudris, ACM Trans. Embedded Comput. Syst., vol. 17, no. 3, pp. 1–26, Jun. 2018); in the literature "Energy-aware task allocation for Network-on-Chip based heterogeneous multiprocessor systems" (J. Huang, C. Buckl, A. Raabe, and A. Knoll, in Proc. 19th Int. EuromicroConf. Parallel, Distrib. Networkw.-Based Process., Feb. 2011, pp. 447–454), firstly, the integer linear programming formula is extended to simultaneously consider the processing core communication energy, and then a simulated annealing (SA) method with timing adjustment is proposed to enhance the mapping optimization performance; the literature “Cluster based application mapping strategy for 2D NoC” (A. Aravindhan, S. Salini, and G. Lakshminarayanan, Procedia Techn ol., vol. 25, pp. 505–512, 2016) proposes a cluster-based mapping method to reduce communication costs, and evaluates the mapping solution performance on multiple benchmarks.The paper “Bandwidth-constrained multi-objective segmented brute-force alg orithm for efficient mapping of embedded applications on NoC architecture” (Khan, S. Anju m, UAGulzari, T. Umer, and B.-S. Kim, IEEE Access, vol. 6, pp. 11242–11254, 2018) proposes a bandwidth-constrained multi-objective segmented brute-force mapping (SBMAP) algorithm, which reduces the computational complexity and communication energy of NoC design; the paper “Elixir: A new bandwidth-constrained mapping for networks-on-chip” (Re shadi, A. Khademzadeh, and A. Reza, IEICE Electron. Exp., vol. 7, no. 2, pp. 73–79, 2010) proposes a two-step bandwidth-constrained algorithm Elixir, which first uses the search tree method to define the mapping with the minimum communication cost, and then obtains the optimal mapping scheme with the minimum delay and power consumption by using the Polaris tool chain technology.

[0004] However, most of the algorithms currently studied are based on the unrealistic and unreasonable assumption that each PE in the NoC has a large enough local memory, that is, the memory limit is not considered. The TMP solution obtained in this way is not feasible, because the memory required by the PE is much larger than the actual physical available memory, which may lead to very serious consequences. Since the hardware architecture of MPSoC determines the memory limit of each core, that is, the amount of memory must not exceed the amount of available memory (see "A Study of the Impact of For mulation of Cost Function in Task Mapping Problem on NoCs", JB de Barros, N. Anant harajaiah, M. Ayala-Rincón, CHLlanos and J. Becker, 2020 IEEE Nordic Circuits and Systems Conference (NorCAS), 2020, pp. 1-7), the hardware resources of NoC are also subject to certain restrictions, which will directly affect the lookup table resources used to store nonlinear operation result data, that is, each grid can only be allocated a limited number of lookup tables. Therefore, considering the resource limitation of the lookup table, the present invention proposes a task mapping method (RCM method) for NoC resource limitation. Through this method, a more reasonable and more feasible NoC task mapping solution can be obtained.

[0005] Since each PE on the NoC can only be allocated a specified number of lookup tables, and one lookup table corresponds to one nonlinear task, nonlinear task mapping has a very important impact on NoC task mapping under resource-constrained conditions. The method proposed in the present invention takes the lookup table resource limitation into account in the solution of NoC task mapping. Since genetic algorithm is a commonly used NoC mapping optimization algorithm, as a heuristic method, it can provide unbiased search in the partial order space, effectively improving the potential of finding schedulable task mapping (see "Simultaneous Multi-Objective Optimisation for Low-Power Real-Time Networks-On-Chip", MNSham Mohd Sayuti, 2018 4th International Conference on Electrical, Electronics and System Engineering (ICEESE), 2018, pp. 23-28). Therefore, this method first uses genetic algorithms to optimize the mapping of linear tasks while minimizing the impact of nonlinear tasks on linear task mapping, and obtains the optimal mapping solution for linear tasks; then, the nonlinear tasks are mapped, and first dynamically adjusted and allocated according to the adjustment coefficient. If the dynamic allocation cannot be performed beyond the adjustment range, static allocation is performed according to the priority and correlation; the above steps are repeated many times to obtain the task mapping solution with the best performance. In this way, the task mapping solution obtained by this method is more reasonable and feasible, and the performance in terms of delay and power consumption is also very good.

[0006] The present invention can be widely used in the field of task allocation for hardware resources in wireless communication systems. For example, due to the limited resources of the lookup table (LUT) in each FPGA, it is impossible to execute certain tasks that require the use of LUT resources on the FPGA without restriction. Therefore, a method is needed to effectively constrain the specific tasks assigned to the platform. The on-chip network task mapping method under resource-constrained conditions described in the present invention can fully consider the hardware resource limitations of each processing unit, so that the execution amount of tasks mapped to each processing unit is within an acceptable range, so that the mapping tasks can be normally executed in actual operation. Summary of the invention

[0007] The present invention proposes a method for mapping network tasks on a chip under resource-constrained conditions, which specifically includes the following steps:

[0008] 1) Input the implementation constraints of the RCM method and the information of the function to be mapped, including the number of lookup tables configured for each grid of the network on chip (NoC) (i.e., the maximum number of nonlinear tasks allowed to be mapped on a PE), the total number of iterations of the RCM method (i.e., the number of times the linear task mapping and nonlinear task mapping are repeatedly performed and the mapping results are recorded), and the task information of the function to be mapped (which corresponds to the original DFG and reflects all the edge and node information of the function)

[0009] 2) Perform linear task mapping: By modifying the original DFG, constructing a new DFG, and using a genetic algorithm to optimize the mapping, the mapping result of the linear task is obtained;

[0010] 3) Perform nonlinear task mapping: Continuously adjust the mapping of nonlinear tasks according to the correlation and implementation constraints, and finally obtain the optimal nonlinear task mapping result that meets the constraints;

[0011] 4) Record task mapping results: Since the tasks of the original DFG are divided into linear tasks and nonlinear tasks, and step 2) obtains the mapping results of all linear tasks, and step 3) obtains the mapping results of all nonlinear tasks, the different task mapping results obtained in these two steps are combined to obtain the complete task mapping results of the original DFG;

[0012] 5) Performing a complete operation of steps 2)-4) is called an iteration. Each iteration obtains a linear task mapping result and a nonlinear task mapping result. The two results are combined to obtain a complete task mapping result. Repeat steps 2)-4) for multiple iterations until the set total number of iterations is reached, that is, a total of different task mapping results of the total number of iterations can be obtained;

[0013] 6) Select the task mapping result with the largest evaluation value as the final mapping result.

[0014] Different from general task mapping methods, such as typical node priority algorithms ASAP (As Soon As Possible), ALAP (As Late As Possible) and CPF (Critical Path First) algorithms, they all simply consider the task processing delay to make the system's Makespan as small as possible, while the present invention not only considers the task processing delay, but also the power consumption on the processing platform, and more importantly, it fully considers the hardware resource limitations of each processing unit, so that the number of nonlinear tasks mapped to each processing unit is within an acceptable range, so that the mapping tasks can be normally executed in actual operation. Therefore, the task mapping scheme obtained by the present invention is more reasonable and feasible, and the performance in terms of delay and power consumption is also very good. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Schematic diagram of the NoC task mapping process

[0016] Figure 2 Schematic diagram to distinguish between linear and nonlinear task flow graphs (original DFG)

[0017] Figure 3 The overall flow chart of the on-chip network task mapping method under resource-constrained conditions of the present invention is

[0018] Figure 4 This is a linear task mapping flow chart of the present invention

[0019] Figure 5 Schematic diagram of DFG with virtual nodes added to the present invention

[0020] Figure 6 Schematic diagram of DFG for hiding nonlinear tasks in the present invention

[0021] Figure 7 Schematic diagram of DFG2 constructed in the present invention

[0022] Figure 8 Nonlinear task mapping flow chart of the present invention

[0023] Fig. 9 Schematic diagram of the association of task data to be assigned in the nonlinear task mapping of the present invention

[0024] Fig.10 Performance simulation comparison diagram of the embodiment of the present invention DETAILED DESCRIPTION

[0025] The following is a more detailed description of the embodiments of the present invention in conjunction with the accompanying drawings and the accompanying drawings so that those skilled in the art can implement the embodiments after reading the description. It should be understood that the embodiments described in this example are only for explaining the present invention and are not intended to limit the present invention.

[0026] Compared with general NoC task mapping, the present invention proposes task mapping under resource-constrained conditions. First, as one of the keys to NoC design, general task mapping firstly represents the application that needs to be processed on the NoC platform using a task flow graph, and then maps each task node of the task flow graph according to appropriate constraints and objective functions, and allocates each task node of the task flow graph to multiple processing units of the NoC platform for processing, that is, the task flow graph is allocated to the resource flow graph.

[0027] Among them, the task flow graph (DFG) is a directed acyclic weighted graph G 1 =G(V,E), where G represents a graph, V is the set of vertices in G, E is the set of edges in G, and G1 Each node represents a task, the number of tasks is |V|, and the node weight represents the processing time required for the task; each edge represents a data transmission path, the number of direct edges is |E|, and the edge e k =e i″,j″ The weight represents the i″ To node v j″ The amount of data transmitted on the directed link. Figure 1 The middle left figure represents a special function DFG with 7 tasks.

[0028] The resource flow graph is a directed graph G that abstracts the NoC structure. 2 =G(T,R), where G represents a graph, T is the set of vertices in G, R is the set of edges in G, and G 2 Each node t i″′ ∈T,i″′=1,2,...,|T| represents a grid of NoC, which is composed of a processing unit and a routing node. The number of grids is |T|; each edge r i″′,j″′ ∈R,i″′,j″′=1,2,...,|T| represents the slave node t i″′ To node t j″′ The number of unidirectional links is |R|. Figure 1 The middle right image represents a resource flow graph of a 3×3 2D-Mesh structure.

[0029] For task mapping under resource-constrained conditions, the NoC platform handles linear tasks and nonlinear tasks differently. Nonlinear tasks generally use lookup tables to obtain calculation results. Due to the limitation of NoC hardware resources, the number of lookup tables allocated to each grid is limited, so nonlinear task mapping needs to be performed within certain constraints.

[0030] like Figure 2 As shown in the figure, it represents the original DFG. The gray nodes on it represent linear tasks, the white nodes represent nonlinear tasks, the numbers on them represent the node weights, and the numbers on each directed edge represent the edge weights of the corresponding directed links. Assuming that each grid of the NoC is configured with m lookup tables, each PE is assigned at most m nonlinear tasks, and this limit cannot be exceeded, otherwise it cannot run normally in practice. For example, if the number of lookup tables in each grid is set to 2, the upper limit of the number of nonlinear tasks for each PE is 2. Although the performance of the entire system may be better when more than 2 nonlinear tasks are assigned to the same PE, in practice, due to hardware resource limitations, these nonlinear tasks cannot be executed normally. Therefore, it is necessary to limit the number of nonlinear tasks assigned to ensure that the number of nonlinear tasks assigned to each PE does not exceed its resource upper limit.

[0031] Before mapping, due to the hardware resource limitation of NoC, it is necessary to first determine whether the number of nonlinear tasks in the function to be mapped is within the mappable range. If it exceeds the mappable range, the function to be mapped cannot be mapped, and at this time, consider improving the hardware resources of NoC; if it is within the mappable range, all tasks including linear and nonlinear tasks in the function to be mapped can be mapped using the on-chip network task mapping method under resource-constrained conditions proposed by the present invention. Figure 3 FIG. 4 shows an overall flow chart of the on-chip network task mapping method (called RCM method) under resource-constrained conditions provided by this embodiment, as shown in FIG. Figure 3 As shown, the key steps of the on-chip network task mapping method under resource-constrained conditions include: S1) linear task mapping; S2) nonlinear task mapping; S3) overall iteration, which requires mapping linear tasks with the smallest impact of nonlinear tasks, and then mapping nonlinear tasks to obtain the complete task mapping result. Repeat the iteration N times to obtain N different mapping schemes, use the evaluation function to calculate the evaluation value of each mapping scheme, and select the mapping scheme with the largest evaluation value as the final mapping scheme. The overall process of the RCM method is shown in Figure 3 , the detailed process of a single iteration can be found in Figure 4 .

[0032] S1) Input the implementation constraints of the RCM method and the function information to be mapped:

[0033] S11) Input the number of lookup tables configured for each grid of the on-chip network (NoC), that is, the maximum number of nonlinear tasks allowed to be mapped on a PE;

[0034] S12) setting the overall number of iterations of the RCM method, that is, the number of times the task mapping (including linear task mapping and nonlinear task mapping) is repeatedly performed and the mapping results are recorded;

[0035] S13) Input the task information of the function to be mapped. What is input here is the task flow graph corresponding to the function to be mapped, that is, all the edge and node information of the original DFG.

[0036] S2) The specific steps of linear task mapping include:

[0037] S21) construct a new DFG, namely DFG2 (obtained from the original DFG by adding virtual nodes and hiding nonlinear tasks);

[0038] S22) Genetic algorithm optimization.

[0039] Wherein, S21) is used to map the linear task while minimizing the impact of the nonlinear task, so as to avoid the nonlinear task becoming the head and tail nodes of the original DFG (the head node here is all nodes without a parent node in the DFG, and the tail node is all nodes without a child node in the DFG). The step S21) is mainly divided into two sub-steps, specifically:

[0040] S211) Add virtual nodes: In order to better hide nonlinear tasks in step S212) (avoid nonlinear tasks as the head and tail nodes of the original DFG, which is not conducive to building a new DFG), such as Figure 5 As shown in the figure, a virtual in-node and out-node are added to the head and tail of the original DFG (the head and tail here refer to the part where the head and tail nodes of the DFG are located), that is, a virtual node with zero computation and communication overhead, that is, the node and edge weights are both 0 and it is a linear task is added to the head and tail of the original DFG;

[0041] S212) Hiding nonlinear tasks: Figure 6 As shown, on the basis of step S211), the topological position of the nonlinear task in the original DFG is retained, the weight of the nonlinear task is set to 0, and the weight of the edge connecting the nonlinear task is also set to 0; then the two linear tasks connecting a nonlinear task are directly connected, and the weight of this new edge (which directly connects the two linear tasks) is taken as the arithmetic average of the original two edge weights (i.e., the two edges between the two linear tasks originally connected to the nonlinear task and the nonlinear task), and DFG2 is obtained, that is, the constructed new DFG, as shown in FIG. Figure 7 shown.

[0042] Finally, in step S22), a genetic algorithm is used to perform mapping optimization on DFG2, thereby obtaining a mapping solution for the linear task.

[0043] Among them, step S212) is to avoid the occurrence of isolated nodes and discontinuous task numbers. When constructing DFG2, nonlinear tasks cannot be directly deleted. Instead, the presence of nonlinear tasks in DFG is reduced as much as possible, and nonlinear tasks are hidden to obtain DFG2 and a nonlinear task set (that is, the set of all nonlinear tasks remaining after removing linear tasks from the task set of the original DFG).

[0044] Since the mapping optimization problem is essentially an NP-hard problem, the optimal solution cannot be obtained unless it is exhaustively enumerated (see "An IP Core Mapping Algorithm Based on Neural Networks", Q. Chen, W. Huang, Y. Zhang and Y. Huang, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 1, pp. 189-202, Jan. 2021). As the scale of the problem increases, the mapping solution space will grow exponentially, and it is obvious that the exhaustive method is no longer applicable. In the task mapping problem for NoC, recent studies have found that heuristic algorithms can solve the mapping problem in a relatively short time and obtain an ideal solution (see "Real-time low-power task mapping in Networks-on-Chip", MNSM Sayuti and L. S. Indrusiak, 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2013, pp. 14-19). Among the heuristic algorithms, the genetic algorithm (GA) is the most widely used in dealing with task mapping problems. It simulates the biological evolution process of survival of the fittest in nature, and continuously iterates the selection, crossover and mutation operations to retain the performance of individuals with good adaptability, thereby obtaining the most ideal solution (see "Mapping Applications to Reconfigurable Mesh using Genetic Algorithm," P.Kulluand S.Tosun, 2019 22 nd Euromicro Conference on Digital System Design (DSD), 2019, pp.13-18).

[0045] And in step S22), when the DFG2 task mapping is optimized using the genetic algorithm, the optimal mapping result of the DFG2 task is found through multiple iterations, and the linear task mapping result is recorded.

[0046] After the linear tasks are assigned, nonlinear tasks need to be assigned. Here, it is assumed that there are NL nonlinear tasks to be mapped, and each PE can map at most k nonlinear tasks (k is the maximum number of nonlinear tasks allowed to be mapped on a PE set at the beginning). Nonlinear task mapping dynamically adjusts the nonlinear task mapping according to the task relevance, and finally obtains the optimal mapping result of all nonlinear tasks. The specific process of nonlinear task mapping is as follows: Figure 8 shown.

[0047] S3) The specific steps of nonlinear task mapping include:

[0048] S31) judging whether all nonlinear tasks are mapped and whether they are completed, if not, jumping to S32);

[0049] S32) finding the PE corresponding to the maximum correlation of the nonlinear task according to the correlation vector of the current nonlinear task to be mapped;

[0050] S33) Check whether the PE corresponding to the maximum correlation degree meets the hardware resource limit: if it does not exceed the hardware resource limit, jump to S34); if it exceeds the hardware resource limit, jump to S35);

[0051] S34) mapping the current nonlinear task to be mapped to the PE corresponding to the maximum correlation, and then jumping to S31);

[0052] S35) obtaining a PE sequence D corresponding to the current nonlinear task to be mapped in descending order of relevance;

[0053] S36) Initialize j=1, R=0 (j is used for counting to determine whether there is a j-th PE in the PE sequence D, and R represents the sum of the correlations of the mapped nonlinear tasks);

[0054] S37) Determine whether there is a j-th PE in sequence D, if yes, jump to S39); if no, jump to S38);

[0055] S38) updating the nonlinear task mapping result corresponding to R at this time (i.e., the mapping scheme of the nonlinear task), and then jumping to S31);

[0056] S39) Temporarily map the current nonlinear task to be mapped to the jth PE in D, and obtain the nonlinear task set T mapped to the jth PE j (T j The subscript j in the jth PE is consistent with the subscript j in the jth PE), let t = 1 (t is used for counting and judging the nonlinear task set T j Is there a t-th nonlinear task in );

[0057] S310) Get the task The corresponding PE sequence D2 is arranged in descending order of association, and m=1 (m is used for counting to determine whether there is an mth PE in the PE sequence D2);

[0058] S311) Check whether D2 has the mth PE, if so, jump to S312); if not, jump to S315);

[0059] S312) Check whether the mth PE in D2 meets the hardware resource limit: if it does not exceed the limit, jump to S313); if it exceeds the limit, set m=m+1, and then jump to S311);

[0060] S313) Task Map to the mth PE in D2, and calculate the sum of the correlations R2 (the sum of the correlations of the currently mapped nonlinear tasks);

[0061] S314) if R2>R, set R=R2, record the nonlinear task mapping result corresponding to R2 at this time (i.e., the mapping scheme of the current nonlinear task), and then jump to S315), otherwise R remains unchanged, and directly jump to S315);

[0062] S315) Let t = t + 1, if there is a task Then jump to S310), otherwise let j=j+1, and then jump to S37).

[0063] Performing a complete operation of steps S2)-S3) is called an iteration. Each iteration obtains a linear task mapping result and a nonlinear task mapping result. These two results are combined to obtain a complete task mapping result of the original DFG (because the tasks of the original DFG are divided into linear tasks and nonlinear tasks). Repeat steps S2)-S3) for multiple iterations until the set total number of iterations N is reached, and a total of N different task mapping results can be obtained. Among them, each iteration not only obtains a linear task mapping result and a nonlinear task mapping result, but also needs to record the linear task mapping result and the nonlinear task mapping result.

[0064] Since NoC mapping focuses on latency and power consumption, a trade-off needs to be achieved between these two aspects. Here, an evaluation function is used to evaluate the performance of each mapping scheme.

[0065] The minimum delay and power consumption are denoted as T min and P min , the maximum values ​​are respectively represented as T max and P maxThe present invention adopts simple additive weighting (SAW) to evaluate the obtained mapping scheme. This method has obvious advantages in processing dynamic scheduling of data sets and selecting relatively good scheduling schemes for each strategy.

[0066] S4) The specific steps of obtaining the final output mapping result include:

[0067] S41) calculating and obtaining evaluation values ​​of all mapping results;

[0068] S42) Select the mapping result with the largest evaluation value as the final task mapping result.

[0069] The specific steps of calculating the evaluation value in S41) include:

[0070] S411) Find the maximum and minimum values ​​of the delay, and the maximum and minimum values ​​of the power consumption in all mapping results respectively,

[0071] S412) The performance values ​​of the delay and power consumption of each iteration are standardized to obtain the standardized performance values ​​of the delay and power consumption of each mapping result, respectively, and the expressions are:

[0072]

[0073] Where N is the total number of iterations, i represents the i-th iteration, T′(i) represents the normalized delay value of the i-th iteration, T max represents the maximum value of delay, T(i) represents the delay value of the i-th iteration, P′(i) represents the power consumption value after normalization of the i-th iteration, P max represents the maximum power consumption, and P(i) represents the power consumption value of the i-th iteration.

[0074] S413) normalizes the standardized performance value to obtain normalized performance values ​​of delay and power consumption, respectively, and the expressions thereof are:

[0075]

[0076]

[0077] Wherein, T″(i) represents the normalized delay value of the i-th iteration, and P″(i) represents the normalized power consumption value of the i-th iteration. S414) The evaluation value Fit is obtained by using the evaluation function, and the calculation formula is:

[0078] Fit(i)=T″(i)·w T +P″(i)·w P

[0079] In step S413), the normalized performance values ​​of delay and power consumption are in the range of [0,1] (that is, the value ranges of T″(i) and P″(i) are both [0,1]), and the normalized solutions are distributed in a plane composed of two performance value axes. Each solution corresponds to a binary group (delay, power consumption), and the evaluation value Fit(i) is used to weigh each binary group.

[0080] In step S414), w T and w P are the weights of delay and power consumption respectively, satisfying the following constraints:

[0081]

[0082] Since it is hoped that the delay and power consumption values ​​T(i) and P(i) of the mapping result are as small as possible, that is, the larger the evaluation value of the mapping result, the more ideal the corresponding mapping result performance. In S4), the evaluation function given in step S414) can be used to obtain N evaluation values ​​corresponding to the N mapping results, and the mapping result corresponding to the maximum evaluation value is selected as the final task mapping result.

[0083] Here, the present invention explains the important parameters used in nonlinear task mapping: relevance (the relevance of the mapping task, such as Fig. 9 shown),

[0084] Due to the data dependency between tasks, the execution of a task must wait for all its predecessor tasks to complete and obtain the data they pass before it can start. In addition, because the efficiency of intra-core communication of tasks is much higher than that of inter-core communication and consumes less energy, in addition, the data transmission delay between tasks within the core is very small and negligible. Therefore, appropriate task kernel allocation can effectively reduce the inter-core communication of tasks, thereby minimizing system delay and power consumption. Intra-core communication here refers to the communication between two tasks with data dependency assigned to the same PE. Generally, the energy consumed by intra-core communication can be ignored; while inter-core communication refers to the communication between two tasks with data dependency assigned to two different PEs. It is mainly related to the number of hops between the two PEs and the amount of communication data.

[0085] For the task to be assigned T p ,like Fig. 9 As shown, task T p There may be data association with multiple tasks. Task T p The evaluation function is as follows:

[0086]

[0087] It represents the task T p Relative to PE x(PE x represents the data correlation strength (correlation degree) of the x-th PE, where the value of x is any integer in [1, M], Represents task T p The communication time between the predecessor and successor tasks, where i′=1,2,...,m represents task T p With the predecessor task T ui′ The communication time between j′=1,2,...,n represents task T p and the successor task T vj′ The communication time between tasks is assumed to be p There are m predecessor tasks and n successor tasks (the predecessor task here refers to task T p All directly related parent node tasks, that is, task T p Get data from the predecessor task; the successor task refers to task T p All directly associated child node tasks, i.e. task T p Output data to the subsequent task); parameter σ represents the p Whether the associated tasks are assigned to PE x In the example, σ is 0 or 1. 1 Represents task T 1 Is it assigned to PE? x In: If task T 1 Has been assigned in PE x In 1 Take 1; otherwise σ 1 Take 0.

[0088] σ ui′ Represents task T p The predecessor task T ui′ Is it assigned to PE? x In, if T ui′ Assigned in PE x Zhong Ze σ ui′ is 1, otherwise it is 0; vj′ Represents task T p The successor task T vj′ Is it assigned to PE? x In, if T vj′ Assigned in PE x Zhong Ze σ vj′ is 1 if the value is true, otherwise it is 0.

[0089] Since the on-chip network contains multiple PEs, assuming there are M PEs, the value of x is an integer in the interval [1, M]. p , an M-dimensional correlation vector can be obtained through the evaluation function formula, as follows:

[0090] R(T p )=(R 1 (T p ),R 2 (T p ),…,R M (T p ))

[0091] It represents task T p The strength of data association relative to each PE, that is, the degree of association.

[0092] The sum R of the correlations of the current feasible nonlinear task mapping results is calculated by adding the correlations of the currently mapped nonlinear task and its corresponding PEs.

[0093] Example

[0094] The present invention verifies the method proposed by the present invention by setting simulation environment and parameters and obtaining simulation results.

[0095] When designing a receiver for wireless communication systems, many communication-related algorithms are involved, such as channel equalization, channel estimation, precoding, and signal detection. In the process of implementing these algorithms, there are a lot of numerical operations and matrix operations. In the performance verification of the method of the present invention, we selected one of the classic implementation algorithms of channel equalization and channel estimation as a mapping example for simulation, which are the minimum mean square error-interference rejection combining MMSE-IRC (Minimum Mean Square Error-Interference Rejection Combining) and singular value decomposition SVD (Singular Value Decomposition) algorithms.

[0096] The simulation tool used in the present invention is MATLAB R2018a, and the operating environment is Windows 10. The simulation parameters are set as follows:

[0097] NoC system parameter settings: system clock frequency is 500MHz; data transmission rate is 8Gbps; power supply voltage is 1.2V; the data bit width of a flit (communication data packets are evenly divided into multiple flits, i.e., flits, during transmission) is 32 bits (the size of the cache buffer is measured in flits); the topology of the NoC is a 4×4 two-dimensional grid.

[0098] The parameter settings of the RCM method proposed in the present invention are as follows: the upper limit of the number of nonlinear tasks for each PE is 2, the number of iterations is 100, and the genetic algorithm parameters in the linear task mapping optimization are set as follows:

[0099] The population size is 30; the number of iterations is 100; the number of gene solutions is 100; the probabilities of selection, crossover and mutation are 0.5, 0.8 and 0.01 respectively.

[0100] Simulation performance comparison Fig.10 As shown, Fig.10 The left and right figures are the simulation results of the task mapping performance of MMSE-IRC and SVD respectively. The task mapping method proposed by the present invention under resource constraints is compared with the task mapping optimization method that does not consider resource constraints and uses genetic algorithms alone in terms of delay and power consumption, and random mapping is added as a reference. It can be seen that the performance of the task mapping method that considers resource constraints is better than random mapping overall, but not as good as the mapping that does not consider resource constraints, especially in terms of delay. This is because the nonlinear tasks originally mapped to the same PE could have obtained better delay performance, but due to the consideration of resource constraints, they have to be mapped to different PEs to meet the on-chip network resource constraints, which will lead to an increase in the amount of communication between PEs and an extension of the task execution time, which will inevitably cause a certain degree of attenuation in delay and power consumption performance, but the attenuation is not too large.

[0101] According to the simulation data, it can be seen that compared with the genetic algorithm, the performance degradation of the task mapping method considering resource constraints is within an acceptable range: for MMSE-IRC task mapping, its delay performance decreased by about 1.158%, and its power consumption performance decreased by about 0.166%; for SVD task mapping, its delay performance decreased by about 0.473%, and its power consumption performance decreased by about 4.241%.

[0102] Through simulation experiment analysis, it can be seen that the performance of the on-chip network task mapping method under resource-constrained conditions proposed by the present invention in terms of delay and power consumption has a certain degree of decline compared with the genetic algorithm mapping optimization method, but the decline is not very obvious and is within an acceptable range. This method actually sacrifices a small amount of system performance and fully considers the actual hardware resource limitations on the on-chip network, thereby avoiding the situation in which nonlinear tasks cannot be executed normally due to resource bottlenecks in actual task mapping operations, making the resulting task mapping scheme more feasible and greatly improving the reliability and stability of on-chip network task mapping.

[0103] The embodiments described above are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

Claims

1. A method for mapping network-on-chip tasks under resource-constrained conditions, characterized in that: The method comprises the following steps: S1) inputting implementation constraints and to-be-mapped function information of the on-chip network task mapping method under resource-constrained conditions, specifically including: S11) inputting the number of lookup tables configured for each grid of the on-chip network NoC, that is, the maximum number of nonlinear tasks k allowed to be mapped on a processing unit PE; S12) setting the total number of iterations N of the on-chip network task mapping method under the resource-constrained condition, that is, the total number of times the task mapping is repeatedly performed and the obtained mapping results are recorded, wherein the task mapping includes linear task mapping and nonlinear task mapping; S13) Inputting the task information of the function to be mapped, where the input is all the edge and node information of the task flow graph corresponding to the function to be mapped, wherein the task flow graph corresponding to the function to be mapped is called the original DFG; The task flow graph DFG is a directed acyclic weighted graph G1=G(V,E), where G represents a graph, V is the set of vertices in G, E is the set of edges in G, and each node v in G1 i″ Represents a task, the number of tasks is The node weight represents the processing time required for the task; each edge e k =e i″,j″ Represents a data transmission path, and the number of direct edges is Edge k =e i″,j″ The weight represents the i″ To node v j″ The amount of data transmitted on the directed link, j″=1,2,...,|V|; S2) performs linear task mapping, which specifically includes the following sub-steps: S21) The new DFG is obtained by adding virtual nodes and hiding nonlinear tasks from the original DFG, namely DFG2; S22) Genetic algorithm optimization of DFG2 task mapping; Wherein step S21) is used to map the linear task while minimizing the impact of the nonlinear task, so as to avoid the nonlinear task becoming the head and tail nodes of the original DFG. The head node here is all nodes without a parent node in the task flow graph, and the tail node is all nodes without a child node in the task flow graph. The step S21) is mainly divided into two sub-steps, specifically: S211) Adding virtual nodes: In order to better hide nonlinear tasks in step S212), a virtual in-node and out-node are added to the head and tail of the original DFG respectively, that is, a virtual node with zero computation and communication overhead, that is, a virtual node with zero node and edge weights and a linear task is added to the head and tail of the original DFG respectively, where the head and tail refer to the part where the head and tail nodes of the DFG are located; S212) Hide the nonlinear task: Based on step S211), retain the topological position of the nonlinear task in the original DFG, set the weight of the nonlinear task to 0, and set the edge weight connecting the nonlinear task to 0; then use a new edge to directly connect the two linear tasks connecting a nonlinear task, and the weight of the new edge directly connecting the two linear tasks is the arithmetic average of the weights of the two edges between the two linear tasks originally connected to the nonlinear task and the nonlinear task, and obtain DFG2, that is, the constructed new DFG; Finally, step S22) uses a genetic algorithm to optimize the task mapping of DFG2, thereby obtaining a linear task mapping result; S3) Perform nonlinear task mapping After the linear tasks are mapped, nonlinear tasks need to be mapped. Here, it is assumed that there are NL nonlinear tasks to be mapped, and each processing unit PE maps at most k nonlinear tasks. The nonlinear task mapping is to dynamically adjust the nonlinear task mapping according to the task association, and finally obtain the optimal mapping results of all nonlinear tasks. Step S3) specifically includes the following sub-steps: S31) judging whether all nonlinear tasks are mapped and whether they are completed, if not, jumping to S32); S32) finding the processing unit PE corresponding to the maximum correlation of the nonlinear task according to the correlation vector of the current nonlinear task to be mapped; S33) Check whether the processing unit PE corresponding to the maximum correlation degree meets the hardware resource limit: if it does not exceed the hardware resource limit, jump to S34); if it exceeds the hardware resource limit, jump to S35); S34) mapping the current nonlinear task to be mapped to the processing unit PE corresponding to the maximum correlation, and then jumping to S31); S35) obtaining a processing unit PE sequence D corresponding to the nonlinear task to be mapped in descending order of relevance; S36) Initialize j=1, R=0, where j is used for counting, to determine whether there is a j-th PE in the processing unit PE sequence D, and R represents the sum of the correlations of the mapped nonlinear tasks; S37) Determine whether there is a j-th PE in sequence D, if yes, jump to S39); if no, jump to S38); S38) updating the nonlinear task mapping result corresponding to R at this time, and then jumping to S31); S39) Temporarily map the current nonlinear task to be mapped to the jth PE in the sequence D, and obtain the nonlinear task set T mapped to the jth PE j , let t = 1, where t is used for counting, to determine the nonlinear task set T j Is there a t-th nonlinear task in S310) obtain a nonlinear task Arrange the corresponding processing unit PE sequence D2 in descending order of association, set m=1, where m is used for counting, and determine whether there is an mth PE in the processing unit PE sequence D2; S311) Check whether the sequence D2 has the mth PE, if so, jump to S312); if not, jump to S315); S312) Check whether the mth PE in sequence D2 meets the hardware resource limit: if it does not exceed the hardware resource limit, jump to S313); if it exceeds the hardware resource limit, set m=m+1, and then jump to S311); S313) Nonlinear tasks Map to the mth PE in the sequence D2, and calculate the sum of the correlations of the currently mapped nonlinear tasks R2; S314) If R2>R, then set R=R2, record the nonlinear task mapping result corresponding to R2 at this time, and then jump to S315), otherwise R remains unchanged and directly jump to S315); S315) Let t = t + 1, if there is a nonlinear task Then jump to S310); otherwise, let j=j+1, and then jump to S37); S4) Get the final task mapping result Executing a complete step S2)-S3) operation is called an iteration. Each iteration obtains a linear task mapping result and a nonlinear task mapping result. These two mapping results are combined to obtain a complete task mapping result of the original DFG. Repeat steps S2)-S3) for multiple iterations until the set total number of iterations N is reached, and a total of N different task mapping results are obtained. Among them, each iteration not only obtains a linear task mapping result and a nonlinear task mapping result, but also needs to record the linear task mapping result and the nonlinear task mapping result; step S4) specifically includes the following sub-steps: S41) calculating and obtaining evaluation values ​​of all task mapping results; S42) selecting the task mapping result with the largest evaluation value as the final task mapping result; The specific steps of calculating the evaluation value in S41) include: S411) Find the maximum value of the delay T in all task mapping results max , minimum value T min , and the maximum power consumption P max , minimum value P min ; S412) The performance values ​​of the delay and power consumption of each iteration are standardized to obtain the performance values ​​of the delay and power consumption of each task mapping result after standardization, and the expressions are as follows: Wherein, i represents the i-th iteration, T′(i) represents the normalized delay value of the i-th iteration, T(i) represents the delay value of the i-th iteration, P′(i) represents the normalized power consumption value of the i-th iteration, and P(i) represents the power consumption value of the i-th iteration; S413) normalizes the standardized performance value to obtain normalized performance values ​​of delay and power consumption, respectively, and the expressions thereof are: Wherein, T″(i) represents the normalized delay value of the i-th iteration, P″(i) represents the normalized power consumption value of the i-th iteration, and the value range of T″(i) and P″(i) are both [0,1]; S414) The evaluation function is used to obtain the evaluation value Fit(i) of the i-th iteration, and the calculation formula is: Fit(i)=T″(i)·w T +P″(i)·w P where w T and w P are the weights of delay and power consumption respectively, satisfying the following constraints: The evaluation function given in step S414) is used to obtain N evaluation values ​​corresponding to the N task mapping results, and the task mapping result corresponding to the maximum evaluation value is selected as the final task mapping result.

2. The on-chip network task mapping method under resource-constrained conditions according to claim 1, characterized in that: The calculation method of the sum of the association degree, the association degree vector, and the association degree of the currently mapped nonlinear task is: Since the NoC contains multiple processing units PE, assume that there are M processing units PE in total; for the task to be assigned T p , Task T p Relative to PE x The correlation is: Among them, PE x represents the xth PE, and the value range of x is any integer in [1,M]. Represents task T p The communication time between the predecessor and successor tasks, where Represents task T p With the predecessor task T ui′ The communication time between Represents task T p and the successor task T vj′ The communication time between tasks, where the predecessor task is task T p All directly related parent node tasks, that is, task T p Get data from the predecessor task; the successor task refers to task T p All directly associated child node tasks, i.e. task T p Output data to the subsequent task; σ ui′ Represents task T p The predecessor task T ui′ Is it assigned to PE? x In, if T ui′ Assigned in PE x Zhong Ze σ ui′ is 1, otherwise it is 0; vj′ Represents task T p The successor task T vj′ Is it assigned to PE? x In, if T vj′ Assigned in PE x Zhong Ze σ vj′ is 1, otherwise it is 0; For the task to be assigned T p , an M-dimensional correlation vector is obtained by the following formula: R(T p )=(R1(T p ),R2(T p ),…,R M (T p )) R(T p ) vector is composed of task T p The association degree composition with respect to each processing unit PE in the M processing units PE respectively; The sum of the correlations of the currently mapped nonlinear tasks is calculated by adding the currently mapped nonlinear tasks and their correlations with respect to each processing unit PE.

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