Display panel and driving method thereof

Abstract

The embodiment of the present disclosure provides a display panel and a driving method thereof. The display panel includes at least two timing controllers and their corresponding driving circuits, and the driving circuit is used to receive a picture frame to be displayed from the corresponding timing controller and display it in the corresponding display area of ​​the display panel. The driving method includes: when any of the at least two timing controllers receives a picture frame and it is an abnormal frame, the timing controller prevents the abnormal frame from being output to the driving circuit corresponding to the timing controller, and sends a shielding synchronization signal to other timing controllers in the display panel; wherein the shielding synchronization signal is used to instruct the other timing controllers to prevent the received picture frame with the same timing position as the abnormal frame from being output to the corresponding driving circuit. The embodiment of the present disclosure can avoid the phenomenon of serial defects in the picture of the display panel.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a driving method thereof. Background Art

[0002] The display panel is generally driven by two or more driving circuits to display picture frames, and each driving circuit is controlled by a corresponding timing controller.

[0003] like Figure 1 As shown, the system on chip (SoC) at the front end outputs a video signal VBO_R to the first timing controller TCON1, and outputs a video signal VBO_L to the second timing controller TCON2. The first timing controller TCON1 sends a clock embedded differential signal CEDS_R to the first driving circuit Driver1 to display the picture frame in the left display area of ​​the driving panel. The second timing controller TCON2 sends a clock embedded differential signal CEDS_L to the second driving circuit Driver2 to display the picture frame in the right display area of ​​the driving panel.

[0004] When a timing controller in the display panel receives an abnormal frame, the timing controller performs a shielding action on the abnormal frame to prevent the abnormal frame from being output to the corresponding drive circuit. However, the picture frame received by other timing controllers with the same timing position as the abnormal frame may not be an abnormal frame. For example, if it is a normal frame, the timing controller does not perform a shielding action on the normal frame and outputs the normal frame to the corresponding drive circuit. In this case, the picture frames displayed in each display area in the panel at the same time are located at different timing positions. In this way, in some scenarios, serial defects such as staggered lines may occur. Summary of the invention

[0005] The embodiments of the present disclosure provide a display panel and a driving method thereof to solve or alleviate one or more technical problems in the prior art.

[0006] As a first aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a method for driving a display panel, wherein the display panel includes at least two timing controllers and respective corresponding driving circuits, wherein the driving circuit is used to receive a picture frame to be displayed from the corresponding timing controller and display it in a corresponding display area in the display panel, and the driving method includes:

[0007] When any one of the at least two timing controllers receives a picture frame that is an abnormal frame, the timing controller blocks the abnormal frame from being output to a driving circuit corresponding to the timing controller, and sends a shielding synchronization signal to other timing controllers in the display panel;

[0008] The shielding synchronization signal is used to instruct the other timing controllers to prevent the received picture frames having the same timing position as the abnormal frame from being output to the corresponding driving circuit.

[0009] In some possible implementations, the driving method further includes:

[0010] When the power consumption of the driving circuit corresponding to the timing controller exceeds a set power consumption threshold, the timing controller sends an enable signal to the corresponding driving circuit and sends an enable synchronization signal to other timing controllers in the display panel;

[0011] Among them, the enable signal is used to instruct the driving circuit to output the odd-numbered row data in the odd frame to the display panel when the picture frame to be displayed is an odd frame, and to output the even-numbered row data in the even frame to the display panel when the picture frame to be displayed is an even frame, and the enable synchronization signal is used to instruct the other timing controllers to send an enable signal to the corresponding driving circuit.

[0012] In some possible implementations, the driving circuit includes a counter, and the counter is used to count a count value when the driving circuit receives a picture frame to be displayed, so as to indicate whether the current picture frame to be displayed is an odd frame or an even frame.

[0013] In some possible implementations, the driving circuit also includes a control output module; wherein the control end of the control output module is connected to the reset end of the counter, the control end of the control output module is used to receive the enable signal, and the counter is used to reset the count value of the counter when the level of the reset end is detected to be a high level.

[0014] In some possible implementations, the display panel includes a first timing controller, a second timing controller, a first driving circuit, and a second driving circuit; a picture frame output terminal of the first timing controller is connected to a picture frame input terminal of the first driving circuit, and a picture frame output terminal of the second timing controller is connected to a picture frame input terminal of the second driving circuit; the driving method includes:

[0015] When the first timing controller receives a picture frame that is an abnormal frame, the first timing controller blocks the abnormal frame from being output to the first driving circuit, and sends the shielding synchronization signal to the second timing controller;

[0016] When the second timing controller receives the shielding synchronization signal, the second timing controller prevents the received picture frame having the same timing position as the abnormal frame from being output to the second driving circuit;

[0017] When the second timing controller receives a picture frame that is an abnormal frame, the second timing controller blocks the abnormal frame from being output to the second driving circuit, and sends the shielding synchronization signal to the first timing controller;

[0018] In the case where the first timing controller receives the shielding synchronization signal, the first timing controller prevents the received picture frame having the same timing position as the abnormal frame from being output to the first driving circuit.

[0019] As a second aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a display panel, including:

[0020] At least two timing controllers and corresponding driving circuits, wherein the driving circuits are used to receive a picture frame to be displayed from the corresponding timing controller to display it in a corresponding display area of ​​the display panel, and the display panel is configured as follows:

[0021] When any one of the at least two timing controllers receives a picture frame that is an abnormal frame, the timing controller blocks the abnormal frame from being output to a driving circuit corresponding to the timing controller, and sends a shielding synchronization signal to other timing controllers in the display panel;

[0022] The shielding synchronization signal is used to instruct the other timing controllers to prevent the received picture frames having the same timing position as the abnormal frame from being output to the corresponding driving circuit.

[0023] In some possible implementations, the display panel is configured as follows:

[0024] When the power consumption of the driving circuit corresponding to the timing controller exceeds a set power consumption threshold, the timing controller sends an enable signal to the corresponding driving circuit and sends an enable synchronization signal to other timing controllers in the display panel;

[0025] Among them, the enable signal is used to instruct the driving circuit to output the odd-numbered row data in the odd frame to the display panel when the picture frame to be displayed is an odd frame, and to output the even-numbered row data in the even frame to the display panel when the picture frame to be displayed is an even frame, and the enable synchronization signal is used to instruct the other timing controllers to send an enable signal to the corresponding driving circuit.

[0026] In some possible implementations, the driving circuit includes a counter, and the counter is used to count a count value when the driving circuit receives a picture frame to be displayed, so as to indicate whether the current picture frame to be displayed is an odd frame or an even frame.

[0027] In some possible implementations, the driving circuit also includes a control output module; wherein the control end of the control output module is connected to the reset end of the counter, the control end of the control output module is used to receive the enable signal, and the counter is used to reset the count value of the counter when the level of the reset end is detected to be a high level.

[0028] In some possible implementations, the display panel includes a first timing controller, a second timing controller, a first driving circuit, and a second driving circuit; a picture frame output terminal of the first timing controller is connected to a picture frame input terminal of the first driving circuit, and a picture frame output terminal of the second timing controller is connected to a picture frame input terminal of the second driving circuit;

[0029] The first timing controller is configured to, when receiving a picture frame that is an abnormal frame, prevent the abnormal frame from being output to the first driving circuit, and send the shielding synchronization signal to the second timing controller;

[0030] The second timing controller is configured to, when receiving the shielding synchronization signal, prevent the received picture frame having the same timing position as the abnormal frame from being output to the second driving circuit;

[0031] The second timing controller is further configured to, when receiving a picture frame and it is an abnormal frame, prevent the abnormal frame from being output to the second driving circuit, and send the shielding synchronization signal to the first timing controller;

[0032] The first timing controller is further configured to prevent the received picture frame having the same timing position as the abnormal frame from being output to the first driving circuit when the shielding synchronization signal is received.

[0033] The display panel and driving method thereof of the disclosed embodiments are such that, when any timing controller of the display panel receives an abnormal frame, the timing controller prevents the abnormal frame from being output to the corresponding driving circuit, and sends a shielding synchronization signal to other timing controllers to instruct the other timing controllers to prevent the received picture frames having the same timing position as the abnormal frame from being output to the corresponding driving circuit, thereby making each driving circuit output a picture frame having the same timing position to the display panel, thereby avoiding undesirable phenomena such as misaligned lines on the display panel in certain scenarios.

[0034] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present disclosure will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments according to the present disclosure and should not be regarded as limiting the scope of the present disclosure.

[0036] Figure 1 is a schematic diagram of a display panel according to an embodiment of the present disclosure;

[0037] Figure 2 is a schematic diagram of a display panel according to another embodiment of the present disclosure;

[0038] Figure 3 is a schematic diagram of a display panel according to another embodiment of the present disclosure;

[0039] Figure 4 is a flow chart of a method for driving a display panel according to an embodiment of the present disclosure;

[0040] Figure 5a is a flow chart of a method for driving a display panel according to another embodiment of the present disclosure;

[0041] Figure 5b is a schematic diagram of displaying staggered lines on a display panel according to an embodiment of the present disclosure;

[0042] Figure 6 is a schematic diagram of a display panel according to another embodiment of the present disclosure;

[0043] Figure 7 is a schematic diagram of a display panel according to another embodiment of the present disclosure;

[0044] Figure 8 4 is a circuit signal timing diagram of a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.

[0046] Figure 2 FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present disclosure. Figure 2As shown, the display panel 200 includes at least two timing controllers (TCON1, TCON2, . . . , TCONn, where n is a positive integer) and respective corresponding driving circuits (Driver1, Driver 2, . . . , Drivern), and the driving circuits are used to receive the picture frame to be displayed from the corresponding timing controller and display it in the corresponding display area of ​​the display panel. For example, the first driving circuit Driver1 is used to receive the picture frame to be displayed from the first timing controller TCON1 and display it in the corresponding display area of ​​the display panel.

[0047] The display panel driving method provided in the embodiment of the present disclosure can be applied to Figure 2 The display panel shown can be executed by any timing controller in the display panel, and the method includes:

[0048] When any one of the at least two timing controllers receives a picture frame that is an abnormal frame, the timing controller blocks the abnormal frame from being output to a driving circuit corresponding to the timing controller, and sends a shielding synchronization signal to other timing controllers in the display panel;

[0049] The shielding synchronization signal is used to instruct other timing controllers to prevent the received picture frames having the same timing position as the abnormal frame from being output to the corresponding driving circuit.

[0050] In this example, since each timing controller of the display panel can synchronously perform the shielding action, each driving circuit can output a picture frame with the same timing position to the display panel, thereby avoiding undesirable phenomena such as staggered lines on the display panel in certain scenarios.

[0051] Exemplarily, the abnormal frame may include an error frame or an interference frame.

[0052] Exemplarily, when the timing controller receives a picture frame that is an abnormal frame, the timing controller prevents the abnormal frame from being output to a driving circuit corresponding to the timing controller, which is also called performing a masking action on the abnormal frame.

[0053] Exemplarily, the mask synchronization signal may include the timing position of the abnormal frame.

[0054] For example, Figure 3 As shown, the display panel 300 includes a first timing controller TCON1, a second timing controller TCON2, a first driving circuit Driver1 and a second driving circuit Driver2; the picture frame output end of the first timing controller TCON1 is connected to the picture frame input end of the first driving circuit Driver1, and the picture frame output end of the second timing controller TCON2 is connected to the picture frame input end of the second driving circuit Driver2. The driving method of the display panel includes:

[0055] When the first timing controller TCON1 receives a picture frame that is an abnormal frame, the first timing controller TCON1 blocks the abnormal frame from being output to the first driving circuit Driver1 and sends a shielding synchronization signal to the second timing controller TCON2;

[0056] When the second timing controller TCON2 receives the shielding synchronization signal, the second timing controller TCON2 prevents the received picture frame having the same timing position as the abnormal frame from being output to the second driving circuit Driver2;

[0057] When the second timing controller TCON2 receives a picture frame that is an abnormal frame, the second timing controller TCON2 blocks the abnormal frame from being output to the second driving circuit Driver2 and sends a shielding synchronization signal to the first timing controller TCON1;

[0058] When the first timing controller TCON1 receives the shielding synchronization signal, the first timing controller TCON1 prevents the received picture frame having the same timing position as the abnormal frame from being output to the first driving circuit Driver1 .

[0059] For example, Figure 4 As shown, S41, the first timing controller TCON1 performs a mask action on the abnormal frame; S42, the first timing controller TCON1 sends a shielding synchronization signal to the second timing controller TCON2; S43, when the second timing controller TCON2 receives the shielding synchronization signal, it performs a mask action on the picture frame with the same timing position as the abnormal frame. S44, the second timing controller TCON2 performs a mask action on the abnormal frame; S45, the second timing controller TCON2 sends a shielding synchronization signal to the first timing controller TCON1; S46, when the first timing controller TCON1 receives the shielding synchronization signal, it performs a mask action on the picture frame with the same timing position as the abnormal frame. This embodiment does not limit the above steps to be performed in sequence. For example, step S44 can be before step S41, and step S41 and step S42 can be performed in parallel.

[0060] For large-size, high-resolution, and high-refresh-rate display panels, due to excessive load, the display panel's drive circuit power consumption is too high, and problems such as excessive temperature of the drive circuit and the chip-on-chip board where the drive circuit is located will occur. At this time, the frame displayed by the panel is an overloaded frame. When any timing controller detects an overloaded frame, each timing controller in the display panel will synchronously turn on the brightness deviation elimination technology (Smart_TP) function, so that each drive circuit outputs odd-numbered row data in an odd-numbered frame to the display panel when the frame to be displayed is an odd-numbered frame, and outputs even-numbered row data in an even-numbered frame when the frame to be displayed is an even-numbered frame.

[0061] In some embodiments, the method for driving a display panel may further include:

[0062] When the power consumption of a driving circuit corresponding to any timing controller exceeds a set power consumption threshold, the timing controller sends an enable signal to the corresponding driving circuit and sends an enable synchronization signal to other timing controllers in the display panel;

[0063] Among them, the enable signal is used to instruct the driving circuit to output odd-numbered row data in the odd frame to the display panel when the picture frame to be displayed is an odd frame, and to output even-numbered row data in the even frame to the display panel when the picture frame to be displayed is an even frame; the enable synchronization signal is used to instruct other timing controllers to send enable signals to the corresponding driving circuits.

[0064] For example, Figure 5a As shown, Figure 3 Taking the display panel 300 in FIG. 1 as an example, the process of executing the Smart_TP function may be as follows:

[0065] S51, the first timing controller TCON1 detects a reloaded image;

[0066] S52, when the first timing controller TCON1 detects a reloaded screen, the first timing controller TCON1 sends an enable signal to the first driving circuit Driver1;

[0067] S53, when the first driving circuit Driver1 receives the enable signal, the first driving circuit Driver1 performs the Smart_TP function;

[0068] S54, the first timing controller TCON1 sends an enable synchronization signal to the second timing controller TCON2;

[0069] S55, when the second timing controller TCON2 receives the enable synchronization signal, the second timing controller TCON2 sends an enable signal to the second driving circuit Driver2;

[0070] S56: When the second driving circuit Driver2 receives the enable signal, the second driving circuit Driver2 performs the Smart_TP function.

[0071] In this example, the first timing controller and the second timing controller refer to one of the timing controllers, and the first and the second do not represent a sequential relationship. In the case where the display panel includes more than two timing controllers, the second timing controller refers to all other timing controllers except the first timing controller, and the process of executing the Smart_TP function is not illustrated one by one here.

[0072] In this example, when any timing controller performs a shielding action on an abnormal frame, other timing controllers each synchronously perform a shielding action on a picture frame having the same timing position as the abnormal frame, so that the driving circuit can still output the picture frame having the same timing position to the display panel. In this way, when the display panel detects an overloaded picture and executes the Smart_TP function, even if the timing controller receives an abnormal frame, the display panel will not have a situation where one driving circuit outputs odd-numbered line data in an odd-numbered frame and another driving circuit outputs even-numbered line data in an even-numbered frame, thereby avoiding the occurrence of misaligned lines on the display panel.

[0073] For example, if one driving circuit in the display panel outputs odd-numbered line data in an odd-numbered frame and the other driving circuit outputs even-numbered line data in an even-numbered frame, the display panel will appear as follows: Figure 5b Wrong line shown.

[0074] In some embodiments, Figure 6 As shown, the driving circuit 600 includes a counter 601. The counter 601 is used to count the count value Count when the driving circuit 600 receives a picture frame to be displayed, so as to indicate whether the current picture frame to be displayed is an odd frame or an even frame.

[0075] Exemplarily, the initial count value of the counter 601 is zero, and the count value Count is increased by one each time a picture frame is received.

[0076] Exemplarily, the initial count value of the counter 601 is a relatively large fixed value, and the count value Count is reduced by one each time a picture frame is received.

[0077] Therefore, when the driving circuit 600 performs the Smart_TP function, the driving circuit 600 can determine whether the current picture frame is an odd frame or an even frame according to the count value Count, thereby avoiding outputting an erroneous frame to the display panel.

[0078] In some embodiments, if the driving circuit is disturbed when receiving the picture frame from the timing controller, the count value of the driving circuit is wrong. In this way, when the driving circuit performs the Smart_TP function, the driving circuit outputs the picture data according to the wrong count value, which may output the wrong odd and even frame. For example, for a certain driving circuit in the panel, the current frame is actually an even frame, but due to the counting error, the count value is an odd number, then the driving circuit recognizes that the current frame is an odd frame, and outputs the odd-numbered row data in the current frame to the area 1 of the display panel. At the same time, for another driving circuit in the panel, the current frame is an even frame, and the count is accurate, and the count value is an even number, then the driving circuit recognizes that the current frame is an even frame, and outputs the even-numbered row data in the current frame to the area 2 of the display panel. In this case, if area 1 and area 2 are spliced ​​together for display, the phenomenon of misalignment will occur.

[0079] In some embodiments, the reset end of the counter is connected to the port of the driving circuit that receives the enable signal OE-EN. When each timing controller synchronously outputs the enable signal OE-EN, the counter of each driving circuit is pulled up by the high-level enable signal and reset synchronously, so that when each driving circuit executes the Smart_TP function, the counter starts counting from the starting count value to avoid the phenomenon of wrong row.

[0080] For example, Figure 6 As shown, the driving circuit 600 also includes a control output module 602; wherein the control terminal OE-EN-IN of the control output module 602 is connected to the reset terminal Reset of the counter, and the control terminal OE-EN-IN of the control output module 602 is used to receive the enable signal OE-EN output by the corresponding timing controller 603, and the counter 601 is used to reset the count value Count of the counter 601 when the level of the reset terminal Reset is detected to be high. The counter 601 transmits the count value Count to the control output module 602, and the control output module 602 determines whether the current picture frame is an odd frame or an even frame according to the count value Count.

[0081] In this example, when the display panel executes the Smart_TP function, the counter 601 can be reset synchronously and start counting from the starting count value Count, so as to avoid the phenomenon of serial defects in the display panel caused by inaccurate historical count values ​​of the driving circuit.

[0082] For example, Figure 7As shown, the timing controller 603 includes a video signal receiving end 701, a storage control module 702, a frame buffer module 703 and a data processing module 704. The video signal receiving end 701 receives a video signal VBO from a system on chip 705 located in the front, and transmits it to the storage control module 702. The storage control module 702 buffers the picture frame provided by the video signal VBO in the frame buffer module 703. When the storage control module 702 detects that the current picture frame is an abnormal frame, a mask action is performed on the abnormal frame in the frame buffer module 703. At this time, the abnormal frame will not be output to the data processing module 704, and the data processing module 704 will not output the abnormal frame to the driving circuit 600. For normal frames, the storage control module 702 will not mask them, but output them to the data processing module 704, and the data processing module 704 will convert the normal frame into a clock embedded differential signal CEDS and output it to the driving circuit 600.

[0083] Combination Figure 1 The circuit structure block diagram of the display panel provided and Figure 8 A circuit signal timing diagram is provided. An application example of the display panel and the driving method thereof provided by the present disclosure will be described below.

[0084] In response to errors or interference frames in the front-end on-chip system, each timing controller TCON masks the abnormal frames according to the existing mask function. However, this only masks the abnormal frames, and does not mask the normal frames with the same timing position as the abnormal frames. This will cause the picture frames output to the panel by each driver circuit at the same time to not be at the same timing position, and the counts between the driver circuits will be out of sync. When the driver circuit Driver executes the Smart_TP function, it outputs the odd-numbered line data of the odd frame when the current picture frame is an odd frame, and outputs the even-numbered line data of the even frame when the current picture frame is an even frame. Since the Driver count is out of sync, the following will occur: Figure 5b Wrong line shown.

[0085] like Figure 2 As shown, the circuit architecture of the display panel is a dual timing controller structure. Figure 8 As shown, VBO-R and VBO-L are given respectively Figure 2The VBO signals of the first timing controller TCON1 and the second timing controller TCON2. Assume that the interference from the front end to the first timing controller TCON1 and the second timing controller TCON2 is not synchronized, the second frame of VBO-R is an interference frame, and the second frame of VBO-L is a normal frame. Then, the first timing controller TCON1 performs a mask action on the second frame of VBO-R to shield it, and the first timing controller does not output it to the first driving circuit Driver1, then the first driving circuit Driver1 will not count the frame. However, in the existing scheme, since the second frame of VBO-L is a normal frame and the second timing controller TCON2 will not shield it, the second driving circuit Driver2 will count the frame. At this time, the signal timing output by the two timing controllers to the corresponding driving circuits can be as follows Figure 8 In this way, the count values ​​of the first driving circuit Driver1 and the second driving circuit Driver2 are not synchronized. When the first driving circuit Driver1 and the second driving circuit Driver2 execute the display strategy required by Smart_TP, the following will occur: Figure 5b Wrong line shown.

[0086] By adopting the scheme provided by the present disclosure, the mask action is synchronously performed on VBO-R and VBO-L, and the correct timing of CEDS is obtained. That is, the first timing controller TCON1 performs the mask action on the second frame of VBO-R (which is an abnormal frame), and the second timing controller TCON2 also performs the mask action on the second frame of VBO-L (which is a normal frame). Furthermore, the count values ​​of the first driving circuit Driver1 and the second driving circuit Driver2 are synchronized, and the first driving circuit Driver1 and the second driving circuit Driver2 will not appear when executing the display strategy required by Smart_TP. Figure 5b Wrong line shown.

[0087] The situation where an error frame appears in the front end is not limited to the above situation, and it may be the following situations: an error frame appears in the first timing controller TCON1, an error frame appears in the second timing controller TCON2, or an error frame appears in both the first timing controller TCON1 and the second timing controller TCON2. In any case, the first timing controller TCON1 and the second timing controller TCON2 both perform mask power on the current frame to ensure the synchronization of GSP counts in the back-end driving circuit.

[0088] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0089] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0090] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0091] In the present disclosure, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being “above”, “above”, and “above” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0092] The disclosure above provides many different embodiments or examples to implement different structures of the present disclosure. In order to simplify the present disclosure, the components and settings of specific examples are described above. Of course, they are only examples, and the purpose is not to limit the present disclosure. In addition, the present disclosure can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.

[0093] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of various changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for driving a display panel, characterized in that: The display panel includes at least two timing controllers and corresponding driving circuits, wherein the driving circuits are used to receive a picture frame to be displayed from the corresponding timing controllers and display it in a corresponding display area of ​​the display panel, and the driving method includes: When any one of the at least two timing controllers receives a picture frame that is an abnormal frame, the timing controller blocks the abnormal frame from being output to a driving circuit corresponding to the timing controller, and sends a shielding synchronization signal to other timing controllers in the display panel; The shielding synchronization signal is used to instruct the other timing controllers to prevent the received picture frames having the same timing position as the abnormal frame from being output to the corresponding driving circuit; the shielding synchronization signal includes the timing position of the abnormal frame; The driving method further comprises: When the power consumption of the driving circuit corresponding to the timing controller exceeds a set power consumption threshold, the timing controller sends an enable signal to the corresponding driving circuit and sends an enable synchronization signal to other timing controllers in the display panel; Among them, the enable signal is used to instruct the driving circuit to output the odd-numbered row data in the odd frame to the display panel when the picture frame to be displayed is an odd frame, and to output the even-numbered row data in the even frame to the display panel when the picture frame to be displayed is an even frame, and the enable synchronization signal is used to instruct the other timing controllers to send an enable signal to the corresponding driving circuit.

2. The method according to claim 1, characterized in that The driving circuit comprises a counter, and the counter is used to count a count value when the driving circuit receives a picture frame to be displayed, so as to indicate whether the current picture frame to be displayed is an odd frame or an even frame.

3. The method according to claim 2, characterized in that The driving circuit also includes a control output module; wherein the control end of the control output module is connected to the reset end of the counter, the control end of the control output module is used to receive the enable signal, and the counter is used to reset the count value of the counter when the level of the reset end is detected to be a high level.

4. The driving method according to claim 1, characterized in that: The display panel includes a first timing controller, a second timing controller, a first driving circuit and a second driving circuit; the picture frame output end of the first timing controller is connected to the picture frame input end of the first driving circuit, and the picture frame output end of the second timing controller is connected to the picture frame input end of the second driving circuit; the driving method includes: When the first timing controller receives a picture frame that is an abnormal frame, the first timing controller blocks the abnormal frame from being output to the first driving circuit, and sends the shielding synchronization signal to the second timing controller; When the second timing controller receives the shielding synchronization signal, the second timing controller prevents the received picture frame having the same timing position as the abnormal frame from being output to the second driving circuit; When the second timing controller receives a picture frame that is an abnormal frame, the second timing controller blocks the abnormal frame from being output to the second driving circuit, and sends the shielding synchronization signal to the first timing controller; In the case where the first timing controller receives the shielding synchronization signal, the first timing controller prevents the received picture frame having the same timing position as the abnormal frame from being output to the first driving circuit.

5. A display panel, characterized in that: include: At least two timing controllers and corresponding driving circuits, wherein the driving circuits are used to receive a picture frame to be displayed from the corresponding timing controller to display it in a corresponding display area of ​​the display panel, and the display panel is configured as follows: When any one of the at least two timing controllers receives a picture frame that is an abnormal frame, the timing controller blocks the abnormal frame from being output to a driving circuit corresponding to the timing controller, and sends a shielding synchronization signal to other timing controllers in the display panel; The shielding synchronization signal is used to instruct the other timing controllers to prevent the received picture frames having the same timing position as the abnormal frame from being output to the corresponding driving circuit; the shielding synchronization signal includes the timing position of the abnormal frame; When the power consumption of the driving circuit corresponding to the timing controller exceeds a set power consumption threshold, the timing controller sends an enable signal to the corresponding driving circuit and sends an enable synchronization signal to other timing controllers in the display panel; Among them, the enable signal is used to instruct the driving circuit to output the odd-numbered row data in the odd frame to the display panel when the picture frame to be displayed is an odd frame, and to output the even-numbered row data in the even frame to the display panel when the picture frame to be displayed is an even frame, and the enable synchronization signal is used to instruct the other timing controllers to send an enable signal to the corresponding driving circuit.

6. The display panel according to claim 5, characterized in that: The driving circuit comprises a counter, and the counter is used to count a count value when the driving circuit receives a picture frame to be displayed, so as to indicate whether the current picture frame to be displayed is an odd frame or an even frame.

7. The display panel according to claim 6, characterized in that: The driving circuit also includes a control output module; wherein the control end of the control output module is connected to the reset end of the counter, the control end of the control output module is used to receive the enable signal, and the counter is used to reset the count value of the counter when the level of the reset end is detected to be a high level.

8. The display panel according to claim 5, characterized in that: The display panel includes a first timing controller, a second timing controller, a first driving circuit and a second driving circuit; a picture frame output terminal of the first timing controller is connected to a picture frame input terminal of the first driving circuit, and a picture frame output terminal of the second timing controller is connected to a picture frame input terminal of the second driving circuit; The first timing controller is configured to, when receiving a picture frame that is an abnormal frame, prevent the abnormal frame from being output to the first driving circuit, and send the shielding synchronization signal to the second timing controller; The second timing controller is configured to, when receiving the shielding synchronization signal, prevent the received picture frame having the same timing position as the abnormal frame from being output to the second driving circuit; The second timing controller is further configured to, when receiving a picture frame and it is an abnormal frame, prevent the abnormal frame from being output to the second driving circuit, and send the shielding synchronization signal to the first timing controller; The first timing controller is further configured to prevent the received picture frame having the same timing position as the abnormal frame from being output to the first driving circuit when the shielding synchronization signal is received.

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