Semiconductor structure and method of fabricating the same
By employing ion implantation methods with different energies in the 3D DRAM structure, the problem of insufficient doping control capability was solved, a uniform distribution of dopant ion concentration was achieved, and the reliability and performance of the device were improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-05-24
- Publication Date
- 2026-06-05
AI Technical Summary
In 3D DRAM structures, the doping control capability of ion doping technology is relatively weak, resulting in uneven distribution of dopant ion concentration, which affects the refresh time and performance of the device.
By performing ion implantation on the first and second semiconductor layers in the stacked structure and using different energy controls, the concentration of doped ions in the bit line region and capacitor region is ensured to be within a preset range. This includes forming a mask layer and adjusting the ion implantation energy, using a shielding layer to protect the surface, and performing multiple ion implantations to achieve uniform distribution.
This improves the doping control capability of stacked devices, ensures uniformity of dopant ion concentration, and enhances the reliability and performance of semiconductor structures.
Smart Images
Figure CN114999904B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for fabricating the same. Background Technology
[0002] With the increasing demand for high performance and low cost of semiconductor devices, higher requirements are also being placed on the integration density of semiconductor devices.
[0003] 3D Dynamic Random Access Memory (3D DRAM) stacks memory cells on top of logic cells to achieve higher throughput per unit wafer area. Compared to conventional planar DRAM structures, 3D DRAM structures can effectively reduce the unit cost of DRAM.
[0004] However, ion doping is a crucial process step that affects the refresh time of 3D DRAM devices. Since 3D DRAM is a stacked device structure, the doping control capability of the ion doping process is weakened, which in turn leads to problems such as uneven concentration distribution of dopant ions in the semiconductor structure. Summary of the Invention
[0005] This disclosure provides a semiconductor structure and a method for fabricating the same, which can at least improve the doping control capability of stacked devices.
[0006] This disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate, the substrate including adjacent word line regions, bit line regions, and capacitor regions, wherein the bit line regions and capacitor regions are located on opposite sides of the word line regions; forming a first stacked structure covering the surface of the substrate, the first stacked structure including a first sacrificial layer on the surface of the substrate and a first semiconductor layer on the surface of the first sacrificial layer; forming a second stacked structure covering the surface of the first stacked structure, the second stacked structure including a second sacrificial layer on the surface of the first stacked structure and a second semiconductor layer on the surface of the second sacrificial layer; performing ion implantation on the first semiconductor layer and the second semiconductor layer, wherein the energy of ion implantation on the first semiconductor layer is greater than the energy of ion implantation on the second semiconductor layer, so as to maintain the concentration of doped ions in the first semiconductor layer located in the bit line regions and capacitor regions within a preset concentration range, and the concentration of doped ions in the second semiconductor layer located in the bit line regions and capacitor regions within a preset concentration range.
[0007] In some embodiments, ion implantation of a first semiconductor layer and a second semiconductor layer includes: forming a mask layer located on the surface of the second semiconductor layer in a word line region; implanting ions into the first semiconductor layer with a first energy in a direction perpendicular to the substrate; changing the ion implantation energy to a second energy and implanting ions into the second semiconductor layer with the second energy; wherein the magnitude of the first energy is greater than the magnitude of the second energy.
[0008] In some embodiments, ion implantation of a first semiconductor layer and a second semiconductor layer includes: forming a mask layer located on the surface of the second semiconductor layer in a word line region; ion implanting the first semiconductor layer with a first energy in a direction perpendicular to the substrate; and ion implanting the second semiconductor layer with a second energy in a direction perpendicular to the substrate; wherein the magnitude of the first energy is greater than the magnitude of the second energy.
[0009] In some embodiments, ion implantation of a first semiconductor layer and a second semiconductor layer includes: forming a first mask layer located on the surface of the second semiconductor layer in a word line region and a capacitor region; performing first ion implantation on the first semiconductor layer with a first energy and performing first ion implantation on the second semiconductor layer with a second energy in a direction perpendicular to the substrate; removing the first mask layer and forming a second mask layer located on the surface of the second semiconductor layer in a word line region and a bit line region; performing second ion implantation on the first semiconductor layer with a first energy and performing second ion implantation on the second semiconductor layer with a second energy in a direction perpendicular to the substrate, and removing the second mask layer; wherein the types of doped ions used for the first ion implantation and the second ion implantation are different.
[0010] In some embodiments, the relationship between the ion implantation depth y and the ion implantation energy x is y = -0.0001x. 2 +1.0647x+131.19, where the ion implantation energy x is in keV, the ion implantation depth y is in nm, and the ion implantation energy x ranges from 2keV to 3000keV.
[0011] In some embodiments, the preset concentration range is 1E. 15 cm -2 ~1E 18 cm -2 .
[0012] In some embodiments, after forming the second stacked structure and before forming the mask layer, the method further includes forming a shielding layer that covers the surface of the second stacked structure.
[0013] In some embodiments, after forming the second stacked structure, the method further includes: forming alternating layers of a third sacrificial layer and a third semiconductor layer on the surface of the second stacked structure, wherein the number of layers of the third semiconductor layer is greater than or equal to 1; performing ion implantation on the first semiconductor layer and the second semiconductor layer, further including: performing ion implantation on the third semiconductor layer; wherein the energy for performing ion implantation on the third semiconductor layer is less than the energy for performing ion implantation on the second semiconductor layer, so as to keep the concentration of doped ions in the third semiconductor layer located in the bit line region and the capacitance region within a preset concentration range.
[0014] In some embodiments, the materials used to form the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are the same.
[0015] In some embodiments, ion implantation is performed a corresponding number of times based on the sum of the number of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer.
[0016] In some embodiments, the dopant ions implanted include one of phosphorus ions, arsenic ions, antimony ions, boron ions, indium ions, or boron fluoride ions.
[0017] This disclosure also provides a semiconductor structure, using a method for fabricating the semiconductor structure provided in the above embodiments, comprising: a substrate, the substrate including adjacent word line regions, bit line regions, and capacitor regions, wherein the bit line regions and capacitor regions are located on opposite sides of the word line regions; a first stacked structure located on the surface of the substrate, the first stacked structure including a first sacrificial layer located on the surface of the substrate and a first semiconductor layer located on the surface of the first sacrificial layer; a second stacked structure located on the surface of the first stacked structure, the second stacked structure including a second sacrificial layer located on the surface of the first stacked structure and a second semiconductor layer located on the surface of the second sacrificial layer; wherein the concentration of doped ions in the first semiconductor layer located in the bit line regions and capacitor regions is within a preset concentration range, and the concentration of doped ions in the second semiconductor layer located in the bit line regions and capacitor regions is within a preset concentration range.
[0018] In some embodiments, the semiconductor structure further includes a shielding layer that covers the surface of the second stacked structure.
[0019] In some embodiments, the surface of the second stacked structure further includes: a third sacrificial layer and a third semiconductor layer stacked alternately in sequence, wherein the number of third semiconductor layers is greater than or equal to 1, and the concentration of doped ions in the third semiconductor layer located in the bit line region and the capacitor region is within a preset range.
[0020] In some embodiments, the preset concentration range is 1E. 15 cm -2 ~1E 18 cm -2 .
[0021] The technical solution provided by the embodiments of this disclosure has at least the following advantages: by using different energies to perform ion implantation on the first semiconductor layer and the second semiconductor layer in the stacked structure, wherein the energy for ion implantation on the first semiconductor layer is greater than the energy for ion implantation on the second semiconductor layer, the concentration of doped ions in the first semiconductor layer located in the bit line region and the capacitor region is kept within a preset concentration range, and the concentration of doped ions in the second semiconductor layer located in the bit line region and the capacitor region is kept within a preset concentration range, thereby improving the doping control capability of the stacked device. Attached Figure Description
[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0023] Figures 1 to 11 A schematic diagram of the structure corresponding to each step of the method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
[0024] Figure 12 A graph showing the relationship between ion implantation energy and depth provided in the embodiments of this disclosure;
[0025] Figures 13 to 14 A schematic diagram of the structure corresponding to each step of a method for fabricating another semiconductor structure according to an embodiment of this disclosure;
[0026] Figure 15 This is a schematic diagram of a semiconductor structure provided in an embodiment of this disclosure. Detailed Implementation
[0027] As is known from the background art, during the semiconductor structure fabrication process, there is a problem of weak doping control when performing doping processes on stacked devices, which leads to uneven concentration distribution of dopant ions in the semiconductor structure.
[0028] Analysis revealed that the causes of the above problems include: the stacking arrangement of the internal structure of semiconductor devices makes the internal structure of semiconductor devices complex. For example, when a semiconductor device has a three-layer silicon / germanium / silicon structure stacked sequentially, there is a germanium / silicon gap between the silicon in the first layer and the silicon in the third layer. As a result, during the ion implantation process, the presence of germanium / silicon prevents dopant ions from being uniformly implanted into the silicon in the first and third layers. This leads to an uneven distribution of dopant ion concentration in the silicon in the first and third layers, which in turn affects the reliability of the semiconductor device and reduces its performance.
[0029] One embodiment of this disclosure provides a semiconductor structure and a method for fabricating the same, to improve the doping control capability of stacked devices.
[0030] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.
[0031] Figures 1 to 11 This is a schematic diagram of the various steps corresponding to the semiconductor structure fabrication method provided in this embodiment. Figure 12 A graph showing the relationship between ion implantation energy and depth provided in an embodiment of this disclosure. Figures 13 to 14 The following is a schematic diagram of the various steps in a method for fabricating a semiconductor structure according to an embodiment of this disclosure. The method for fabricating the semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings:
[0032] refer to Figures 1 to 11 as well as Figures 13 to 14 Methods for fabricating semiconductor structures include:
[0033] refer to Figure 1 A substrate 100 is provided, which includes a word line region 101, a bit line region 102 and a capacitor region 103 disposed adjacently, wherein the bit line region 102 and the capacitor region 103 are located on opposite sides of the word line region 101.
[0034] For substrate 100, substrate 100 is a semiconductor material, including but not limited to one of silicon substrate, germanium substrate, germanium silicon substrate or silicon carbide substrate.
[0035] For word line region 101, word line region 101 is used to form gate structure, and the voltage signal in the gate structure can control the opening or closing of the corresponding transistor.
[0036] In some embodiments, the gate structure may include a gate conductive layer and a gate protective layer. The gate conductive layer is used for signal transmission, and the gate protective layer is used to protect the gate conductive layer, thereby reducing the stress on the gate conductive layer when the semiconductor structure is subjected to stress. In some embodiments, the material of the gate conductive layer may be a metal material such as tungsten, and the material of the gate protective layer may be an insulating material such as silicon nitride.
[0037] Bit line region 102 is used to form a bit line structure, which is used to read data information stored in the capacitor or to write data information into the capacitor for storage.
[0038] In some embodiments, the material forming the bit line structure can be a single metal, a metal compound, or an alloy. The single metal can be copper, aluminum, tungsten, gold, or silver; the metal compound can be tantalum nitride or titanium nitride; and the alloy can be an alloy material composed of at least two of copper, aluminum, tungsten, gold, or silver. Furthermore, the material for the bit line structure can also be at least one of nickel, cobalt, or platinum.
[0039] For capacitor region 103, capacitor region 103 is used to form capacitor structure, and capacitor structure is used to store data information.
[0040] refer to Figure 2 A first stacked structure 110 is formed covering the surface of the substrate 100. The first stacked structure 110 includes a first sacrificial layer 111 located on the surface of the substrate 100 and a first semiconductor layer 112 located on the surface of the first sacrificial layer 111.
[0041] For the first sacrificial layer 111, the material forming the first sacrificial layer 111 can be one of silicon, germanium, silicon germanide, silicon carbide and gallium arsenide.
[0042] For the first semiconductor layer 112, the material forming the first semiconductor layer 112 includes one of monocrystalline silicon, polycrystalline silicon, or amorphous silicon or silicon-germanium. In some embodiments, the material forming the first semiconductor layer 111 may be the same as the material of the substrate 100; in other embodiments, the material forming the first semiconductor layer 112 may be different from the material of the substrate 100.
[0043] In some embodiments, the process of forming the first sacrificial layer 111 and the first semiconductor layer 112 can be a deposition process, which can be a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, etc. In other embodiments, the process of forming the first sacrificial layer 111 and the first semiconductor layer 112 can be an epitaxial growth process, which can be a molecular beam epitaxy process, an atmospheric pressure and depressurized pressure epitaxy process, or an ultra-high vacuum chemical vapor deposition process, etc.
[0044] refer to Figure 3 A second stacked structure 120 is formed covering the surface of the first stacked structure 110. The second stacked structure 120 includes a second sacrificial layer 121 located on the surface of the first stacked structure 110 and a second semiconductor layer 122 located on the surface of the second sacrificial layer 121.
[0045] For the second sacrificial layer 121, the material forming the second sacrificial layer 121 includes one of silicon, germanium, silicon germanide, silicon carbide, and gallium arsenide. In some embodiments, the material forming the second sacrificial layer 121 may be the same as the material forming the first sacrificial layer 111; in other embodiments, the material forming the second sacrificial layer 121 may be different from the material forming the first sacrificial layer 111.
[0046] For the second semiconductor layer 122, the material forming the second semiconductor layer 122 includes one of monocrystalline silicon, polycrystalline silicon, or amorphous silicon or silicon-germanium. In some embodiments, the material forming the second semiconductor layer 122 may be the same as the material forming the first semiconductor layer 112; in other embodiments, the material forming the second semiconductor layer 122 may be different from the material forming the first semiconductor layer 112.
[0047] In some embodiments, the process for forming the second sacrificial layer 121 and the second semiconductor layer 122 can be a deposition process, which can be a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, etc. In other embodiments, the process for forming the second sacrificial layer 121 and the second semiconductor layer 122 can be an epitaxial growth process, which can be a molecular beam epitaxy process, an atmospheric pressure and depressurized pressure epitaxy process, or an ultra-high vacuum chemical vapor deposition process, etc.
[0048] Ion implantation is performed on the first semiconductor layer 112 and the second semiconductor layer 122, wherein the energy of ion implantation on the first semiconductor layer 112 is greater than the energy of ion implantation on the second semiconductor layer 122, so as to keep the concentration of doped ions in the first semiconductor layer 112 located in the bit line region 102 and the capacitor region 103 within a preset concentration range, and the concentration of doped ions in the second semiconductor layer 122 located in the bit line region 102 and the capacitor region 103 within a preset concentration range.
[0049] In this embodiment, the preset concentration range can be 1E. 15 cm -2 ~1E 18 cm -2 Specifically, it could be 1E 15 cm -2 1E 17 cm -2 Or 1E 18 cm -2Ion implantation, based on different dopant ions, can achieve uniform light or heavy doping in a specific region of a semiconductor structure during the ion implantation process.
[0050] Specifically, refer to Figure 4 In some embodiments, a method for ion implantation of a first semiconductor layer 112 and a second semiconductor layer 122 includes: forming a mask layer 200 located on the surface of the second semiconductor layer 122 in a word line region 101; ion implanting the first semiconductor layer 112 with a first energy in a direction perpendicular to the substrate 100; changing the ion implantation energy to a second energy and ion implanting the second semiconductor layer 122 with the second energy; wherein the magnitude of the first energy is greater than the magnitude of the second energy. That is, during the ion implantation process, the first energy is first used to implant ions into the first semiconductor layer 112 near the substrate 100, so that the doped ion concentration in the first semiconductor layer 112 reaches a preset concentration range; then the ion implantation energy is reduced, and the second energy is used to implant ions into the second semiconductor layer 122 located away from the substrate 100, so that the doped ion concentration in the second semiconductor layer 122 reaches a preset concentration range. By using a larger first energy to perform ion implantation on the first semiconductor layer 112, the doped ions can directly reach the first semiconductor layer 112 without stopping; by using a smaller second energy to perform ion implantation on the second semiconductor layer 122, the doped ions can only reach the second semiconductor layer 122, so that the doped ion concentration in the second semiconductor layer 122 reaches a preset range without changing the doped ion concentration in the first semiconductor layer 112.
[0051] Specifically, in some embodiments, the method for ion implantation of the first semiconductor layer 112 and the second semiconductor layer 122 can also be as follows: forming a mask layer 200 located on the surface of the second semiconductor layer 122 in the word line region 101; ion implanting the first semiconductor layer 112 with a first energy in a direction perpendicular to the substrate 100; and ion implanting the second semiconductor layer 122 with a second energy in a direction perpendicular to the substrate 100; wherein the magnitude of the first energy is greater than the magnitude of the second energy. That is, two ion implantations are performed: one ion implantation of the first semiconductor layer 112 using the first energy, and then ion implantation of the second semiconductor layer 122 using the second energy, wherein the magnitude of the first energy is greater than the magnitude of the second energy. When using the first energy, the doped ions directly reach the first semiconductor layer 112 close to the substrate 100; when using the second energy, the doped ions can only reach the second semiconductor layer 122 far from the substrate 100, thereby allowing ion implantation to be performed on the first semiconductor layer 112 and the second semiconductor layer 122 respectively. In some embodiments, the type of dopant ions implanted into the first semiconductor layer 112 is the same as the type of dopant ions implanted into the second semiconductor layer 122; in other embodiments, the type of dopant ions implanted into the first semiconductor layer 112 may be different from the type of dopant ions implanted into the second semiconductor layer 122.
[0052] In some embodiments, the material forming the mask layer 200 may be polycrystalline silicon, silicon oxide, or silicon nitride, etc. In some embodiments, the process for forming the mask layer 200 may be a deposition process, which may be a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
[0053] Further, refer to Figure 5 In some embodiments, after forming the second stacked structure 120 and before forming the mask layer 200, a shielding layer 201 is further formed, which covers the surface of the second stacked structure 120. The shielding layer 201 can protect the surface of the second semiconductor layer 122 from damage or contamination during ion implantation, thus avoiding any impact on the performance of the semiconductor structure.
[0054] For the shielding layer 201, the material forming the shielding layer 201 can be silicon oxide.
[0055] In some embodiments, the process of forming the shield 201 may employ a deposition process, which may be a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. In other embodiments, the process of forming the shield layer 201 may employ an oxidation process, which may be a rapid thermal oxidation process or a low-pressure rapid oxidation thermal annealing process.
[0056] More specifically, the aforementioned method of performing two ion implantations includes: (Refer to...) Figure 6 A first mask layer 211 is formed, located on the surface of the second semiconductor layer 122 in the word line region 101 and the capacitor region 103; in a direction perpendicular to the substrate 100, the first semiconductor layer 112 is subjected to first ion implantation with a first energy, and the second semiconductor layer 122 is subjected to first ion implantation with a second energy; Reference Figure 7 The first mask layer 211 is removed and a second mask layer 212 is formed. The second mask layer 212 is located on the surface of the second semiconductor layer 122 in the word line region 101 and the bit line region 102. In the direction perpendicular to the substrate 100, the first semiconductor layer 112 is implanted with a first energy and the second semiconductor layer 122 is implanted with a second energy. The first mask layer 211 is removed.
[0057] In some embodiments, the type of dopant ions used for the first ion implantation is different from the type of dopant ions used for the second ion implantation; in other embodiments, the type of dopant ions used for the first ion implantation is the same as the type of dopant ions used for the second ion implantation.
[0058] More specifically, the aforementioned method of performing two ion implantations can also be: (Refer to...) Figure 6 A first mask layer 211 is formed, located on the surface of the second semiconductor layer 122 in the word line region 101 and the capacitor region 103; in a direction perpendicular to the substrate 100, the first semiconductor layer 112 is subjected to a third ion implantation with a first energy and a fourth ion implantation with a second energy; Reference Figure 7 The first mask layer 211 is removed and a second mask layer 212 is formed. The second mask layer 212 is located on the surface of the second semiconductor layer 122 in the word line region 101 and the bit line region 102. In the direction perpendicular to the substrate 100, the first semiconductor layer 112 is implanted with a first energy for a fifth ion implantation and the second semiconductor layer 122 is implanted with a second energy for a sixth ion implantation. The first mask layer 211 is then removed.
[0059] In some embodiments, the type of dopant ions used for the third ion implantation may be different from the type of dopant ions used for the fourth ion implantation; the type of dopant ions used for the fifth ion implantation may be different from the type of dopant ions used for the sixth ion implantation, so that different types of dopant ions can be implanted for semiconductor layers with different numbers of layers in the same region.
[0060] Furthermore, in some embodiments, reference is made to... Figure 8After forming the second stacked structure 120 and before forming the first mask layer 211, the method further includes: forming a first shielding layer 202, the first shielding layer 202 covering the surface of the second stacked structure 120 in the bit line region 102; Reference Figure 9 After removing the first mask layer 211 and before forming the second mask layer 212, the method further includes: removing the first shielding layer 202 and forming a second shielding layer 203, wherein the second shielding layer 203 covers the surface of the second stacked structure 120 in the capacitor region 103. The first shielding layer 202 can protect the surface of the second semiconductor layer 122 in the bit line region 102 from damage or contamination during ion implantation; the second shielding layer 203 can protect the surface of the second semiconductor layer 122 in the capacitor region 103 from damage or contamination during ion implantation, thus avoiding any impact on the performance of the semiconductor structure. In other embodiments, refer to... Figure 10 and Figure 11 After forming the second stacked structure 120 and before forming the first mask layer 211, the method further includes forming a third shielding layer 204, which covers the surface of the second stacked structure 120. The third shielding layer 204 protects the surface of the second semiconductor layer 122 from the ion implantation process, preventing damage or contamination and thus protecting the performance of the semiconductor structure. Simultaneously, when removing the first mask layer 211 or the second mask layer 212, the third shielding layer 204 also serves as a protective layer for the second semiconductor layer 122, preventing damage or contamination to its surface during the removal process.
[0061] In this embodiment, the removal process can be an etching process, which can be a dry etching process or a wet etching process.
[0062] In this embodiment, the doped ions implanted include N-type ions or P-type ions. Specifically, N-type ions can be phosphorus ions, arsenic ions, or antimony ions; and P-type ions can be boron ions, indium ions, or boron fluoride ions.
[0063] In this embodiment, reference Figure 12 The relationship between the ion implantation depth y and the ion implantation energy x is y = -0.0001. 2 +1.0647+131.19, where the goodness of fit Rfit 2 The value is 0.9995. The unit of ion implantation energy x is keV, the unit of ion implantation depth y is nm, and the range of ion implantation energy x is 2keV to 3000keV, specifically 2keV, 1000keV or 3000keV.
[0064] Understandably, due to the different layers in a stacked structure, the required penetration depth of dopant ions during ion implantation varies. In the actual fabrication of semiconductor structures, the required penetration depth of dopant ions can be determined based on the location of the material to be doped. This allows for the selection of appropriate energy levels for ion implantation, enabling targeted ion implantation at a specific depth. This improves the accuracy and uniformity of dopant ion concentration during implantation, thereby enhancing the doping control capability of stacked devices.
[0065] In some embodiments, an annealing process is included after the ion implantation process described above. During ion implantation, dopant ions are injected into the semiconductor structure. The high-energy incident dopant ions collide with atoms in the crystal lattice, causing some lattice atoms to shift, creating numerous vacancies. This results in disordered atomic arrangement or the formation of an amorphous region in the ion-implanted area. The annealing process, by placing the semiconductor structure at a specific temperature, can restore the crystal structure and eliminate defects. Furthermore, the annealing process activates donor and acceptor impurities, allowing some dopant ions in interstitial positions to move into their replacement sites through annealing.
[0066] In some embodiments, the annealing process temperature can be 200℃ to 800℃, specifically 200℃, 400℃ or 800℃.
[0067] In some embodiments, reference Figure 13 After forming the second stacked structure 120, the method further includes forming alternating layers of a third sacrificial layer 131 and a third semiconductor layer 132 on the surface of the second stacked structure 120. The third sacrificial layer 131 and the third semiconductor layer 132 constitute the third stacked layer 130, and the number of third semiconductor layers 132 is greater than or equal to 1, specifically 2, 5, or 10 layers. It should be noted that, according to reference... Figure 13 In this embodiment, the third semiconductor layer 132 has two layers. In other embodiments, the third semiconductor layer 132 may have five or eight layers.
[0068] Accordingly, ion implantation of the first semiconductor layer 112 and the second semiconductor layer 122 further includes ion implantation of the third semiconductor layer 132; wherein the energy of ion implantation of the third semiconductor layer 132 is less than the energy of ion implantation of the second semiconductor layer 122, so as to keep the concentration of doped ions in the third semiconductor layer 132 located in the bit line region 102 and the capacitor region 103 within a preset concentration range.
[0069] Specifically, refer to Figure 14Ion implantation is performed on the first semiconductor layer 112, the second semiconductor layer 122, and the third semiconductor layer 132, including: forming a mask layer 200, which covers the surface of the third stacked layer 130 in the word line region 101. Ion implantation is performed on the first semiconductor layer 112 with a first energy in a direction perpendicular to the substrate 100; the ion implantation energy is changed to a second energy, and ion implantation is performed on the second semiconductor layer 122 with the second energy; the ion implantation energy is changed to a third energy, and ion implantation is performed on the third semiconductor layer 132 in the third stacked layer 130 near the substrate 100 with the third energy; the ion implantation energy is further changed to a fourth energy, and ion implantation is performed on the third semiconductor layer 132 in the third stacked layer 130 away from the substrate 100 with the fourth energy; wherein the magnitude of the first energy is greater than the magnitude of the second energy, the magnitude of the second energy is greater than the magnitude of the third energy, and the magnitude of the third energy is greater than the magnitude of the fourth energy. It is understandable that the first semiconductor layer 112, the second semiconductor layer 122, and the third semiconductor layer 132 are at different layers, and therefore the depth to which the dopant ions need to penetrate during ion implantation is different. Since the first semiconductor layer 112, the second semiconductor layer 122, and the third semiconductor layer 132 are at different positions, different energies need to be selected for ion implantation in order to achieve the goal that the concentration of dopant ions in the first semiconductor layer 112, the second semiconductor layer, and the third semiconductor layer 132 are all within a preset range.
[0070] In some embodiments, the number of ion implantations can be based on the sum of the number of layers of the first semiconductor layer 112, the second semiconductor layer 122, and the third semiconductor layer 132. For example, if the third semiconductor layer 132 has 2 layers, then the sum of the number of layers of the first semiconductor layer 112, the second semiconductor layer 122, and the third semiconductor layer 132 is 4, and the corresponding number of ion implantations is 4.
[0071] Specifically, the method for ion implantation of the first semiconductor layer 112, the second semiconductor layer 122, and the third semiconductor layer 132 includes: forming a mask layer 200 covering the surface of the third stacked layer 130 in the word line region 101; ion implanting the first semiconductor layer 112 with a first energy in a direction perpendicular to the substrate 100; ion implanting the second semiconductor layer 122 with a second energy in a direction perpendicular to the substrate 100; ion implanting the third semiconductor layer 132 in the third stacked layer 130 near the substrate 100 with a third energy in a direction perpendicular to the substrate 100; and ion implanting the third semiconductor layer 132 in the third stacked layer 130 away from the substrate 100 with a fourth energy in a direction perpendicular to the substrate 100; wherein the magnitude of the first energy is greater than the magnitude of the second energy, the magnitude of the second energy is greater than the magnitude of the third energy, and the magnitude of the third energy is greater than the magnitude of the fourth energy.
[0072] It is understandable that performing four separate ion implantations can target the first semiconductor layer 112, the second semiconductor layer 122, and the third semiconductor layer 132, which are located at different layers. When the thickness of the first semiconductor layer 112, the second semiconductor layer 122, and the third semiconductor layer 132 is relatively thin, the change in ion implantation energy during the ion implantation process is small. Consequently, the penetration depth of the dopant ions will change during the energy transition period, which may lead to errors in the concentration of dopant ions in different semiconductor layers, thus exceeding the preset range. Performing four separate ion implantations can prevent inaccuracies in dopant ion concentration caused by energy changes during the ion implantation process, thereby improving the doping control capability of the stacked device.
[0073] In some embodiments, the type of dopant ions implanted into the first semiconductor layer 112 may be the same as the type of dopant ions implanted into the third semiconductor layer 132; the type of dopant ions implanted into the second semiconductor layer 122 may be the same as the type of dopant ions implanted into the third semiconductor layer 132. In other embodiments, the type of dopant ions implanted into the first semiconductor layer 112 may be different from the type of dopant ions implanted into the third semiconductor layer 132; the type of dopant ions implanted into the second semiconductor layer 122 may be different from the type of dopant ions implanted into the third semiconductor layer 132.
[0074] In some embodiments, the materials forming the first semiconductor layer 112, the second semiconductor layer 122, and the third semiconductor layer 132 are the same. The materials forming the first semiconductor layer 112, the second semiconductor layer 122, and the third semiconductor layer 132 can be monocrystalline silicon, polycrystalline silicon, or amorphous silicon or silicon germanium.
[0075] In some embodiments, the materials forming the first sacrificial layer 111, the second sacrificial layer 121, and the third sacrificial layer 131 may be the same, and the materials forming the first sacrificial layer 111, the second sacrificial layer 121, and the third sacrificial layer 131 may be one of silicon, germanium, silicon germanide, silicon carbide, and gallium arsenide.
[0076] The method for fabricating a semiconductor structure provided in this disclosure involves forming a stacked structure and performing ion implantation on a first semiconductor layer 112 and a second semiconductor layer 122 in the stacked structure at different energies. The energy for ion implantation on the first semiconductor layer 112 is greater than the energy for ion implantation on the second semiconductor layer 122. This method aims to maintain the concentration of doped ions in the first semiconductor layer 112 located in the bit line region 102 and the capacitor region 103 within a preset concentration range, and also maintain the concentration of doped ions in the second semiconductor layer 112 located in the bit line region 102 and the capacitor region 103 within a preset concentration range, thereby improving the doping control capability of the stacked device.
[0077] Another embodiment of this disclosure provides a semiconductor structure, employing the above-described method for fabricating the semiconductor structure to improve the performance of the formed semiconductor structure. It should be noted that the parts that are the same as or corresponding to those in the above embodiments can be referred to the corresponding descriptions in the foregoing embodiments, and will not be elaborated upon further below.
[0078] Figure 15 This is a schematic diagram of a semiconductor structure provided in this embodiment. The semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings:
[0079] refer to Figure 15 A semiconductor structure includes: a substrate 100, which includes a word line region 101, a bit line region 102, and a capacitor region 103 disposed adjacently, wherein the bit line region 102 and the capacitor region 103 are located on opposite sides of the word line region 101; a first stacked structure 110 located on the surface of the substrate 100, which includes a first sacrificial layer 111 located on the surface of the substrate 100 and a first semiconductor layer 112 located on the surface of the first sacrificial layer 111; and a second stacked structure 120 located on the surface of the first stacked structure 110, which includes a second sacrificial layer 121 located on the surface of the first stacked structure 110 and a second semiconductor layer 122 located on the surface of the second sacrificial layer 121; wherein the concentration of doped ions in the first semiconductor layer 112 located in the bit line region 102 and the capacitor region 103 is within a preset concentration range, and the concentration of doped ions in the second semiconductor layer 122 located in the bit line region 102 and the capacitor region 103 is within a preset concentration range.
[0080] In this embodiment, the preset concentration range is 1E. 15 cm -2 ~1E 18 cm -2 Specifically, it could be 1E 15 cm -2 1E 17 cm -2 Or 1E 18 cm -2 .
[0081] For substrate 100, substrate 100 is a semiconductor material, including but not limited to one of silicon substrate, germanium substrate, germanium silicon substrate or silicon carbide substrate.
[0082] The material of the first sacrificial layer 111 can be one of silicon, germanium, silicon germanide, silicon carbide, and gallium arsenide.
[0083] The material of the first semiconductor layer 112 includes monocrystalline silicon, polycrystalline silicon, or silicon or silicon germanium with an amorphous structure.
[0084] The material of the second sacrificial layer 121 includes one of silicon, germanium, silicon germanide, silicon carbide, and gallium arsenide.
[0085] For the second semiconductor layer 122, the material of the second semiconductor layer 122 includes one of monocrystalline silicon, polycrystalline silicon, or amorphous silicon or silicon germanium.
[0086] In some embodiments, reference Figure 13 On the surface of the second stacked structure 120, there are also: a third sacrificial layer 131 and a third semiconductor layer 132 alternately stacked in sequence, wherein the number of third semiconductor layers 132 is greater than or equal to 1, specifically 2, 5 or 8 layers, and the concentration of doped ions in the third semiconductor layers 132 located in the bit line region 102 and the capacitor region 103 is within a preset range. It should be noted that in this embodiment of the present disclosure, the number of third semiconductor layers 132 is 2 layers, while in other embodiments, the number of third semiconductor layers 132 can be 4 or 8 layers.
[0087] For the third sacrificial layer 131, the material of the third sacrificial layer 131 may be one of silicon, germanium, silicon germanide, silicon carbide, and gallium arsenide. In some embodiments, the material of the third sacrificial layer 131 may be the same as the material of the first sacrificial layer 111 and / or the material of the second sacrificial layer 121; in other embodiments, the material of the third sacrificial layer 131 may be different from the material of the first sacrificial layer 111 and / or the material of the second sacrificial layer 121.
[0088] For the third semiconductor layer 132, the material of the third semiconductor layer 132 may be monocrystalline silicon, polycrystalline silicon, or amorphous silicon or silicon-germanium. In some embodiments, the material of the third semiconductor layer 132 may be the same as the material of the first semiconductor layer 112 and / or the material of the second semiconductor layer 122; in other embodiments, the material of the third semiconductor layer 132 may be different from the material of the first semiconductor layer 112 and / or the material of the second semiconductor layer 122.
[0089] In some embodiments, the semiconductor structure may further include a shielding layer covering the surface of the second stacked structure 120. During ion implantation, the shielding layer protects the surface of the second stacked structure 120 from damage or contamination, preventing any impact on the performance of the semiconductor structure. In some embodiments, the shielding layer is made of silicon oxide.
[0090] The semiconductor structure provided in this disclosure, based on the above-described semiconductor structure fabrication method, has a stacked structure, and the concentration of doped ions in the first semiconductor layer 112 located in the bit line region 102 and the capacitor region 103 is within a preset concentration range, and the concentration of doped ions in the second semiconductor layer 122 located in the bit line region 102 and the capacitor region 103 is within a preset concentration range, thereby improving the doping control capability of the stacked device.
[0091] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a word line region, a bit line region and a capacitor region disposed adjacently, wherein the bit line region and the capacitor region are located on opposite sides of the word line region; A first stacked structure covering the surface of the substrate is formed, the first stacked structure including a first sacrificial layer located on the surface of the substrate and a first semiconductor layer located on the surface of the first sacrificial layer; A second stacked structure is formed covering the surface of the first stacked structure, the second stacked structure including a second sacrificial layer located on the surface of the first stacked structure and a second semiconductor layer located on the surface of the second sacrificial layer; Ion implantation is performed on the first semiconductor layer and the second semiconductor layer, wherein the energy of ion implantation on the first semiconductor layer is greater than the energy of ion implantation on the second semiconductor layer, so as to keep the concentration of doped ions in the first semiconductor layer located in the bit line region and the capacitance region within a preset concentration range, and the concentration of doped ions in the second semiconductor layer located in the bit line region and the capacitance region within the preset concentration range.
2. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The ion implantation of the first semiconductor layer and the second semiconductor layer includes: A mask layer is formed, the mask layer being located on the surface of the second semiconductor layer in the word line region; Ion implantation is performed on the first semiconductor layer in a direction perpendicular to the substrate with a first energy; The energy of the ion implantation is changed to a second energy, and the second semiconductor layer is ion implanted with the second energy; The magnitude of the first energy is greater than the magnitude of the second energy.
3. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The ion implantation of the first semiconductor layer and the second semiconductor layer includes: A mask layer is formed, the mask layer being located on the surface of the second semiconductor layer in the word line region; Ion implantation is performed on the first semiconductor layer in a direction perpendicular to the substrate with a first energy; Ion implantation is performed on the second semiconductor layer in a direction perpendicular to the substrate using a second energy. The magnitude of the first energy is greater than the magnitude of the second energy.
4. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The ion implantation of the first semiconductor layer and the second semiconductor layer includes: A first mask layer is formed, the first mask layer being located on the surface of the second semiconductor layer in the word line region and the capacitor region; In a direction perpendicular to the substrate, the first semiconductor layer is implanted with a first ion using a first energy, and the second semiconductor layer is implanted with a second energy. The first mask layer is removed and a second mask layer is formed, the second mask layer being located on the surface of the second semiconductor layer in the word line region and the bit line region; In a direction perpendicular to the substrate, the first semiconductor layer is implanted with a first energy to perform a second ion implantation, the second semiconductor layer is implanted with a second energy to perform a second ion implantation, and the second mask layer is removed. The types of dopants used in the first ion implantation and the second ion implantation are different.
5. The method for fabricating a semiconductor structure according to any one of claims 1 to 4, characterized in that, The relationship between the ion implantation depth y and the ion implantation energy x is y = -0.0001x. 2 +1.0647x+131.19, where the energy x of the ion implantation is in keV, the depth y of the ion implantation is in nm, and the energy x of the ion implantation ranges from 2keV to 3000keV.
6. The method for fabricating a semiconductor structure according to any one of claims 1 to 4, characterized in that, The preset concentration range is 1E. 15 cm -2 ~1E 18 cm -2 .
7. The method for fabricating a semiconductor structure as described in claim 2 or 3, characterized in that, After forming the second stacked structure and before forming the mask layer, the method further includes: A shielding layer is formed, which covers the surface of the second stacked structure.
8. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, After forming the second stacked structure, the process also includes: An alternating third sacrificial layer and a third semiconductor layer are formed on the surface of the second stacked structure, wherein the number of layers of the third semiconductor layer is greater than or equal to 1; The ion implantation of the first semiconductor layer and the second semiconductor layer further includes: ion implantation of the third semiconductor layer; The energy used for ion implantation in the third semiconductor layer is less than the energy used for ion implantation in the second semiconductor layer, so as to keep the concentration of doped ions in the third semiconductor layer located in the bit line region and the capacitor region within the preset concentration range.
9. The method for fabricating a semiconductor structure as described in claim 8, characterized in that, The materials used to form the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are the same.
10. The method for fabricating a semiconductor structure as described in claim 8, characterized in that, The ion implantation is performed a corresponding number of times based on the sum of the number of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer.
11. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The dopant ions implanted include one of the following: phosphorus ions, arsenic ions, antimony ions, boron ions, indium ions, or boron fluoride ions.
12. A semiconductor structure, fabricated using the method for any one of claims 1 to 11, characterized in that, include: The substrate includes a word line region, a bit line region, and a capacitor region disposed adjacently, wherein the bit line region and the capacitor region are located on opposite sides of the word line region; A first stacked structure is located on the surface of the substrate, the first stacked structure including a first sacrificial layer located on the surface of the substrate and a first semiconductor layer located on the surface of the first sacrificial layer; A second stacked structure is located on the surface of the first stacked structure, and the second stacked structure includes a second sacrificial layer located on the surface of the first stacked structure and a second semiconductor layer located on the surface of the second sacrificial layer. Wherein, the concentration of doped ions in the first semiconductor layer located in the bit line region and the capacitor region is within the preset concentration range, and the concentration of doped ions in the second semiconductor layer located in the bit line region and the capacitor region is within the preset concentration range.
13. The semiconductor structure as described in claim 12, characterized in that, It also includes a shielding layer that covers the surface of the second stacked structure.
14. The semiconductor structure as described in claim 12, characterized in that, The surface of the second stacked structure further includes: a third sacrificial layer and a third semiconductor layer stacked alternately in sequence, wherein the number of layers of the third semiconductor layer is greater than or equal to 1, and the concentration of doped ions in the third semiconductor layer located in the bit line region and the capacitor region is within a preset range.
15. The semiconductor structure as described in claim 12, characterized in that, The preset concentration range is 1E. 15 cm -2 ~1E 18 cm -2 .