Method of manufacturing shallow trench isolation

Abstract

This invention discloses a method for manufacturing shallow trench isolation, comprising: Step 1, performing a first etching process on a semiconductor substrate in the shallow trench formation area using a dry etching process to form a shallow trench; during the first etching, metal ions are precipitated in the dry etching process cavity and deposited on the inner surface of the shallow trench, and the metal ions diffuse and form a contamination layer; Step 2, performing a second etching process on the semiconductor substrate exposed on the inner surface of the shallow trench using a wet etching process to remove the contamination layer on the inner surface of the shallow trench. This invention can remove the metal ions precipitated in the dry etching process cavity and deposited on the inner surface of the shallow trench during the dry etching process, thereby avoiding the impact of metal ions on the yield of products, especially CMOS image sensors.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor integrated circuits, and more particularly to a method for manufacturing shallow trench isolation (STI). Background Technology

[0002] Existing CMOS image sensors (CIS) consist of pixel unit circuits and CMOS circuits. Compared to CCD image sensors, CMOS image sensors have better integrability because they are manufactured using the CMOS standard process. They can be integrated with other analog-to-digital computing and control circuits on the same chip, making them more adaptable to future development.

[0003] Based on the number of transistors contained in the pixel unit circuit of existing CMOS image sensors, they are mainly divided into 3T type structure and 4T type structure.

[0004] like Figure 1 The diagram shown is an equivalent circuit diagram of the pixel unit circuit of an existing 3T CMOS image sensor. The pixel unit circuit of the existing 3T CMOS image sensor includes a photodiode D1 and a CMOS pixel readout circuit. The CMOS pixel readout circuit is a 3T pixel circuit, including a reset transistor M1, an amplification transistor M2, and a selection transistor M3, all of which are NMOS transistors.

[0005] The N-type region of the photodiode D1 is connected to the source of the reset transistor M1.

[0006] The gate of the reset transistor M1 is connected to the reset signal Reset, which is a potential pulse. When the reset signal Reset is high, the reset transistor M1 is turned on and absorbs electrons from the photodiode D1 into the power supply Vdd of the readout circuit to achieve reset. When light shines on it, the photodiode D1 generates photoelectrons, its potential rises, and the electrical signal is transmitted after amplification. The gate of the selection transistor M3 is connected to the horizontal selection signal Rs, which is used to select the output of the amplified electrical signal, i.e., the output signal Vout.

[0007] like Figure 2 The diagram shown is an equivalent circuit diagram of the pixel unit circuit of an existing 4T CMOS image sensor; and Figure 1 The difference between the structures shown is that, Figure 2The structure shown includes an additional transfer transistor, or transmission transistor M4. The source region of the transfer transistor M4 is the N-type region connected to the photodiode D1, and the drain region is a floating diffusion (FD) region. The gate of the transfer transistor M4 is connected to the transmission control signal Tx. After the photodiode D1 generates photoelectrons, they are transferred to the floating diffusion region through the transfer transistor M4, and then connected to the gate of the amplifier transistor M2 through the floating diffusion region to amplify the signal.

[0008] In existing CMOS image sensors, pixel unit circuits are formed in pixel regions, and CMOS circuits are formed in logic regions. Active regions need to be defined in both pixel and logic regions. These active regions are formed using STI (Shallow Trench Etching) or Local Field Oxide (LOCOS) isolation. Specifically, the semiconductor substrate located within the STI or LOCOS surrounding area serves as the active region, where device structures, such as the individual devices in the pixel unit circuit, are formed. STI or LOCOS prevents interference between devices in different active regions. STI is formed using shallow trench etching and filling processes and is applied to active region definitions at smaller process nodes. This application primarily focuses on improving the manufacturing method of STI, particularly its application in CMOS image sensors.

[0009] In existing CMOS image sensors, due to the different device isolation requirements of the pixel area and the logic area, a shallow trench isolation with double depth is usually required. This results in different depths of the shallow trenches in the pixel area and the logic area. Therefore, a shallow trench with double depth needs to be formed first in the formation of the CMOS image sensor.

[0010] In existing processes, shallow trenches are typically formed by dry etching of semiconductor substrates, such as silicon substrates. This dry etching process takes place in a dry etching chamber, which contains components made of metal. During the dry etching process, plasma is used, causing metal ions to precipitate from the chamber and deposit on the surface of the shallow trenches. These deposited metal ions then diffuse further into the semiconductor substrate at the trench surface during thermal processes.

[0011] Typically, metal ions deposited during shallow trench etching do not adversely affect devices in the logic area. However, these metal ions can significantly impact the pixel area. This is because the pixel area primarily utilizes the depletion region of a photodiode to collect photons and convert them into electrons through photoelectric conversion. Image detection relies on collecting these electrons. When metal ions, especially heavy metal ions, are present in the active area of ​​the pixel, they can cause leakage current. This leakage current is not actually generated through photoelectric conversion but is treated as if it were generated by electrons, resulting in white spots. An increase in white spots reduces product yield and can even lead to the scrapping of a large number of wafers. In semiconductor integrated circuits, a wafer typically refers to a semiconductor substrate, such as a silicon substrate, which is a single, circular wafer.

[0012] In summary, while CMOS image sensing is being used more and more widely in the present technology, the following problems exist: CMOS image sensors are extremely sensitive to metal contamination, especially heavy metal contamination; however, metal contamination testing has a long cycle and is subject to many interfering factors, making it difficult to accurately interpret the results. Because the etching cavity uses plasma for the etching process of the working area, the inherent characteristic of high metal precipitation inevitably leads to metal contamination of the CMOS image sensor working area; this results in a serious increase in white spots, low wafer yield, and even large-scale scrapping. Summary of the Invention

[0013] The technical problem to be solved by the present invention is to provide a manufacturing method for shallow trench isolation, which can remove metal ions precipitated and deposited on the inner surface of the shallow trench during the dry etching process, thereby avoiding the impact of metal ions on the yield of products, especially CMOS image sensors.

[0014] To solve the above-mentioned technical problems, the manufacturing method of shallow trench isolation provided by the present invention includes the following steps: Step 1: Provide a semiconductor substrate, define the shallow trench formation area, and use a dry etching process to perform the first etching on the semiconductor substrate in the shallow trench formation area to form the shallow trench.

[0015] The first etching is performed in a dry etching process chamber. During the first etching, metal ions are precipitated in the dry etching process chamber and deposited on the inner surface of the shallow trench. The metal ions deposited on the inner surface of the shallow trench diffuse into the semiconductor substrate at the inner surface of the shallow trench and form a contamination layer.

[0016] Step 2: A wet etching process is used to perform a second etching on the semiconductor substrate exposed on the inner surface of the shallow trench to remove the contamination layer on the inner surface of the shallow trench. The semiconductor substrate in the area surrounded by the shallow trench after the second etching constitutes the active region.

[0017] A further improvement is that, after step two, a first oxide layer is filled into the shallow trench to form a shallow trench isolation.

[0018] A further improvement is that the semiconductor substrate comprises a silicon substrate.

[0019] A further improvement is that the semiconductor substrate is used to form a CMOS image sensor, which includes pixel areas and logic areas.

[0020] The shallow trench includes a first shallow trench and a second shallow trench.

[0021] The first shallow trench is a shallow trench located in the pixel area, and the second shallow trench is a shallow trench located in the logic area.

[0022] A further improvement is that the depth of the second shallow trench is greater than the depth of the first shallow trench.

[0023] A further improvement is that, in step one, a hard mask layer is used when defining the formation area of ​​the shallow trench, including the following sub-steps: Step 11: Form the hard mask layer on the surface of the semiconductor substrate.

[0024] Step 12: Pattern the hard mask layer. The opening of the patterned hard mask layer opens up the formation area of ​​the shallow trench.

[0025] Step 13: Then, the first etching is performed using the patterned hard mask layer as a mask.

[0026] A further improvement is that, in step two, before the second etching, a third etching process is performed on the hard mask layer using a wet etching process, which enlarges the opening of the hard mask layer.

[0027] A further improvement is that the hard mask layer is composed of a second oxide layer and a third nitride layer stacked together.

[0028] A further improvement is that, in the third etching, phosphoric acid is used to etch the third nitride layer and hydrofluoric acid is used to etch the second oxide layer.

[0029] A further improvement is that, in step 12, after the hard mask layer is patterned, the formation regions of the first shallow trench and the formation regions of the second shallow trench are defined simultaneously.

[0030] In step 13, the first etching is divided into a first dry etching step and a second dry etching step. Step 13 includes the following sub-steps.

[0031] Step 131: Perform the first dry etching step simultaneously on the semiconductor substrate in the formation regions of the first shallow trench and the second shallow trench until the depth of the first shallow trench reaches the target value. The first dry etching step forms the first shallow trench and a portion of the second shallow trench.

[0032] Step 132: Form a second mask layer to cover the pixel area and open the logic area.

[0033] Step 133: Perform the second dry etching step to continue etching the semiconductor substrate in the formation region of the second shallow trench until the depth of the second shallow trench reaches the target value. After the second dry etching step is completed, the second shallow trench is formed.

[0034] Step 134: Remove the second mask layer.

[0035] A further improvement is that, in step 132, the material of the second mask layer includes photoresist, and the patterned structure of the second mask layer is formed by photoresist coating, exposure and development.

[0036] A further improvement is that in step 134, a desmearing process and a wet cleaning process are used to remove the second mask layer.

[0037] A further improvement is that, in step two, the wet etching solution for the second etching includes: KOH, NaOH, or TMAH.

[0038] A further improvement is that, in step two, the thickness of the semiconductor substrate removed by the second etching is 30 Å or more.

[0039] This invention adds a wet etching process after the dry etching process of shallow trenches to remove the contamination layer on the inner surface of the semiconductor substrate, i.e., the shallow trench, which is contaminated by metal ions deposited in the dry etching process cavity during the dry etching process of shallow trenches. Therefore, this invention can remove the metal ions deposited in the dry etching process cavity of shallow trenches and deposited on the inner surface of the shallow trench.

[0040] Since CMOS image sensors are particularly sensitive to contamination by metal ions, especially heavy metal ions, this invention can reduce white spots in CMOS image sensors by removing metal ions deposited on the inner surface of shallow trenches during dry etching, thereby improving the yield of CMOS image sensors and avoiding large-scale wafer scrapping. Attached Figure Description

[0041] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is an equivalent circuit diagram of the pixel unit circuit of an existing 3T CMOS image sensor; Figure 2 This is an equivalent circuit diagram of the pixel unit circuit of an existing 4T CMOS image sensor; Figure 3 This is a flowchart of the manufacturing method of shallow trench isolation according to an embodiment of the present invention; Figures 4A-4C This is a schematic diagram of the device structure in each step of the manufacturing method of shallow trench isolation according to an embodiment of the present invention; Figures 5A-5E This is a schematic diagram of the device structure in each step of the manufacturing method of shallow trench isolation according to a preferred embodiment of the present invention. Detailed Implementation

[0042] like Figure 3 The diagram shown is a flowchart of a shallow trench isolation manufacturing method according to an embodiment of the present invention; as shown Figures 4A to 4C The diagram shown is a schematic representation of the device structure in each step of the manufacturing method of shallow trench isolation according to an embodiment of the present invention. The manufacturing method of shallow trench isolation according to an embodiment of the present invention includes the following steps: Step 1, such as Figure 4A As shown, a semiconductor substrate 101 is provided, and a shallow trench 103a is defined in the formation region. The shallow trench 103a is formed by first etching the semiconductor substrate 101 in the shallow trench 103a formation region using a dry etching process. Figure 4A In the text, the shallow trench after the first etching is marked separately with the symbol 103a.

[0043] The semiconductor substrate 101 includes a silicon substrate.

[0044] The first etching is performed in a dry etching process chamber. During the first etching, metal ions 104 are precipitated in the dry etching process chamber and deposited on the inner surface of the shallow trench 103a. The metal ions 104 deposited on the inner surface of the shallow trench 103a diffuse into the semiconductor substrate 101 on the inner surface of the shallow trench 103a and form a contamination layer. Figure 4AIn the diagram, the arrow at the metal ion 104 indicates the diffusion of the metal ion 104, which will diffuse during the thermal process.

[0045] In this embodiment of the invention, step one, in which a hard mask layer 102 is used to define the formation area of ​​the shallow trench 103a, includes the following sub-steps: Step 11: Form the hard mask layer 102 on the surface of the semiconductor substrate 101.

[0046] The hard mask layer 102 is formed by stacking a second oxide layer 102a and a third nitride layer 102b.

[0047] Step 12: Pattern the hard mask layer 102. The opening of the patterned hard mask layer 102 opens up the formation area of ​​the shallow trench 103a.

[0048] Typically, the hard mask layer 102 is patterned using a photolithography and etching process, including: applying photoresist, exposing and developing it to form a photoresist pattern, then using the photoresist pattern as a mask to etch the hard mask layer 102, and finally removing the photoresist pattern.

[0049] Step 13: Then, the first etching is performed using the patterned hard mask layer 102 as a mask.

[0050] Step 2, as follows Figure 4C As shown, a wet etching process is used to perform a second etching on the semiconductor substrate 101 exposed on the inner surface of the shallow trench 103a to remove the contamination layer on the inner surface of the shallow trench 103a. The semiconductor substrate 101 in the area surrounded by the shallow trench 103a after the second etching constitutes the active region. Figure 4C In the text, the shallow trench after the second etching is completed is marked separately with 103.

[0051] In step two, the wet etching solution for the second etching is TMAH. In other embodiments, the wet etching solution for the second etching may also include KOH or NaOH.

[0052] In step two, the thickness of the semiconductor substrate 101 removed by the second etching is 30 Å or more.

[0053] In this embodiment of the invention, when the second etching is performed using TMAH, the etching rate varies depending on the crystal orientation of the semiconductor substrate 101. The etching rate of the second etching on the (110) surface, the etching rate on the (100) surface, and the etching rate on the (111) surface decreases sequentially. In this embodiment of the invention, the etching rate of the side surface of the shallow trench 103a is greater than the etching rate of the bottom surface during the second etching. This ensures that the metal ions 104 on the side surface of the shallow trench 103 are removed after the second etching. Although some metal ions 104 on the bottom surface of the shallow trench 103 are not removed, since the active region is composed of the semiconductor substrate 101 between the shallow trenches 103, it will not adversely affect the performance of the device. Figure 4C The dashed box 105 represents the area where the shallow trench 103a was formed before the second etching. It can be seen that the width of the shallow trench 103 after the second etching will be increased to a certain extent. By pre-defining the area where the shallow trench 103a was formed in step one, the width of the shallow trench 103 formed in the end can be made to match the required value.

[0054] In this embodiment of the invention, in step two, as follows: Figure 4B As shown, before the second etching, a third etching process is performed on the hard mask layer 102 using a wet etching process, which enlarges the opening of the hard mask layer 102.

[0055] In the third etching, phosphoric acid is used to etch the third nitride layer 102b and hydrofluoric acid is used to etch the second oxide layer 102a.

[0056] Step two is followed by filling the shallow trench 103a with a first oxide layer to form a shallow trench isolation.

[0057] In this embodiment of the invention, after the dry etching process of the shallow trench, a wet etching process is added to remove the contamination layer on the inner surface of the semiconductor substrate 201, i.e. the shallow trench, which is contaminated by metal ions 206 deposited in the dry etching process cavity during the dry etching process of the shallow trench. Therefore, this invention can remove the metal ions 206 deposited in the dry etching process cavity of the shallow trench and deposited on the inner surface of the shallow trench.

[0058] Since CMOS image sensors are particularly sensitive to contamination by metal ions 206, especially heavy metal ions 206, this invention can reduce white spots in CMOS image sensors by removing metal ions 206 deposited on the inner surface of shallow trenches during dry etching, thereby improving the yield of CMOS image sensors and avoiding large-scale wafer scrap.

[0059] like Figures 5A to 5E The diagram shown is a schematic representation of the device structure in each step of the manufacturing method of shallow trench isolation according to a preferred embodiment of the present invention. The manufacturing method of shallow trench isolation according to a preferred embodiment of the present invention includes the following steps: Step 1, such as Figure 5A As shown, a semiconductor substrate 201 is provided, defining a shallow trench formation region. A dry etching process is used to perform a first etching of the semiconductor substrate 201 in the shallow trench formation region to form the shallow trench. The semiconductor substrate 201 includes a silicon substrate.

[0060] like Figure 5B As shown, the first etching is performed in a dry etching process chamber. During the first etching, metal ions 206 are precipitated in the dry etching process chamber and deposited on the inner surface of the shallow trench. The metal ions 206 deposited on the inner surface of the shallow trench diffuse into the semiconductor substrate 201 on the inner surface of the shallow trench and form a contamination layer. Figure 5C In the diagram, the arrow at the metal ion 206 indicates the diffusion of the metal ion 206, which will diffuse during the thermal process.

[0061] In a preferred embodiment of the present invention, such as Figure 5A As shown, the semiconductor substrate 201 is used to form a CMOS image sensor, which includes a pixel area 301 and a logic area 302. Figure 5A In the diagram, the pixel area 301 and the logic area 302 are located on both sides of the dashed line AA.

[0062] Please refer to this first. Figure 5E As shown, the shallow trench includes a first shallow trench 2031 and a second shallow trench 2032.

[0063] The first shallow trench 2031 is a shallow trench located in the pixel area 301, and the second shallow trench 2032 is a shallow trench located in the logic area 302.

[0064] The depth of the second shallow trench 2032 is greater than the depth of the first shallow trench 2031.

[0065] like Figure 5A As shown, in step one, a hard mask layer 202 is used to define the formation area of ​​the shallow trench, which includes the following sub-steps: Step 11: Form the hard mask layer 202 on the surface of the semiconductor substrate 201.

[0066] The hard mask layer 202 is composed of a second oxide layer 202a and a third nitride layer 202b.

[0067] Step 12: Pattern the hard mask layer 202. The opening of the patterned hard mask layer 202 opens up the formation area of ​​the shallow trench.

[0068] Typically, the hard mask layer 202 is patterned using a photolithography and etching process, including: applying photoresist, exposing and developing it to form a photoresist pattern, then using the photoresist pattern as a mask to etch the hard mask layer 202, and finally removing the photoresist pattern.

[0069] like Figure 5A As shown, in step 12, after the hard mask layer 202 is patterned, the formation areas of the first shallow trench 2031a and the formation areas of the second shallow trench are defined simultaneously. Figure 5A In the text, the first shallow trench is indicated separately by the designation 2031a and Figure 5A The image shows only a portion of the second shallow trench, and the portion of the second shallow trench is represented separately by label 2032a. The area of ​​the opening after the hard mask layer 202 is patterned is used to define the formation area of ​​the first shallow trench corresponding to label 2031a and the formation area of ​​the second shallow trench corresponding to label 2032a.

[0070] Step 13: Then, the first etching is performed using the patterned hard mask layer 202 as a mask. In step 13, the first etching is divided into a first dry etching step and a second dry etching step, and step 13 includes the following sub-steps.

[0071] Step 131, as follows Figure 5A As shown, the semiconductor substrate 201 in the formation regions of the first shallow trench 2031a and the second shallow trench 2032a is etched simultaneously during the first dry etching step until the depth of the first shallow trench 2031a reaches the target value. The first dry etching step forms the first shallow trench 2031a and a portion of the second shallow trench 2032a.

[0072] Step 132, as follows Figure 5A As shown, a second mask layer 204 is formed to cover the pixel area 301 and open the logic area 302.

[0073] Step 133, as follows Figure 5B As shown, the semiconductor substrate 201 in the formation region of the second shallow trench is further etched by the second dry etching step until the depth of the second shallow trench reaches the target value. After the second dry etching step is completed, the second shallow trench 2032b is formed. Figure 5B In the text, the second shallow trench after the second dry etching step is represented by the symbol 2032b.

[0074] Figure 5B The image shows the metal ions 206 deposited during the second dry etching step, which are located on the surface of the second mask layer 204 of the pixel region 301, the hard mask layer 202 of the logic region, and the inner surface of the second shallow trench 2032b.

[0075] In a preferred embodiment of the present invention, the material of the second mask layer 204 includes photoresist, and the patterned structure of the second mask layer 204 is formed by photoresist coating, exposure, and development. Because the photoresist is relatively soft, the metal ions 206 on the surface of the second mask layer 204 will gradually migrate to the surface of the first shallow trench 302a.

[0076] Step 134, as Figure 5C As shown, the second mask layer 204 is removed.

[0077] The second mask layer 204 is removed using a desmearing process and a wet cleaning process.

[0078] The metal ions 206 located on the surfaces of the first shallow trench 2031a and the second shallow trench 2032b will diffuse into the semiconductor substrate 201 during thermal processes, such as during the high-temperature process of resist removal. Figure 5C The arrow line corresponding to the metal ion 206 indicates the diffusion of the metal ion 206, and the area where the metal ion 206 diffuses in the semiconductor substrate 201 will form the contamination layer.

[0079] Step 2, as follows Figure 5E As shown, a wet etching process is used to perform a second etching on the semiconductor substrate 201 exposed on the inner surface of the shallow trench to remove the contamination layer on the inner surface of the shallow trench. The semiconductor substrate 201 in the area surrounded by the shallow trench 103 after the second etching constitutes the active region. Figure 5C In the text, the shallow trench after the second etching is completed is marked separately with 103.

[0080] The wet etching solution used for the second etching is TMAH. In other embodiments, the wet etching solution for the second etching may also include KOH or NaOH.

[0081] The thickness of the semiconductor substrate 201 removed by the second etching is 30 Å or more.

[0082] In a preferred embodiment of the present invention, when the second etching is performed using TMAH, the etching rate varies depending on the crystal orientation of the semiconductor substrate 201. The etching rate of the second etching on the (110) surface, the etching rate on the (100) surface, and the etching rate on the (111) surface decreases sequentially. In a preferred embodiment of the present invention, the etching rate of the second etching on the sides of the shallow trench is greater than the etching rate on the bottom surface. This ensures that the metal ions 206 on the sides of the shallow trench 103 are removed after the second etching. Although some metal ions 206 on the bottom surface of the shallow trench 103 are not removed, since the active region is composed of the semiconductor substrate 201 between the shallow trenches 103, it will not adversely affect the performance of the device. Figure 5E The dashed box 303 represents the formation area of ​​the first shallow trench 2031a before the second etching, and the dashed box 304 represents the formation area of ​​the second shallow trench 2032b before the second etching. It can be seen that the width of the first shallow trench 2031 and the second shallow trench 2032 will be increased to a certain extent after the second etching. By predefining the formation areas of the first shallow trench 2031a and the second shallow trench in step one, the width of the finally formed first shallow trench 2031 and the second shallow trench 2032 can be made to match the required value.

[0083] In a preferred embodiment of the present invention, in step two, as follows: Figure 5D As shown, before the second etching, a third etching process is performed on the hard mask layer 202 using a wet etching process, which enlarges the opening of the hard mask layer 202.

[0084] In the third etching, phosphoric acid is used to etch the third nitride layer and hydrofluoric acid is used to etch the second oxide layer 202a.

[0085] Step two is followed by filling the shallow trench with a first oxide layer to form a shallow trench isolation.

[0086] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A method for manufacturing shallow trench isolation, characterized in that, Includes the following steps: Step 1: Provide a semiconductor substrate, define the shallow trench formation area, and use a dry etching process to perform the first etching on the semiconductor substrate in the shallow trench formation area to form the shallow trench. The first etching is performed in a dry etching process chamber. During the first etching, metal ions are precipitated in the dry etching process chamber and deposited on the inner surface of the shallow trench. The metal ions deposited on the inner surface of the shallow trench diffuse into the semiconductor substrate at the inner surface of the shallow trench and form a contamination layer. Step 2: A wet etching process is used to perform a second etching on the semiconductor substrate exposed on the inner surface of the shallow trench to remove the contamination layer on the inner surface of the shallow trench. The semiconductor substrate in the area surrounded by the shallow trench after the second etching constitutes the active region.

2. The manufacturing method of the shallow trench isolation as described in claim 1, characterized in that: Step two is followed by filling the shallow trench with a first oxide layer to form a shallow trench isolation.

3. The manufacturing method of the shallow trench isolation as described in claim 1, characterized in that: The semiconductor substrate includes a silicon substrate.

4. The manufacturing method of the shallow trench isolation as described in claim 3, characterized in that: The semiconductor substrate is used to form a CMOS image sensor, which includes a pixel area and a logic area. The shallow trench includes a first shallow trench and a second shallow trench; The first shallow trench is a shallow trench located in the pixel area, and the second shallow trench is a shallow trench located in the logic area.

5. The manufacturing method of the shallow trench isolation as described in claim 4, characterized in that: The depth of the second shallow trench is greater than the depth of the first shallow trench.

6. The manufacturing method of shallow trench isolation as described in claim 5, characterized in that: In step one, a hard mask layer is used to define the formation area of ​​the shallow trench, which includes the following sub-steps: Step 11: Form the hard mask layer on the surface of the semiconductor substrate; Step 12: Pattern the hard mask layer. The opening of the patterned hard mask layer opens up the formation area of ​​the shallow trench. Step 13: Then, the first etching is performed using the patterned hard mask layer as a mask.

7. The manufacturing method of the shallow trench isolation as described in claim 6, characterized in that: In step two, before the second etching is performed, a third etching process is used to etch the hard mask layer using a wet etching process, which enlarges the opening of the hard mask layer.

8. The manufacturing method of shallow trench isolation as described in claim 7, characterized in that: The hard mask layer is composed of a second oxide layer and a third nitride layer stacked together.

9. The manufacturing method of the shallow trench isolation as described in claim 8, characterized in that: In the third etching, phosphoric acid is used to etch the third nitride layer and hydrofluoric acid is used to etch the second oxide layer.

10. The manufacturing method of shallow trench isolation as described in claim 6, characterized in that: In step 12, after the hard mask layer is patterned, the formation areas of the first shallow trench and the formation areas of the second shallow trench are defined simultaneously. In step 13, the first etching is divided into a first dry etching step and a second dry etching step. Step 13 includes the following sub-steps; Step 131: Perform the first dry etching step and simultaneously etch the semiconductor substrate in the formation regions of the first shallow trench and the second shallow trench until the depth of the first shallow trench reaches the target value. The first dry etching step forms the first shallow trench and a portion of the second shallow trench. Step 132: Form a second mask layer to cover the pixel area and open the logic area; Step 133: Perform the second dry etching step to continue etching the semiconductor substrate in the formation region of the second shallow trench until the depth of the second shallow trench reaches the target value. After the second dry etching step is completed, the second shallow trench is formed. Step 134: Remove the second mask layer.

11. The manufacturing method of shallow trench isolation as described in claim 10, characterized in that: In step 132, the material of the second mask layer includes photoresist, and the patterned structure of the second mask layer is formed by photoresist coating, exposure and development.

12. The manufacturing method of shallow trench isolation as described in claim 11, characterized in that: In step 134, the second mask layer is removed using a desmearing process and a wet cleaning process.

13. The manufacturing method of shallow trench isolation as described in claim 4, characterized in that: In step two, the wet etching solution used for the second etching includes KOH, NaOH, or TMAH.

14. The manufacturing method of the shallow trench isolation as described in claim 4, characterized in that: In step two, the thickness of the semiconductor substrate removed by the second etching is 30 Å or more.

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