Semiconductor packaging structure

Abstract

The present invention discloses a semiconductor package structure, which includes: a semiconductor chip having a plurality of pads on its first surface; a plurality of conductive pillars respectively formed on the plurality of pads, and a solder layer is provided on the top of each of the plurality of conductive pillars; an extension structure protruding from the surface of at least one of the plurality of conductive pillars, and at least a part of the extension structure laterally protrudes beyond the side region of the corresponding conductive pillar; a package carrier electrically connected to the semiconductor chip through the plurality of conductive pillars and the solder layer located on the top of each conductive pillar; and a molding compound for encapsulating the semiconductor chip, the plurality of conductive pillars, the extension structure and the package carrier. The present invention can not only increase the contact area between the molding compound and the conductive pillars, reduce the risk of delamination, but also reduce the risk of brittle cracking of the solder joint.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and particularly to a semiconductor packaging structure. Background Art

[0002] Over time, semiconductor packaging structures are becoming smaller and more concentrated, and are manufactured in a variety of shapes. According to the connection method, semiconductor packaging structures are typically divided into wire bonding (WB) type or flip chip (FC) bonding type. The packaging structure of the wire bonding type uses conductive bonding wires to achieve the connection between the electrodes of a semiconductor chip (referred to as a chip in this article) and a packaging frame, while the packaging structure of the flip chip type uses conductive bumps placed on the solder joints of the semiconductor chip electrodes to achieve the connection between the chip circuit and the packaging frame. The packaging structure of the flip chip bonding type has a shorter electrical connection path and a higher density of interconnection requirements than the packaging structure of the wire bonding type, thus providing excellent thermal and electrical properties and a smaller packaging structure size.

[0003] Currently, in the process of forming a flip chip package, generally, a low-melting-point solder is deposited at the interconnection position, and a pad bump is formed on the semiconductor chip, as Figure 1 shown. The pad bump may include a conductive column 6 such as a copper column protruding from the pad 4 of the semiconductor chip 1, and a solder ball 7 formed by reflow on the free end of the conductive column 6. Then, the solder ball 7 on the chip and the semiconductor chip 1 are inverted and placed on the packaging carrier 9. Next, the temperature is raised. When the temperature reaches a certain condition, the semiconductor chip 1 and the packaging carrier 9 are connected to each other by hot pressing the solder ball 7 on the surface of the conductive column 6 at high temperature, thereby forming a connection structure such as copper-tin-copper. Finally, encapsulation is performed using an encapsulant 8 to form a semiconductor packaging structure as Figure 2 shown.

[0004] However, during the pre-treatment and high and low temperature cycle tests after the flip chip package is manufactured, the encapsulant 8 of the flip chip package often delaminates, as Figure 3 shown, and the delamination mainly occurs at the joint between the conductive column 6 and the packaging carrier 9; after delamination, a gap appears (as shown in the A area in Figure 3 ). When the temperature reaches the melting point of the solder, it will also cause the liquid solder to flow into the delaminated position, resulting in solder loss, thereby affecting the signal transmission ability of the flip chip.

[0005] Therefore, it is necessary to provide an improved technical solution to overcome the above technical problems existing in the prior art. Summary of the Invention

[0006] To solve the above technical problems, the present invention provides a semiconductor package structure, which can not only increase the contact area between the plastic package and the conductive pillars, reduce the risk of delamination, but also reduce the risk of brittle cracking of the solder joints.

[0007] According to a first aspect of the present disclosure, there is provided a semiconductor package structure, comprising:

[0008] A semiconductor chip having a plurality of pads on a first surface thereof;

[0009] A plurality of conductive pillars respectively formed on the plurality of pads, and a solder layer is provided on the top of each of the plurality of conductive pillars;

[0010] An extension structure protruding from the surface of at least one of the plurality of conductive pillars, and at least a part of the extension structure laterally protrudes beyond the side region of the corresponding conductive pillar;

[0011] A package carrier electrically connected to the semiconductor chip through the plurality of conductive pillars and the solder layer located on the top of each conductive pillar;

[0012] A plastic package for encapsulating the semiconductor chip, the plurality of conductive pillars, the extension structure and the package carrier.

[0013] Optionally, the extension structure includes at least one of a first extension structure and a second extension structure,

[0014] wherein, the first extension structure protrudes from the side of at least one of the plurality of conductive pillars; at least a part of the second extension structure protrudes beyond the top surface and the side of at least one of the plurality of conductive pillars at the same time.

[0015] Optionally, when the extension structure includes the first extension structure, the first extension structure is arranged as a spiral convex layer surrounding the side of the corresponding conductive pillar.

[0016] Optionally, when the extension structure includes the first extension structure, the first extension structure is arranged as at least one layer of annular convex layer or gear-shaped convex layer surrounding the side of the corresponding conductive pillar.

[0017] Optionally, the first extension structure has at least a first surface coplanar with the top surface of the corresponding conductive pillar.

[0018] Optionally, when the extension structure includes the first extension structure, the first extension structure is arranged as a plurality of convex blocks spaced apart from each other.

[0019] Optionally, when the extension structure includes the second extension structure, the second extension structure at least includes a circular convex layer portion located between the top of the corresponding conductive column and the solder layer.

[0020] Optionally, the material for forming the extension structure is metal.

[0021] Optionally, the extension structure is formed on the corresponding conductive column by electroplating.

[0022] Optionally, the surface of the extension structure has a microstructure formed after roughening treatment.

[0023] Optionally, the height of the portion of the extension structure protruding from the side surface of the corresponding conductive column is less than half of the spacing distance between adjacent conductive columns among the plurality of conductive columns.

[0024] Optionally, the encapsulation carrier includes any one of a lead frame and an encapsulation substrate.

[0025] The beneficial effects of the present invention at least include:

[0026] In the embodiment of the present invention, by protruding an extension structure on the outer surface of the conductive column and setting at least part of the extension structure to protrude beyond the side surface of the conductive column, the contact area between the encapsulant and the conductive column can be increased during plastic encapsulation, thereby increasing the adhesion between the encapsulant material for forming the encapsulant and the conductive column, which is beneficial to reducing the delamination risk. Additionally, when a certain surface of the extension structure is coplanar with the top surface of the conductive column, the area of the top surface of the conductive column can also be enlarged, enabling the top of the conductive column to accommodate a larger volume of solder, thickening the thickness of the solder layer when the conductive column is joined to the frame carrier, and thus being beneficial to reducing the risk of solder brittle cracking.

[0027] In a further preferred embodiment, based on the microstructure formed after roughening treatment on the surface of the extension structure, the surface roughness of the extension structure is increased, which is beneficial to further increasing the adhesion between the encapsulant material and the conductive column.

[0028] It should be noted that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present invention. Description of the Drawings

[0029] Figure 1 Showing a schematic structural diagram of a pad protrusion on a conventional semiconductor chip;

[0030] Figure 2 Showing a schematic structural diagram of a conventional semiconductor package structure;

[0031] Figure 3 Showing a schematic structural diagram of a conventional semiconductor package structure when delamination occurs;

[0032] Figure 4 A structural schematic diagram showing a semiconductor packaging structure provided according to an embodiment of the present invention;

[0033] Figure 5a and Figure 5b respectively show Figure 4 different cross-sectional structural schematic diagrams of the first extension structure in [[ID=]] at the straight line l1;

[0034] Figure 6a and Figure 6b respectively show Figure 4 different cross-sectional structural schematic diagrams of the second extension structure in [[ID=]] at the straight line l2. Detailed implementation manners

[0035] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure content of the present invention more thorough and comprehensive.

[0036] As Figure 4 shown, the semiconductor packaging structure disclosed by the present invention includes: a semiconductor chip 1, the first surface of the semiconductor chip 1 having a plurality of pads 4; a plurality of conductive pillars 6 respectively formed on the plurality of pads 4, and a solder layer 7 provided on the top of each conductive pillar 6; a packaging carrier 9, which is used to carry the semiconductor chip 1 (for example, any one of a lead frame and a packaging substrate) and is electrically connected to the semiconductor chip 1 through the plurality of conductive pillars 6 and the solder layer 7 located on the top of each conductive pillar 6; an extension structure protruding from the outer surface (including the side surface and / or the top surface) of at least one of the plurality of conductive pillars 6, and at least a part of the extension structure protruding laterally beyond the side area of the corresponding conductive pillar 6; and a molding compound 8 formed by curing the molding compound in a molten state for encapsulating the semiconductor chip 1, the plurality of conductive pillars 6, the extension structure, and the packaging carrier 9.

[0037] In the present invention, the semiconductor chip (referred to as the chip) 1 is a general term. To simplify the drawings and highlight the inventive points, the internal structure of the semiconductor chip 1 is not shown in the drawings, but the internal structure of the semiconductor chip 1 can be understood according to the prior art. For example, semiconductor devices and redistribution layers are formed in the semiconductor chip 1. The semiconductor devices and the plurality of pads 4 can be located on the same side surface of the chip 1 or on different side surfaces of the chip 1. When the semiconductor devices and the plurality of pads 4 are located on different side surfaces of the chip 1, a through-hole penetrating the chip can be used to electrically connect the plurality of pads 4 to the semiconductor devices. In this embodiment, the semiconductor devices and the plurality of pads 4 are located on the first surface of the chip 1, and the semiconductor devices and the plurality of pads 4 are electrically connected, and the circuit structure in the chip is electrically connected to the corresponding pins on the packaging carrier 9 and the external circuit by using the plurality of pads 4.

[0038] The plurality of conductive pillars 6 can be formed on the plurality of pads 4 by, for example, electroplating, and the plurality of conductive pillars 6 correspond to the plurality of pads 4 one by one, that is, a corresponding conductive pillar 6 is formed on each of the plurality of pads 4. The materials of the plurality of pads 4 are aluminum, copper, gold, silver, etc.

[0039] Furthermore, in the packaging structure of the flip-chip in the embodiment of the present invention, an insulating layer 2 is further formed on the first surface of the chip 1. The insulating layer 2 can be formed by depositing an oxidation material such as silicon oxide on the first surface of the semiconductor chip. In a possible embodiment of the present invention, the plurality of pads 4 are also disposed on the first surface of the chip 1. The plurality of pads 4 are directly connected to the semiconductor devices in the chip 1 and are exposed through the openings etched on the insulating layer 2. In another possible embodiment of the present invention, the plurality of pads 4 are disposed on the surface of the insulating layer 2 away from the chip 1, that is, the insulating layer 2 is formed between the semiconductor chip 1 and the plurality of pads 4, and the plurality of pads 4 are connected to the semiconductor devices in the chip 1 through the plurality of vias on the insulating layer 2. Optionally, the insulating layer 2 is a single layer or a multi-layer stacked structure of a silicon oxide layer, a silicon nitride layer, a polyimide resin layer, or a benzoxazine resin layer, for protecting the chip 1. In this embodiment, the insulating layer 2 is a silicon oxide layer.

[0040] Furthermore, in the packaging structure of the flip-chip in the embodiment of the present invention, an electroplating seed layer is further formed on the surface of the plurality of pads 4. The material of the electroplating seed layer is one or a mixture of several of aluminum, copper, gold, and silver. The process for forming the electroplating seed layer is a sputtering process or a physical vapor deposition process. When the material of the electroplating seed layer is aluminum, the process for forming the electroplating seed layer is a sputtering process. When the material of the electroplating seed layer is one of copper, gold, and silver, the process for forming the electroplating seed layer is a physical vapor deposition process. In this embodiment, the material of the electroplating seed layer is copper.

[0041] Preferably, in this embodiment, an Under Bump Metallurgy (UBM) 5 is formed on the surface of the plurality of pads 4 away from the chip 1 to serve as an electroplating seed layer.

[0042] In this embodiment, the plurality of pads 4 and the Under Bump Metallurgy 5 located on the surface of the plurality of pads 4 constitute a metal interconnection layer. Subsequently, a plurality of conductive pillars 6 are formed on the Under Bump Metallurgy 5. The material of the plurality of conductive pillars 6 is copper or other suitable metals, and the plurality of conductive pillars 6 are formed on the surface of the Under Bump Metallurgy 5 by electroplating. The Under Bump Metallurgy 5 is a metallization transition layer between the chip pad 4 and the conductive pillar 6, mainly playing the roles of adhesion and diffusion barrier. The Under Bump Metallurgy 5 is usually composed of multiple metal films such as an adhesion layer, a diffusion barrier layer, and a wetting layer. Methods such as sputtering, evaporation, electroless plating, and electroplating can be used to form the Under Bump Metallurgy 5.

[0043] Furthermore, in the flip-chip packaging structure of the embodiment of the present invention, a passivation layer 3 is further formed on the surface of the insulating layer 2 away from the semiconductor chip 1. An opening is formed in the passivation layer 3, and the passivation layer 3 covers a part of each of the plurality of pads 4, and even covers a part of the Under Bump Metallurgy 5 on each pad 4. Since the pads 4 produced by the chip manufacturer are often large, the size of the columnar electrodes, i.e., the metal electrodes 6, directly formed on the pads 4 is also large. Therefore, by forming a passivation layer 3 on the surface of the insulating layer 2, and using the passivation layer 3 to cover a part of each pad 4, the exposed area of each pad 4 is reduced, so that the size of the subsequent formed conductive pillars 6 is reduced, which helps to form a packaging structure with high density.

[0044] Optionally, the extension structure disclosed in the present invention includes at least one of a first extension structure 101 and a second extension structure 102. Among them, for the first extension structure 101, it protrudes from the side surface of at least one of the plurality of conductive pillars 6. It can be understood that the first extension structure 101 can increase the contact area between the encapsulant 8 and the conductive pillars 6 during encapsulation, thereby increasing the adhesion force between the encapsulant material forming the encapsulant 8 and the conductive pillars 6, which is beneficial to reducing the delamination risk. For the second extension structure 102, at least a part of it protrudes beyond the top surface and the side surface of at least one of the plurality of conductive pillars 6 at the same time. It can be understood that the second extension structure 102 can not only further increase the contact area between the encapsulant 8 and the conductive pillars 6, but also expand the area of the top surface of the conductive pillars 6, so that the top of the conductive pillars 6 can accommodate a larger volume of solder, and further thicken the thickness of the solder layer 7 when the conductive pillars 6 are joined to the frame carrier 9 (since the hardness of the conductive pillars 6 is generally greater than the hardness of the solder layer 7, when the thickness of the solder layer 7 is thin, the risk of solder brittle cracking will be greatly increased), thereby being beneficial to reducing the risk of solder brittle cracking.

[0045] Exemplarily, the material for forming the extension structure is metal (which may be the same as or different from the material for forming the conductive post 6, and the present invention does not limit this). Moreover, the extension structure is formed on the corresponding conductive post 6 by electroplating. That is to say, for the first extension structure 101, its forming material is metal and is formed on the corresponding conductive post 6 by electroplating. For the second extension structure 102, its forming material is also metal and can also be formed on the corresponding conductive post 6 by electroplating. In this way, while ensuring that there is a fixed connection structure between the extension structure and the corresponding conductive post 6 that is not affected by temperature changes, it can also increase the contact area between the encapsulant 8 and the conductive post 6 during encapsulation, thereby increasing the adhesion between the encapsulant material for forming the encapsulant and the conductive post 6, achieving the purpose of reducing the risk of delamination in the encapsulated structure during high and low temperature cycling.

[0046] For the first extension structure 101, optionally, in the first embodiment of the present invention, the first extension structure 101 is arranged as a spiral convex layer surrounding the side surface of the corresponding conductive post 6. In this embodiment, it can well accommodate the complexity of the preparation process of the first extension structure 101 and the requirement for a larger contact area. In the second embodiment of the present invention, the first extension structure 101 is arranged as at least one layer of annular convex layer surrounding the side surface of the corresponding conductive post 6, and the cross-sectional shape of each layer of the annular convex layer in the first extension structure 101 is as Figure 5a shown. In this embodiment, the preparation process of the first extension structure 101 is relatively simple. In the third embodiment of the present invention, the first extension structure 101 is arranged as at least one layer of gear-shaped convex layer surrounding the side surface of the corresponding conductive post 6, and the cross-sectional shape of each layer of the gear-shaped convex layer in the first extension structure 101 is as Figure 5b shown. In this embodiment, although the preparation process of the first extension structure 101 is relatively complex, it can achieve a larger contact area between the encapsulant 8 and the conductive post 6. In the fourth embodiment of the present invention, the first extension structure 101 is arranged as a plurality of spaced-apart bumps. In this embodiment, it is beneficial to flexibly adjust the contact area between the encapsulant 8 and the conductive post 6. In a further embodiment, the first extension structure 101 has at least a first surface coplanar with the top surface of the corresponding conductive post 6. For example, the uppermost surface of the first extension structure 101 is coplanar with the top surface of the corresponding conductive post 6. At this time, the first extension structure 101 can also simultaneously perform the corresponding function of the second extension structure 102, that is, it can also expand the area of the top surface of the conductive post 6, so that the top of the conductive post 6 can accommodate a larger volume of solder.

[0047] For the second extension structure 102, it at least includes a circular convex layer portion located between the top of the corresponding conductive column 6 and the solder layer 7. Optionally, in a possible embodiment of the present invention, a part of the second extension structure 102 is arranged as an annular convex layer surrounding the side surface near the top of the corresponding conductive column 6, and another part is arranged as a circular convex layer between the top of the corresponding conductive column 6 and the solder layer 7. That is, at this time, the top surface of the corresponding conductive column 6 is located inside the second extension structure 102. At this time, the cross-sectional shape of the second extension structure 102 along the straight line l2 is as Figure 6a or Figure 6b shown. In another possible embodiment of the present invention, the whole of the second extension structure 102 is arranged as a circular convex layer between the top of the corresponding conductive column 6 and the solder layer 7. That is, at this time, the top surface of the corresponding conductive column 6 and the surface of the second extension structure 102 away from the solder layer 7 are coplanar. At this time, the cross-sectional shape of the second extension structure 102 is as Figure 6b shown.

[0048] Furthermore, after forming the above extension structure, the present invention also includes roughening the surface of each extension structure so that the surface of the extension structure can have microstructures formed after roughening treatment, that is, increasing the surface roughness of the extension structure, thereby further increasing the contact surface area between the encapsulant 8 and the conductive column 6, which is beneficial to further increasing the adhesion force between the encapsulant material forming the encapsulant 8 and the conductive column 6, and thus further reducing the delamination risk.

[0049] Referring to Figure 4 、 Figure 5a 、 Figure 5b 、 Figure 6a and Figure 6b , in the present invention, the height of the part of the above extension structure protruding from the side surface of the corresponding conductive column (whether it is the height h1 of the part of the first extension structure 101 protruding from the side surface of the corresponding conductive column 6 or the height h2 of the part of the second extension structure 102 protruding from the side surface of the corresponding conductive column 6) is less than half of the spacing distance between adjacent conductive columns among the plurality of conductive columns. In this way, short circuit between adjacent conductive columns 6 can be avoided. However, it can be understood that in practical applications, the convex height and convex layer thickness of the extension structure corresponding convex layer need to be comprehensively set in combination with specific process capabilities and conductive column density and other factors, and the present invention does not limit its specific data.

[0050] In summary, in the embodiments of the present invention, an extended structure is convexly provided on the outer surface of the conductive post, and at least a part of the extended structure protrudes beyond the side surface of the conductive post. Thus, the contact area between the encapsulant and the conductive post can be increased during encapsulation, thereby increasing the adhesion between the encapsulant material forming the encapsulant and the conductive post, which is beneficial to reducing the delamination risk. In addition, when a certain surface of the extended structure is coplanar with the top surface of the conductive post, the area of the top surface of the conductive post can also be enlarged, so that the top of the conductive post can accommodate a larger volume of solder, thickening the solder layer when the conductive post is joined to the frame carrier, which is thus beneficial to reducing the risk of brittle cracking of the solder joint.

[0051] In a further preferred embodiment, based on the microstructures formed after roughening treatment on the surface of the extended structure, the surface roughness of the extended structure is increased, which is beneficial to further increasing the adhesion between the encapsulant material and the conductive post.

[0052] Finally, it should be noted that: Obviously, the above embodiments are merely examples for clearly illustrating the present invention and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or modifications derived therefrom are still within the protection scope of the present invention.

Claims

1. A semiconductor package structure, wherein, comprising: a semiconductor chip, the first surface of the semiconductor chip having a plurality of pads; a plurality of conductive pillars, respectively formed on the plurality of pads, and a solder layer is provided on the top of each of the plurality of conductive pillars; an extension structure, protruding from the surface of at least one of the plurality of conductive pillars, and at least a part of the extension structure laterally protrudes beyond the side region of the corresponding conductive pillar, and a microstructure formed after roughening treatment is provided on the surface of the extension structure; a package carrier, electrically connected to the semiconductor chip through the plurality of conductive pillars and the solder layer located on the top of each conductive pillar; a molding compound, for encapsulating the semiconductor chip, the plurality of conductive pillars, the extension structure and the package carrier, wherein, the extension structure includes a first extension structure and a second extension structure; the first extension structure and the second extension structure are spaced apart on the conductive pillar; the first extension structure protrudes from the side of at least one of the plurality of conductive pillars, and at least a part of the second extension structure protrudes beyond the top surface and the side of at least one of the plurality of conductive pillars at the same time.

2. The semiconductor package structure according to claim 1, wherein, the first extension structure is configured as one of a spiral convex layer surrounding the side of the corresponding conductive pillar, at least one layer of annular convex layer and at least one layer of gear-shaped convex layer.

3. The semiconductor package structure according to claim 2, wherein, the first extension structure has at least a first surface coplanar with the top surface of the corresponding conductive pillar.

4. The semiconductor package structure according to claim 1, wherein, the first extension structure is configured as a plurality of spaced-apart bumps.

5. The semiconductor package structure according to claim 1, wherein, the second extension structure at least includes a circular convex layer portion located between the top of the corresponding conductive pillar and the solder layer.

6. The semiconductor package structure according to claim 1, wherein, the forming material of the extension structure is metal.

7. The semiconductor package structure according to claim 1, wherein, the extension structure is formed on the corresponding conductive pillar by electroplating.

8. The semiconductor package structure according to claim 1, wherein, the height of the part of the extension structure protruding from the side of the corresponding conductive pillar is less than half of the spacing distance between adjacent conductive pillars among the plurality of conductive pillars.

9. The semiconductor package structure according to claim 1, wherein, the package carrier includes any one of a lead frame and a package substrate.

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