Semiconductor devices

Abstract

The purpose is to provide a semiconductor device that can be miniaturized and has a reduced inductance between a high potential terminal and a low potential terminal. The semiconductor device (100) comprises: an insulating substrate (1); a circuit pattern (5) comprising a low potential circuit pattern (2) arranged on the insulating substrate (1) and a high potential circuit pattern (3) arranged in a region adjacent to the low potential circuit pattern (2) on the insulating substrate (1); a plurality of semiconductor chips (6) mounted on the circuit pattern (5); a low potential terminal (7) having one end connected to the low potential circuit pattern (2); and a high potential terminal (8) having one end connected to the high potential circuit pattern (3), wherein the high potential terminal (8) and the low potential terminal (7) have: flat plate portions (8b, 7b) that constitute parallel flat plates arranged vertically parallel to each other and extend on the low potential circuit pattern (2) side; and electrode portions (8c, 7c) that protrude from the insulating substrate (1).

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] Currently, there are semiconductor devices that form an electric circuit by mounting a plurality of semiconductor chips on an insulating substrate. When a plurality of semiconductor chips are used to form an electric circuit, the electric circuit becomes complicated and the area of ​​the wiring region increases, so there is a concern that the semiconductor device will become larger.

[0003] In order to solve such a problem, for example, Patent Document 1 proposes a technology for improving circuit wiring within a semiconductor device having a complex electric circuit to achieve miniaturization of the semiconductor device.

[0004] Patent Document 1: International Publication No. 2016 / 084622

[0005] However, in the technology described in Patent Document 1, the main terminal on the low potential side (equivalent to the low potential terminal) and the main terminal on the high potential side (equivalent to the high potential terminal) do not form parallel plates. Therefore, there is a problem that the inductance on the path from the main terminal on the high potential side to the main terminal on the low potential side becomes large. Summary of the invention

[0006] Therefore, an object of the present invention is to provide a semiconductor device that can be downsized and has a reduced inductance between a high potential terminal and a low potential terminal.

[0007] The semiconductor device involved in the present invention comprises: an insulating substrate; a circuit pattern, which includes a circuit pattern on a low potential side arranged on the insulating substrate and a circuit pattern on a high potential side arranged in an area adjacent to the circuit pattern on the low potential side on the insulating substrate; a plurality of semiconductor chips, which are mounted on the circuit pattern; a low potential terminal, one end of which is connected to the circuit pattern on the low potential side; and a high potential terminal, one end of which is connected to the circuit pattern on the high potential side, the high potential terminal and the low potential terminal having: a middle portion, which constitutes parallel flat plates arranged parallel to each other up and down, extending on the side of the circuit pattern on the low potential side; and the other end, which protrudes from the insulating substrate.

[0008] Effects of the Invention

[0009] According to the present invention, the circuit pattern on the high potential side is formed at a position adjacent to the circuit pattern on the low potential side, so one end of the high potential terminal and one end of the low potential terminal are arranged at adjacent positions, thereby shortening the length from one end of the high potential terminal to one end of the low potential terminal, increasing the length of the parallel plate formed by the middle portion of the high potential terminal and the low potential terminal, and further increasing the area of ​​the parallel plate.

[0010] Thus, by shortening the length from one end of the high potential terminal to one end of the low potential terminal and increasing the area of ​​the parallel plate, the semiconductor device can be miniaturized and the inductance between the high potential terminal and the low potential terminal can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a top view of the semiconductor device according to the first embodiment.

[0012] Figure 2 This is a side view of the semiconductor device according to the first embodiment.

[0013] Figure 3 This is a circuit diagram showing an equivalent circuit of the semiconductor device according to the first embodiment.

[0014] Figure 4 It is a top view of the semiconductor device involved in Embodiment 2.

[0015] Figure 5 It is a side view of the semiconductor device involved in Embodiment 2. DETAILED DESCRIPTION

[0016] <Implementation method 1>

[0017] Hereinafter, Embodiment 1 will be described using the drawings. Figure 1 1 is a plan view of the semiconductor device 100 according to the first embodiment. Figure 2 is a side view of the semiconductor device 100. Figure 1 and Figure 2 In order to make the internal structure of the semiconductor device 100 easier to see, the insulating material serving as the packaging material is omitted from the illustration.

[0018] like Figure 1 As shown, the semiconductor device 100 includes an insulating substrate 1, a circuit pattern 5, a plurality of (e.g., 12) semiconductor chips 6, a low potential terminal 7, a high potential terminal 8, and an output terminal 9. Furthermore, the semiconductor device 100 includes an insulating material such as gel (not shown) that encapsulates the insulating substrate 1, the circuit pattern 5, the plurality of semiconductor chips 6, a portion of the low potential terminal 7, a portion of the high potential terminal 8, and a portion of the output terminal 9.

[0019] The insulating substrate 1 is made of, for example, ceramics, and is formed into a rectangular shape when viewed from above. In addition, a circuit pattern 5 is provided on the upper surface of the insulating substrate 1. The circuit pattern 5 includes a low potential circuit pattern 2 as a circuit pattern on the low potential side, a high potential circuit pattern 3 as a circuit pattern on the high potential side, and an output circuit pattern 4 as a circuit pattern on the output side.

[0020] The low potential circuit pattern 2 is provided from the other end than the central portion to one end of the upper surface of the insulating substrate 1 in the length direction. The high potential circuit pattern 3 is provided in a region adjacent to the low potential circuit pattern 2. Specifically, the high potential circuit pattern 3 is provided from the other end than the central portion to the other end of the upper surface of the insulating substrate 1 in the length direction.

[0021] Here, at the other end of the upper surface of the insulating substrate 1 in the longitudinal direction than the center, the high potential circuit pattern 3 is shaped to surround the outer periphery of the low potential circuit pattern 2 so that the low potential circuit pattern 2 does not contact the high potential circuit pattern 3 .

[0022] The output circuit pattern 4 is provided on the outer periphery of the low potential circuit pattern 2 and the high potential circuit pattern 3 on the upper surface of the insulating substrate 1. Specifically, the output circuit pattern 4 is provided along two sides of the upper surface of the insulating substrate 1 in the longitudinal direction.

[0023] like Figure 1 As shown, a plurality of semiconductor chips 6, such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor), are mounted on the circuit pattern 5. Specifically, 12 semiconductor chips 6 are SiC-MOSFETs, of which 6 semiconductor chips 6 are arranged in pairs of 3 on the high potential circuit pattern 3, and are connected to a portion of the output circuit pattern 4 located on the high potential circuit pattern 3 side using a plurality of aluminum wires 6a.

[0024] The remaining six semiconductor chips 6 are arranged in pairs of three at the location of the output circuit pattern 4 on the side of the low potential circuit pattern 2, and are connected to the low potential circuit pattern 2 using a plurality of aluminum wires 6a. Figure 1 In the embodiment, 12 semiconductor chips 6 are mounted, but the present invention is not limited to this, and it is sufficient as long as 2 or more semiconductor chips 6 are mounted.

[0025] Here, the “low potential circuit pattern 2 side” refers to a region 17 from the center of the upper surface of the insulating substrate 1 to one end in the longitudinal direction. The “high potential circuit pattern 3 side” refers to a region 18 from the center of the upper surface of the insulating substrate 1 to the other end in the longitudinal direction.

[0026] like Figure 1 and Figure 2As shown, the low potential terminal 7 and the high potential terminal 8 constitute parallel flat plates arranged one above the other with the insulating paper 11 interposed therebetween. The low potential terminal 7 has: a connecting portion 7a, which is one end connected to the low potential circuit pattern 2; a flat plate portion 7b, which is a midway portion constituting a parallel flat plate with the high potential terminal 8; and an electrode portion 7c, which is the other end protruding from the insulating substrate 1.

[0027] The plate portion 7b is arranged above the insulating substrate 1 and parallel to the insulating substrate 1. The plate portion 7b extends toward the low potential circuit pattern 2 of the insulating substrate 1 and covers the upper surface of the low potential circuit pattern 2 and a portion of the upper surface of the output circuit pattern 4.

[0028] The connection portion 7 a extends in the vertical direction, one end of which is connected to a portion of the low potential circuit pattern 2 on the high potential circuit pattern 3 side, and the other end of which is connected to one end of the flat plate portion 7 b .

[0029] The electrode portion 7c is formed to be narrower than the flat plate portion 7b in a plan view and is formed in an L-shape in a side view. One end of the electrode portion 7c is connected to the other end of the flat plate portion 7b, and the electrode portion 7c is bent upward and then extends to the outside of the insulating substrate 1 in parallel with the flat plate portion 7b. That is, the electrode portion 7c protrudes from one end in the longitudinal direction of the insulating substrate 1.

[0030] like Figure 1 and Figure 2 As shown, the high potential terminal 8 has: a connecting portion 8a, which is one end portion connected to the high potential circuit pattern 3; a flat plate portion 8b, which is a midway portion forming a parallel flat plate with the low potential terminal 7; and an electrode portion 8c, which is the other end portion protruding from the insulating substrate 1.

[0031] The flat plate portion 8b is arranged above the insulating substrate 1 in parallel with the insulating substrate 1 and is located on the upper side of the flat plate portion 7b of the low potential terminal 7. In other words, the flat plate portion 7b of the low potential terminal 7 is arranged on the lower side of the flat plate portion 8b of the high potential terminal 8. In addition, the flat plate portion 8b extends on the low potential circuit pattern 2 side of the insulating substrate 1, covering the upper surface of the low potential circuit pattern 2 and a portion of the upper surface of the output circuit pattern 4.

[0032] The connection portion 8a extends in the vertical direction, one end of which is connected to a portion of the high potential circuit pattern 3 adjacent to the connection portion 7a of the low potential terminal 7, and the other end of which is connected to one end of the flat plate portion 8b.

[0033] The electrode portion 8c is formed to be narrower than the flat plate portion 8b in a plan view. One end of the electrode portion 8c is connected to the other end of the flat plate portion 8b, and the electrode portion 8c extends to the outside of the insulating substrate 1. That is, the electrode portion 8c protrudes from one end in the length direction of the insulating substrate 1. In addition, the electrode portion 7c of the low potential terminal 7 and the electrode portion 8c of the high potential terminal 8 are located at the same height position.

[0034] like Figure 1 and Figure 2 As shown, the output terminal 9 is a terminal to which the output of the semiconductor chip 6 is given, and has: two connecting portions 9a, which are one end portions connected to the portion of the output circuit pattern 4 located on the high potential circuit pattern 3 side; a plate-like portion 9b, which connects the two connecting portions 9a; and two electrode portions 9c, which are the other end portions protruding from the insulating substrate 1.

[0035] The two connection portions 9a extend in the vertical direction and face each other across the high potential circuit pattern 3. One end of the two connection portions 9a is connected to a portion of the output circuit pattern 4 located on the high potential circuit pattern 3 side. The plate-like portion 9b is arranged above the insulating substrate 1 and parallel to the insulating substrate 1.

[0036] The two electrode portions 9c are formed to have the same width as the plate-shaped portion 9b and are formed at the same height as the plate-shaped portion 9b. In addition, the two electrode portions 9c protrude from the other end of the insulating substrate 1 in the length direction, which is opposite to the protrusion direction of the electrode portion 7c of the low potential terminal 7 and the electrode portion 8c of the high potential terminal 8.

[0037] Assuming that the output terminal 9 is arranged on the low potential circuit pattern 2 side of the output circuit pattern 4, that is, when the two connecting portions 9a are connected to the portion of the output circuit pattern 4 located on the low potential circuit pattern 2 side, and the two electrode portions 9c protrude from one end in the length direction of the insulating substrate 1, the parasitic resistance between the semiconductor chip 6 arranged on the high potential circuit pattern 3 side and the output terminal 9 becomes larger, and the power loss of the electrical circuit composed of multiple semiconductor chips 6 becomes larger.

[0038] In addition, when the two electrode portions 9c are connected to the portion of the output circuit pattern 4 located on the high potential circuit pattern 3 side and the two electrode portions 9c protrude from one end in the length direction of the insulating substrate 1, the length Lb (refer to Figure 2 ) becomes longer, and therefore, the inductance of the output terminal 9 increases.

[0039] In order to solve such a problem, in the first embodiment, the output terminal 9 is provided on the high potential circuit pattern 3 side of the output circuit pattern 4. That is, the two connecting portions 9a are connected to the portion of the output circuit pattern 4 located on the high potential circuit pattern 3 side, and the two electrode portions 9c protrude from the other end in the longitudinal direction of the insulating substrate 1.

[0040] In addition, the main electrode mounting portion 10 is provided on the electrode portion 7 c of the low potential terminal 7 , the electrode portion 8 c of the high potential terminal 8 , and the electrode portion 9 c of the output terminal 9 .

[0041] Figure 3 is a circuit diagram showing an equivalent circuit of the semiconductor device 100. Figure 3 As shown, the semiconductor device 100 has six parallel semiconductor chips 6 arranged on the upper bridge arm side between the P electrode (equivalent to the high potential terminal 8) and the AC electrode (equivalent to the output terminal 9), and has six parallel semiconductor chips 6 arranged on the lower bridge arm side between the AC electrode (equivalent to the output terminal 9) and the N electrode (equivalent to the low potential terminal 7). Here, the P electrode side is referred to as the upper bridge arm, and the N electrode side is referred to as the lower bridge arm.

[0042] Furthermore, in the above description, the semiconductor chip 6 is described as a SiC-MOSFET, but the present invention is not limited thereto, and the semiconductor chip 6 may be a single-chip structure including a switching element such as an RC-IGBT (Reverse Conductive Insulated Gate Bipolar Transistor) and a freewheeling element.

[0043] As described above, the semiconductor device 100 is packaged with an insulating material (not shown), and the electrode portion 7 c of the low potential terminal 7 , the electrode portion 8 c of the high potential terminal 8 , and the electrode portion 9 c of the output terminal 9 are exposed from the insulating material.

[0044] As described above, the semiconductor device 100 involved in embodiment 1 comprises: an insulating substrate 1; a circuit pattern 5, which includes a low potential circuit pattern 2 arranged on the insulating substrate 1 and a high potential circuit pattern 3 arranged in an area adjacent to the low potential circuit pattern 2 on the insulating substrate 1; a plurality of semiconductor chips 6, which are mounted on the circuit pattern 5; a low potential terminal 7, one end of which is connected to the low potential circuit pattern 2; and a high potential terminal 8, one end of which is connected to the high potential circuit pattern 3, the high potential terminal 8 and the low potential terminal 7 have: flat plate portions 8b, 7b, which constitute parallel flat plates arranged parallel to each other up and down and extend on the side of the low potential circuit pattern 2; and electrode portions 8c, 7c, which protrude from the insulating substrate 1.

[0045] The high potential circuit pattern 3 is formed at a position adjacent to the low potential circuit pattern 2, so the connection portion 8a of the high potential terminal 8 and the connection portion 7a of the low potential terminal 7 are arranged at adjacent positions, thereby shortening the length from the connection portion 8a of the high potential terminal 8 to the connection portion 7a of the low potential terminal 7, and increasing the length La of the parallel plate formed by the plate portions 8b and 7b of the high potential terminal 8 and the low potential terminal 7 (see Figure 2 ), thereby increasing the area of ​​the parallel plates.

[0046] Thus, by shortening the length from the connection portion 8 a of the high potential terminal 8 to the connection portion 7 a of the low potential terminal 7 and increasing the area of ​​the parallel plate, the semiconductor device 100 can be miniaturized and the inductance between the high potential terminal 8 and the low potential terminal 7 can be reduced.

[0047] In addition, 6 semiconductor chips 6 out of the 12 semiconductor chips 6 are arranged in pairs of 3 on the high potential circuit pattern 3, and are connected to the portion of the output circuit pattern 4 located on the high potential circuit pattern 3 side using a plurality of aluminum wires 6a. The remaining 6 semiconductor chips 6 are arranged in pairs of 3 at the portion of the output circuit pattern 4 located on the low potential circuit pattern 2 side, and are connected to the low potential circuit pattern 2 using a plurality of aluminum wires 6a.

[0048] By arranging the semiconductor chip 6 in this way, the wiring freedom of the aluminum wire 6a increases, so the number of aluminum wires 6a can be increased and the current density per aluminum wire 6a can be reduced. Thus, the inductance between the plurality of aluminum wires 6a can be reduced.

[0049] In addition, the semiconductor device 100 also has an output terminal 9 to which the output of the semiconductor chip 6 is assigned, and the circuit pattern 5 also includes an output circuit pattern 4 arranged on the peripheral side of the low potential circuit pattern 2 and the high potential circuit pattern 3 on the insulating substrate 1, and the output terminal 9 has a connecting portion 9a connected to a portion of the output circuit pattern 4 located on the high potential circuit pattern 3 side and an electrode portion 9c protruding from the insulating substrate 1.

[0050] Therefore, the length Lb of the output terminal 9 from the connection portion 9a to the electrode portion 9c can be shortened (see Figure 2 ), so the parasitic resistance between the semiconductor chip 6 arranged on the high potential circuit pattern 3 side and the output terminal 9 can be reduced.

[0051] In addition, since the semiconductor chip 6 is a SiC-MOSFET, it is possible to realize high-speed current cutoff during the turn-off operation of the semiconductor chip 6. Thus, it is possible to reduce power loss generated when the semiconductor chip 6 cuts off the current.

[0052] Furthermore, since the semiconductor chip 6 is formed by integrating the switching element and the freewheeling element into a single chip, the semiconductor device 100 can be densely packed and further miniaturized.

[0053] In addition, the flat plate portion 7b of the low potential terminal 7 is arranged below the flat plate portion 8b of the high potential terminal 8, so that the flat plate portion 7b of the low potential terminal 7 constituting the lower portion of the parallel plate is at the same potential as the low potential circuit pattern 2 and the aluminum wire 6a located below the parallel plate, and the height position of the parallel plate can be lowered. Thus, the semiconductor device 100 can be further miniaturized.

[0054] <Implementation method 2>

[0055] Next, a semiconductor device 100A according to a second embodiment will be described. Figure 4 It is a top view of a semiconductor device 100A according to the second embodiment. Figure 5 It is a side view of the semiconductor device 100A. In the second embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

[0056] like Figure 4 and Figure 5 As shown, in embodiment 2, the area where the output circuit pattern 4 is provided is changed relative to the case of embodiment 1, and accordingly, as for the semiconductor device 100A, the output terminal 9 is replaced with an output terminal 19, and the output terminal 19 has its own shape and the connection portion with the output circuit pattern 4 changed relative to the output terminal 9.

[0057] The output circuit pattern 4 is provided along two sides of the upper surface of the insulating substrate 1 in the longitudinal direction, and is also provided on the side of the upper surface of the insulating substrate 1 at the other end in the longitudinal direction.

[0058] The output terminal 19 has a connection portion 19 a as one end connected to the side of the output circuit pattern 4 on the other end side of the upper surface of the insulating substrate 1 in the longitudinal direction, and an electrode portion 19 b as the other end protruding from the insulating substrate 1 .

[0059] The connection portion 19a is provided along the other longitudinal end side of the upper surface of the insulating substrate 1 and extends in the vertical direction. One end of the connection portion 19a is connected to a portion of the output circuit pattern 4 located on the other longitudinal end side of the upper surface of the insulating substrate 1 .

[0060] The electrode portion 19b is formed in a U-shape when viewed from above, and is arranged above the insulating substrate 1 and in parallel with the insulating substrate 1. The electrode portion 19b extends from the other end of the connecting portion 19a to the opposite side to the direction in which the electrode portion 7c of the low potential terminal 7 and the electrode portion 8c of the high potential terminal 8 protrude. The two front ends of the U-shape in the electrode portion 19b protrude from the other end in the longitudinal direction of the insulating substrate 1, and the main electrode mounting portion 10 is provided at the two front ends of the U-shape in the electrode portion 19b.

[0061] As described above, in the semiconductor device 100A according to the second embodiment, the connection portion 19a of the output terminal 19 is connected to the end portion of the output circuit pattern 4 on the insulating substrate 1 on the opposite side to the direction in which the electrode portions 8c and 7c of the high potential terminal 8 and the low potential terminal 7 protrude.

[0062] Therefore, the length Lb from the connection portion 19 a of the output terminal 19 to the two distal ends of the U-shape of the electrode portion 19 b can be made shorter than that in the first embodiment.

[0063] In addition, the output circuit pattern 4 is provided on the side of the other end in the longitudinal direction of the upper surface of the insulating substrate 1, and the connection portion 19a of the output terminal 19 is connected to this portion. Since the high potential terminal 8 and the low potential terminal 7 are not provided on the side of the other end in the longitudinal direction of the upper surface of the insulating substrate 1, the area of ​​the connection portion between the output terminal 19 and the output circuit pattern 4 can be increased. Thus, the contact resistance of the connection portion between the output terminal 19 and the output circuit pattern 4 can be reduced.

[0064] In addition, each embodiment can be freely combined, or each embodiment can be appropriately modified or omitted.

[0065] Description of the label

[0066] 1 insulating substrate, 2 low potential circuit pattern, 3 high potential circuit pattern, 4 output circuit pattern, 5 circuit pattern, 6 semiconductor chip, 7 low potential terminal, 7a connecting portion, 7b flat portion, 7c electrode portion, 8 high potential terminal, 8a connecting portion, 8b flat portion, 8c electrode portion, 9 output terminal, 9a connecting portion, 9b plate portion, 9c electrode portion, 19 output terminal, 19a connecting portion, 19b electrode portion, 100, 100A semiconductor device.

Claims

1. A semiconductor device comprising: Insulating substrate; a circuit pattern including a circuit pattern on a low potential side provided on the insulating substrate and a circuit pattern on a high potential side provided in a region adjacent to the circuit pattern on the low potential side on the insulating substrate; a plurality of semiconductor chips mounted on the circuit pattern; A low potential terminal, one end of which is connected to the circuit pattern on the low potential side; a high potential terminal having one end connected to the circuit pattern on the high potential side; and output terminal, which is given to the output of the semiconductor chip, The high potential terminal and the low potential terminal have: a middle portion, which constitutes parallel flat plates arranged vertically parallel to each other and extends on the circuit pattern side of the low potential side; and the other end portion, which protrudes from the insulating substrate, The circuit pattern further includes an output-side circuit pattern provided on the insulating substrate on the outer periphery of the low-potential-side circuit pattern and the high-potential-side circuit pattern. The output terminal includes one end connected to a portion of the output-side circuit pattern located on the high-potential-side circuit pattern side and the other end protruding from the insulating substrate.

2. The semiconductor device according to claim 1, wherein The semiconductor chip is formed by integrating a switching element and a freewheeling element into a single chip.

3. The semiconductor device according to claim 1, wherein The one end of the output terminal is connected to a portion of the output-side circuit pattern at an end portion on the insulating substrate on the opposite side to a direction in which the other ends of the high potential terminal and the low potential terminal protrude.

4. The semiconductor device according to claim 1 or 3, wherein: The semiconductor chip is a SiC-MOSFET.

5. The semiconductor device according to any one of claims 1 to 3, wherein: The midway portion of the low potential terminal is arranged below the midway portion of the high potential terminal.

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