Packaging structure of high temperature and high frequency power device with direct chip voltage measurement

Abstract

The application discloses a packaging structure of a high-temperature and high-frequency power device with direct chip voltage measurement, wherein a first semiconductor chip, a third metal signal terminal, a fourth metal signal terminal and a third metal power terminal are located on one side of a metal insulating ceramic conductive plate; a second semiconductor chip, a second metal power terminal, a first metal signal terminal and a second metal signal terminal are located on the other side of the metal insulating ceramic conductive plate. The packaging method has simple structure, extremely low parasitic parameters, thermal resistance and thermal mechanical stress, and has the ability of directly measuring the chip voltage in the package, so that the power device / module adopting the packaging structure can safely and efficiently operate in a high-temperature and high-frequency environment.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology and relates to a packaging structure for a high-temperature, high-frequency power device with direct chip voltage measurement. Background Technology

[0002] Power electronic devices are developing towards higher frequencies, higher operating temperatures, and higher power densities. For example, wide-bandgap power semiconductor technologies, represented by silicon carbide and gallium nitride, have made revolutionary progress compared to traditional silicon-based power semiconductors. However, while power semiconductor technology has developed, corresponding packaging technology has not kept pace. Relatively outdated power semiconductor technologies suffer from drawbacks such as large parasitic packaging parameters, large thermal parameters, inability to operate at high temperatures, and low reliability. These shortcomings severely restrict the application of power semiconductor technology. As the core device of a power conversion system, the technological development level of power electronic devices determines the performance of the power conversion system. Therefore, proposing an advanced power device / module packaging method with low inductance and low thermal resistance is crucial for fully utilizing the excellent characteristics of power semiconductors. The power device / module packaging method proposed in this invention is applicable to all applications involving power conversion, especially in fields requiring devices to operate at high temperatures, such as oil drilling and defense. It can provide underlying technical support for the full electrification, miniaturization, and high-density of related devices or units.

[0003] Currently, the most advanced power semiconductor packaging method is the double-sided heat dissipation packaging structure. Although this method eliminates the bonding wire interconnection method of traditional power devices / modules, improving the module from traditional single-sided heat dissipation to double-sided heat dissipation, the following drawbacks have been found in practical applications:

[0004] 1. When power devices operate at extremely high switching speeds, the parasitic parameters of the package can induce significant voltage changes due to sudden current fluctuations. When measuring the drain-source voltage of traditional power devices / modules, the true chip drain-source voltage cannot be obtained due to the presence of internal package parasitic inductance. The measured drain-source voltage will have a smaller turn-off voltage overshoot, a larger turn-on voltage drop, and a larger loop resonance compared to the actual drain-source voltage of the chip. This leads to incorrect safety margin estimations in the design of corresponding power electronic converters (e.g., resulting in a lower safe operating region) and prevents the power electronic conversion system from obtaining accurate electrical signals during operation (e.g., a large turn-on voltage resonance makes the dead time unpredictable), thereby reducing system robustness and stability.

[0005] 2. Although double-sided heat dissipation packaging structures utilize double-sided heat dissipation, considering the small conduction area of ​​wide-bandgap power semiconductor dies, one side of the double-sided heat dissipation often has a large thermal resistance. Therefore, the improvement in heat dissipation capacity is only 10%-30% of the original capacity, resulting in a very limited double-sided heat dissipation effect. Considering the manufacturing difficulties of double-sided heat dissipation packaging methods, their practical application value is low.

[0006] 3. Double-sided heat dissipation packaging structures can significantly reduce the parasitic inductance of traditional bonded wire power devices / modules. However, for power semiconductors such as gallium nitride operating at higher frequencies, the package inductance is still relatively large, typically above 2nH. Therefore, double-sided heat dissipation packaging methods largely limit the application of power semiconductors in high-frequency applications.

[0007] In summary, in order to further leverage the potential characteristics of power semiconductors and reduce the application limitations imposed by the packaging and integration process in high-frequency and high-temperature applications, it is necessary to propose novel packaging and integration technologies to overcome the shortcomings of existing technologies. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of the prior art and provide a packaging structure for a high-temperature, high-frequency power device with direct chip voltage measurement, which can operate safely and efficiently in high-temperature and high-frequency environments.

[0009] To achieve the above objectives, the packaging structure of the high-temperature, high-frequency power device with direct chip voltage measurement described in this invention includes a first metal power terminal, a second metal power terminal, a third metal power terminal, a first metal signal terminal, a second metal signal terminal, a third metal signal terminal, a fourth metal signal terminal, a first semiconductor chip, a second semiconductor chip, and a metal-insulated ceramic conductive electrode plate.

[0010] The first semiconductor chip, the second metal power terminal, the third metal power terminal, the first metal signal terminal, and the first metal signal terminal are located on one side of the metal-insulated ceramic conductive electrode plate;

[0011] The second semiconductor chip, the first metal power terminal, the third metal signal terminal, and the fourth metal signal terminal are located on the other side of the metal-insulated ceramic conductive electrode plate.

[0012] The first metal power terminal, the second metal power terminal, the first metal signal terminal, and the second metal signal terminal are connected to the second semiconductor chip;

[0013] The first metal power terminal, the third metal power terminal, the third metal signal terminal, and the fourth metal signal terminal are connected to the first semiconductor chip.

[0014] The third metal power terminal is connected to the first semiconductor chip via the first interconnect solder layer.

[0015] The third metal power terminal is connected to the metal-insulated ceramic conductive electrode plate via the second interconnect solder layer and the third interconnect solder layer;

[0016] The first metal power terminal is connected to the first semiconductor chip via the fourth interconnect layer, the first conductive via array on the metal-insulated ceramic conductive electrode plate, and the fifth interconnect layer.

[0017] The second metal power terminal is connected to the second semiconductor chip via the sixth interconnect layer, the second conductive via array on the metal-insulated ceramic conductive electrode plate, and the seventh interconnect layer.

[0018] The first metal power terminal is connected to the second semiconductor chip via the eighth interconnect bonding layer;

[0019] The first metal power terminal is connected to the metal-insulated ceramic conductive electrode plate via the ninth interconnect solder layer.

[0020] The first semiconductor chip and the second semiconductor chip are silicon-based chips, silicon carbide chips, or gallium nitride chips.

[0021] The present invention has the following beneficial effects:

[0022] The high-temperature, high-frequency power device packaging structure with direct chip voltage measurement described in this invention, through adjustments to the distribution of each component, significantly shortens the distances from the first, second, and third metal power terminals to the chip. This makes the packaging parasitic parameters at this distance approximately zero, thus the measured voltage of the power chip surface electrodes is unaffected by packaging parasitic parameters. Therefore, it exhibits higher reliability in online safety testing of power devices, such as short-circuit protection and undersaturation protection. Compared to traditional double-sided heat dissipation packaging structures, the proposed packaging structure has lower junction thermal resistance, resulting in higher heat dissipation capacity. Compared to traditional power devices, it exhibits more uniform thermomechanical stress distribution, a simpler and more reliable structure, and can operate safely and efficiently in high-temperature, high-frequency environments. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of the present invention;

[0024] Figure 2 This is a schematic diagram of the present invention;

[0025] Figure 3 This is a cross-sectional view of the present invention;

[0026] Figure 4 This is a schematic diagram of the direct voltage measurement principle of the present invention;

[0027] Figure 5 This is a diagram showing the installation location of the decoupling capacitors;

[0028] Figure 6 This is a commutation circuit diagram for power devices.

[0029] Wherein, 100 is the first metal power terminal, 101 is the second metal power terminal, 102 is the third metal power terminal, 103 is the first metal signal terminal, 104 is the second metal signal terminal, 105 is the third metal signal terminal, 106 is the fourth metal signal terminal, 107 is the metal insulating ceramic conductive electrode plate, 201 is the first conductive via array, 202 is the fourth interconnect bonding layer, 203 is the second semiconductor chip, 204 is the eighth interconnect bonding layer, 205 is the seventh interconnect bonding layer, 206 is the second conductive via array, 207 is the ninth interconnect bonding layer, 208 is the sixth interconnect bonding layer, 209 is the third interconnect bonding layer, 210 is the first semiconductor chip, 211 is the fifth interconnect bonding layer, 212 is the first interconnect bonding layer, and 213 is the second interconnect bonding layer. Detailed Implementation

[0030] To enable those skilled in the art to better understand the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present invention, not all embodiments, and are not intended to limit the scope of the present invention. Furthermore, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion regarding the concepts disclosed in the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0031] The accompanying drawings show structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not drawn to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0032] refer to Figures 1 to 6The packaging structure of the high-temperature high-frequency power device with direct chip voltage measurement described in this invention includes a first metal power terminal 100, a second metal power terminal 101, a third metal power terminal 102, a first metal signal terminal 103, a second metal signal terminal 104, a third metal signal terminal 105, a fourth metal signal terminal 106, a first semiconductor chip 210, a second semiconductor chip 203, and a metal-insulated ceramic conductive electrode plate 107.

[0033] The first semiconductor chip 210, the second metal power terminal 101, the third metal power terminal 102, the first metal signal terminal 103 and the second metal signal terminal 104 are located on one side of the metal insulated ceramic conductive electrode plate 107.

[0034] The second semiconductor chip 203, the first metal power terminal 100, the third metal signal terminal 105 and the fourth metal signal terminal 106 are located on the other side of the metal insulating ceramic conductive electrode plate 107.

[0035] The first metal power terminal 100, the second metal power terminal 101, the first metal signal terminal 103 and the second metal signal terminal 104 are connected to the second semiconductor chip 203;

[0036] The first metal power terminal 100, the third metal power terminal 102, the third metal signal terminal 105, and the fourth metal signal terminal 106 are connected to the first semiconductor chip 210.

[0037] The third metal power terminal 102 is connected to the first semiconductor chip 210 via the first interconnect solder layer 212;

[0038] The third metal power terminal 102 is connected to the metal insulating ceramic conductive electrode plate 107 via the second interconnect solder layer 213 and the third interconnect solder layer 209.

[0039] The first metal power terminal 100 is connected to the first semiconductor chip 210 via the fourth interconnect layer 202, the first conductive via array 201 on the metal insulating ceramic conductive electrode plate 107, and the fifth interconnect layer 211.

[0040] The second metal power terminal 101 is connected to the second semiconductor chip 203 via the sixth interconnect layer 208, the second conductive via array 206 on the metal insulating ceramic conductive electrode plate 107, and the seventh interconnect layer 205.

[0041] The first metal power terminal 100 is connected to the second semiconductor chip 203 via the eighth interconnect bonding layer 204;

[0042] The first metal power terminal 100 is connected to the metal-insulated ceramic conductive electrode plate 107 via the ninth interconnect solder layer 207.

[0043] The first metal power terminal 100, the second metal power terminal 101, the third metal power terminal 102, the first metal signal terminal 103, the second metal signal terminal 104, the third metal signal terminal 105, and the fourth metal signal terminal 106 are made of copper-molybdenum alloy material, which is used to balance the thermomechanical stress generated by the power device during high-temperature operation. Under other requirements, the metal material used can be conductive materials such as copper and aluminum, and metal plating can be selected.

[0044] The main structure of the metal-insulated ceramic conductive electrode plate 107 is a composite material of metal and ceramic. The metal is a conductive material such as copper or aluminum, and the surface is generally coated with gold, silver, nickel, etc. The ceramic material is generally an insulating material such as alumina, aluminum nitride and silicon nitride, or it can be a resin insulating material such as epoxy board and fiberglass board.

[0045] The present invention facilitates the integration of decoupling capacitors, wherein the decoupling capacitors are connected to the second metal power terminal 101 and the third metal power terminal 102, thereby avoiding the influence of other components of the power electronic conversion system on the power devices.

[0046] In this invention, the first semiconductor chip 210 and the second semiconductor chip 203 can be silicon-based chips, silicon carbide chips, or gallium nitride chips; various chips can be packaged, such as IGBTs, MOSFETs, and diodes; various power electronic converter topologies can be packaged, such as single-switch structures, half-bridge structures, and full-bridge structures. The number of packaged chips can be two or more.

[0047] refer to Figure 6 The power device commutation circuit is composed of straight lines 601, 602 and 603 in the figure. Straight lines 601 and 602 are at the top of the figure, and the dashed line 603 is inside the power device.

[0048] Each interconnect layer is formed by nano-silver sintering, which can effectively simplify the process and improve the operating temperature and yield of power devices.

[0049] This invention has the following characteristics:

[0050] This invention features extremely low package parasitic inductance. It eliminates the metal pad / pillar structure and the structure of two metal-insulating ceramic conductive substrates found in current double-sided power devices. Instead, the first metal power terminal 100, the second metal power terminal 101, and the third metal power terminal 102 are directly connected to the upper and lower surface electrodes of the power chip, significantly reducing the current conduction path of the power device in the vertical z-direction. Figure 1As shown, it is easy to adopt an interleaved arrangement in the horizontal xy direction (referencing patent CN201911360511.3), which greatly reduces the current conduction path inside the power device, and the mutual inductance of multiple current paths cancels each other out, thus greatly reducing the parasitic inductance of the power device package.

[0051] This invention features extremely low thermal resistance in its packaging. It retains only a single metal-insulated ceramic conductive electrode plate 107 and employs a packaging method where metal busbars / terminals are directly connected to the upper and lower surface electrodes of the power chip. This simplifies the packaging structure of traditional single-sided and double-sided power devices, reduces the distance and material types required for heat transfer from the packaged power chip to the outside environment, and thus reduces the thermal resistance in the packaging.

[0052] This invention features the ability to directly measure the second semiconductor chip 203 and the first semiconductor chip 210. This invention makes the distances from the first metal power terminal 100, the second metal power terminal 101, and the third metal power terminal 102 to the chip very short, resulting in packaging parasitic parameters at this distance being approximately zero. Therefore, the measured voltage of the power chip surface electrodes is not affected by packaging parasitic parameters. (Reference) Figure 4 The locations for measuring the drain-source voltage of the chip include 406 and 104, and 405 and 106, and do not contain the package parasitic inductances 401, 402, 403, and 404. Compared with single-sided bonded wire structures and double-sided heat dissipation power devices / modules, this invention can directly obtain the voltage waveform between the chip electrodes, rather than the distorted drain-source voltage waveform affected by parasitic parameters.

Claims

1. A packaging structure for a high-temperature, high-frequency power device with direct chip voltage measurement, characterized in that, It includes a first metal power terminal (100), a second metal power terminal (101), a third metal power terminal (102), a first metal signal terminal (103), a second metal signal terminal (104), a third metal signal terminal (105), a fourth metal signal terminal (106), a first semiconductor chip (210), a second semiconductor chip (203), and a metal-insulated ceramic conductive electrode plate (107). The first semiconductor chip (210), the second metal power terminal (101), the third metal power terminal (102), the first metal signal terminal (103) and the second metal signal terminal (104) are located on one side of the metal-insulated ceramic conductive electrode plate (107); The second semiconductor chip (203), the first metal power terminal (100), the third metal signal terminal (105) and the fourth metal signal terminal (106) are located on the other side of the metal-insulated ceramic conductive electrode plate (107); The first metal power terminal (100), the second metal power terminal (101), the first metal signal terminal (103), and the second metal signal terminal (104) are connected to the second semiconductor chip (203); The first metal power terminal (100), the third metal power terminal (102), the third metal signal terminal (105), and the fourth metal signal terminal (106) are connected to the first semiconductor chip (210); The third metal power terminal (102) is connected to the first semiconductor chip (210) via the first interconnect bonding layer (212); The third metal power terminal (102) is connected to the metal-insulated ceramic conductive electrode plate (107) via the second interconnect solder layer (213) and the third interconnect solder layer (209); The first metal power terminal (100) is connected to the first semiconductor chip (210) via the fourth interconnect bonding layer (202), the first conductive via array (201) on the metal insulating ceramic conductive electrode plate (107) and the fifth interconnect bonding layer (211); The second metal power terminal (101) is connected to the second semiconductor chip (203) via the sixth interconnect bonding layer (208), the second conductive via array (206) on the metal insulating ceramic conductive electrode plate (107), and the seventh interconnect bonding layer (205); The first metal power terminal (100) is connected to the second semiconductor chip (203) via the eighth interconnect bonding layer (204); The first metal power terminal (100) is connected to the metal-insulated ceramic conductive electrode plate (107) via the ninth interconnect solder layer (207).

2. The packaging structure of the high-temperature, high-frequency power device with direct chip voltage measurement according to claim 1, characterized in that, The first semiconductor chip (210) and the second semiconductor chip (203) are silicon-based chips, silicon carbide chips, or gallium nitride chips.

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