Semiconductor device and method for forming the same, electronic device

Abstract

The application discloses a semiconductor device and a forming method thereof and an electronic device, wherein the semiconductor device comprises a substrate, a source layer is formed in the substrate, a plurality of discrete gate structures are formed in the substrate, the bottom of the gate structure is located on the surface of the source layer, a plurality of drains are formed in the substrate on both sides of the top of the gate structure, and each drain is located between two adjacent gates. The application can realize the common source scheme of the corresponding semiconductor device, reduce the size of the semiconductor device, and improve the area utilization of the chip.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor device and its formation method, and an electronic device. Background Technology

[0002] Single-chip dual MOS (field-effect transistor) integration technology is widely used in solutions such as fast charging. Figure 1a The common-drain connection scheme shown is often used in Figure 1b In the fast charging circuit shown, the above common drain connection scheme in the fast charging circuit was tested and found that: (1) When wirelessly charging, the voltage VBUS at the BUS (bus) terminal is the wireless terminal voltage minus the voltage drop of Q2 (the voltage drop is low and is ignored here), and the voltage drop of the drain D1 inside Q1 is VBUS-VFD; (2) When wired charging is inserted (assuming that the voltage VUSB at the USB terminal is greater than the voltage Vwireless at the wireless terminal), when the MOS at the wireless terminal is not turned off or the voltage VBUS is still present, and the MOS at the wired terminal is not turned on, the voltage difference VUSB-VBUS across the NMOS on the left side of Q1, where VBUS is the bus voltage, will flow through a large peak current (depending on the size of the voltage difference), which will impact the MOS body diode and affect the reliability of the system; in addition, the wired and wireless charging ports are not completely isolated, which poses a safety hazard. Summary of the Invention

[0003] In view of this, this application provides a semiconductor device and a method for forming the same, as well as an electronic device, to solve the problem that existing common-drain interconnect schemes affect system reliability and pose safety hazards.

[0004] This application provides a semiconductor device comprising: A substrate in which an active electrode layer is formed; A plurality of discrete gate structures located within the substrate, wherein the bottom of the gate structures is located on the surface of the source layer; Multiple drains are located in the substrate on both sides of the top of the gate structure, with each drain located between two adjacent gates.

[0005] Optionally, the semiconductor device further includes a source connection structure electrically connected to the source layer.

[0006] Optionally, the plurality of gate structures include a plurality of first gate structures and a plurality of second gate structures, wherein the drain located between adjacent first gate structures is a first drain, and the drain located between adjacent second gate structures is a second drain. The semiconductor device further includes: a first drain connection structure interconnected with the first drain; and a second drain connection structure interconnected with the second drain.

[0007] Optionally, the semiconductor device further includes: a dielectric layer located on the surface of the substrate; The source connection structure includes: a first conductive plug located within the dielectric layer and a source connection region located on the surface of the dielectric layer; The first drain connection structure includes: a second conductive plug located within the dielectric layer and a first drain connection region located on the surface of the dielectric layer, wherein the second conductive plug is connected between the first drain connection region and each corresponding first drain electrode; the second drain connection structure includes: a third conductive plug located within the dielectric layer and a second drain connection region located on the surface of the dielectric layer, wherein the third conductive plug is connected between the second drain connection region and each corresponding second drain electrode.

[0008] Optionally, the semiconductor device further includes a source connection portion located between the first gate structure and the second gate structure, wherein the first conductive plug connects the source connection portion and the source connection region.

[0009] Optionally, the semiconductor device further includes: a passivation layer covering the dielectric layer, the first drain connection region, the second drain connection region and the source connection region, the passivation layer having a first opening that exposes the interconnection portions of the first drain connection region, the second drain connection region and the source connection region.

[0010] Optionally, the source connection structure is disposed on the back side of the substrate.

[0011] Optionally, the gate structure includes a gate and a gate dielectric layer located between the gate and the substrate.

[0012] Optionally, the gate includes a first partial gate at the top and a second partial gate at the bottom; the first partial gate and the second partial gate are interconnected.

[0013] Optionally, the substrate further includes a doped layer; the gate structure and the drain are formed within the doped layer.

[0014] This application also provides a method for forming a semiconductor device, comprising: A substrate is provided, the substrate comprising a source layer and a doped layer located on the surface of the source layer; Multiple gates are formed within the doped layer, and a drain is formed between each pair of adjacent gates.

[0015] Optionally, the plurality of gate structures include a plurality of first gate structures and a plurality of second gate structures, wherein the drain located between adjacent first gate structures is a first drain, and the drain located between adjacent second gate structures is a second drain.

[0016] Optionally, the forming method further includes: Within the doped layer, a source connection portion is formed that connects to the source layer, and the source connection portion is located between the first gate structure and the second gate structure.

[0017] Optionally, the method for forming the source connection includes: A hole is drilled between the first gate structure and the second gate structure to form a first via exposing the source layer; The source electrode material is filled into the first through hole to obtain the source electrode connection portion.

[0018] Optionally, the forming method further includes: After the drain is formed, a source connection structure connecting the source connection portion is formed, and a first drain connection structure connecting each first drain and a second drain connection structure connecting each first drain are formed.

[0019] Optionally, the method for forming the source connection structure, the first drain connection structure, and the second drain connection structure includes: A dielectric layer is formed on the surface of the doped layer; The dielectric layer is etched to form the source connection portion, the second vias corresponding to each of the first drains and the second drains, and conductive material is filled into each of the second vias to form the first conductive plug corresponding to the source connection portion, the second conductive plug corresponding to each of the first drains and the third conductive plug corresponding to each of the second drains. A conductive layer is formed on the surface of the dielectric layer, and the conductive layer is patterned to form a source connection region connecting the first conductive plug, a first drain connection region connecting each of the second conductive plugs, and a second drain connection region connecting each of the third conductive plugs.

[0020] Optionally, the forming method further includes: A passivation layer is formed covering the dielectric layer, the first drain connection region, the second drain connection region, and the source connection region; the passivation layer has a first opening that exposes the interconnection portions of the first drain connection region, the second drain connection region, and the source connection region.

[0021] Optionally, the method for forming the substrate includes: A substrate is provided, and the interior of the substrate is doped to form the source layer and a doped layer located on the surface of the source layer; Alternatively, a substrate is provided, the surface of the substrate is doped to form a source layer on the surface of the substrate, and a doped layer is epitaxially formed on the surface of the source layer.

[0022] Optionally, the forming method further includes: The back side of the substrate is etched to form a first opening that exposes a portion of the back side of the source layer. A source connection structure is formed within the first opening.

[0023] Optionally, the method of forming a plurality of gates within the doped layer further includes: The doped layer is etched to form multiple trenches, an oxide layer is formed on the sidewalls of each trench, and semiconductor material is filled into each trench to form a gate. The surface of the doped layer is used as a stop layer for planarization.

[0024] Optionally, the method of etching the doped layer to form a plurality of trenches, forming an oxide layer on the sidewalls of each trench, and filling each trench with semiconductor material to form a gate further includes: The doped layer is etched to form the main body of the trench; A first sub-oxide layer is formed on the sidewall of the main body; The protrusion of the trench is formed by etching from the bottom of the main body toward the substrate, and the main body and the protrusion constitute the trench. A second sub-oxide layer is formed on the sidewall of the trench, and the first sub-oxide layer and the second sub-oxide layer constitute the oxide layer; Semiconductor material is filled into the trench to form a gate.

[0025] Optionally, the method of filling the trench with semiconductor material to form a gate further includes: A first semiconductor material is filled into the trench, and the first semiconductor material above the protrusion is removed to form a first partial gate located within the protrusion; An interconnect structure is formed on the first portion of the gate surface; A second semiconductor material is filled into the surface of the interconnect structure to form a second partial gate located within the main body.

[0026] This application also provides an electronic device, including any of the above-described semiconductor devices and a controller; the controller is used to control the semiconductor device to be turned on or off.

[0027] The semiconductor device, its formation method, and electronic device described in this application employ a single source structure to access the source signal, enabling a common-source scheme for the corresponding semiconductor device. This blocks the reverse-current path of the body diode, preventing reverse current and improving the reliability of the semiconductor device during operation, thereby enhancing the reliability of the corresponding electronic device. Furthermore, by placing the source layer at the bottom of the gate structure and providing a drain between two adjacent gates, the size of the formed semiconductor device can be reduced, increasing the area utilization of the chip and thus improving the cell integration density, resulting in superior on-resistance performance. In addition, the aforementioned semiconductor device is not constrained by packaging process rules, further improving the area utilization of the corresponding chip. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1a , Figure 1b and Figure 1c This is a schematic diagram of the connections of relevant semiconductor devices in a traditional solution; Figure 2 This is a schematic diagram of a semiconductor device structure according to an embodiment of this application; Figure 3 This is a schematic diagram of a semiconductor device structure according to another embodiment of this application; Figure 4 This is a schematic diagram of a semiconductor device structure according to another embodiment of this application; Figure 5 This is a schematic diagram of a semiconductor device structure according to another embodiment of this application; Figure 6 This is a schematic diagram of a semiconductor device structure according to another embodiment of this application; Figure 7 This is a schematic diagram of the gate structure according to an embodiment of this application; Figure 8 This is a schematic flowchart of a method for forming a semiconductor device according to an embodiment of this application; Figure 9a and Figure 9b This is a schematic diagram of the structure obtained in each step of an embodiment of this application; Figure 10 This is a schematic diagram of a semiconductor device structure according to another embodiment of this application; Figure 11a , Figure 11b , Figure 11c and Figure 11dThis is a schematic diagram of a semiconductor structure in another embodiment of this application; Figure 12 This is a schematic diagram of a semiconductor device structure according to another embodiment of this application; Figure 13a and Figure 13b This is a schematic diagram of the structure obtained in each step of another embodiment of this application; Figure 14a , Figure 14b and Figure 14c This is a schematic diagram of the structure obtained in each step of another embodiment of this application; Figure 15a , Figure 15b , Figure 15c , Figure 15d and Figure 15e This is a schematic diagram of the structure obtained in each step of another embodiment of this application; Figure 16a , Figure 16b and Figure 16c This is a schematic diagram of the structure obtained by each step in another embodiment of this application. Detailed Implementation

[0030] The inventor targeted Figure 1b The fast charging circuit shown in the figure has issues such as affecting system reliability and posing safety hazards. Research has found that if such a common-drain connection scheme is adopted... Figure 1c The common-source interconnect scheme shown can block the reverse current path of the body diode, preventing reverse current flow and ensuring safety performance to a certain extent. However, the chips corresponding to the common-source interconnect scheme are often relatively large in size, resulting in low chip area utilization.

[0031] To address the aforementioned issues, the semiconductor device and its formation method, as well as the electronic device provided in this application, employ a source layer to implement a common-source scheme. This can block the reverse current path of the body diode and prevent reverse current. By placing the source layer at the bottom of the gate structure, the space occupied by the source structure can be minimized, thereby reducing the volume of the corresponding semiconductor device and improving the area utilization of the corresponding chip. This enhances the performance of fast charging circuits and / or electronic devices using the semiconductor device.

[0032] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0033] The first aspect of this application provides a semiconductor device, with reference to... Figure 2 As shown, the semiconductor device includes: A substrate, wherein an active electrode layer 123 is formed therein; A plurality of discrete gate structures 124 are located within the substrate, with the bottom of the gate structures 124 located on the surface of the source layer 123; A plurality of drains 126 are located in the substrate on both sides of the top of the gate structure 124, and each drain 126 is located between two adjacent gates 124.

[0034] The aforementioned semiconductor device employs a common-source scheme with a source layer 123, which can block the reverse current path of the body diode and prevent reverse current. By placing the source layer 123 at the bottom of the gate structure 124, the source layer 123 occupies as little space as possible between and / or on both sides of the gate structure 124, thereby saving space and reducing the size of the semiconductor device. The source layer 123, gate structure 124, and drain 126 are all disposed within the semiconductor device, which can improve the chip area utilization and MOS cell integration, resulting in better on-resistance performance. In one embodiment, reference Figure 3 and Figure 4 As shown, the semiconductor device further includes a source connection structure 140a electrically connected to the source layer 123.

[0035] Specifically, the plurality of gate structures 124 include a plurality of first gate structures and a plurality of second gate structures, the drain located between adjacent first gate structures is the first drain, and the drain located between adjacent second gate structures is the second drain. The semiconductor device further includes: a first drain connection structure 140b interconnected with the first drain; and a second drain connection structure 140c interconnected with the second drain.

[0036] Optionally, the first drain connection structure 140b and the second drain connection structure 140c are located on both sides of the source connection structure 140a, respectively.

[0037] In one example, the semiconductor device further includes a dielectric layer 130 located on the surface of the substrate; The source connection structure 140a includes: a first conductive plug 131 located within the dielectric layer 130 and a source connection region 141 located on the surface of the dielectric layer 130; The first drain connection structure 140b includes: a second conductive plug 132 located within the dielectric layer 130 and a first drain connection region 142 located on the surface of the dielectric layer 130, wherein the second conductive plug 132 is connected between the first drain connection region 142 and each corresponding first drain electrode; the second drain connection structure 140c includes: a third conductive plug 133 located within the dielectric layer 130 and a second drain connection region 143 located on the surface of the dielectric layer 130, wherein the third conductive plug 133 is connected between the second drain connection region 143 and each corresponding second drain electrode.

[0038] Accordingly, the first conductive plug 131 has a dielectric region 134 between the second conductive plug 132 and the third conductive plug 133, and there is a dielectric region 134 between two adjacent second conductive plugs 132 and two adjacent third conductive plugs 133.

[0039] Furthermore, the semiconductor device further includes a source connection portion 127 located between the first gate structure and the second gate structure, wherein the first conductive plug 131 connects the source connection portion 127 and the source connection region 141 to provide the source connection portion 127 with the required electrical signal.

[0040] In one example, such as Figure 4 As shown, the semiconductor device further includes a passivation layer 145. The passivation layer 145 covers the dielectric layer 130, the first drain connection region 141, the second drain connection region 142, and the source connection region 143. The passivation layer has a first opening that exposes the interconnection portions of the first drain connection region, the second drain connection region, and the source connection region, respectively. This allows the exposed interconnection portions to connect to other circuits and / or related structures, and covers the gaps and partial surfaces between the source connection region 141 and each drain connection region to protect the source connection region 141 and each drain connection region, reducing losses in each connection region. Optionally, the source connection region 141 and / or each drain connection region exposes at least one interconnection portion, for example... Figure 4 As shown, the source connection region 141 exposes only one interconnection site, while the first drain connection region 142 and the second drain connection region 143 expose two interconnection sites respectively.

[0041] In one embodiment, the aforementioned source connection structure may be disposed on the back side of the substrate to eliminate the source connection portion between the first gate structure and the second gate structure, thereby saving the space occupied by the source connection portion, reducing the gap between the first gate structure and the second gate structure, and further reducing the size of the semiconductor device.

[0042] Specifically, refer to Figure 5As shown, the above-mentioned substrate also includes a substrate 111, which is located on the back side 123 of the source layer to protect and support the source layer 123 and other structures.

[0043] Optionally, the source connection structure includes a first conductive plug 131 and a source connection region 141. For example... Figure 6 As shown, the source interconnect region 141 is disposed on the back side of the substrate 111 to provide a source interconnect terminal on the back side of the substrate 111. Figure 6 As shown, the source connection region 141 can be disposed inside the substrate 111, with its surface aligned with the bottom surface of the substrate 111 and exposed by the bottom surface of the substrate 111. Correspondingly, the first conductive plug 131 can be disposed inside the substrate 111 to realize the interconnection between the source 123 and the source connection region 141.

[0044] In one embodiment, the gate structure 124 includes a gate and a gate dielectric layer located between the gate and the substrate to isolate the gate and the substrate. Specifically, the gate is made of a semiconductor material, such as polycrystalline silicon and / or monocrystalline silicon, etc.

[0045] Specifically, such as Figure 7 As shown, the gate includes a first partial gate 124b located at the top and a second partial gate 124a located at the bottom; the first partial gate 124b and the second partial gate 124a are interconnected.

[0046] In one embodiment, the substrate further includes a doped layer; the gate structure and the drain are formed within the doped layer. Accordingly, as Figures 4 to 6 As shown, there is a doped region 125 between the source 123 and the drain 126, and the two adjacent gate structures 124 also have a doped region 125.

[0047] Specifically, both the source layer 123 and the drain layer 126 are doped with first-type ions; the doped layer is doped with second-type ions. Optionally, the doped region 125 is a lightly doped region corresponding to the second type. Optionally, the source layer 123 is a heavily doped region corresponding to the first-type ions to reduce resistivity. The drain layer 126 can be doped with first-type ions to varying degrees, such as the lower layer of the drain layer 126 being a lightly doped region corresponding to the first-type ions, and the upper layer being a heavily doped region corresponding to the first-type ions, etc.

[0048] The first type differs from the second type to ensure the operational performance of the formed semiconductor device. Specifically, when the first type is N-type (e.g., arsenic, germanium ions), the first type is P-type (e.g., boron, boron fluoride, phosphorus ions); or, when the first type is P-type, the first type is N-type.

[0049] In one embodiment, the materials of the first conductive plug 131, the second conductive plug 132, and / or the third conductive plug 133 include at least one of aluminum, copper, and tungsten to have good electrical conductivity.

[0050] The above-mentioned semiconductor devices, through the source connection structure 140a, provide a source signal to the corresponding semiconductor devices, enabling a common-source scheme and improving the reliability of the semiconductor devices during operation. Furthermore, by placing the source layer 123 at the bottom of the gate structure 124, the source layer 123 occupies as little space as possible between and / or on both sides of the gate structure 124, achieving space saving, thereby reducing the size of the semiconductor devices, increasing the area utilization of the chip, and thus improving the corresponding cell integration density, resulting in better on-resistance performance. In addition, the above-mentioned semiconductor devices are not constrained by packaging process rules, further improving the area utilization of the corresponding chip.

[0051] This application provides a method for forming a semiconductor device in a second aspect, referring to... Figure 8 As shown, the forming method includes S210 and S220. S210 provides a substrate, such as Figure 9a As shown, the substrate includes a source layer 323 and a doped layer 321 located on the surface of the source layer 323; S210, such as Figure 9b As shown, a plurality of gate electrodes 324 are formed in the doped layer 321, and a drain electrode 326 is formed between each pair of adjacent gate electrodes 324. Specifically, the drain electrode 326 is located on the top side of the corresponding gate electrode 324, and a doped region 325 is formed between the drain electrode 326 and the source layer 323, and a doped region 325 is also formed between each pair of adjacent gate electrodes 324.

[0052] In one embodiment, the plurality of gate structures includes a plurality of first gate structures and a plurality of second gate structures, wherein the drain located between adjacent first gate structures is a first drain, and the drain located between adjacent second gate structures is a second drain.

[0053] Furthermore, such as Figure 10 As shown, the forming method further includes: Within the doped layer 321, a source connection portion 327 is formed to connect the source layer 323, and the source connection portion 327 is located between the first gate structure and the second gate structure.

[0054] Specifically, the method for forming the source connection portion includes: drilling a hole between the first gate structure and the second gate structure to form a first through hole exposing the source layer 323; filling the first through hole with source material to obtain the source connection portion 327.

[0055] In one example, the forming method further includes: After the drain 326 is formed, a source connection structure is formed to connect the source connection portion 327 to allow electrical signals to be connected to the source. A first drain connection structure and a second drain connection structure are formed to connect the first drains to the two drains to allow electrical signals to be connected to the two drains.

[0056] Specifically, the method for forming the source connection structure, the first drain connection structure, and the second drain connection structure includes: like Figure 11a As shown, a dielectric layer 330 is formed on the surface of the doped layer 321; The dielectric layer 330 is etched to form second vias corresponding to the source connection portion, each first drain, and each second drain, respectively. Conductive material is then filled into each second via, such as... Figure 11b As shown, a first conductive plug 331 corresponding to the source connection portion, a second conductive plug 332 corresponding to each of the first drains, and a third conductive plug 333 corresponding to each of the second drains are formed; a dielectric region 334 is provided between each conductive plug; like Figure 11c As shown, a conductive layer 340 is formed on the surface of the dielectric layer 330, and the conductive layer 340 is patterned, as shown below. Figure 11d As shown, a source connection region 341 is formed connecting the first conductive plug 331, a first drain connection region 342 is formed connecting each of the second conductive plugs 332, and a second drain connection region 343 is formed connecting each of the third conductive plugs 333.

[0057] In one embodiment, the forming method further includes: forming a passivation layer 345 covering the dielectric layer 330, the first drain connection region 342, the second drain connection region 343, and the source connection region 341; as Figure 12 As shown, the passivation layer 345 has a plurality of first openings, the first openings exposing the interconnection portions of the first drain connection region 341, the second drain connection region 343 and the source connection region 341.

[0058] Specifically, in this embodiment, passivation material layers covering the source connection region 341, each drain connection region, and the dielectric region 333 can be formed through processes such as deposition. Then, the passivation material layers are etched to expose the interconnection sites of the source connection region 341 and each drain connection region, forming a passivation layer 345. Optionally, at least one interconnection site is exposed in each of the aforementioned source connection region 341 and / or each drain connection region, for example... Figure 10As shown, the source connection region 341 exposes only one interconnection site, while the first drain connection region 342 and the second drain connection region 343 expose two interconnection sites respectively.

[0059] In one embodiment, the method for forming the substrate includes: A substrate is provided, and the interior of the substrate is doped to form the source layer 323 and the doped layer 321 located on the surface of the source layer 323; Or, refer to Figure 13a As shown, a substrate 311 is provided, and the surface of the substrate 311 is doped to form a source layer 323 on the surface of the substrate 311. A doped layer 321 is epitaxially formed on the surface of the source layer 323.

[0060] Optionally, the forming method further includes: The back side of the substrate 131 is etched to form a first opening that exposes a portion of the back side of the source layer 323. A source connection structure is formed within the first opening, such as... Figure 13b As shown, the source connection structure includes a first conductive plug 331 and a source connection region 341. The source connection region 341 can be disposed inside the substrate 311, with its surface aligned with the bottom surface of the substrate 311 and exposed by the bottom surface of the substrate 311. Correspondingly, the first conductive plug 331 can be disposed inside the substrate 311 to realize the interconnection between the source 323 and the source connection region 341.

[0061] In one embodiment, both the source layer 323 and the drain 326 are doped with a first type of ion; the doped layer 321 is doped with a second type of ion. Optionally, the source 123 is a heavily doped region corresponding to the first type of ions to reduce resistivity. The drain 326 can be doped with the first type of ions to varying degrees, such as the lower layer of the drain 326 being a lightly doped region corresponding to the first type of ions, and the upper layer being a heavily doped region corresponding to the first type of ions, etc.

[0062] The first type differs from the second type to ensure the operational performance of the formed semiconductor device. Specifically, when the first type is N-type (e.g., arsenic, germanium ions), the first type is P-type (e.g., boron, boron fluoride, phosphorus ions); or, when the first type is P-type, the first type is N-type.

[0063] In one embodiment, the method of forming a plurality of gates 324 within the doped layer 321 further includes: The doped layer 321 is etched to form a plurality of trenches 322, which can be as follows: Figure 14a As shown, Figure 14b As shown, an oxide layer 328 is formed on the sidewall of each of the trenches 322, such as Figure 14cAs shown, semiconductor material is filled into each of the trenches 322 to form a gate 324; The surface of the doped layer 321 is used as a stop layer for planarization.

[0064] Specifically, the method of etching the doped layer 321 to form a plurality of trenches 322, forming an oxide layer 328 on the sidewalls of each trench 322, and filling each trench 322 with semiconductor material to form a gate 324 further includes: like Figure 15a As shown, the doped layer 321 is etched to form the main body 322a of the trench 322; like Figure 15b As shown, a first sub-oxide layer 328a is formed on the sidewall of the main body portion 332a; like Figure 15c As shown, the protrusion 322b of the trench 322 is formed by etching from the bottom of the main body portion 322a toward the substrate 311, and the main body portion 322a and the protrusion 322b constitute the trench 322; like Figure 15d As shown, a second sub-oxide layer 328b is formed on the sidewall of the trench 322, and the first sub-oxide layer 328a and the second sub-oxide layer 328b constitute the oxide layer 328; like Figure 15e As shown, a semiconductor material is filled in the trench 322 to form a gate 324.

[0065] Optionally, the method of filling the trench 322 with semiconductor material to form the gate 324 further includes: like Figure 16a As shown, a first semiconductor material is filled in the trench 322, and the first semiconductor material above the protrusion 322b is removed to form a first partial gate 324a located in the protrusion 322b; like Figure 16b As shown, an interconnect structure 324c is formed on the surface of the first portion of the gate 324a; like Figure 16c As shown, a second semiconductor material is filled on the surface of the interconnect structure 324c to form a second partial gate 324b located within the main body portion 322a.

[0066] The semiconductor device forming methods provided in the above embodiments can form the semiconductor device provided in any of the above embodiments, which has all the beneficial effects of the above semiconductor devices, and will not be repeated here.

[0067] A third aspect of this application provides an electronic device including the semiconductor device and controller described in any of the above embodiments; the controller is used to control the semiconductor device to be turned on or off. The electronic device may include battery-powered terminal devices such as mobile phones and / or tablet computers. Specifically, the semiconductor device may be housed within the electronic device in electrical signal control circuits such as charging control, discharging control, overvoltage protection, and / or overcurrent protection to improve the reliability of the electrical signal control process and thereby enhance the reliability of the corresponding electronic device.

[0068] The fourth aspect of this application provides a fast charging circuit, including the semiconductor device and controller described in any of the above embodiments, wherein the semiconductor device adopts a common source scheme, which can block the reverse current path of the diode in the body, prevent reverse current, and has high reliability, thereby improving the reliability of the fast charging circuit.

[0069] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.

[0070] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0071] Furthermore, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0072] The above description has been provided to enable any person skilled in the art to implement and use this application. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: A substrate in which an active electrode layer is formed; A plurality of discrete gate structures located within the substrate, wherein the bottom of the gate structures is located on the surface of the source layer; Multiple drains are located in the substrate on both sides of the top of the gate structure, and each drain is located between two adjacent gates; The plurality of gate structures include a plurality of first gate structures and a plurality of second gate structures, wherein the drain located between adjacent first gate structures is a first drain, and the drain located between adjacent second gate structures is a second drain; the semiconductor device further includes: a first drain connection structure interconnected with the first drain; and a second drain connection structure interconnected with the second drain. The semiconductor device further includes: a dielectric layer located on the surface of the substrate, and a source connection structure electrically connected to the source layer; the source connection structure includes: a first conductive plug located within the dielectric layer and a source connection region located on the surface of the dielectric layer; the first drain connection structure includes: a second conductive plug located within the dielectric layer and a first drain connection region located on the surface of the dielectric layer, the second conductive plug being connected between the first drain connection region and each corresponding first drain; the second drain connection structure includes: a third conductive plug located within the dielectric layer and a second drain connection region located on the surface of the dielectric layer, the third conductive plug being connected between the second drain connection region and each corresponding second drain; The semiconductor device uses a source connection structure to access the source signal in order to achieve a common source scheme.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a source connection portion located between the first gate structure and the second gate structure, wherein the first conductive plug connects the source connection portion and the source connection region.

3. The semiconductor device according to claim 1 or 2, characterized in that, The semiconductor device further includes a passivation layer covering the dielectric layer, the first drain connection region, the second drain connection region, and the source connection region, the passivation layer having a first opening that exposes the interconnection portions of the first drain connection region, the second drain connection region, and the source connection region.

4. The semiconductor device according to claim 1, characterized in that, The gate structure includes a gate and a gate dielectric layer located between the gate and the substrate.

5. The semiconductor device according to claim 4, characterized in that, The gate includes a first portion gate located at the top and a second portion gate located at the bottom; the first portion gate and the second portion gate are interconnected.

6. The semiconductor device according to claim 1, characterized in that, The substrate further includes a doped layer; the gate structure and the drain are formed within the doped layer.

7. A method for forming a semiconductor device, characterized in that, The forming method is used to form the semiconductor device according to any one of claims 1 to 6, comprising: A substrate is provided, the substrate comprising a source layer and a doped layer located on the surface of the source layer; Multiple gates are formed within the doped layer, and a drain is formed between each pair of adjacent gates; After the drain is formed, a source connection structure connecting the source connection portion is formed, and a first drain connection structure for each first drain and a second drain connection structure connecting each first drain are formed. The method for forming the source connection structure, the first drain connection structure, and the second drain connection structure includes: A dielectric layer is formed on the surface of the doped layer; The dielectric layer is etched to form the source connection portion, the second vias corresponding to each of the first drains and the second drains, and conductive material is filled into each of the second vias to form the first conductive plug corresponding to the source connection portion, the second conductive plug corresponding to each of the first drains and the third conductive plug corresponding to each of the second drains. A conductive layer is formed on the surface of the dielectric layer, and the conductive layer is patterned to form a source connection region connecting the first conductive plug, a first drain connection region connecting each of the second conductive plugs, and a second drain connection region connecting each of the third conductive plugs.

8. The method for forming a semiconductor device according to claim 7, characterized in that, The plurality of gate structures include a plurality of first gate structures and a plurality of second gate structures, wherein the drain located between adjacent first gate structures is a first drain, and the drain located between adjacent second gate structures is a second drain.

9. The method for forming a semiconductor device according to claim 8, characterized in that, The forming method further includes: Within the doped layer, a source connection portion is formed that connects to the source layer, and the source connection portion is located between the first gate structure and the second gate structure.

10. The method for forming a semiconductor device according to claim 9, characterized in that, The method for forming the source connection portion includes: A hole is drilled between the first gate structure and the second gate structure to form a first via exposing the source layer; The source electrode material is filled into the first through hole to obtain the source electrode connection portion.

11. The method for forming a semiconductor device according to claim 7, further comprising: A passivation layer is formed covering the dielectric layer, the first drain connection region, the second drain connection region, and the source connection region; The passivation layer has a first opening that exposes the interconnection between the first drain connection region, the second drain connection region, and the source connection region.

12. The method for forming a semiconductor device according to claim 9, characterized in that, The method for forming the substrate includes: A substrate is provided, and the interior of the substrate is doped to form the source layer and a doped layer located on the surface of the source layer; Alternatively, a substrate is provided, the surface of the substrate is doped to form a source layer on the surface of the substrate, and a doped layer is epitaxially formed on the surface of the source layer.

13. The method for forming a semiconductor device according to claim 12, characterized in that, The forming method further includes: The back side of the substrate is etched to form a first opening that exposes a portion of the back side of the source layer. A source connection structure is formed within the first opening.

14. The method for forming a semiconductor device according to claim 7, characterized in that, The method of forming a plurality of gates within the doped layer further includes: The doped layer is etched to form multiple trenches, an oxide layer is formed on the sidewalls of each trench, and semiconductor material is filled into each trench to form a gate. The surface of the doped layer is used as a stop layer for planarization.

15. The method for forming a semiconductor device according to claim 14, characterized in that, The method of etching the doped layer to form a plurality of trenches, forming an oxide layer on the sidewalls of each trench, and filling each trench with semiconductor material to form a gate further includes: The doped layer is etched to form the main body of the trench; A first sub-oxide layer is formed on the sidewall of the main body; The protrusion of the trench is formed by etching from the bottom of the main body toward the substrate, and the main body and the protrusion constitute the trench. A second sub-oxide layer is formed on the sidewall of the trench, and the first sub-oxide layer and the second sub-oxide layer constitute the oxide layer; Semiconductor material is filled into the trench to form a gate.

16. The method for forming a semiconductor device according to claim 15, characterized in that, The method of filling the trench with semiconductor material to form a gate further includes: A first semiconductor material is filled into the trench, and the first semiconductor material above the protrusion is removed to form a first partial gate located within the protrusion; An interconnect structure is formed on the first portion of the gate surface; A second semiconductor material is filled into the surface of the interconnect structure to form a second partial gate located within the main body.

17. An electronic device, characterized in that, Includes a semiconductor device and a controller as described in any one of claims 1 to 6; the controller is used to control the semiconductor device to be turned on or off.

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