An interface phase change memory material, a phase change memory, and a method for its fabrication.

Abstract

This invention relates to an interface phase change memory material, a phase change memory (PDM), and a method for fabricating the same. The phase change memory material comprises a van der Waals buffer layer and a superlattice PDM layer composed of alternating layers of transition metal and PDM material. The PDM comprises a bottom electrode layer, an interface PDM material, and a top electrode layer. This invention improves the storage performance of the material by embedding atomically thin transition metal interface materials into the PDM material. The PDM exhibits fast, low-power erase / write characteristics, stable multi-level resistance states, and good fatigue characteristics, and is expected to be applied in neuromorphic devices and high-density memory applications.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, and specifically relates to an interface phase change memory material, a phase change memory, and a method for preparing the same. Background Technology

[0002] With the advent of the big data era and the rapid rise of artificial intelligence, cloud computing, and 5G technologies, the output of information data has accelerated, leading to an explosive growth in data. People's demands for the storage and processing capabilities of massive amounts of data are constantly increasing. Phase-change memory (PDM), as a novel non-volatile storage technology, possesses advantages such as large data capacity, fast read / write speeds, low power consumption, and good miniaturization, and is expected to fill the performance gap between dynamic random access memory (DRAM) and flash memory architectures, becoming the next generation of information storage technology.

[0003] Phase-change memory (PCM) using chalcogenides as the core storage medium stores data through the change in resistance between the phase-change storage medium. Chalcogenide storage media exist in both crystalline and amorphous states, exhibiting significant differences in resistance due to variations in atomic arrangement. The crystalline state exhibits low resistance and high reflectivity, while the amorphous state exhibits high resistance and low reflectivity. Ge₂Sb₂Te₅ (GST) is the most researched, technologically mature, and widely used PCM material. However, its development is limited by several drawbacks: slow conversion speed, high power consumption, and large resistance drift coefficient, making it difficult to apply in low-power and high-density storage applications. GST alone can no longer meet the development needs of PCM, leading to the search for new PCM materials to replace GST.

[0004] Common phase change materials include Ge-Sb-Te systems, Sb-Te binary systems, and Ge-Te systems. Researchers typically seek suitable elements to incorporate into these phase change material systems. However, doping methods face a series of challenges in terms of process reliability, uniformity of element doping at the nanoscale, and phase separation after multiple cycles. Therefore, in recent years, more attention has been paid to interface phase change memories based on Sb2Te3-GeTe superlattice materials, which offer faster conversion speeds and lower power consumption. However, studies have shown that the stability of this superlattice structure is heavily dependent on the GeTe crystalline material. The GeTe material layer is sensitive to structural deformation and has poor stability. Ge atoms often undergo significant interlayer atomic diffusion under thermal effects, causing local atomic imbalances in the material and leading to device failure (Janne Kalikka et al. Nature Communications 10.1038 / ncomms11983). In addition, the multilayer phase change materials proposed in the published patents have relatively complex preparation processes. The formation of the thin film requires multiple growth methods such as chemical vapor deposition and physical vapor deposition, which will greatly increase the manufacturing cost (Patent: Superlattice phase change thin film with two-dimensional material improvement, phase change memory and preparation method, CN110556476A). Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an interface phase change memory material, a phase change memory and a method for preparing the same, so as to overcome the defects of high power consumption and large resistance drift coefficient of the existing phase change memory material.

[0006] The present invention provides an interface phase change memory material, characterized in that it comprises a van der Waals structure buffer layer and a superlattice phase change memory layer composed of alternating stacks of transition metal layers and phase change material layers, wherein the superlattice phase change memory layer is located on the van der Waals structure buffer layer.

[0007] Preferably, the van der Waals buffer layer has a thickness of 5-10 nm and is made of a two-dimensional chalcogenide compound with van der Waals and hexagonal structures. This type of material has an out-of-plane height (0 0L) structural orientation perpendicular to the substrate.

[0008] Preferably, the two-dimensional chalcogenide compound includes one or more of Sb2Te3 and Bi2Te3.

[0009] Preferably, the thickness of the superlattice phase change storage layer is 40–100 nm.

[0010] Preferably, the thickness of the transition metal layer is 0.5–2 nm, and the material is a transition metal element.

[0011] Preferably, the transition metal element includes one or more of Ti, Mo, W, Zr, Hf, V, Nb, Pt, and Ta.

[0012] Preferably, the phase change material layer has a thickness of 3–10 nm and is a sulfide compound.

[0013] Preferably, the chalcogenide material includes one or more of Sb2Te3, Sb2Te, and Bi2Te3.

[0014] Preferably, the superlattice phase change storage layer is used to provide a growable out-of-plane height (00L) structural orientation for the interface phase change storage material.

[0015] Preferably, the interface phase change storage material has an out-of-plane height (0 0 L) structural orientation.

[0016] Preferably, the interface phase change storage material exists in the form of a thin film.

[0017] This invention also provides a method for preparing an interface phase change memory material, comprising:

[0018] A substrate is provided, a van der Waals buffer layer is grown on the substrate, and a transition metal layer and a phase change material layer are alternately grown on the van der Waals buffer layer to obtain an interface phase change storage material.

[0019] Preferably, the substrate comprises one or more of single-crystal silicon, silicon carbide, gallium nitride, polyimide, polyethylene terephthalate, and sapphire substrate.

[0020] Preferably, the growth method includes: atomic layer deposition, chemical vapor deposition, magnetron sputtering, pulsed laser deposition, or molecular beam epitaxy.

[0021] Preferably, the alternating growth of the transition metal layer and the phase change material layer is performed by magnetron sputtering. The process parameters for magnetron sputtering are: alternating sputtering of corresponding targets in an argon atmosphere, with a target purity greater than 99.99% and a background vacuum degree less than 2 × 10⁻⁶. -5 Pa, sputtering chamber temperature is 200-350℃, argon flow rate is 10-50 sccm, sputtering pressure is 0.1-0.6 Pa.

[0022] Preferably, the transition metal layer and the phase change material layer are alternately grown for 5 to 20 cycles.

[0023] The present invention also provides a phase change memory, characterized in that it includes a bottom electrode layer, the aforementioned interface phase change memory material, and a top electrode layer, wherein the bottom electrode layer is located below the interface phase change memory material, and the top electrode layer is located above the interface phase change memory material.

[0024] Preferably, the thickness of the top electrode layer is 50–300 nm, and the material includes one or more of TiN, W, Al, Ti, Au, Pt, TiSiN, and C.

[0025] This invention also provides a method for fabricating a phase-change memory, comprising:

[0026] A substrate with a bottom electrode layer is provided, a van der Waals structure buffer layer is grown on the substrate, a superlattice phase change storage layer is grown on the buffer layer, and a top electrode layer is grown on the lattice phase change storage layer.

[0027] Preferably, the growth method includes atomic layer deposition, chemical vapor deposition, magnetron sputtering, pulsed laser deposition, or molecular beam epitaxy.

[0028] This invention also provides an application of phase-change memory.

[0029] The phase change memory material of this invention has a specific crystal plane growth orientation, and can undergo an amorphous-crystalline state transition under the action of an electrical pulse. Different intermediate states of resistance are formed depending on the ratio of amorphous to crystalline states in the structure, and these intermediates can exist stably at room temperature.

[0030] Beneficial effects

[0031] In this invention, the transition metal X in the interface phase change memory material combines with Te atoms in the phase change material to form an X-Te compound, constructing an atomically thick interface layer. This interface layer facilitates the layered stacking of the phase change material, improving its crystallization rate and the stability of device operation. During the amorphous-to-crystalline state transition under voltage pulses, the X-Te compound interface layer of the phase change memory device fabricated based on the interface phase change memory material remains intact, effectively limiting the longitudinal growth of the phase change material grains and refining the grain size. During device reset, due to the different proportions of amorphous and crystalline states, multiple intermediate states with different resistance values ​​exist. These intermediate resistance states can exist stably without significant resistance drift. The phase change memory device based on this interface effect regulation has the advantages of high speed, low power consumption, high-density storage, and low resistance drift. It is expected to be applied in neuromorphic devices and high-density storage fields. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the phase change storage material of the present invention.

[0033] Figure 2 The flowcharts ((a) to (e)) of the preparation method of the phase change storage material of the present invention are shown.

[0034] Figure 3 The following are schematic diagrams of the fabrication method of the phase change storage device of the present invention ((a)~(c)).

[0035] Figure 4 The image shows the X-ray diffraction pattern of the phase change storage film in Example 1.

[0036] Figure 5 The curves (RV curves) show the changes in the unit resistance of the phase change memory based on interface effect regulation in Example 2 under different electrical pulses.

[0037] Figure 6 The curves (RV curves) showing the change in unit resistance of the phase change memory based on Sb2Te3 material in Comparative Example 1 under different electrical pulses are shown.

[0038] Figure 7 The image shows the cyclic erase / write fatigue characteristic curves of the phase-change memory device cell based on interface effect regulation in Example 2.

[0039] Figure 8 The relationship (Rt) between the resistance values ​​of various intermediate states of the phase change memory based on interface effect regulation in Example 2 and time. Detailed Implementation

[0040] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0041] Example 1

[0042] A multilayer thin film with interface modulation, comprising:

[0043] Van der Waals buffer layer (102);

[0044] Phase change storage material layer: consists of eight alternating deposition cycles of transition metal Mo(103) and Sb2Te3(104) alloy.

[0045] Preparation method:

[0046] like Figure 2 As shown in (a), a substrate (101) is provided. The substrate used in this example is a silicon wafer. The silicon wafer is placed in acetone and alcohol solution and cleaned by ultrasonic waves for 10 min in sequence. After rinsing with deionized water for 30 s, it is dried with N2 and then placed in an oven at 80°C for 20 min.

[0047] like Figure 2 As shown in (b), a 5 nm thick Sb2Te3 buffer layer (102) was deposited on a silicon wafer using magnetron sputtering.

[0048] like Figure 2 As shown in (cd), eight cycles of alternating deposition of Mo (103) and Sb2Te3 (104) were performed on the buffer layer (102) using magnetron sputtering, wherein the thickness of the Mo layer was [missing information]. The Sb2Te3 layer is 5 nm thick.

[0049] In this example, the purity of the Mo and Sb₂Te₃ targets was greater than 99.99%. The argon gas purity exceeded 99.999%. The sputtering conditions were: sputtering chamber temperature 300℃, and background vacuum better than 2×10⁻⁶. -5 The sputtering power of the Mo target was 30W, the sputtering power of the Sb2Te3 target was 30W, the argon flow rate was 25sccm, and the sputtering pressure was 0.55Pa.

[0050] In this example, after the film deposition was completed, the heating stage was turned off, and the sample was placed in the reaction chamber to cool to room temperature to prevent film oxidation.

[0051] like Figure 4 As shown, X-ray diffraction results reveal that the thin film exhibits a high (0 0L) structural orientation. Using this thin film in a phase-change memory (PCM) enables faster switching operations. The transition metal Mo combines with Te atoms in the PCM to form a Mo-Te compound, constructing an atomic-level interface layer that facilitates the rapid layered stacking of Sb₂Te₃ crystals, thereby improving its crystallization speed and efficiency.

[0052] Example 2

[0053] like Figure 3 As shown, a phase-change memory cell has the following structure:

[0054] A substrate with a bottom electrode (201);

[0055] Sb2Te3 buffer layer (202);

[0056] A multilayer thin film (203) composed of Mo and Sb2Te3 with atomic-level thickness;

[0057] Top electrode layer (204).

[0058] The preparation method is as follows:

[0059] Using a substrate (201) with a bottom electrode, the silicon wafer is placed in acetone and alcohol solution and cleaned by ultrasonic cleaning for 10 minutes to remove surface oil and dust; then it is rinsed with deionized water for secondary cleaning, and finally the substrate is dried.

[0060] A 5 nm thick Sb₂Te₃ buffer layer (202) and a 6-cycle Mo-Sb₂Te₃ multilayer thin film (203) were grown on a substrate, wherein the Mo layer was thicker than 10 nm. The Sb2Te3 layer is 5 nm thick.

[0061] The above-mentioned thin film was prepared by magnetron sputtering, and the sputtering conditions were the same as in Example 1, so they will not be described in detail again.

[0062] After cooling to room temperature, the top electrode (204) is grown by sputtering. In this example, the top electrode is TiN with a thickness of 50 nm.

[0063] Top electrode sputtering conditions: TiN alloy target with purity greater than 99.999%, sputtering power 60W, background vacuum 2×10⁻⁶. -5 Pa, sputtering pressure 0.55 Pa.

[0064] Photoresist is applied to the deposited substrate. The application method can be spin coating, roller coating, or blade coating.

[0065] After the adhesive is applied, the substrate is dried. The drying conditions are: temperature 80℃, time 20 minutes.

[0066] The phase change memory unit was patterned using ultraviolet exposure and development, and the substrate was placed on a heating plate at 120°C and baked for 10 minutes.

[0067] Combination Figure 3 As shown, a dry etching process is used to remove excess top electrode and phase change film to obtain discrete device units.

[0068] The etching process consists of two steps. The first step involves etching away the excess TiN top electrode layer. Figure 3 b) Etching conditions: Base vacuum 1×10⁻⁶ -5 Pa, etching power 200W, etching time 4min. The second step is to etch the phase change material layer ( Figure 3 c) Etching conditions: Base vacuum 1×10⁻⁶ -5 The etching method features a high etching speed, good etching morphology, minimal etching damage, and wide applicability. The etching parameters are Pa, etching power 200W, and etching time 90s.

[0069] After etching the substrate, remove the photoresist barrier layer. Place the substrate in an acetone solution for 5 minutes to dissolve the photoresist, then soak it in an alcohol solution for 5 minutes to remove any residual acetone. Finally, rinse thoroughly with deionized water and place in an oven to dry.

[0070] After etching, deep holes will form in the areas not covered by photoresist. SiO2 can be grown in these channels to fill them (205). Excess SiO2 can then be etched or polished. Figure 3 As shown in (d).

[0071] The prepared phase change memory device is connected to an electrical testing system via a probe or wire. Applying an electrical pulse signal can induce a reversible transition between the amorphous and crystalline states of Mo and Sb2Te3 phase change materials, thereby testing the read / write, fatigue, and stability of each intermediate resistance state of the phase change memory device and studying the performance of the phase change memory device under this structure.

[0072] like Figure 5 The diagram shows the resistance-voltage relationship of a phase-change memory (PCM) based on interface effect modulation. To ensure data reliability, the results for each pulse width are averaged after multiple measurements. The high-resistance state is considered the device's reset state, and the low-resistance state is considered the set state. Under the action of a voltage pulse, the device can quickly complete the set process, resulting in an order-of-magnitude decrease in resistance. The reset process, on the other hand, involves a gradual increase in resistance, with multiple intermediate resistance states. As the applied pulse width decreases, the required reset voltage becomes higher, reaching nearly 6.7V at 6 ns. The device fabricated from the phase-change material provided by this invention has the advantages of high speed and low power consumption.

[0073] like Figure 7 As shown, the fatigue characteristic curve of the phase-change memory based on interface effect modulation is obtained by applying electrical pulses to the memory cells of the device to complete the RV window and setting appropriate erase and write pulse widths. The phase-change memory in this invention operates stably between the high and low resistance states for more than 4 × 10⁻⁶. 5 Second-rate.

[0074] like Figure 8 As shown, the resistance drift characteristics of a phase-change memory (PCM) based on interface effect modulation are illustrated. During the RV test, the pulse application was paused when the device was in a reset state, and the resistance change over time was measured at room temperature. The PCM device fabricated in this invention exhibits a low drift coefficient, and multiple (8) intermediate states can exist stably, improving the device's stability. Storing multiple bits of data in a single cell without increasing process complexity or cost helps improve the storage density of PCMs, making them promising for applications in multi-level storage and neuromorphic devices.

[0075] Comparative Example 1

[0076] A phase change memory cell, with the same structure as in Embodiment 2, consists of a bottom electrode substrate, a phase change material layer, and a top electrode. The phase change material layer is Sb₂Te₃.

[0077] The same preparation method as in Example 2 was used: a 40 nm thick Sb₂Te₃ layer was deposited on the bottom electrode substrate by magnetron sputtering at 300 °C. The top electrode layer was a 50 nm thick TiN layer.

[0078] The fabricated device underwent electrical performance testing. The test results are as follows: Figure 6 As shown. Compared to the phase change memory material provided by this invention, Sb2Te3 requires a higher voltage and consumes more power during the reset process. Furthermore, devices using Sb2Te3 as the phase change material generally suffer from poor stability and are prone to failure due to the formation of large grains during the phase change process.

[0079] The above examples are merely illustrative of the principles and applications of the present invention and are not intended to limit the invention. Any person skilled in the art may modify or alter the above examples without departing from the spirit and scope of the present invention. Modifications and alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of this invention.

Claims

1. An interface phase change memory material, characterized in that, The superlattice phase change storage layer comprises a van der Waals buffer layer and a superlattice phase change storage layer composed of alternating stacked transition metal layers and phase change material layers, wherein the superlattice phase change storage layer is located on the van der Waals buffer layer; The transition metal layer uses Mo as the transition metal element, and the phase change material layer uses Sb2Te3 as the chalcogenide compound material.

2. The interface phase change storage material according to claim 1, characterized in that, The van der Waals buffer layer has a thickness of 5-10 nm and is made of a two-dimensional chalcogenide compound with van der Waals and hexagonal structures, including one or more of Sb2Te3 and Bi2Te3.

3. The interface phase change storage material according to claim 1, characterized in that, The thickness of the superlattice phase change storage layer is 40–100 nm; the thickness of the transition metal layer is 0.5–2 nm; and the thickness of the phase change material layer is 3–10 nm.

4. A method for preparing the interface phase change memory material as described in claim 1, comprising: A substrate is provided, a van der Waals buffer layer is grown on the substrate, and a transition metal layer and a phase change material layer are alternately grown on the van der Waals buffer layer to obtain an interface phase change storage material.

5. The preparation method according to claim 4, characterized in that, The substrate includes one or more of single-crystal silicon, silicon carbide, gallium nitride, polyimide, polyethylene terephthalate, and sapphire substrate; the growth method includes atomic layer deposition, chemical vapor deposition, magnetron sputtering, pulsed laser deposition, or molecular beam epitaxy; and the transition metal layer and phase change material layer are alternately grown for 5 to 20 cycles.

6. A phase-change memory, characterized in that, It includes a bottom electrode layer, the interface phase change memory material as described in claim 1, and a top electrode layer, wherein the bottom electrode layer is located below the interface phase change memory material, and the top electrode layer is located above the interface phase change memory material.

7. The phase-change memory according to claim 6, characterized in that, The thickness of the top electrode layer is 50–300 nm, and the material includes one or more of TiN, W, Al, Ti, Au, Pt, TiSiN, and C.

8. A method for fabricating a phase-change memory, comprising: A substrate with a bottom electrode layer is provided, a van der Waals structure buffer layer of claim 1 is grown on the substrate, a superlattice phase change storage layer of claim 1 is grown on the buffer layer, and a top electrode layer is grown on the lattice phase change storage layer.

9. The preparation method according to claim 8, characterized in that, The growth methods include atomic layer deposition, chemical vapor deposition, magnetron sputtering, pulsed laser deposition, or molecular beam epitaxy.

10. An application of the phase-change memory as described in claim 6.

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