A Miller compensation circuit for a three-stage operational amplifier active network

Abstract

This invention discloses a three-stage operational amplifier active network Miller compensation circuit, belonging to the field of electronic circuits, including a first capacitor C. C1 Second capacitor C C2 Third capacitor C L NMOS transistors MN1-MN7 and PMOS transistors MP1-MP8; NMOS transistors MN1-MN4 and PMOS transistors MP1-MP5 constitute the first gain stage of the operational amplifier, which is a folded cascode input structure; NMOS transistor MN5 and PMOS transistor MP6 constitute the second gain stage of the operational amplifier, which is an inverting amplification structure; NMOS transistors MN6 and PMOS transistors MP7-MP8 constitute the third gain stage of the operational amplifier, and NMOS transistor MN7 is a feedforward gain stage. Together, they form a pseudo-Class AB push-pull output structure, which can improve the driving capability of the operational amplifier output for capacitive loads; the first capacitor C C1 Second capacitor C C2 To compensate for the capacitor, NMOS transistor MN2 is an active transconductance feedback compensation stage. This invention compensates based on the transconductance gain stage inherent in the three-stage operational amplifier's structure, eliminating the need for additional components, simplifying logic design, and reducing circuit power consumption. After compensation, the zero point in the left half-plane of the loop is moved to the right half-plane, significantly improving the circuit's phase margin and stability.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a Miller compensation circuit for a three-stage operational amplifier active network. Background Technology

[0002] Traditional operational transconductance amplifiers (op-amps) are a fundamental building block widely used in modern electronic product design. With the development of the integrated circuit industry, the feature size of design processes and the supply voltage of products are constantly decreasing. Therefore, multi-stage op-amps that can achieve high gain and wide output swing at low supply voltages are attracting increasing attention from designers. However, in the design of multi-stage op-amps, as the gain stages increase, the number of high-impedance nodes and low-frequency poles in the loop also increases accordingly, requiring frequency compensation to avoid stability issues.

[0003] The second gain stage of a traditional three-stage operational amplifier typically employs an inverting amplification structure and uses an inverted Miller network for frequency compensation. A small-signal model of a traditional inverted Miller network compensation circuit is attached. Figure 1 As shown, due to the compensation capacitor C C1 and C C2 This will create a feedforward path in the loop, resulting in zeros in the right half-plane of the loop. These zeros will reduce the op-amp loop phase margin, decrease op-amp stability, and limit the op-amp's maximum achievable bandwidth. Summary of the Invention

[0004] The purpose of this invention is to provide a Miller compensation circuit for a three-stage operational amplifier active network to solve the problems of reduced circuit phase margin and bandwidth, and decreased stability caused by Miller compensation of a traditional three-stage operational amplifier inverted network.

[0005] To address the aforementioned technical problems, this invention provides a three-stage operational amplifier active network Miller compensation circuit, including a first capacitor C. C1 Second capacitor C C2 Third capacitor C L NMOS transistors MN1 to MN7 and PMOS transistors MP1 to MP8; among which,

[0006] NMOS transistors MN1-MN4 and PMOS transistors MP1-MP5 constitute the first gain stage of the operational amplifier, which is a folded common-source common-gate input structure.

[0007] NMOS transistor MN5 and PMOS transistor MP6 constitute the second gain stage of the operational amplifier, which is an inverting amplification structure.

[0008] NMOS transistor MN6 and PMOS transistors MP7 to MP8 constitute the third gain stage of the operational amplifier, with NMOS transistor MN7 being the feedforward gain stage. Together, they form a pseudo-Class AB push-pull output structure, which can improve the operational amplifier's output driving capability for capacitive loads.

[0009] First capacitor C C1 Second capacitor C C2 To compensate for the capacitor, NMOS transistor MN2 is an active transconductance feedback compensation stage.

[0010] In one embodiment, the first capacitor C C1 The upper end is connected to the source terminal of NMOS transistor MN2, and the lower end is connected to the drain terminal of PMOS transistor MP8; the second capacitor C C2 The upper end is connected to the drain of PMOS transistor MP5, and the lower end is connected to the drain of PMOS transistor MP6; the third capacitor C L The upper end is connected to the output V OUT The lower end is connected to GND.

[0011] In one embodiment, the drain of the NMOS transistor MN1 is connected to the drain of the PMOS transistor MP4, and the gate is connected to a third bias voltage V. B3 The source terminal is connected to the drain terminal of NMOS transistor MN3; the drain terminal of NMOS transistor MN2 is connected to the drain terminal of PMOS transistor MP5, and the gate terminal is connected to the third bias voltage V. B3 The source terminal is connected to the drain terminal of NMOS transistor MN4; the drain terminal of NMOS transistor MN3 is connected to the drain terminal of PMOS transistor MP2, and the gate terminal is connected to the second bias voltage V. B2 The source terminal is connected to GND; the drain terminal of NMOS transistor MN4 is connected to the drain terminal of PMOS transistor MP3, and the gate terminal is connected to the second bias voltage V. B2 The source of NMOS transistor MN5 is connected to GND; the drain of NMOS transistor MN5 is connected to the drain of PMOS transistor MP6, the gate of NMOS transistor MN2 is connected to the drain of NMOS transistor MN2, and the source of NMOS transistor MN6 is connected to the drain of PMOS transistor MP7, the gate of NMOS transistor MN5 is connected to the drain of NMOS transistor MN5, and the source of NMOS transistor MN7 is connected to the drain of PMOS transistor MP8, the gate of NMOS transistor MN2 is connected to the drain of NMOS transistor MN2, and the source of NMOS transistor MN7 is connected to GND.

[0012] In one embodiment, the drain of PMOS transistor MP1 is simultaneously connected to the source of both PMOS transistor MP2 and PMOS transistor MP3, and the gate of PMOS transistor MP1 is connected to a first bias voltage V. B1 Source end connected to V DD The drain of PMOS transistor MP2 is connected to the drain of NMOS transistor MN3, and its gate is connected to the negative input terminal V of the operational amplifier. in- The source terminal is connected to the drain terminal of PMOS transistor MP1; the drain terminal of PMOS transistor MP3 is connected to the drain terminal of NMOS transistor MN4, and the gate terminal is connected to the positive input terminal V of the operational amplifier. in+ The source terminal is connected to the drain terminal of PMOS transistor MP1; the drain terminal of PMOS transistor MP4 is connected to the drain terminal of NMOS transistor MN1, the gate terminal is connected to the drain terminal of NMOS transistor MN1, and the source terminal is connected to V. DDThe drain of PMOS transistor MP5 is connected to the drain of NMOS transistor MN2, the gate is connected to the gate of PMOS transistor MP4, and the source is connected to V. DD The drain of PMOS transistor MP6 is connected to the drain of NMOS transistor MN5, and the gate is connected to the first bias voltage V. B1 Source end connected to V DD The drain of PMOS transistor MP7 is connected to the drain of NMOS transistor MN6, the gate is connected to the drain of NMOS transistor MN6, and the source is connected to V. DD The drain of PMOS transistor MP8 is connected to the drain of NMOS transistor MN7, the gate is connected to the gate of PMOS transistor MP7, and the source is connected to V. DD .

[0013] The Miller compensation circuit of a three-stage operational amplifier active network provided by this invention has the following beneficial effects:

[0014] (1) The present invention is based on the transconductance gain stage in the inherent structure of the three-stage operational amplifier for compensation, without the need to introduce additional devices, which can simplify logic design and reduce circuit power consumption.

[0015] (2) After compensation, the zero point in the left half-plane of the loop is moved to the right half-plane, the phase margin of the circuit is greatly improved, and the stability is increased. Attached Figure Description

[0016] Figure 1 This is a small-signal model diagram of a traditional reverse network Miller compensation circuit;

[0017] Figure 2 A diagram of a three-stage operational amplifier active network Miller compensation circuit is provided for this invention.

[0018] Figure 3 This invention provides a small-signal model diagram of a three-stage operational amplifier active network Miller compensation circuit. Detailed Implementation

[0019] The Miller compensation circuit of a three-stage operational amplifier active network proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0020] This invention provides a three-stage operational amplifier active network Miller compensation circuit, the specific structure of which is as follows: Figure 2 As shown, it includes a first capacitor C. C1 Second capacitor C C2 Third capacitor C LThe op-amp consists of NMOS transistors MN1 to MN7 and PMOS transistors MP1 to MP8. NMOS transistors MN1 to MN4 and PMOS transistors MP1 to MP5 form the first gain stage, which is a folded cascode input structure. NMOS transistors MN5 and MP6 form the second gain stage, which is an inverting amplification structure. NMOS transistors MN6 and MP7 to MP8 form the third gain stage, and NMOS transistor MN7 is a feedforward gain stage. Together, they form a pseudo-Class AB push-pull output structure, which improves the op-amp's ability to drive capacitive loads. C1 C C2 To compensate for the capacitor, NMOS transistor MN2 is an active transconductance feedback compensation stage.

[0021] The first capacitor C C1 The upper end is connected to the source terminal of NMOS transistor MN2, and the lower end is connected to the drain terminal of PMOS transistor MP8; the second capacitor C C2 The upper end is connected to the drain of PMOS transistor MP5, and the lower end is connected to the drain of PMOS transistor MP6; the third capacitor C L The upper end is connected to the output V OUT The lower end is connected to GND;

[0022] The drain of the NMOS transistor MN1 is connected to the drain of the PMOS transistor MP4, and the gate is connected to the third bias voltage V. B3 The source terminal is connected to the drain terminal of NMOS transistor MN3; the drain terminal of NMOS transistor MN2 is connected to the drain terminal of PMOS transistor MP5, and the gate terminal is connected to the third bias voltage V. B3 The source terminal is connected to the drain terminal of NMOS transistor MN4; the drain terminal of NMOS transistor MN3 is connected to the drain terminal of PMOS transistor MP2, and the gate terminal is connected to the second bias voltage V. B2 The source terminal is connected to GND; the drain terminal of NMOS transistor MN4 is connected to the drain terminal of PMOS transistor MP3, and the gate terminal is connected to the second bias voltage V. B2 The source of NMOS transistor MN5 is connected to GND; the drain of NMOS transistor MN5 is connected to the drain of PMOS transistor MP6, the gate of NMOS transistor MN2 is connected to the drain of NMOS transistor MN2, and the source of NMOS transistor MN6 is connected to the drain of PMOS transistor MP7, the gate of NMOS transistor MN5 is connected to the drain of NMOS transistor MN5, and the source of NMOS transistor MN6 is connected to GND; the drain of NMOS transistor MN7 is connected to the drain of PMOS transistor MP8, the gate of NMOS transistor MN2 is connected to the drain of NMOS transistor MN2, and the source of NMOS transistor MN6 is connected to GND.

[0023] The drain of PMOS transistor MP1 is connected to the source of both PMOS transistor MP2 and PMOS transistor MP3. The gate of PMOS transistor MP1 is connected to the first bias voltage V. B1 Source end connected to V DD The drain of PMOS transistor MP2 is connected to the drain of NMOS transistor MN3, and its gate is connected to the negative input terminal V of the operational amplifier. in-The source terminal is connected to the drain terminal of PMOS transistor MP1; the drain terminal of PMOS transistor MP3 is connected to the drain terminal of NMOS transistor MN4, and the gate terminal is connected to the positive input terminal V of the operational amplifier. in+ The source terminal is connected to the drain terminal of PMOS transistor MP1; the drain terminal of PMOS transistor MP4 is connected to the drain terminal of NMOS transistor MN1, the gate terminal is connected to the drain terminal of NMOS transistor MN1, and the source terminal is connected to V. DD The drain of PMOS transistor MP5 is connected to the drain of NMOS transistor MN2, the gate is connected to the gate of PMOS transistor MP4, and the source is connected to V. DD The drain of PMOS transistor MP6 is connected to the drain of NMOS transistor MN5, and the gate is connected to the first bias voltage V. B1 Source end connected to V DD The drain of PMOS transistor MP7 is connected to the drain of NMOS transistor MN6, the gate is connected to the drain of NMOS transistor MN6, and the source is connected to V. DD The drain of PMOS transistor MP8 is connected to the drain of NMOS transistor MN7, the gate is connected to the gate of PMOS transistor MP7, and the source is connected to V. DD .

[0024] The working principle of this invention is as follows:

[0025] Figure 3 In the small-signal model diagram of the Miller compensation circuit of the three-stage operational amplifier active network shown, g m1 -g m2 g m3 For the equivalent transconductance of the first to third gain stages, R o1 ~R o3 C represents the equivalent output impedance of the first to third gain stages. o1 C o2 C L C represents the equivalent output capacitance of the first to third gain stages. C1 For compensation capacitors, the compensation capacitor C C1 Connected in series with an active feedback stage, g mb and R b For the transconductance and input impedance of the active feedback stage, g mb =1 / R b C C2 The compensation capacitor is connected in parallel with the second gain stage; -g mf It is a feedforward gain stage.

[0026] Properly select circuit component parameters to ensure that the compensation capacitance is greater than the parasitic capacitance (i.e., C). C1 >>C o1 C C2 >>C o2 ) and the amplification factor of each gain stage is much greater than 1 (i.e., g m1 R o1 >>1, g m2 R o2>>1, g m3 R o3 >>1), then the open-loop transfer function of the three-stage operational amplifier can be obtained as shown in equation (1):

[0027]

[0028] Where A0 represents the DC gain, as shown in equation (2); ω p1 The principal pole is represented by equation (3):

[0029] A0 = g m1 R o1 g m2 R o2 g m3 R o3 (2)

[0030]

[0031] Unity-gain bandwidth is shown in equation (4):

[0032]

[0033] For example, g mf >g m3 Then, in equation (1), both zeros are located in the left half-plane; such as g mf =g m3 Then, in equation (1), there exists only one zero located in the left half-plane, and the transfer function can be simplified to equation (5). In this case, the unique zero is shown in equation (6):

[0034]

[0035]

[0036] Usually C C1 <<C L At this point, equation (7) holds for the phase margin Φ, where Φ z Represents the phase shift caused by the zero point.

[0037]

[0038] Therefore, if the requirement of a specific phase margin Φ is not met, the compensation capacitor C can be completed according to equation (8). C1 Values:

[0039]

[0040] Compensation capacitor C C2 It is not directly connected to the load capacitor, so its value does not affect the closed-loop stability of the op-amp. Meanwhile, as shown in equation (5), C... C2The smaller the value, the higher the frequency of the conjugate complex poles it introduces, thus giving the op-amp better phase margin and stability.

[0041] g mb It cannot be arbitrarily chosen. For example, if we want the circuit to have no overshoot during transient response, then g... mb The condition in equation (9) should be satisfied:

[0042]

[0043] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A three-stage operational amplifier active network Miller compensation circuit, characterized by, comprise a first capacitor C C1 , a second capacitor C C2 , a third capacitor C L , NMOS tubes MN1-MN7 and PMOS tubes MP1- MP8; wherein, NMOS tubes MN1-MN4 and PMOS tubes MP1-MP5 constitute a first gain stage of the operational amplifier, which is a folded cascode input structure; NMOS tube MN5 and PMOS tube MP6 constitute a second gain stage of the operational amplifier, which is a reverse amplification structure; NMOS tube MN6 and PMOS tubes MP7-MP8 constitute a third gain stage of the operational amplifier, wherein NMOS tube MN7 is a feed-forward gain stage, and the two constitute a pseudo-AB class push-pull output structure, which can improve the driving capability of the operational amplifier output to capacitive load; The first capacitor C C1 The second capacitor C C2 The NMOS transistor MN2 is an active transconductance feedback compensation stage for compensating the capacitor. The drain end of the NMOS tube MN1 is connected with the drain end of the PMOS tube MP4, the grid end is connected with the third bias voltage V B3 , and the source end is connected with the drain end of the NMOS tube MN3; the drain end of the NMOS tube MN2 is connected with the drain end of the PMOS tube MP5, the grid end is connected with the third bias voltage V B3 , and the source end is connected with the drain end of the NMOS tube MN4; the drain end of the NMOS tube MN3 is connected with the drain end of the PMOS tube MP2, the grid end is connected with the second bias voltage V B2 , and the source end is connected with GND; the drain end of the NMOS tube MN4 is connected with the drain end of the PMOS tube MP3, the grid end is connected with the second bias voltage V B2 , and the source end is connected with GND; the drain end of the NMOS tube MN5 is connected with the drain end of the PMOS tube MP6, the grid end is connected with the drain end of the NMOS tube MN2, and the source end is connected with GND; the drain end of the NMOS tube MN6 is connected with the drain end of the PMOS tube MP7, the grid end is connected with the drain end of the NMOS tube MN5, and the source end is connected with GND; the drain end of the NMOS tube MN7 is connected with the drain end of the PMOS tube MP8, the grid end is connected with the drain end of the NMOS tube MN2, and the source end is connected with GND; The drain end of the PMOS transistor MP1 is connected to the source end of the PMOS transistor MP2 and the source end of the PMOS transistor MP3, the gate end of the PMOS transistor MP1 is connected to the first bias voltage V B1 , the source end is connected to V DD ; the drain end of the PMOS transistor MP2 is connected to the drain end of the NMOS transistor MN3, the gate end is connected to the negative input end V in- of the operational amplifier, and the source end is connected to the drain end of the PMOS transistor MP1; the drain end of the PMOS transistor MP3 is connected to the drain end of the NMOS transistor MN4, the gate end is connected to the positive input end V in+ of the operational amplifier, and the source end is connected to the drain end of the PMOS transistor MP1; the drain end of the PMOS transistor MP4 is connected to the drain end of the NMOS transistor MN1, the gate end is connected to the drain end of the NMOS transistor MN1, and the source end is connected to V DD ; the drain end of the PMOS transistor MP5 is connected to the drain end of the NMOS transistor MN2, the gate end is connected to the gate end of the PMOS transistor MP4, and the source end is connected to V DD ; the drain end of the PMOS transistor MP6 is connected to the drain end of the NMOS transistor MN5, the gate end is connected to the first bias voltage V B1 , and the source end is connected to V DD ; the drain end of the PMOS transistor MP7 is connected to the drain end of the NMOS transistor MN6, the gate end is connected to the drain end of the NMOS transistor MN6, and the source end is connected to V DD ; the drain end of the PMOS transistor MP8 is connected to the drain end of the NMOS transistor MN7, the gate end is connected to the gate end of the PMOS transistor MP7, and the source end is connected to V DD .

2. The three-stage operational amplifier active network Miller compensation circuit of claim 1, wherein, The upper end of the first capacitor C C1 connects with the source end of NMOS tube MN2, and the lower end connects with the drain end of PMOS tube MP8; the upper end of the second capacitor C C2 connects with the drain end of PMOS tube MP5, and the lower end connects with the drain end of PMOS tube MP6; the upper end of the third capacitor C L connects with the output V OUT , and the lower end connects with GND.

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