Pixel processing circuit and reading method thereof, and image sensor

Abstract

The present invention provides a pixel processing circuit and a reading method thereof, and an image sensor, wherein the pixel processing circuit includes: a pixel array, an ADC module, and a switch selection module; the pixel units in each column of the pixel array are electrically connected to one end of the switch selection module disposed at both ends of the pixel array through an output bus; the other end of the switch selection module is electrically connected to one of the analog-to-digital converters in the ADC module, and each of the switch selection modules is only electrically connected to two corresponding analog-to-digital converters in the ADC module; the pixel array includes a Bayer array. The present invention controls the state of the switch selection module to achieve ADC conversion of the pixel signals passing through the Gr channel and the Gb channel at the same end of the output bus, thereby ensuring that the pixel signals of the Gr channel and the Gb channel will not have value deviations, thereby avoiding the "maze pattern" phenomenon after image interpolation and ensuring image quality.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a pixel processing circuit and a reading method thereof, and an image sensor applied to a CMOS image sensor. Background Art

[0002] CMOS image sensors (CIS) have been widely used in imaging fields such as video, surveillance, industrial manufacturing, automobiles, and home appliances. The mainstream readout circuit structure of CIS is a readout circuit based on column-level analog-to-digital converters (ADCs) to ensure that CIS has sufficient conversion accuracy and speed under reasonable power consumption. When the pixel size is small, the parallel column ADC readout structure with unilateral arrangement cannot achieve one column of ADC corresponding to one column of pixels, so it can only be achieved by using a bilateral arrangement on the pixel array. The two ADC arrays of this bilateral arrangement will inevitably have mismatches, which will lead to fixed odd and even column differences. This difference will cause deviations in the values ​​of the two green channels Gr and Gb in the Bayer array (Bayer Pattern), which will cause obvious boundary lines at the boundaries of the pixel cells after interpolation, that is, the image will show the so-called "maze pattern". The difference between the ADCs of the above two arrays is caused by factors such as processing technology, so even if the process and layout design are optimized, the difference can only be reduced to a certain extent. However, when the gain is large, the above abnormal phenomenon still exists. The existing pixel circuit, such as the patent document with publication number CN109040624A, discloses a pixel circuit and a reading method, but does not solve the technical problem proposed by the present invention.

[0003] Therefore, the present invention proposes a pixel processing circuit and a reading method thereof, and an image sensor, which can eliminate the difference between the Gr channel and the Gb channel, thereby avoiding the "maze pattern" phenomenon appearing in the image. Summary of the invention

[0004] The present invention provides a pixel processing circuit and a reading method thereof, and an image sensor. By adding a switch selection module between a pixel array and an ADC module, and controlling the state of the switch selection module, the pixel signals passing through the Gr channel and the Gb channel are all converted by the ADC on the same end side of an output bus, thereby ensuring that there is no value deviation in the pixel signals passing through the Gr channel and the Gb channel, thereby avoiding the "maze pattern" phenomenon after image interpolation and ensuring image quality.

[0005] In a first aspect, the present invention provides a pixel processing circuit, which is applied to an image sensor with a bilateral parallel ADC readout architecture, comprising: a pixel array composed of pixel units, an ADC module composed of at least two analog-to-digital converters, and a switch selection module, wherein the number of the switch selection modules is half the number of the analog-to-digital converters; the pixel units in each column of the pixel array are electrically connected to one end of the switch selection module arranged at both ends of the pixel array through an output bus; the other end of the switch selection module is electrically connected to one of the analog-to-digital converters in the ADC module, and each of the switch selection modules is only electrically connected to two corresponding analog-to-digital converters in the ADC module; the pixel array comprises a Bayer array.

[0006] Its beneficial effect is that: by controlling the state of the switch selection module, the pixel signals passing through the Gr channel and the Gb channel are converted by the ADC on the same end side of the output bus, ensuring that there will be no value deviation in the pixel signals passing through the Gr channel and the Gb channel, thereby avoiding the "maze pattern" phenomenon after image interpolation and ensuring image quality.

[0007] Optionally, the ADC module includes an analog-to-digital converter arranged on both sides of the pixel array; the switch selection module includes a first switch circuit, a second switch circuit, a third switch circuit and a fourth switch circuit; wherein the number of columns of the pixel array is an even number; the pixel units of the odd-numbered columns in the pixel array are respectively electrically connected to one end of the first switch circuit, and are respectively electrically connected to one end of the third switch circuit; wherein each of the pixel units of the odd-numbered columns is electrically connected to only one first switch circuit and one third switch circuit; the pixel units of the even-numbered columns in the pixel array are respectively electrically connected to one end of the second switch circuit, and are respectively electrically connected to one end of the fourth switch circuit; wherein each of the pixel units of the even-numbered columns is only electrically connected to only one second switch circuit and one fourth switch circuit; wherein the other ends of the adjacent first switch circuit and the second switch circuit are electrically connected to one analog-to-digital converter, the other ends of the adjacent third switch circuit and the fourth switch circuit are electrically connected to one analog-to-digital converter, and each of the first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit is only electrically connected to one analog-to-digital converter.

[0008] Further optionally, the first switch circuit includes at least one switch, the second switch circuit includes at least one switch, the third switch circuit includes at least one switch, and the fourth switch circuit includes at least one switch.

[0009] Optionally, each column of pixel units is connected to an output bus respectively.

[0010] Optionally, the pixel unit includes a photodiode, a transfer transistor, a reset transistor, a source follower transistor and a row enable transistor; one end of the photodiode is grounded, and the other end is connected to the drain of the transfer transistor; the gate of the transfer transistor is used to access the TX signal, the source of the transfer transistor is connected to the drain of the reset transistor, and is connected to the gate of the source follower transistor; the source of the reset transistor is connected to the power supply, and the gate of the reset transistor is connected to the RX signal; the source of the source follower transistor is connected to the power supply, the drain of the source follower transistor is connected to the source of the row enable transistor, the gate of the row enable transistor is connected to the SEL signal, and the drain of the row enable transistor is connected to the output bus of the pixel unit; wherein the drain of the reset transistor is connected to the source of the row enable transistor to obtain a row selection control signal for controlling the row selection output of the pixel array.

[0011] Optionally, the analog-to-digital converter includes an electrically connected comparator and a counter.

[0012] In a second aspect, the present invention provides a method for reading a pixel processing circuit, which is applied to the pixel processing circuit as described in any one of the first aspects, comprising:

[0013] According to the row selection control signal, pixel units in the pixel array are read and quantized row by row, including:

[0014] The transmission transistor is disconnected, and the conduction state of the switch selection module is controlled, so that the reset signal of the green pixel unit and the reset signals of the other color pixel units are read respectively through the analog-to-digital converters connected to different end sides of the pixel array;

[0015] The transmission transistor is turned on, and the conduction state of the switch selection module is adjusted so that the integrated signal of the green pixel unit is read by the same analog-to-digital converter;

[0016] The remaining color pixel units are red pixel units or blue pixel units.

[0017] Optionally, the conduction state of the switch selection module includes: at the same moment in the reading phase, the conduction states of the first switch circuit and the fourth switch circuit of one switch selection module are the same, the conduction states of the second switch circuit and the third switch circuit are the same, the conduction states of the first switch circuit and the third switch circuit are opposite, and the conduction state of the switch selection module is opposite when reading odd rows and even rows of the pixel array.

[0018] In a third aspect, the present invention provides an image sensor, comprising: a pixel processing circuit, a control logic module, and a data processing module as described in any one of the first aspects; the control logic module is used to control the processing of pixel signals by the pixel processing circuit; the data processing module is used to obtain signals processed by the pixel processing circuit.

[0019] For the beneficial effects of the second aspect or the third aspect, reference may be made to the description of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the overall circuit structure of a CMOS image sensor;

[0021] Figure 2 A schematic diagram of a CIS readout circuit architecture;

[0022] Figure 3 is a schematic diagram of another CIS readout circuit architecture;

[0023] Figure 4 is a schematic diagram of a pixel array based on the Bayer pattern;

[0024] Figure 5 A schematic diagram of the structure of a pixel processing circuit embodiment provided by the present invention;

[0025] Figure 6 This is a schematic diagram of the circuit structure of a CIS standard four-pixel unit;

[0026] Figure 7 Schematic diagram of an operation timing example of a SIC standard four-tube pixel unit. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application. Among them, in the description of the embodiments of the present application, the terms used in the following embodiments are only for the purpose of describing specific embodiments, and are not intended to be used as limitations on the present application. As used in the specification and the appended claims of the present application, the singular expressions "a", "the", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear indication to the contrary in the context. It should also be understood that in the following embodiments of the present application, "at least one", "one or more" refer to one or more (including two). The term "and / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist; for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in a "or" relationship.

[0028] References to "one embodiment" or "some embodiments" etc. described in this specification mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Thus, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways. The term "connection" includes direct connection and indirect connection, unless otherwise specified. "First" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0029] In the embodiments of the present application, the words "exemplarily" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example" is intended to present related concepts in a specific way.

[0030] In the prior art, the overall circuit structure of a CMOS image sensor is as follows: Figure 1 As shown. The circuit structure consists of a pixel array, a column ADC module, and a column storage unit ( Figure 1 The pixel array is composed of a plurality of pixel units, which convert the photocharge into an analog voltage after being exposed to light. The pixel units in each column of the pixel array are converted into analog-to-digital values ​​by the corresponding ADC in the column ADC module, and the analog voltage is converted into a corresponding digital value, and then the subsequent data processing is performed. Among them, Figure 1 The pixel array has m+1 columns, so there are m+1 ADCs corresponding to it. These ADCs can be ADC(0), ADC(1), ..., ADC(m), that is, each column in the pixel array corresponds to an ADC.

[0031] The currently commonly used CIS readout circuit architecture adopts a single-sided parallel ADC readout architecture, such as Figure 2As shown. That is, each ADC corresponds to the output of a column of pixels, and the width (PZ) of each ADC in the column ADC module is exactly the same as the width of each column of pixel units in the pixel array. When the pixel unit size is relatively small, for example, PZ < 2um, due to process limitations, it is difficult to implement ADC in such a small width. Therefore, in this case, the ADCs in the column ADC module are arranged in a way that they are set on both sides of the pixel array, as shown in the figure. Figure 3 As shown. However, due to the layout, the ADC is set on both sides of the pixel array, so the deviations in the processing technology, power supply, etc. on both sides of the pixel array will cause a slight difference in the ADC on both sides. This difference is fixed for the same CIS chip. If the light is evenly distributed in the environment, there will be a difference in the ADC on both sides of the pixel array. That is, Figure 3 There is a fixed deviation between the output bus PIX_OUT(0) and the output bus PIX_OUT(1) corresponding to the pixel signal output through the Gr channel in the even column and the pixel signal output through the Gb channel in the odd column. The Gr channel refers to the channel formed by the green pixel unit Gr and the transmission bus connected to the pixel; the Gb channel refers to the channel formed by the red pixel Gb and the transmission bus connected to the pixel.

[0032] The filter implementation method used by general CIS is based on the Bayer Pattern, that is, RGB, including R (red), B (blue), Gr (green), and Gb (green) components. After normal light is irradiated, light of different colors will pass through the color filter, allowing R light, G light, and B light to reach the CIS respectively. Then, after the CIS completes the conversion of light intensity to digital quantity, the final image is synthesized through the corresponding interpolation algorithm. Figure 4 FIG. 4 shows a simple pixel array based on the Bayer pattern, including a green pixel unit Gr, a green pixel unit Gb, a red pixel unit R and a blue pixel unit B. Figure 4As shown, assuming that the red pixel unit R is the pixel point that needs to be interpolated, so if the green light component is interpolated to this point, it is necessary to collect the values ​​of the four nearby green light components (Gr1, Gr2, Gb1, Gb2) to synthesize the green component of this pixel point. Ideally, the average of the four surrounding green components is the interpolation amount, and the gradient of this pixel point from the four surrounding pixels that pass through the G component is 0, that is, R = Gr1 = Gr2 = Gb1 = Gb2. However, if there is a channel difference ΔK between the Gr channel and the Gb channel, Gr1 = Gr2 = Gb1 + ΔK = Gb2 + ΔK. Taking the more common bilinear interpolation as an example, R = [(Gr1 + Gr1) / 2 + (Gb1 + Gb2) / 2] / 2 = Gb1 + ΔK / 4, at this time, the gradient of the red pixel unit R from the green pixel unit Gr is |Gr1–R| + |Gr2–R| = 3 / 2*ΔK; the gradient of the red pixel unit R from the green pixel unit Gb is |Gb1–PC| + |Gb2–PC| = 1 / 2*ΔK; because there are different gradients, it is inevitable that steps or pseudo edges appear in the flat area. The actual CIS interpolation synthesis algorithm is not so simple. This kind of edge will have no rules, and the so-called "maze pattern" will be formed on the image.

[0033] In order to eliminate the maze patterns caused by the above-mentioned deviations, the present invention proposes a pixel processing circuit, which is applied to an image sensor with a bilateral parallel ADC readout architecture, comprising: a pixel array composed of pixel units, an ADC module composed of at least two analog-to-digital converters, and a switch selection module, wherein the number of the switch selection modules is half the number of the analog-to-digital converters; the pixel units in each column of the pixel array are electrically connected to one end of the switch selection module arranged at both ends of the pixel array through an output bus; the other end of the switch selection module is electrically connected to one of the analog-to-digital converters in the ADC module, and each of the switch selection modules is only electrically connected to two corresponding analog-to-digital converters in the ADC module; the pixel array comprises a Bayer array.

[0034] By controlling the state of the switch selection module, the pixel signals passing through the Gr channel and the Gb channel are converted by the ADC on the same end of the output bus, ensuring that there is no value deviation in the pixel signals passing through the Gr channel and the Gb channel, thereby avoiding the "maze pattern" phenomenon after image interpolation and ensuring image quality.

[0035] Optionally, the ADC module includes an analog-to-digital converter arranged on both sides of the pixel array; the switch selection module includes a first switch circuit, a second switch circuit, a third switch circuit and a fourth switch circuit; wherein the number of columns of the pixel array is an even number; the pixel units of the odd-numbered columns in the pixel array are respectively electrically connected to one end of the first switch circuit, and are respectively electrically connected to one end of the third switch circuit; wherein each of the pixel units of the odd-numbered columns is electrically connected to only one first switch circuit and one third switch circuit; the pixel units of the even-numbered columns in the pixel array are respectively electrically connected to one end of the second switch circuit, and are respectively electrically connected to one end of the fourth switch circuit; wherein each of the pixel units of the even-numbered columns is only electrically connected to only one second switch circuit and one fourth switch circuit; wherein the other ends of the adjacent first switch circuit and the second switch circuit are electrically connected to one analog-to-digital converter, the other ends of the adjacent third switch circuit and the fourth switch circuit are electrically connected to one analog-to-digital converter, and each of the first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit is only electrically connected to one analog-to-digital converter.

[0036] Further optionally, the first switch circuit includes at least one switch, the second switch circuit includes at least one switch, the third switch circuit includes at least one switch, and the fourth switch circuit includes at least one switch.

[0037] Optionally, each column of pixel units is connected to an output bus respectively.

[0038] Optionally, the pixel unit includes a photodiode, a transfer transistor, a reset transistor, a source follower transistor and a row enable transistor; one end of the photodiode is grounded, and the other end is connected to the drain of the transfer transistor; the gate of the transfer transistor is used to access the TX signal, the source of the transfer transistor is connected to the drain of the reset transistor, and is connected to the gate of the source follower transistor; the source of the reset transistor is connected to the power supply, and the gate of the reset transistor is connected to the RX signal; the source of the source follower transistor is connected to the power supply, the drain of the source follower transistor is connected to the source of the row enable transistor, the gate of the row enable transistor is connected to the SEL signal, and the drain of the row enable transistor is connected to the output bus of the pixel unit; wherein the drain of the reset transistor is connected to the source of the row enable transistor to obtain a row selection control signal for controlling the row selection output of the pixel array.

[0039] Optionally, the analog-to-digital converter includes an electrically connected comparator and a counter.

[0040] For example, Figure 5A pixel processing circuit shown is applied to an image sensor with a bilateral parallel ADC readout architecture, comprising: a pixel array composed of pixel units, an ADC module composed of n+1 analog-to-digital converters, and a switch selection module, wherein n is an odd number greater than 1. The switch selection module comprises a first switch circuit, a second switch circuit, a third switch circuit, and a fourth switch circuit. One of the switch selection modules comprises a first switch circuit S0, a second switch circuit S1, a third switch circuit S3, and a fourth switch circuit S2. The ADC module includes analog-to-digital converters arranged on both sides of the pixel array; wherein the number of columns of the pixel array is n+1; the pixel units of the odd-numbered columns in the pixel array are respectively electrically connected to one end of the first switch circuit, and are respectively electrically connected to one end of the third switch circuit; wherein each of the pixel units of the odd-numbered columns is electrically connected to only one first switch circuit and one third switch circuit; the pixel units of the even-numbered columns in the pixel array are respectively electrically connected to one end of the second switch circuit, and are respectively electrically connected to one end of the fourth switch circuit; wherein each of the pixel units of the even-numbered columns is electrically connected to only one second switch circuit and one fourth switch circuit; wherein the other ends of adjacent first switch circuits and second switch circuits are electrically connected to one analog-to-digital converter, the other ends of adjacent third switch circuits and fourth switch circuits are electrically connected to one analog-to-digital converter, and each of the first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit is electrically connected to only one analog-to-digital converter. The ADC module includes: ADC (0), ADC (1), ADC (2), ADC (3), ... ADC (n-1), ADC (n), and ADC (0), ADC (2), ..., ADC (n-1) and ADC (1), ADC (3), ..., ADC (n) are respectively arranged on both sides of the pixel array.

[0041] Figure 5 This is only an embodiment of a pixel processing circuit provided by the present invention, but it does not limit the protection scope of the pixel processing circuit provided by the present invention. Optionally, through different process means and actual application requirements, the analog-to-digital converter can be arranged on the same side of the pixel array.

[0042] Based on the pixel processing circuit provided in the above embodiment, the present invention further provides a method for reading the pixel processing circuit, comprising: reading and quantizing the pixel units in the pixel array row by row according to a row selection control signal, comprising:

[0043] The transmission transistor is disconnected, and the conduction state of the switch selection module is controlled, so that the reset signal of the green pixel unit and the reset signals of the other color pixel units are read respectively through the analog-to-digital converters connected to different end sides of the pixel array;

[0044] The transmission transistor is turned on, and the conduction state of the switch selection module is adjusted so that the integrated signal of the green pixel unit is read by the same analog-to-digital converter;

[0045] The remaining color pixel units are red pixel units or blue pixel units.

[0046] In a possible embodiment, the conduction state of the switch selection module includes: at the same time in the reading phase, the conduction states of the first switch circuit and the fourth switch circuit of one switch selection module are the same, the conduction states of the second switch circuit and the third switch circuit are the same, the conduction states of the first switch circuit and the third switch circuit are opposite, and the conduction state of the switch selection module is opposite when reading odd rows and even rows of the pixel array.

[0047] The reading process of pixel signals related to different colors in the pixel array is explained based on the working principles of the first switch circuit S0, the second switch circuit S1, the third switch circuit S3 and the fourth switch circuit S2. Figure 5 The pixel array in the embodiment includes a green pixel unit Gr, a green pixel unit Gb, a red pixel unit R, and a blue pixel unit B arranged in a Bayer pattern. When the control signal state of the first switch circuit S0 is "high", the first switch circuit S0 is turned on; when the control signal state of the first switch circuit S0 is "low", the first switch circuit S0 is turned off; the second switch circuit S1, the fourth switch circuit S2, and the third switch circuit S3 are turned on and off in the same manner.

[0048] like Figure 5As shown, when the first row of pixel units of the pixel array includes a green pixel unit Gb and a blue pixel unit B, and when the TX signal is "low", the transmission transistor is turned off, firstly, the first switch circuit S0 and the fourth switch circuit S2 are controlled to be turned off, and the second switch circuit S1 and the third switch circuit S3 are turned on, and the reset signal of the blue pixel unit B is read as B_VRST through ADC (1), and the reset signal Gb_VRST of the green pixel unit Gb is read through ADC (0); then, the first switch circuit S0, the second switch circuit S1, the fourth switch circuit S2 and the third switch circuit S3 are controlled to remain unchanged, and when the TX signal becomes "high", the transmission transistor is turned on, and the integral signal Gb_VSIG of the green pixel unit Gb is read through ADC (0), and the integral signal B_VSIG of the blue pixel unit B is read through ADC (1). Then, similarly, the pixels of the first row of pixel units are read, so that the signals of the green pixel unit and the blue pixel unit are read respectively through the analog-to-digital converters connected to different ends of the pixel array. It can be seen that the pixel signals through the Gb channel electrically connected to the first switch circuit S0 are all read out by ADC (0), so when reading out the signal of the green pixel unit Gr, it is necessary to control and adjust the first switch circuit S0, the second switch circuit S1, the fourth switch circuit S2 and the third switch circuit S3 so that the conduction states of the first switch circuit S0, the second switch circuit S1, the fourth switch circuit S2 and the third switch circuit S3 are opposite, so that the signal through the Gr channel electrically connected to the second switch circuit S1 is also read out by ADC (0). Specifically, when reading the second row of pixel units, the first switch circuit S0 and the fourth switch circuit S2 are controlled to be turned on, and the second switch circuit S1 and the third switch circuit S3 are turned off. The reset signal of the red pixel unit R is read out as R_VRST through ADC (1), and the reset signal Gr_VRST of the green pixel unit Gr is read out through ADC (0); then the first switch circuit S0, the second switch circuit S1, the fourth switch circuit S2 and the third switch circuit S3 are controlled to remain unchanged. When the TX signal becomes "high", the transmission transistor is turned on, and the integral signal Gr_VSIG of the green pixel unit Gr is read out through ADC (0), and the integral signal R_VSIG of the red pixel unit R is read out through ADC (1). By analogy, the above timing control method can ensure that the pixel signals of the Gr channel and the Gb channel are read out by the ADC on the same side of the pixel array, and no error occurs. Figure 3 The traditional bilateral parallel ADC architecture reads out the differences in Gr and Gb channels generated by different ADC arrays.

[0049] The following is a supplementary description of the basic structure and operation sequence of the pixel unit:

[0050] Figure 6It is a CIS standard four-tube pixel unit circuit structure, which consists of a photodiode PD, a transfer transistor Mtg, a reset transistor Mrst, a source follower transistor Msf, and a row selection transistor Msel. One end of the photodiode PD is grounded, and the other end is connected to the drain of the transfer transistor Mtg; the gate of the transfer transistor Mtg is used to access the TX signal, the source of the transfer transistor Mtg is connected to the drain of the reset transistor Mrst, and connected to the gate of the source follower transistor Msf; the source of the reset transistor Mrst is connected to the power supply, and the gate of the reset transistor Mrst is connected to the RX signal; the source of the source follower transistor Msf is connected to the power supply, the drain of the source follower transistor Msf is connected to the source of the row selection transistor Msel, the source of the row selection transistor Msel is connected to the SEL signal, and the drain of the row selection transistor Msel is connected to the row output line of the pixel array. When PD is sensitive to light, it generates photoelectrons proportional to the light intensity. The function of Mtg is to transfer photoelectrons in PD. When the TX signal is at a high potential, Mtg is turned on and the photoelectrons in PD are transferred to the floating node FD. The function of Mrst is to reset FD when the RX signal is at a high potential. Msf is an amplifier. When SEL is at a high potential, Msel is turned on. Msf, Msel and the current source to the ground form a path. At this time, Msf follows the change of FD potential and is finally output by PIX_OUT.

[0051] Figure 7 This is the operation timing of the CIS standard four-tube pixel unit, which is divided into reset (Rst), exposure (Exp), and signal reading (Read). In the Rst stage, the TX signal and the RX signal are at a "high" potential, Mtg and Mrst are both turned on, the FD is reset and its potential is pulled up to the power supply voltage VDD. After that, the RX signal and the TX signal become "low" potentials, entering the Exp stage, and the PD is sensitive to light and accumulates electrons. Then, in the Read stage, SEL is at a "high" potential, the RX signal is first at a "high" potential, and after resetting the FD, the RX signal is pulled to a "low" potential, and the TX signal remains at a "low" potential. At this time, Msf is controlled by the FD potential and outputs the reset potential VRST through PIX_OUT. After that, the TX signal is pulled to a "high" potential, and the electrons on the PD are transferred to the FD. At this time, Msf is controlled by the FD potential and outputs the integral potential VSIG through PIX_OUT. The difference between VRST-VSIG is the analog voltage corresponding to the photoelectrons on the PD. VRST and VSIG potentials are converted into digital quantities by the analog-to-digital converter (ADC) circuit and subtracted to obtain the digital quantity corresponding to the actual photoelectrons on the PD. If the ADC is 12 bits and the ADC reference voltage range is VREF, the final output is DOUT = (VRST-VSIG) × 2 12 / VREF.

[0052] Based on the pixel processing circuit provided in any one of the above embodiments, an embodiment of the present application provides an image sensor, including: a pixel processing circuit, a control logic module, and a data processing module as described in any one of the above embodiments; the control logic module is used to control the processing of pixel signals by the pixel processing circuit; the data processing module is used to obtain signals processed by the pixel processing circuit.

[0053] The above is only a specific implementation of the embodiment of the present application, but the protection scope of the embodiment of the present application is not limited thereto, and any changes or replacements within the technical scope disclosed in the embodiment of the present application should be included in the protection scope of the embodiment of the present application. Therefore, the protection scope of the embodiment of the present application should be based on the protection scope of the claims.

Claims

1. A pixel processing circuit, characterized in that: An image sensor applied to a bilateral parallel ADC readout architecture comprises: a pixel array composed of pixel units, an ADC module composed of at least two analog-to-digital converters, and a switch selection module, wherein the number of the switch selection modules is half the number of the analog-to-digital converters; The pixel units in each column of the pixel array are respectively electrically connected to one end of the switch selection module disposed at two ends of the pixel array through an output bus; The other end of the switch selection module is electrically connected to one of the analog-to-digital converters in the ADC module, and each of the switch selection modules is only electrically connected to two corresponding analog-to-digital converters in the ADC module; The pixel array comprises a Bayer array; The ADC module includes analog-to-digital converters arranged on both sides of the pixel array; the switch selection module includes a first switch circuit, a second switch circuit, a third switch circuit and a fourth switch circuit; wherein the number of columns of the pixel array is an even number; The pixel units of the odd-numbered columns in the pixel array are respectively electrically connected to one end of the first switch circuit and one end of the third switch circuit; wherein each of the pixel units of the odd-numbered columns is only electrically connected to one of the first switch circuits and one of the third switch circuits; The pixel units of the even-numbered columns in the pixel array are respectively electrically connected to one end of the second switch circuit and one end of the fourth switch circuit; wherein each of the pixel units of the even-numbered columns is only electrically connected to one of the second switch circuits and one of the fourth switch circuits; Among them, the other ends of the adjacent first switch circuit and the second switch circuit are electrically connected to one of the analog-to-digital converters, the other ends of the adjacent third switch circuit and the fourth switch circuit are electrically connected to one of the analog-to-digital converters, and each of the first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit is electrically connected to only one analog-to-digital converter.

2. The pixel processing circuit according to claim 1, characterized in that: The first switch circuit includes at least one switch, the second switch circuit includes at least one switch, the third switch circuit includes at least one switch, and the fourth switch circuit includes at least one switch.

3. The pixel processing circuit according to claim 1, characterized in that: Each column of pixel units is connected to an output bus respectively.

4. The pixel processing circuit according to claim 1, characterized in that: The pixel unit includes a photodiode, a transfer transistor, a reset transistor, a source follower transistor and a row gate transistor; One end of the photodiode is grounded, and the other end is connected to the drain of the transmission transistor; the gate of the transmission transistor is used to access the TX signal, the source of the transmission transistor is connected to the drain of the reset transistor, and connected to the gate of the source follower transistor; the source of the reset transistor is connected to the power supply, and the gate of the reset transistor is connected to the RX signal; The source of the source follower transistor is connected to a power supply, the drain of the source follower transistor is connected to the source of the row selection transistor, the gate of the row selection transistor is connected to a SEL signal, and the drain of the row selection transistor is connected to the output bus of the pixel unit; The drain of the reset transistor is connected to the source of the row selection transistor to obtain a row selection control signal for controlling the row selection output of the pixel array.

5. The pixel processing circuit according to claim 4, characterized in that: The analog-to-digital converter includes an electrically connected comparator and a counter.

6. A method for reading a pixel processing circuit, characterized in that: A pixel processing circuit as claimed in any one of claims 1 to 5, comprising: According to the row selection control signal, pixel units in the pixel array are read and quantized row by row, including: The transmission transistor is disconnected to control the conduction state of the switch selection module, so that the reset signal of the green pixel unit and the reset signals of the other color pixel units are read respectively through the analog-to-digital converters connected to different end sides of the pixel array; The transmission transistor is turned on, and the conduction state of the switch selection module is adjusted so that the integrated signal of the green pixel unit is read by the same analog-to-digital converter; The remaining color pixel units are red pixel units or blue pixel units.

7. The method for reading a pixel processing circuit according to claim 6, characterized in that: The conduction state of the switch selection module includes: At the same moment in the reading phase, the conduction states of the first switch circuit and the fourth switch circuit of one switch selection module are the same, the conduction states of the second switch circuit and the third switch circuit are the same, the conduction states of the first switch circuit and the third switch circuit are opposite, and the conduction state of the switch selection module is opposite when reading the odd rows and the even rows of the pixel array.

8. An image sensor, characterized in that: include: The pixel processing circuit, control logic module, and data processing module as described in any one of claims 1 to 5; The control logic module is used to control the processing of the pixel signal by the pixel processing circuit; the data processing module is used to obtain the signal processed by the pixel processing circuit.

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